Padmaja Kavuri

408-476-1744 (m)
padmajakavuri2000@yahoo.com

SUMMARY
Seeking a challenging position as hardware Design and Verification
Engineer. Over four years of experience in hardware design and verification
environment developement. Gate level simulation, Synthesis and timing
constraints experience in DDR2 controller and Ethernet MAC.
Strong knowledge in Ethernet IEEE 802.3 protocol, AMBA AHB bus
protocol. Understanding of ARM Cortex M1,Tilera Tilepro, Altera and
Xilinx FPGA design flow.

SKILL PROFILE
Programming Languages: Verilog, C and MIPS assembly language
Script language: Perl,Tcl
Verilog design/Simulation tools: Modelsim, VCS, Synopsys design
compiler, VirSim, Synopsys Design Analyzer, Xilinx ISE, Altera QuartusII.
FPGA Families: Xilinx Virtex-IV, Altera Cyclone-III
Circuit Design tools: Cadence Virtuoso (Schematic, layout and Spice
Spectre)
PROFESSIONAL EXPERIENCE

Atria Logic Inc., Sunnyvale, CA (10/06-Present)

Ethernet MAC
Designed and implemented Ethernet MAC according to IEEE802.3 protocol
for 10/100/1000Mbps speeds with MII/GMII/RGMII interface logic.
Responsibilities include design, RTL coding using Verilog, unit and system
level test bench set up, test plan developement and implementation on Altera
CycloneIII and Xilinx Virtex IV FPGA. Performed functional simulation
using ModelSim SE. Involved in SoC bring up of H.264 video decoder with
ARM Cortex M1, DDR2 memory controller and Ethernet MAC in Altera
Cyclone III FPGA.

DDR2 SDRAM Memory Controller

Assisted in RTL coding of DDR2 memory controller. The design was
implemented on Altera Cyclone III board running at 266 Mhz. Synthesized
using Altera Quartus II software, performed timing analysis using Time-
Quest TA and implemented on Cyclone III EP3C120F780C7 FPGA.
Responsible for set up verification environment in unit level, test plans,
timing constraints for source synchronous inputs of DDR and debugging
using gate level simulation and Logic Analyzer.
H.264 Video Decoder
Involved in H.264 Video Decoder implementation on Altera Cyclone-III
FPGA and Xilinx Virtex IV. Responsibilities include top level integration
(ARM Cortex-M1, DDR2-DRAM, Flash Controllers etc), reset and clock
implementation, testbench setup. Ported video decoder unit simulation tests
to top level. Converted Verilog simulation tests into C diagnostics to run on
Cortex-M1 using ARM u-Vision IDE.

AMBA AHB Bus

Implemented AMBA AHB bus slave interface for DDR1 memory controller.
Coded design in Verilog RTL and setup testbench infrastructure to verify
AHB slave functionality.

Ethernet Packet Generator

Assisted in testbench development for a 4-port 10G Ethernet Switch FPGA
design by building an Ethernet packet generator. Packets were generated
with L2, L3, L4 headers, VLAN tagging and jumbo payload using Verilog
task calls. Later developed functional tests for the FPGA using the packet
generator task calls.

Dew Software Inc., Fremont, CA (08/05-09/06)

Detailed study and understanding of Clarkspur DSP (CD2450A)

Implemented MP3 decoder algorithm in C language targeted for 16bit fixed
point CDSP. Developed assembly code for MP3 decoder ported on DSP
CD2450A board. Documented MP3 decoder implementation for 16bit fixed
point CDSP.

DDR SDRAM Memory Controller

Assisted in RTL development of double data rate SDRAM memory
controller. The design was implemented on Virtex 4 FX Xilinx ML403
board running at 133.3 MHz. Responsible for functional gate level
simulation verification, data specific test, random data tests, boundary
crossing tests were performed.

ACADEMIC EXPERIENCE

Router Design
Designed RTL Code for the Router. Verified functionality of the Router
using a testbench. Synthesized the Router to achieve optimal performance at
maximum frequency. Verified post-synthesized gate level netlist. Performed
back annotation on Verilog netlist and SDF Files using Synopsys tool.

MIPS 4300 series 32bit processor

Designed data path (Multicycle implementation) and controller (sequencer
architecture) for MIPS RISC processor. Generated RTL code and simulated
using Altera Quartus tool. Developed test cases using MIPS instructions to
verify the functionality.

Implementation of Tomasulo Algorithm

Implemented Tomasulo Algorithm that is a dynamic scheduling scheme
used to avoid data hazards.Generated the RTL code for this algorithm.
Verified functionality of the Tomasulo algorithm with test cases using VCS
simulator and debugged using Synopsis design compiler.

Memory BIST Design

Designed March 12N algorithm in MBIST controller to detect different
memory faults including SAFs, TFs,CFinv and CFid.
Developed RTL code and simulated using VCS tool.
Developed functional verification environment for memory BIST using
Verilog.
Synthesized the design using Synopsys design compiler.

8-Bit ALU (Arithmetic and Logic Unit)

Designed an 8-bit ALU using dynamic logic in Cell-based implementation
and generated various testcases
for Pre-Layout design. Performed parasitic extraction of layout using
Cadence tools and verified all testcases for Post-Layout Extraction
Simulation with timing information using TSMC's 0.25-µm process.

6-Bit Current Mode DAC (Digital to Analog Converter)

Designed a 6 bit Current Mode DAC (Digital to Analog Converter) in Cell-
based implementation and
generated various test cases for Pre-Layout design. Performed parasitic
extraction of layout using Cadence tools and verified all test cases for Post-
Layout Extraction Simulation with timing information using TSMC’s 0.25-
µm process.

Teaching Assistant (10/98-10/00)

Involved in teaching operation of analog devices like OPAMP, Oscillators,
Filters, and Amplifiers, ADC, DAC, 8085 and 8086 assembly language
programming.

EDUCATION
MSEE (Master of science in Electrical Engg), with Specialization in
ASIC/VLSI Circuits, San Jose State University, San Jose California.
Dec2004

Master of science in Electronics, Nagarjuna University, INDIA.

Secured FIRST RANK awarded Gold medal.