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DDR3L SDRAM
Device Operation
Contents
1. Functional Description
1.1 Simplified State Diagram
1.2 Basic Functionality
1.3 RESET and Initialization Procedure
1.3.1 Power-up Initialization Sequence
1.3.2 Reset Initialization with Stable Power
1.4 Register Definition
1.4.1 Programming the Mode Registers
1.4.2 Mode Register MR0
1.4.3 Mode Register MR1
1.4.4 Mode Register MR2
1.4.5 Mode Register MR3
2. DDR3 DRAM Command Description and Operation
2.1 Command Truth Table
2.2 CKE Truth Table
2.3 No Operation (NOP) Command
2.4 Deselect Command
2.5 DLL-off Mode
2.6 DLL on/off switching procedure
2.6.1 DLL on to DLL off Procedure
2.6.2 DLL off to DLL on Procedure
2.7 Input clock frequency change
2.8 Write Leveling
2.8.1 DRAM setting for write leveling & DRAM termination function in that mode
2.8.2 Procedure Description
2.8.3 Write Leveling Mode Exit
2.9 Extended Temperature Usage
2.9.1 Auto Self-Refresh mode - ASR Mode
2.9.2 Self-Refresh Temperature Range - SRT
2.10 Multi Purpose Register
2.10.1 MPR Functional Description
2.10.2 MPR Register Address Definition
2.10.3 Relevant Timing Parameters
2.10.4 Protocol Example
2.11 ACTIVE Command
2.12 PRECHARGE Command
2.13 READ Operation
2.13.1 READ Burst Operation
2.13.2 READ Timing Definitions
2.13.3 Burst Read Operation followed by a Precharge
2.14 WRITE Operation
2.14.1 Burst Operation
2.14.2 WRITE Timing Violations
2.14.3 Write Data Mask
2.14.4 tWPRE Calculation
2
1. Functional Description
1.1 Simplified State Diagram
This Simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling of
on-die termination, and some other events are not captured in full detail.
Power
applied
Power
On
Reset
Procedure
MRS, MPR,
Write
Leveling
Initialization
Self
Refresh
SRE
ZQCL
MRS
from any
state
RESET
ZQ
Calibration
SRX
REF
ZQCL,ZQCS
Idle
Refreshing
PDE
ACT
PDX
Active
Power
Down
Precharge
Power
Down
Activating
PDX
PDE
Bank
Active
WRITE
WRITE
READ
WRITE A
Writing
READ
READ A
READ
Reading
WRITE
READ A
WRITE A
WRITE A
READ A
PRE, PREA
Writing
PRE, PREA
Reading
PRE, PREA
Precharging
Automatic
Sequence
Command
Sequence
Function
Abbreviation
Function
Abbreviation
Function
ACT
PRE
PREA
MRS
REF
ZQCL
Active
Precharge
Precharge All
Mode Register Set
Refresh
ZQ Calibration Long
Read
Read A
Write
Write A
RESET
ZQCS
PDE
PDX
SRE
SRX
MPR
-
Enter Power-down
Exit Power-down
Self-Refresh entry
Self-Refresh exit
Multi-Purpose Register
-
Note : See "2.1 Command Truth Table" on page 21 for more details.
The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank
DRAM. The DDR3 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch
architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four clock data transfer
at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O
pins.
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and continue
for a burst length of eight or a chopped burst of four in a programmed sequence. Operation begins with the
registration of an Active command, which is then followed by a Read or Write command. The address bits
registered coincident with the Active command are used to select the bank and row to be activated (BA0-BA2
select the bank; A0-A15 select the row; refer to DDR3 SDRAM Addressing in each datasheet for specific
requirements). The address bits registered coincident with the Read or Write command are used to select the
starting column location for the burst operation, determine if the auto precharge command is to be issued (via
A10), and select BC4 or BL8 mode on the fly (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner. The
following sections provide detailed information covering device reset and initialization, register definition,
command descriptions, and device operation.
Tb
Ta
CK, CK#
Tc
Te
Td
((
))
((
))
((
))
((
))
((
))
((
))
Tf
Ti
Th
Tg
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Tj
Tk
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
))
VALID
((
))
((
))
((
))
((
))
VALID
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKSRX
VDD, VDDQ
T = 200s
RESET#
T = 500s
((
))
((
))
tIS
Tmin = 10ns
CKE
((
))
((
))
((
))
tDLLK
tMRD
tXPR
tIS
((
))
((
))
COMMAND
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
ODT
((
))
((
))
((
))
((
))
((
))
((
))
RTT
((
))
((
))
((
))
1)
((
))
((
))
tMRD
tMRD
MRS
((
))
((
))
MRS
((
))
((
))
MR2
((
))
((
))
MR3
((
))
((
))
MRS
MR1
tZQinit
tMOD
((
))
((
))
MRS
((
))
((
))
((
))
((
))
MR0
((
))
((
))
ZQCL
((
))
((
))
1)
tIS
tIS
((
((
((
((
))
))
))
))
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or( LOW
(
((
((
((
))
))
))
))
((
))
((
))
((
))
NOTE 1. From time point Td until Tk NOP or DES commands must be applied between MRS and ZQCL commands.
((
))
((
))
((
))
TIME BREAK
VALID
DONT CARE
Ta
CK, CK#
Tc
Te
Td
((
))
((
))
((
))
((
))
((
))
((
))
Tf
Ti
Th
Tg
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
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((
))
((
))
((
))
((
))
((
))
((
))
Tj
Tk
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
))
VALID
((
))
((
))
((
))
((
))
VALID
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKSRX
VDD, VDDQ
T = 100 ns
RESET#
T = 500s
((
))
((
))
Tmin = 10ns
CKE
((
))
((
))
tIS
((
))
tDLLK
tMRD
tXPR
tIS
((
))
((
))
COMMAND
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
ODT
((
))
((
))
((
))
((
))
((
))
((
))
RTT
((
))
((
))
((
))
1)
((
))
((
))
tMRD
tMRD
MRS
((
))
((
))
MRS
((
))
((
))
MR2
((
))
((
))
MR3
((
))
((
))
MRS
MR1
tZQinit
tMOD
((
))
((
))
MRS
((
))
((
))
((
))
((
))
MR0
((
))
((
))
ZQCL
((
))
((
))
1)
tIS
tIS
((
((
((
((
))
))
))
))
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
((
((
((
((
))
))
))
))
((
))
((
))
((
))
NOTE 1. From time point Td until Tk NOP or DES commands must be applied between MRS and ZQCL commands.
((
))
((
))
((
))
TIME BREAK
VALID
DONT CARE
For application flexibility, various functions, features, and modes are programmable in four Mode Registers,
provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register
Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, contents of Mode
Registers must be fully initialized and/or re-initialized, i.e., written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of
the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which means these commands
can be executed any time after power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode
register and is the minimum time required between two MRS commands shown in Figure 4
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Command
VALID
VALID
VALID
MRS
NOP/DES
NOP/DES
MRS
NOP/DES
NOP/DES
VALID
VALID
Address
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CK#
CK
CKE
Old Settings
Settings
Updating Settings
New Settings
tMRD
tMOD
VALID
ODTLoff + 1
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
((
))
((
))
Time Break
VALID
Dont Care
The MRS command to Non-MRS command delay, tMOD, is required for the DRAM to update the features,
except DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown in Figure 5
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Command
VALID
VALID
VALID
MRS
NOP/DES
NOP/DES
NOP/DES
NOP/DES
NOP/DES
VALID
VALID
Address
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CK#
CK
CKE
Old Settings
Settings
Updating Settings
New Settings
tMOD
VALID
ODTLoff + 1
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
((
))
((
))
Time Break
VALID
Dont Care
10
11
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls
burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge PowerDown, which include various vendor specific options to make DDR3 SDRAM useful for various applications.
The mode register is written by asserting low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to Figure 6.
BA2
BA1
0*1
A8
0*1
A7
A8
A7
DLL
TM
mode
A6
A5
A4
CAS Latency
A3
A3
A2
A1
A0
Mode Register 0
BL
RBT CL
Address Field
A1
A0
BL
8 (Fixed)
No
Normal
Nibble Sequential
Yes
Test
Interleave
BC4 (Fixed)
Reserved
A12
BA0
MR Select
MR0
A9
WR
DLL Reset
BA1
0
PPD
A10
MR1
A10
A9
WR(cycles)
16
*2
A6
A5
A4
A2
CAS Latency
Reserved
5*2
6*2
7*2
8*2
10
*2
10
11 (Optional for
DDR3-1600)
12
13
14
Reserved for 15
Reserved for 16
Reserved
Reserved
Reserved
MR2
MR3
12*2
14*2
*1: BA2 and A13~A15 are RFU and must be programmed to 0 during MRS.
*2: WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up
to the next integer: WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to
be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
*3: The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables
for each frequency
*4: The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timingtable.
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is
selected via bit A3 as shown in Figure 6. The ordering of accesses within a burst is determined by the burst
length, burst type, and the starting column address as shown in Table 2. The burst length is defined by bits
A0-A1. Burst length options include fixed BC4, fixed BL8, and on the fly which allows BC4 or BL8 to be
selected coincident with the registration of a Read or Write command via A12/BC#.
Table 2: Burst Type and Burst Order
Burst
Length
READ/WRI
TE
4
Chop
READ
Starting
Column
ADDRESS
(A2,A1,A0)
Notes
000
0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
1, 2, 3
001
1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T
1, 2, 3
010
2,3,0,1,T,T,T,T
2,3,0,1,T,T,T,T
1, 2, 3
011
3,0,1,2,T,T,T,T
3,2,1,0,T,T,T,T
1, 2, 3
100
4,5,6,7,T,T,T,T
4,5,6,7,T,T,T,T
1, 2, 3
101
5,6,7,4,T,T,T,T
5,4,7,6,T,T,T,T
1, 2, 3
110
6,7,4,5,T,T,T,T
6,7,4,5,T,T,T,T
1, 2, 3
111
7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
1, 2, 3
WRITE
0,V,V
0,1,2,3,X,X,X,X
0,1,2,3,X,X,X,X
1, 2, 4, 5
1,V,V
4,5,6,7,X,X,X,X
4,5,6,7,X,X,X,X
1, 2, 4, 5
8
READ
000
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2
001
1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
2
010
2,3,0,1,6,7,4,5
2,3,0,1,6,7,4,5
2
011
3,0,1,2,7,4,5,6
3,2,1,0,7,6,5,4
2
100
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
2
101
5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
2
110
6,7,4,5,2,3,0,1
6,7,4,5,2,3,0,1
2
111
7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
2
WRITE
V,V,V
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2, 4
NOTE 1 In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles
earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two
clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal write operation starts at
the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
NOTE 2 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
NOTE 3 T: Output driver for data and strobes are in high impedance.
NOTE 4 V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
NOTE 5 X: Dont Care.
13
The CAS Latency is defined by MR0 (bits A9-A11) as shown in Figure 9. CAS Latency is the delay, in clock
cycles, between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM
does not support any half-clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL)
+ CAS Latency (CL); RL = AL + CL. For more information on the supported CL and AL settings based on the
operating clock frequency, refer to Standard Speed Bins in each datasheet. For detailed Read operation,
refer to "2.13 READ Operation" on page 44.
The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values shown
in Figure 6. Programming bit A7 to a 1 places the DDR3 SDRAM into a test mode that is only used by the
DRAM Manufacturer and should NOT be used. No operations or functionality is specified if A7 = 1.
The DLL Reset bit is self-clearing, meaning that it returns back to the value of 0 after the DLL reset function
has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any time that the
DLL reset function is used, tDLLK must be met before any functions that require the DLL can be used (i.e.,
Read commands or ODT synchronous operations).
The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with
tRP to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing
tWR (in ns) by tCK (in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]).
The WR must be programmed to be equal to or larger than tWR(min).
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12 = 0), or
slow-exit, the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit
requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or fast-exit, the DLL is
maintained after entering precharge power-down and upon exiting power-down requires tXP to be met prior
to the next valid command.
14
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, Rtt_Nom
impedance, additive latency, Write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by
asserting low on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states
of address pins according to Figure 7.
BA2
BA1
0*1
A11
A10
0*1
A12 A11
A9
Disabled
Enabled
A7
A6
A5
A4
Rtt_Nom
A3
AL
A2
Rtt_Nom
A1
A0
D.I.C DLL
Address Field
Mode Register 1
Rtt_Nom*3
A9 A6 A2
TDQS enable
A8
A0 DLL Enable
0
Rtt_Nom disabled
RZQ/4
RZQ/2
RZQ/6
A7
RZQ/12*4
Disabled
RZQ/8*4
Enabled
Reserved
Reserved
A4
A3
Additive Latency
0 (AL disabled)
CL-1
CL-2
Reserved
A12
Qoff *2
Enable
Disable
A5 A1
RZQ/6
BA1
BA0
MR Select
RZQ/7
MR0
Reserved
MR1
Reserved
MR2
MR3
* 1 : BA2 and A8, A10, and A13 ~ A15 are RFU and must be programmed to 0 during MRS.
15
MR1 (A0 = 0), the DLL is automatically disabled when entering Self-Refresh operation and is automatically
re-enabled upon exit of Self-Refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK
clock cycles must occur before a Read or synchronous ODT command can be issued to allow time for the
internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may
result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation, except when RTT_WR is enabled
and the DLL is required for proper ODT operation. For more detailed information on DLL Disable operation
refer to "2.5 DLL-off Mode" on page 25.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2}
to {0,0,0} via a mode register set command during DLL-off mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR,
MR2 {A10, A9} = {0,0}, to disable Dynamic ODT externally.
The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as shown in
Figure 7.
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal
termination value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be programmed in MR2
to enable a unique RTT value when ODT is enabled during writes. The Rtt_WR value can be applied during
writes even when Rtt_Nom is disabled.
A3
AL
0
0
0 (AL Disabled)
0
1
CL - 1
1
0
CL - 2
1
1
Reserved
NOTE: AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register.
16
DM / TDQS
NU / TDQS
0 (TDQS Disabled)
DM
Hi-Z
1 (TDQS Enabled)
TDQS
TDQS#
17
BA1
0*1
A12 A11
0*1
A10
A9
A8
A7
A6
A5
A4
Rtt_WR
A3
A2
A1
A0
PASR
CWL
Address Field
Mode Register 2
A7
Self-Refresh Temperature
(SRT) Range
Full Array
A10 A9
A2 A1 A0
A6
Rtt_WR *2
A5 A4 A3
RZQ/4
RZQ/2
Reserved
BA1
BA0
MR Select
MR0
MR1
MR2
MR3
* 1 : BA2, A5, A8, A11 ~ A15 are RFU and must be programmed to 0 during MRS.
* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
During write leveling, Dynamic ODT is not available.
18
19
BA1
0*1
A12 A11
A10
A9
A8
A7
A6
A5
A4
A3
0*1
A2
A1
A0
MPR Operation
Address Field
Mode Register 3
MPR Address
A2
MPR
A1
A0
MPR location
Normal operation*3
Predefined pattern*2
RFU
RFU
RFU
BA1
BA0
MR Select
MR0
MR1
MR2
MR3
20
CKE
Abbrevia
Previous Current CS
tion
Cycle
Cycle
A0A9, Notes
A11
RAS
CAS
WE
L
L
L
X
H
L
L
L
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
L
L
H
H
X
H
L
L
H
L
L
L
L
BA
V
V
X
V
BA
V
BA
BA
BA
BA
BA
OP Code
V
V
V
V
V
V
X
X
X
V
V
V
V
L
V
V
H
V
Row Address (RA)
RFU
V
L
CA
RFU
L
L
CA
RFU
H
L
CA
RFU
V
H
CA
MRS
REF
SRE
SRX
H
H
H
L
H
H
L
H
PRE
PREA
ACT
WR
WRS4
WRS8
WRA
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
WRAS4
BA
RFU
CA
WRAS8
BA
RFU
CA
RD
RDS4
RDS8
RDA
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
BA
BA
BA
BA
RFU
RFU
RFU
RFU
V
L
H
V
L
L
L
H
CA
CA
CA
CA
RDAS4
BA
RFU
CA
RDAS8
BA
RFU
CA
NOP
DES
PDE
H
H
H
H
H
L
PDX
ZQ Calibration Long
ZQ Calibration Short
ZQCL
ZQCS
H
H
H
H
L
H
L
H
L
H
L
L
H
X
H
X
H
X
H
H
H
X
H
X
H
X
H
H
H
X
H
X
H
X
L
L
V
X
V
X
V
X
X
X
V
X
V
X
V
X
X
X
V
X
V
X
V
X
X
X
V
X
V
X
V
X
H
L
V
X
V
X
V
X
X
X
V
V
X
V
V
V
7,9,12
7,8,9,
12
10
11
6,12
6,12
21
CKE
Abbrevia
Previous Current CS
tion
Cycle
Cycle
RAS
CAS
WE
A0A9, Notes
A11
NOTE 1 All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of
the clock. The MSB of BA, RA and CA are device density and configuration dependant.
NOTE 2 RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH
during any function.
NOTE 3 Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended)
Mode Register.
NOTE 4 V means H or L (but a defined logic level) and X means either defined or undefined (like floating) logic
level.
NOTE 5 Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
NOTE 6 The Power Down Mode does not perform any refresh operation.
NOTE 7 The state of ODT does not affect the states described in this table. The ODT function is not available during Self
Refresh.
NOTE 8 Self Refresh Exit is asynchronous.
NOTE 9 VREF(Both VrefDQ and VrefCA) must be maintained during Self Refresh operation. VrefDQ supply may be
turned OFF and VREFDQ may take any value between VSS and VDD during Self Refresh operation, provided
that VrefDQ is valid and stable prior to CKE going back High and that first Write operation or first Write Leveling
Activity may not occur earlier than 512 nCK after exit from Self Refresh.
NOTE 10 The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The
purpose of the No Operation command (NOP) is to prevent the DDR3 SDRAM from registerng any unwanted
commands between operations. A No Operation command will not terminate a pervious operation that is still
executing, such as a burst read or write cycle.
NOTE 11 The Deselect command performs the same function as No Operation command.
NOTE 12 Refer to the CKE Truth Table for more detail with CKE transition.
22
State2
Command (N)3
Previous Cycle1 Current Cycle1 RAS#, CAS#, WE#, CS#
(N-1)
(N)
L
H
L
H
Notes
Maintain Power-Down
14, 15
Power-Down Exit
11,14
Maintain Self-Refresh
15,16
Self-Refresh
Self-Refresh Exit
8,12,16
Active Power-Down
Bank(s) Active
H
L
DESELECT or NOP
11,13,14
Entry
Reading
H
L
DESELECT or NOP
Power-Down Entry 11,13,14,17
Writing
H
L
DESELECT or NOP
Power-Down Entry 11,13,14,17
Precharging
H
L
DESELECT or NOP
Power-Down Entry 11,13,14,17
Precharge PowerRefreshing
H
L
DESELECT or NOP
11
Down Entry
Precharge PowerH
L
DESELECT or NOP
11,13,14,18
Down Entry
All Banks Idle
H
L
REFRESH
Self-Refresh
9,13,18
For more details with all signals See "2.1 Command Truth Table" on page 21.
10
NOTE 1 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock
edge.
NOTE 2 Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
NOTE 3 COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND
(N), ODT is not included here.
NOTE 4 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this
document.
NOTE 5 The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh.
NOTE 6 CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must
remain at the valid input level the entire time it takes to achieve the tCKEmin clocks of registeration. Thus,
after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKEmin + tIH.
NOTE 7 DESELECT and NOP are defined in the Command Truth Table.
NOTE 8 On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands may be issued only after tXSDLL is satisfied.
NOTE 9 Self-Refresh mode can only be entered from the All Banks Idle state.
NOTE 10 Must be a legal command as defined in the Command Truth Table.
NOTE 11 Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
NOTE 12 Valid commands for Self-Refresh Exit are NOP and DESELECT only.
NOTE 13 Self-Refresh can not be entered during Read or Write operations. For a detailed list of restrictions See
"2.16 Self-Refresh Operation" on page 64 and See "2.17 Power-Down Modes" on page 66.
Power-Down
L
L
L
L
Action (N)3
X
DESELECT or NOP
X
DESELECT or NOP
23
24
T1
T2
T3
T4
T5
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank,
Col b
CK#
T6
T7
T8
T9
NOP
NOP
NOP
NOP
T10
CK
NOP
RL (DLL_on) = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQS, DQS# (DLL_on)
DIN
b+1
DIN
b
DQ (DLL_on)
RL (DLL_off) = AL + (CL - 1) = 5
DIN
b+2
DIN
b+3
DIN
b+5
DIN
b+4
DIN
b+6
DIN
b+7
tDQSCK(DLL_off)_min
DQ (DLL_off)
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
DIN
b+5
DIN
b+6
tDQSCK(DLL_off)_max
DQS, DQS# (DLL_off)
DIN
b
DQ (DLL_off)
DIN
b+1
DIN
b+2
Note: The tDQSCK is used here for DQS, DQS# and DQ to have a simplified diagram; the DLL_off shift will affect
both timings in the same way and the skew between all DQ and DQS, DQS# signals will still be tDQSQ.
DIN
b+3
DIN
b+4
TRANSITIONING DATA
DIN
b+7
DONT CARE
25
CK#
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
CK
CKE
VALID (8)
COMMAND
MRS (2)
(1)
NOP
SRE (3)
tMOD
SRX (6)
NOP
tCKSRE
(4)
tCKSRX (5)
NOP
MRS (7)
tXS
NOP
VALID (8)
tMOD
tCKESR
ODT
VALID (8)
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
((
))
TIME BREAK
((
))
DONT CARE
4. Change Frequency
5. Clock must be stable tCKSRX
6. Exit SR
7. Update Mode registers with DLL off parameters setting
8. Any valid command
26
CK#
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf1
Tg0
Th0
CK
CKE
VALID
tDLLK
NOP
COMMAND
(1)
SRE (2)
ODTLoff + 1 x tCK
NOP
tCKSRE
tCKSRX (4)
MRS (7)
MRS (6)
SRX (5)
tMRD
tXS
MRS (8)
VALID (9)
tMRD
(3)
tCKESR
ODT
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
((
))
((
))
TIME BREAK
DONT CARE
27
28
T1
T2
Tb0
Tc1
Tc0
Td0
Td1
Te0
Te1
CK#
CK
tCH
tCL
tCH
tCK
tCK
tCKSRX
tIS
tCKE
tIH
CKE
tIS
tCPDED
COMMAND
tCL
tCH
tCK
tCKSRE
tIH
tCL
tCH
tCL
tCK
NOP
NOP
NOP
NOP
NOP
ADDR
MRS
NOP
VALID
DLL RESET
tAOFPD / tAOF
VALID
tIH
tIS
tXP
ODT
DQS, DQS#
High-Z
DQ
High-Z
DM
Enter PRECHARGE
Power-Down Mode
Frequency
Change
tDLLK
Exit PRECHARGE
Power-Down Mode
Indicates a break in
time scale
DONT CARE
NOTES: 1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down
2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements
3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state, as shown in Figure 13. If the RTT_NOM feature was
disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal
can be registered either LOW or HIGH in this case.
29
Source
T1
T2
T3
T5
T4
T6
T7
CK#
CK
diff_DQS
Destination
CK#
T0
Tn
T1
T2
T3
T5
T4
T6
CK
diff_DQS
DQ
0 or 1
DQ
0 or 1
30
MR1
Enable
Disable
A7
A12
DQS/DQS# termination
DQs termination
De-asserted
Off
Off
NOTE:
Asserted
On
Off
In Write Leveling Mode with its output buffer disabled (MR1[bit7] = 1 with
MR1[bit12] = 1) all RTT_Nom settings are allowed; in Write Leveling Mode with its
output buffer enabled (MR1[bit7] = 1 with MR1[bit12] = 0) only RTT_Nom settings
of RZQ/2, RZQ/4 and RZQ/6 are allowed.
The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write
leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or DESELECT commands are allowed, as well as an MRS command to change Qoff bit (MR1[A12]) and an MRS command to exit write leveling (MR1[A7]). Upon exiting write leveling mode, the MRS command performing the
exit (MR1[A7]=0) may also change MR1 bits of A12-A11, A9, A6-A5, and A2-A1. Since the controller levels
one rank at a time, the output of other ranks must be disabled by setting MR1 bit A12 to 1. The Controller may
assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal.
The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has
applied on-die termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS,
DQS# edge which is used by the DRAM to sample CK - CK# driven from controller. tWLMRD(max) timing is
controller dependent.
DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on all the DQ bits
asynchronously after tWLO timing. Either one or all data bits ("prime DQ bit(s)") provide the leveling feedback. The DRAM's remaining DQ bits are driven Low statically after the first sampling procedure. There is a
DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the
transition of the earliest DQ bit to the corresponding transition of the latest DQ bit. There are no read strobes
(DQS/DQS#) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS - DQS# delay setting and launches the next DQS/DQS# pulse after some time, which is controller
dependent. Once a 0 to 1 transition is detected, the controller locks DQS - DQS# delay setting and write leveling is achieved for the device. Figure 15 describes the timing diagram and parameters for the overall Write
Leveling procedure.
31
T1
T2
tWLH
tWLH
tWLS
tWLS
(5)
CK#
CK
(2)
COMMAND
MRS
(3)
NOP
NOP
NOP
NOP NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tMOD
ODT
tWLDQSEN
diff_DQS (4)
tWLMRD
tWLO
tWLO
(1)
tWLO
tWLMRD
tWLOE
tWLO
tWLO
(1)
(1)
Early Prime DQs
tWLOE
tWLO
tWLOE
tWLO
((
))
((
))
TIME BREAK
DONT CARE
NOTES: 1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low,
as shown in above Figure, and maintained at this state through out the leveling procedure.
2. MRS: Load MR1 to enter write leveling mode.
3. NOP: NOP or Deselect.
4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line.
5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent.
Figure 15. Timing details of Write leveling sequence [DQS-DQS is capturing CK-CK low at
T1 and CK-CK high at T2
32
T1
T2
Ta0
NOP
NOP
NOP
NOP
Tb0
Tc0
Tc1
NOP NOP
NOP
NOP
Tc2
Td0
Td1
Te0
Te1
CK#
CK
COMMAND
NOP
NOP
MRS
NOP
VALID
NOP
VALID
tMRD
ADDRESS
VALID
MR1
NOP
tIS
VALID
tMOD
ODT
ODTLoff
RTT_DQS_DQS#
tAOFmin
RTT_NOM
tAOFmax
DQS_DQS#
RTT_DQ
(1)
DQ
tWLO
result = 1
CK = 0
NOTES: 1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS, DQS# signals capturing CK high just after the T0 state.
2. Refer to Figure 15 for specific tWLO timing.
TRANSITIONING
((
))
TIME BREAK
((
))
DONT CARE
33
ASR
Bits
Description
MR2 (A6)
SRT
MR2 (A7)
34
MR2
A[7]
Self-refresh rate appropriate for either the Nor- Normal and Extended (0 - 95 oC)
mal or Extended Temperature Ranges. The
DRAM must support Extended Temperature
Range. The value of the SRT bit can effect selfrefresh power consumption, please refer to the
IDD table for details.
ASR enabled (for devices supporting ASR and Normal and Extended (0 - 95 oC)
Extended Temperature Range). Self-Refresh
power consumption is temperature dependent
Illegal
Self-Refresh operation
35
Memory Core
(all banks precharged)
MR3 [A2]
Multipurpose register
Pre-defined data for Reads
MR3 A[1:0]
Function
MPR
MPR-Loc
0b
dont care
(0b or 1b)
1b
See Table 13
36
*) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of
the selected MPR agent.
37
1b
1b
1b
1b
MR3
A[1:0]
00b
01b
10b
11b
NOTE:
Function
Read Predefined
Pattern for System
Calibration
RFU
RFU
RFU
Burst
Length
Read
Address
A[2:0]
BL8
000b
BC4
000b
BC4
100b
BL8
000b
BC4
000b
BC4
100b
BL8
000b
BC4
000b
BC4
100b
BL8
000b
BC4
000b
BC4
100b
Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to
MSB of the selected MPR agent.
T0
Ta
Tb0
Tb1
Tc0
Tc1
READ
NOP
NOP
NOP
Tc2
Tc3
Tc4
Tc5
Tc6
NOP
NOP
NOP
NOP
NOP
Tc7
Tc8
MRS
NOP
Tc9
Td
CK
COMMAND
MRS
PREA
tRP
(1)
tMOD
NOP
VALID
tMOD
tMPRR
BA
VALID
A[1:0]
VALID
A[2]
A[9:3]
00
VALID
00
VALID
A[11]
VALID
A12, BC#
VALID1
A[15:13]
VALID
(2)
0
(2)
A10, AP
RL
DQS, DQS#
DQ
NOTES:
((
))
((
))
TIME BREAK
DONT CARE
Figure 18. MPR Readout of predefined pattern, BL8 fixed burst order, single readout
39
CK#
T0
Ta
Tb
Tc0
Tc1
Tc2
READ
(1)
NOP
NOP
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tc10
Td
CK
COMMAND
MRS
PREA
tRP
tMOD
BA
READ
(1)
tCCD
VALID
tMOD
VALID
A[1:0]
A[2]
0
(2)
(2)
00
VALID
VALID
00
VALID
VALID
A[11]
VALID
VALID
A12,BC#
VALID
VALID
(1)
VALID
(2)
A[9:3]
A10AP
(1)
0
A[15:13]
VALID
VALID
MRS
tMPRR
VALID
(2)
0
RL
DQS, DQS#
RL
DQ
NOTES:
((
))
((
))
TIME BREAK
DONT CARE
Figure 19. MPR Readout of predefined pattern, BL8 fixed burst order, back-to-back readout
40
T0
CK#
Ta
Tb
Tc0
Tc1
Tc2
READ
(1)
NOP
NOP
Tc3
Tc4
Tc5
Tc6
Tc7
NOP
NOP
NOP
NOP
NOP
Tc8
Tc9
MRS
NOP
Tc10
Td
NOP
VALID
CK
COMMAND
MRS
PREA
tRF
tMOD
READ
(1)
tCCD
tMOD
tMPRR
BA
VALID
VALID
A[1:0]
VALID
(2)
(2)
(3)
(4)
A[2]
00
VALID
VALID
00
VALID
VALID
A[11]
VALID
VALID
A12,BC#
VALID
VALID
(1)
(1)
VALID
VALID
A[9:3]
A10AP
A[15:13]
RL
DQS, DQS#
RL
DQ
NOTES:
((
))
((
))
TIME BREAK
DONT CARE
Figure 20. MPR Readout of predefined pattern, BC4, lower nibble then upper nibble
41
CK#
T0
Ta
Tb
Tc0
Tc1
Tc2
READ
(1)
NOP
NOP
Tc3
Tc4
Tc5
Tc6
Tc7
NOP
NOP
NOP
NOP
NOP
Tc8
Tc9
MRS
NOP
Tc10
Td
NOP
VALID
CK
COMMAND
MRS
PREA
tRF
tMOD
READ
(1)
tCCD
tMOD
tMPRR
BA
VALID
VALID
A[1:0]
VALID
(2)
1
A[2]
1
(4)
(2)
0
(3)
00
VALID
VALID
00
VALID
VALID
A[11]
VALID
VALID
A12,BC#
VALID
VALID
(1)
(1)
VALID
VALID
A[9:3]
A10AP
A[15:13]
RL
DQS, DQS#
RL
DQ
NOTES:
((
))
((
))
TIME BREAK
DONT CARE
Figure 21. MPR Readout of predefined pattern, BC4, upper nibble then lower nibble
42
43
T1
T2
T3
T4
T5
COMMAND3
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS4
Bank,
Col n
T6
T7
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
CK#
CK
tRPRE
tRPST
DQS, DQS#
DOUT
n
DQ2
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
n+4
DOUT
n+5
DOUT
n+7
DOUT
n+6
CL = 5
RL = AL + CL
NOTES: 1. BL8, RL = 5, AL = 0, CL = 5.
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
TRANSITIONING DATA
DONT CARE
T1
T2
T3
T4
T5
COMMAND3
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS4
Bank,
Col n
T6
T7
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
CK#
CK
tRPRE
DQS, DQS#
DOUT
n
DQ2
AL = 4
DOUT
n+1
DOUT
n+2
CL = 5
RL = AL + CL
TRANSITIONING DATA
DONT CARE
44
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK#.
tDQSCK is the actual position of a rising strobe edge relative to CK, CK#.
tQSH describes the DQS, DQS# differential output high time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
CK
tDQSCK,MIN
tDQSCK,MIN
t DQSCK,MAX
tDQSCK,MAX
Rising Strobe
Region
Rising Strobe
Region
t DQSCK
tDQSCK
tQSH
tQSL
t QH
t QH
DQS
DQS
tDQSQ
tDQSQ
Associated
DQ Pins
45
CLK/CLK#
tDQSCK (min)
tDQSCK (min)
tQSH
tLZ(DQS)min
tDQSCK (min)
tQSH
tQSL
tQSL
tDQSCK (min)
tQSH
tHZ(DQS)min
tQSL
DQS,DQS#
Early Strobe
tRPRE
tRPST
Bit 0
Bit 1
Bit 2
tDQSCK (max)
tLZ(DQS)max
Bit 3
Bit 4
tDQSCK (max)
Bit 5
Bit 6
tDQSCK (max)
Bit 7
tHZ(DQS)max
tDQSCK (max)
tRPST
DQS,DQS#
Late Strobe
tQSH
tRPRE
Bit 0
NOTES:
tQSH
tQSL
Bit 1
Bit 2
tQSL
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe edge can vary between tDQSCK(min) and tDQSCK(max).
2. Notwithstanding note 1, a rising strobe edge with tDQSCK(max) at T(n) can not be immediately followed by a rising strobe edge with tDQSCK(min) at T(n+1). This is because other timing
relationships (tQSH, tQSL) exist:
if tDQSCK(n+1) < 0:
tDQSCK(n) < 1.0 tCK - (tQSHmin + tQSLmin) - | tDQSCK(n+1) |
3. The DQS, DQS# differential output high time is defined by tQSH and the DQS, DQS# differential output low time is defined by tQSL.
4. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max are not tied to tDQSCKmax (late strobe case).
5. The minimum pulse width of read preamble is defined by tRPRE(min).
6. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.
7. The minimum pulse width of read postamble is defined by tRPST(min).
8. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
46
T1
T2
T3
T4
T5
READ
NOP
NOP
NOP
NOP
NOP
T6
T7
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
CK#
CK
COMMAND3
RL = AL + CL
ADDRESS 4
Bank,
Col n
tDQSQ (max)
tRPST
tDQSQ (max)
DQS, DQS#
tRPRE
tQH
tQH
DOUT
n
DOUT
n
DOUT
n+1
DOUT
n+1
DOUT
n+1
DOUT
n+2
DOUT
n+2
DOUT
n+2
DOUT
n+4
DOUT
n+3
DOUT
n+3
DOUT
n+4
DOUT
n+3
DOUT
n+4
DOUT
n+5
DOUT
n+5
DOUT
n+6
DOUT
n+6
DOUT
n+5
NOTES: 1. BL = 8, RL = 5 (AL = 0, CL = 5)
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
5. Output timings are referenced to VDDQ/2, and DLL on for locking.
6. tDQSQ defines the skew between DQS,DQS# to Data and does not define DQS,DQS# to Clock.
7. Early Data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst.
DOUT
n+6
DOUT
n+7
DOUT
n+7
DOUT
n+7
TRANSITIONING DATA
DONT CARE
47
CK
CK
CK
CK
tLZ
tHZ
VTT + 2x mV
VOH - x mV
VTT + x mV
VOH - 2x mV
tLZ(DQS), tLZ(DQ)
VTT - x mV
VTT - 2x mV
tHZ(DQS), tHZ(DQ)
T1
T2
T2
T1
VOL + 2x mV
VOL + x mV
Figure 27. tLZ and tHZ method for calculating transitions and endpoints
48
tB
DQS
VTT
tD
VTT
DQS
Single ended signal, provided
as background information
t1
tRPRE_begin
tRPRE
DQS - DQS
t2
tRPRE_end
DQS
VTT
tB
tD
DQS
VTT
tRPST
DQS - DQS
Resulting differential signal,
relevant for tRPST
specification
0
t1
tRPST_begin
t2
tRPST_end
TD_TRPST_DEF
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
NOP
CK#
CK
COMMAND3
NOP
READ
READ
NOP
NOP
tCCD
Bank,
Col n
ADDRESS4
Bank,
Col b
tRPRE
tRPST
DQS, DQS#
DOUT
n
DQ2
RL = 5
DOUT
n+1
DOUT
n+2
DOUT
n+4
DOUT
n+3
DOUT
n+5
DOUT
n+6
DOUT
b
DOUT
n+7
DOUT
b+1
DOUT
b+2
DOUT
b+4
DOUT
b+3
DOUT
b+5
DOUT
b+6
DOUT
b+7
RL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
BL8, RL = 5 (CL = 5, AL = 0)
READ
NOP
NOP
NOP
NOP
CK#
CK
3
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
TCCD = 5
Address 4
Bank,
Col n
Bank,
Col b
tRPST
tRPRE
DQS, DQS#
DQ 2
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
n+4
RL = 5
DOUT
n+5
DOUT
n+6
DOUT
n+7
DOUT
b
DOUT
b+1
DOUT
b+2
DOUT
b+3
DOUT
b+4
DOUT
b+5
DOUT
b+6
Transitioning Data
NOTE: 1.
2.
3.
4.
5.
DOUT
b+7
RL = 5
Dont Care
CK#
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
NOP
CK
COMMAND3
READ
NOP
READ
NOP
NOP
tCCD
ADDRESS4
Bank,
Col n
Bank,
Col b
tRPST
tRPRE
tRPST
tRPRE
DQS, DQS#
DQ2
RL = 5
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
DOUT
b+1
DOUT
b+2
DOUT
b+3
RL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
BC4, RL = 5 (CL = 5, AL = 0)
50
T0
T1
T2
T3
T4
T5
NOP
NOP
NOP
NOP
NOP
T6
T7
T8
T9
WRITE
NOP
NOP
NOP
T10
T11
T12
T13
T14
T15
NOP
NOP
NOP
CK#
CK
COMMAND3
READ
NOP
NOP
NOP
ADDRESS4
tWR
4 clocks
tWTR
Bank,
Col n
Bank,
Col b
tRPRE
tRPST
tWPRE
tWPST
DQS, DQS#
DOUT
n
DQ2
DOUT
n+1
DOUT
n+2
DOUT
n+4
DOUT
n+3
DOUT
n+5
DOUT
n+6
DIN
b
DOUT
n+7
RL = 5
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DIN
b+7
WL = 5
DONT CARE
T1
T2
T3
NOP
NOP
NOP
T4
T5
T6
WRITE
NOP
NOP
T7
T8
T9
NOP
NOP
NOP
T10
T11
T12
T13
T14
T15
NOP
NOP
NOP
NOP
CK#
CK
COMMAND3
READ
NOP
NOP
tWR
4 clocks
tWTR
ADDRESS4
Bank,
Col n
Bank,
Col b
tRPRE
tRPST
tWPRE
tWPST
DQS, DQS#
DOUT
n
DQ2
DOUT
n+1
DOUT
n+2
DIN
b
DOUT
n+3
RL = 5
DIN
b+1
DIN
b+2
DIN
b+3
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
NOP
CK#
CK
COMMAND3
READ
NOP
READ
NOP
NOP
tCCD
ADDRESS4
Bank,
Col n
Bank,
Col b
tRPRE
tRPST
DQS, DQS#
DOUT
n
DQ2
RL = 5
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
n+4
DOUT
n+5
DOUT
n+6
DOUT
n+7
DOUT
b
DOUT
b+1
DOUT
b+2
DOUT
b+3
RL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
RL = 5 (CL = 5, AL = 0)
51
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
NOP
CK#
CK
COMMAND3
READ
NOP
READ
NOP
NOP
tCCD
ADDRESS4
Bank,
Col n
Bank,
Col b
tRPRE
tRPRE
tRPST
tRPST
DQS, DQS#
DOUT
n+1
DOUT
n
DQ2
RL = 5
DOUT
n+2
DOUT
b
DOUT
n+3
DOUT
b+1
DOUT
b+2
DOUT
b+3
DOUT
b+4
DOUT
b+ 5
DOUT
b+ 6
DOUT
b+ 7
RL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
RL = 5 (CL = 5, AL = 0)
T0
T1
T2
T3
NOP
NOP
NOP
T4
T5
WRITE
NOP
T6
T7
T8
T9
NOP
NOP
NOP
T10
T11
T12
T13
T14
T15
NOP
NOP
NOP
NOP
CK#
CK
COMMAND3
READ
NOP
NOP
NOP
tWR
4 clocks
tWTR
ADDRESS4
Bank,
Col n
Bank,
Col b
tRPRE
tRPST
tWPRE
tWPST
DQS, DQS#
DOUT
n
DQ2
DOUT
n+1
DOUT
n+2
RL = 5
DIN
b
DOUT
n+3
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
T1
T2
T3
T4
T5
NOP
NOP
NOP
NOP
NOP
T6
T7
T8
T9
WRITE
NOP
NOP
NOP
T10
T11
T12
T13
T14
T15
NOP
NOP
NOP
CK#
CK
COMMAND3
READ
NOP
NOP
NOP
ADDRESS4
tWR
4 clocks
tWTR
Bank,
Col n
Bank,
Col b
tRPRE
tRPST
tWPRE
tWPST
DQS, DQS#
DOUT
n
DQ2
DOUT
n+1
DOUT
n+2
RL = 5
DOUT
n+3
DOUT
n+4
DOUT
n+5
DOUT
n+6
DOUT
n+7
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
52
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
T5
T6
T7
T8
T9
PRE
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
T15
ACT
NOP
NOP
NOP
NOP
NOP
CK
Command
NOP
Bank a,
Col n
Address
Bank a,
(or all)
Bank a,
Row b
tRP
tRTP
RL = AL + CL
DQS, DQS#
BL4 Operation:
DQ
DO
n
DO
n+1
DO
n+2
DO
n
DO
n+1
DO
n+2
DO
n+3
BL8 Operation:
DQS, DQS#
DQ
NOTE: 1.
2.
3.
4.
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
RL = 5 (CL = 5, AL = 0)
DOUT n = data-out from column n.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
The example assumes tRAS.MIN is satisfied at Precharge command time (T5) and that tRC.MIN is satisfied at the next Active command time (T10).
Transitioning Data
Dont Care
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
NOP
NOP
T15
CK
Command
NOP
PRE
Bank a,
Col n
Address
Bank a,
(or all)
tRP
tRTP
AL = CL - 2 = 3
DQS, DQS#
ACT
Bank a,
Row b
CL = 5
BL4 Operation:
DQ
DO
n
DO
n+1
DO
n+2
DO
n
DO
n+1
DO
n+2
DO
n+3
BL8 Operation:
DQS, DQS#
DQ
NOTE: 1.
2.
3.
4.
RL = 8 (CL = 5, AL = CL - 2)
DOUT n = data-out from column n.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
The example assumes tRAS.MIN is satisfied at Precharge command time (T10) and that tRC.MIN is satisfied at the next Active command time (T15).
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
Transitioning Data
Dont Care
53
54
T1
T2
T3
T4
T5
T6
T7
T8
T9
COMMAND3
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS4
Bank,
Col n
T10
CK#
CK
NOP
WL = AL + CWL
tDQSS tDSH
tDSH
tDSH
tDSH
tWPST(min)
tWPRE(min)
tDQSS(min)
DQS, DQS#
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL(min)
tDQSH(min)
tDSS
tDSS
DIN
n
DQ2
DIN
n+1
tDSS
DIN
n+2
tDSS
DIN
n+4
DIN
n+3
DIN
n+5
tDSS
DIN
n+6
DIN
n+7
DM
tDSH
tDSH
tDSH
tDSH
tWPST(min)
tWPRE(min)
tDQSS(nominal)
DQS, DQS#
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL(min)
tDQSH(min)
tDSS
tDSS
DIN
n
DQ2
DIN
n+1
tDSS
DIN
n+2
tDSS
DIN
n+4
DIN
n+3
DIN
n+5
tDSS
DIN
n+6
DIN
n+7
DM
tDQSS
tDSH
tDSH
tDSH
tDSH
tWPRE(min)
tDQSS(max)
tWPST(min)
DQS, DQS#
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL
tDQSH
tDQSL(min)
tDQSH(min)
tDSS
tDSS
DIN
n
DQ2
DIN
n+1
tDSS
DIN
n+2
DIN
n+3
tDSS
DIN
n+4
DIN
n+5
tDSS
DIN
n+6
DIN
n+7
DM
NOTE: 1.
2.
3.
4.
5.
TRANSITIONING DATA
DONT CARE
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
tDQSS must be met at each rising clock edge.
55
DQS - DQS
0V
tWPRE
t2
tWPRE_end
tWPST
DQS - DQS
Resulting differential signal,
relevant for tWPST
specification
0V
t1
tWPST_begin
t2
tWPST_end
56
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
COMMAND3
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS4
Bank,
Col n
T10
CK#
CK
NOP
WL = AL + CWL
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
NOTE: 1.
2.
3.
4.
DIN
n+1
DIN
n+2
DIN
n+3
DIN
n+4
DIN
n+5
DIN
n+6
DIN
n+7
BL8, WL = 5; AL = 0, CWL = 5.
TRANSITIONING DATA
DONT CARE
T1
T2
T3
T4
T5
T6
T7
T8
T9
COMMAND3
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS4
Bank,
Col n
T10
CK#
CK
NOP
tWPRE
DQS, DQS#
DIN
n
DQ2
AL = 4
DIN
n+1
DIN
n+2
DIN
n+3
CWL = 5
WL = AL + CWL
NOTE: 1.
2.
3.
4.
TRANSITIONING DATA
DONT CARE
57
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T9
Tn
CK#
CK
COMMAND3
WRITE
NOP
READ
tWTR5
ADDRESS4
Bank,
Col n
Bank,
Col b
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+3
RL = 5
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
5.
DONT CARE
BC4, WL = 5, RL = 5.
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T9
Tn
NOP
PRE
CK#
CK
COMMAND3
WRITE
tWR5
ADDRESS4
Bank,
Col n
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+3
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
5.
DONT CARE
BC4, WL = 5, RL = 5.
DIN n = data-in from column n; DOUT b = data-out from column b.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0.
The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7.
tWR specifies the last burst write cycle until the precharge command can be issued to the same bank .
58
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
T7
T8
T9
NOP
NOP
NOP
T10
T11
Ta0
Ta1
T14
PRE
NOP
NOP
CK#
CK
COMMAND3
WRITE
NOP
4 clocks
ADDRESS4
NOP
tWR5
Bank,
Col n
VALID
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+3
WL = 5
NOTE: 1.
2.
3.
4.
5.
((
))
((
))
Dont Care
Time Break
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
NOP
CK#
CK
COMMAND3
WRITE
NOP
NOP
WRITE
NOP
NOP
4 clocks
tCCD
tWR
tWTR
ADDRESS4
Bank,
Col n
Bank,
Col b
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+3
DIN
n+4
DIN
n+5
DIN
n+6
DIN
n+7
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
WL = 5
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
5.
DONT CARE
BL8, WL = 5 (CWL = 5, AL = 0)
DIN n (or b) = data-in from column n (or column b).
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0 and T4.
The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T13.
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
NOP
NOP
T14
CK#
CK
COMMAND3
WRITE
NOP
WRITE
NOP
NOP
4 clocks
tCCD
NOP
tWR
tWTR
ADDRESS4
Bank,
Col n
Bank,
Col b
tWPRE
tWPST
tWPST
tWPRE
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
WL = 5
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
5.
DONT CARE
BC4, WL = 5 (CWL = 5, AL = 0)
DIN n (or b) = data-in from column n (or column b).
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0 and T4.
The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge at T13 (4 clocks from T9).
59
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
READ
NOP
CK#
CK
COMMAND3
WRITE
NOP
tWTR
ADDRESS4
Bank,
Col n
Bank,
Col b
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+4
DIN
n+3
DIN
n+5
DIN
n+6
DIN
n+7
WL = 5
RL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
T7
T8
T9
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
READ
NOP
CK#
CK
COMMAND3
WRITE
NOP
4 clocks
ADDRESS4
tWTR
Bank,
Col n
Bank,
Col b
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+3
WL = 5
RL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T9
T10
T11
T12
T13
T14
READ
NOP
NOP
NOP
CK#
CK
COMMAND3
WRITE
NOP
NOP
tWTR
ADDRESS4
Bank,
Col n
Bank,
Col b
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+3
WL = 5
RL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
60
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
T8
T9
WRITE
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
NOP
NOP
T14
CK#
CK
COMMAND3
WRITE
NOP
NOP
NOP
4 clocks
tCCD
NOP
tWR
tWTR
ADDRESS4
Bank,
Col n
Bank,
Col b
tWPRE
tWPST
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+4
DIN
n+3
DIN
n+5
DIN
n+6
DIN
n+7
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
WL = 5
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
WL = 5 (CWL = 5, AL = 0)
DIN n (or b) = data-in from column n (or column b).
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T4.
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
T10
T11
T12
T13
T14
NOP
NOP
NOP
CK#
CK
COMMAND3
WRITE
NOP
WRITE
NOP
NOP
4 clocks
tCCD
tWR
tWTR
ADDRESS4
Bank,
Col n
Bank,
Col b
tWPRE
tWPST
tWPST
tWPRE
DQS, DQS#
DIN
n
DQ2
DIN
n+1
DIN
n+2
DIN
n+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
WL = 5
WL = 5
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
DONT CARE
WL = 5 (CWL = 5, AL = 0)
DIN n (or b) = data-in from column n (or column b).
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during WRITE command at T4.
61
T0
T1
REF
NOP
Ta0
Ta1
REF
NOP
Tb0
Tb1
Tb2
Tb3
VALID
VALID
VALID
VALID
Tc0
Tc1
Tc2
Tc3
VALID
VALID
VALID
CK
COMMAND
tRFC
NOP
NOP
VALID
REF
tRFC(min)
tREFI (max. 9 x tREFI)
NOTES:
1. Only NOP/DES commands allowed after Refresh command registered until tRFC(min) expires.
((
))
2. Time interval between two Refresh commands may be extended to a maximum of 9 x tREFI.
((
))
TIME BREAK
DONT CARE
62
63
64
T0
T1
Ta0
T2
Tb0
Tc0
Tc1
Td0
Te0
Tf0
VALID
VALID
CK#
CK
tCKSRE
tIS
tCKSRX
tCPDED
CKE
tCKESR
tIS
VALID
ODT
ODTL
COMMAND
NOP
SRE
NOP
SRX
NOP (1)
ADDR
VALID (2)
VALID (3)
VALID
VALID
tXS
tRP
tXSDLL
DONT CARE
TIME BREAK
65
MRS bit
A12
DLL
PD Exit
Active
(A bank or more Open)
Dont Care
On
Fast
Precharged
(All banks Precharged)
Off
Slow
Precharged
(All banks Precharged)
On
Fast
Relevant Parameters
tXP to any valid command
tXP to any valid command. Since it is in precharge state,
commands here will be ACT, REF, MRS, PRE or PREA.
tXPDLL to commands that need the DLL to operate, such
as RD, RDA or ODT control line.
tXP to any valid command.
Also, the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled
during precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low,
RESET# high, and a stable clock signal must be maintained at the inputs of the DDR3 SDRAM, and ODT
should be in a valid state, but all other input signals are Dont Care. (If RESET# goes low during PowerDown, the DRAM will be out of PD mode and into reset state.) CKE low must be maintained until tCKE has
been satisfied. Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect
command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be
applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is
defined in the AC specifications table in Section 8.
Active Power Down Entry and Exit timing diagram example is shown in Figure 60. Timing Diagrams for CKE
with PD Entry, PD Exit with Read and Read with Auto Precharge, Write, Write with Auto Precharge, Activate,
Precharge, Refresh, and MRS are shown in Figure 61 through Figure 69. Additional clarifications are shown
in Figure 70 through Figure 72
66
T0
T1
T2
VALID
NOP
NOP
Ta0
Tb0
Ta1
Tb1
Tc0
CK#
CK
COMMAND
NOP
NOP
NOP
VALID
VALID
VALID
tPD
tIS
CKE
tIH
tCKE
tIH
ADDRESS
tIS
VALID
VALID
tCPDED
tXP
Exit
Power-Down
Mode
Enter
Power-Down
Mode
((
))
((
))
TIME BREAK
DONT CARE
Note: VALID command at T0 is ACT, NOP, DES or PRE with still one bank remaining
open after completion of the precharge command.
CK#
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
RD or
RDA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Ta8
Tb0
Tb1
NOP
NOP
VALID
CK
COMMAND
tIS
tCPDED
VALID
CKE
ADDRESS
VALID
VALID
RL = AL + CL
tPD
DQS, DQS#
DQ BL8
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DQ BC4
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
tRDPDEN
Power-Down
Entry
TRANSITIONING DATA
((
))
((
))
TIME BREAK
DONT CARE
Figure 61. Power-Down Entry after Read and Read with Auto Precharge
67
CK#
T0
T1
Ta0
Ta1
Ta2
WRITE
NOP
NOP
NOP
NOP
Ta3
Ta4
Ta5
Ta6
Ta7
NOP
NOP
NOP
NOP
Tb0
Tb1
Tb2
Tc0
Tc1
NOP
NOP
VALID
CK
COMMAND
NOP
NOP
NOP
tCPDED
tIS
VALID
CKE
ADDRESS
Bank,
Col n
VALID
A10
WL = AL + CWL
tPD
WR (1)
DQS, DQS#
DQ BL8
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DQ BC4
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
Start Internal
Precharge
tWRAPDEN
Power-Down
Entry
TRANSITIONING DATA
((
))
((
))
TIME BREAK
DONT CARE
CK#
T0
T1
Ta0
Ta1
Ta2
WRITE
NOP
NOP
NOP
NOP
Ta3
Ta4
Ta5
Ta6
Ta7
NOP
NOP
NOP
NOP
Tb0
Tb1
Tb2
Tc0
Tc1
NOP
NOP
VALID
CK
COMMAND
NOP
NOP
NOP
tIS
tCPDED
VALID
CKE
ADDRESS
Bank,
Col n
VALID
A10
WL = AL + CWL
tPD
tWR
DQS, DQS#
DQ BL8
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DQ BC4
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
tWRPDEN
Power-Down
Entry
TRANSITIONING DATA
((
))
((
))
TIME BREAK
DONT CARE
68
T0
T1
T2
VALID
NOP
NOP
Ta0
Tb0
Ta1
Tb1
Tc0
CK#
CK
COMMAND
NOP
NOP
VALID
VALID
VALID
tCKE
tCPDED
tIS
CKE
NOP
tIH
tXP
tIS
tPD
Enter
Power-Down
Mode
Exit
Power-Down
Mode
((
))
((
))
TIME BREAK
DONT CARE
Figure 64. Precharge Power-Down (Fast Exit Mode) Entry and Exit
T0
T1
T2
VALID
NOP
NOP
Ta0
Ta1
Tb0
Tb1
Tc0
Td0
CK#
CK
COMMAND
NOP
NOP
VALID
VALID
VALID
VALID
VALID
tCKE
tCPDED
CKE
NOP
tIS
tIH
tPD
tIS
tXP
tXPDLL
Enter
Power-Down
Mode
Exit
Power-Down
Mode
((
))
((
))
TIME BREAK
DONT CARE
Figure 65. Precharge Power-Down (Slow Exit Mode) Entry and Exit
69
T0
T1
T2
T3
COMMAND
VALID
REF
NOP
NOP
ADDRESS
VALID
VALID
Ta0
Ta1
CK#
CK
NOP
VALID
VALID
tCPDED
tPD
tIS
CKE
VALID
tREFPDEN
((
))
((
))
TIME BREAK
DONT CARE
T1
T2
T3
COMMAND
VALID
ACTIVE
NOP
NOP
ADDRESS
VALID
VALID
Ta0
Ta1
CK#
CK
NOP
VALID
VALID
tCPDED
tIS
tPD
CKE
VALID
tACTPDEN
((
))
((
))
TIME BREAK
DONT CARE
70
T0
T1
T2
T3
COMMAND
VALID
PRE or
PREA
NOP
NOP
ADDRESS
VALID
VALID
Ta1
Ta0
CK#
CK
NOP
VALID
VALID
tCPDED
tPD
tIS
CKE
VALID
tPREPDEN
((
))
((
))
TIME BREAK
DONT CARE
T1
MRS
NOP
Ta0
Ta1
Tb0
Tb1
CK#
CK
COMMAND
ADDRESS
NOP
NOP
VALID
VALID
VALID
tCPDED
tIS
tPD
CKE
VALID
tMRSPDEN
((
))
((
))
TIME BREAK
DONT CARE
71
T1
T2
VALID
NOP
NOP
Ta0
Tb0
Ta1
Tb1
Tb2
CK#
CK
COMMAND
NOP
NOP
NOP
NOP
tPD
tPD
tIS
CKE
tIS
tIH
tCKE
tIH
ADDRESS
tIS
VALID
tCPDED
tCPDED
Exit
Power-Down
Mode
Enter
Power-Down
Mode
Enter
Power-Down
Mode
((
))
((
))
TIME BREAK
DONT CARE
T1
T2
VALID
NOP
NOP
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
CK#
CK
COMMAND
NOP
NOP
NOP
REF
NOP
NOP
tPD
tIS
CKE
tIH
tCKE
tIH
ADDRESS
tIS
VALID
tCPDED
tXP
tXPDLL
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Enter
Power-Down
Mode
((
))
((
))
TIME BREAK
DONT CARE
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown in Figure 73
ODT
To other
circuitry
like
RCV, ...
VDDQ / 2
RTT
Switch
DQ, DQS, DM, TDQS
OFF
ON, (OFF, if disabled by MR1 {A9, A6, A2} and MR2 {A10, A9} in general)
73
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2}
to {0,0,0} via a mode register set command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising
clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT
latency is tied to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL - 2 .
74
T0
CK#
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK
CKE
AL=3
CWL - 2
AL=3
ODT
ODTH4, min
ODTLoff = CWL + AL -2
ODTLon = CWL + AL -2
tAOFmin
tAONmin
RTT_NOM
DRAM_RTT
tAONmax
tAOFmax
TRANSITIONING
DONT CARE
Figure 73. Synchronous ODT Timing Example for AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6.0;
ODTLoff = AL + CWL - 2 = 6
CK#
T0
T1
T2
T3
T4
NOP
NOP
NOP
NOP
NOP
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
CKE
COMMAND
NOP
ODTH4
ODTH4min
ODTH4
ODT
ODTLoff = WL - 2
ODTLoff = WL - 2
ODTLon = WL - 2
ODTLon = WL - 2
tAOFmin
tAONmin
tAOFmin
tAONmax
RTT_NOM
DRAM_RTT
tAONmax
tAONmin
tAOFmax
tAOFmax
TRANSITIONING
DONT CARE
75
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
ADDRESS
VALID
ODTLon = CWL + AL - 2
ODTLoff = CWL + AL - 2
ODT
tAOFmin
RTT
RTT_NOM
RTT_NOM
RTT_NOM
RTT_NOM
tAOFmax
tAONmax
RL = AL + CL
DQS, DQS#
DQ
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
TRANSITIONING
DONT CARE
Figure 75. ODT must be disabled externally during Reads by driving ODT low. (example: CL = 6;
AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8)
76
Abbr.
Defined from
Defined to
Unit
registering
ODTLon external ODT
signal high
turning termination on
ODTLon = WL 2
tCK
registering
ODTLoff external ODT
signal low
ODTLoff = WL 2
tCK
ODTLcnw = WL 2
tCK
registering
ODTLcwn4 external write
command
ODTLcwn4 =
4 + ODTLoff
tCK
registering
ODTLcwn8 external write
command
ODTLcwn8 =
6 + ODTLoff
tCK
(avg)
77
Unit
registering ODT
ODT registered low
high
ODTH4 = 4
tCK
(avg)
ODTH4
registering Write
ODT registered low
with ODT high
ODTH4 = 4
tCK
(avg)
ODTH8
registering Write
ODT registered low
with ODT high
ODTH8 = 6
tCK
(avg)
tADC
tCK
(avg)
Abbr.
ODTH4
Defined from
ODTLcnw
ODTLcwn
Defined to
RTT valid
NOTE: tAOF,nom and tADC,nom are 0.5 tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw and
ODTLcwn)
Description
Figure 76 on page 79
Figure 76, Dynamic ODT: Behavior with ODT being asserted before and after the write.
Figure 77 on page 79
Figure 78 on page 79
Figure 78, Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles.
Figure 79 on page 80
Figure 79, Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5.
Figure 80 on page 80
Figure 80, Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 4 clock cycles.
78
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
VALID
ADDRESS
ODTH4
ODTH4
ODTLoff
ODT
ODTLcwn4
ODTLon
tADCmin
tAONmin
RTT
tAOFmin
tADCmin
RTT_WR
RTT_NOM
RTT_NOM
tAONmax
tAOFmax
tADCmax
tADCmax
ODTLcnw
DQS, DQS#
DIN
n
DQ
WL
DIN
n+1
DIN
n+2
DIN
n+3
TRANSITIONING
DONT CARE
NOTE: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the Write command.
In this example, ODTH4 would be satisfied if ODT went low at T8 (4 clocks after the Write command).
Figure 76. Dynamic ODT: Behavior with ODT being asserted before and after the write
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
VALID
VALID
VALID
VALID
VALID
VALID
T9
T10
T11
VALID
VALID
VALID
CK
COMMAND
VALID
VALID
VALID
ADDRESS
ODTH4
ODTLoff
ODTLon
ODT
tAOFmin
tAONmax
RTT_NOM
RTT
tAOFmax
tAONmin
DQS, DQS#
DQ
NOTE: ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
ODT registered low at T5 would also be legal.
TRANSITIONING
DONT CARE
CK#
T0
T1
T2
NOP
WRS8
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
ODTLcnw
ADDRESS
VALID
ODTLoff
ODTH8
ODTLon
ODT
tAOFmin
tADCmax
RTT_WR
RTT
tAOFmax
tAONmin
ODTLcwn8
DQS, DQS#
WL
DQ
DIN
b
DIN
b+1
NOTE: Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH8 = 6 is exactly satisfied.
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
TRANSITIONING
DONT CARE
Figure 78. Dynamic ODT: Behavior with ODT pin being asserted together with write command for a
duration of 6 clock cycles
79
CK#
T0
T1
T2
NOP
WRS4
NOP
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T11
CK
COMMAND
NOP
NOP
ODTLcnw
VALID
ADDRESS
ODTLoff
ODTH4
ODT
ODTLon
tADCmin
tADCmax
tAOFmin
RTT_NOM
RTT_WR
RTT
tAOFmax
tADCmax
tAONmin
ODTLcwn4
DQS, DQS#
WL
DIN
n
DQ
DIN
n+1
DIN
n+2
DIN
n+3
NOTE: ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
ODT registered low at T5 would also be legal.
TRANSITIONING
DONT CARE
Figure 79. Dynamic ODT: Behavior with ODT pin being asserted together with write command for a
duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5.
CK#
T0
T1
T2
NOP
WRS4
NOP
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T10
T11
CK
COMMAND
NOP
NOP
ODTLcnw
ADDRESS
VALID
ODTLoff
ODTH4
ODT
ODTLon
tAOFmin
tADCmax
RTT_WR
RTT
tAOFmax
tAONmin
ODTLcwn4
DQS, DQS#
WL
DQ
DIN
n
DIN
n+1
NOTE: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH4 = 4 is exactly satisfied.
DIN
n+2
DIN
n+3
TRANSITIONING
DONT CARE
Figure 80. Dynamic ODT: Behavior with ODT pin being asserted together with write command for a
duration of 4 clock cycles
80
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK
CKE
tIH
tIH
tIS
tIS
ODT
tAONPDmin
tAOFPDmin
RTT
RTT
tAOFPDmax
tAONPDmax
TRANSITIONING
DONT CARE
Figure 81. Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition: AL is ignored
In Precharge Power Down, ODT receiver remains active, however no Read or Write command can be issued,
as the respective ADD/CMD receivers may be disabled.
Table 17: Asynchronous ODT Timing Parameters for all Speed Bins
Symbol
Description
min
max
Unit
tAONPD
8.5
ns
tAOFPD
8.5
ns
Table 18: ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period
Description
min
max
ODT to RTT
turn-on delay
ODT to RTT
turn-off delay
tANPD
WL -1
82
CK#
T0
T1
T2
T3
T4
T5
NOP
NOP
NOP
NOP
NOP
NOP
T6
T7
T8
T9
NOP
NOP
NOP
NOP
T10
T11
T12
CK
CKE
COMMAND
NOP
tCPDED
tCPDEDmin
tANPD
RTT
ODTLoff
tAOFmax
tAOFPDmax
ODTLoff + tAOFmin
Sync. or async. ODT
tAOFPDmin
RTT
RTT
ODTLoff + tAOFmax
RTT
tAOFPDmax
PD entry transition period
TRANSITIONING
DONT CARE
Figure 82. Synchronous to asynchronous transition during Precharge Power Down (with DLL frozen)
entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4)
83
CK#
T0
T1
T2
T3
T4
T5
NOP
REF
NOP
NOP
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
T9
T10
T11
T12
T13
Ta0
Ta1
Ta2
Ta3
CK
CKE
COMMAND
tRFC(min)
tCPDEDmin
tANPD
RTT
ODTLoff + tAOFPDmin
ODTLoff
tAOFmax
tAOFPDmax
RTT
ODTLoff + tAOFPDmax
RTT
tAOFPDmax
TRANSITIONING
DONT CARE
Figure 83. Synchronous to asynchronous transition after Refresh command (AL = 0; CWL = 5; tANPD
= WL - 1 = 4)
84
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Td0
Td1
CK
CKE
COMMAND
tANPD
NOP
NOP
tXPDLL
RTT
ODTLoff + tAOFmin
tAOFPDmax
tAOFPDmax
Sync. or async. ODT
tAOFPDmin
RTT
RTT
ODTLoff + tAOFmax
ODTLoff
tAOFmax
RTT
TRANSITIONING
DONT CARE
Figure 84. Asynchronous to synchronous transition during Precharge Power Down (with DLL frozen)
exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9)
85
T0
T1
T2
T3
T4
T5
REF
NOP
NOP
NOP
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
T9
T10
T11
T12
T13
T14
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
CKE
tANPD
tRFC(min)
tANPD
tXPDLL
CKE
tANPD
tXPDLL
TRANSITIONING
DONT CARE
Figure 85. Transition period for short CKE cycles, entry and exit period overlapping
(AL = 0, WL = 5, tANPD = WL - 1 = 4)
86
ZQCorrection
----------------------------------------------------------------------------------------------------------------------- TSens Tdriftrate + VSens Vdriftrate
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% / oC, VSens = 0.15% / mV, Tdriftrate = 1 oC / sec and Vdriftrate = 15 mV / sec,
then the interval between ZQCS commands is calculated as
0.5
--------------------------------------------------------- = 0.133 128ms
1.5 1 + 0.15 15
No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit,
tZQoper, or tZQCS. The quiet time on the DRAM channel allows accurate calibration of output driver and ondie termination values. Once DRAM calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.
See "Command Truth Table" on page 21 for a description of the ZQCL and ZQCS commands.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh.
Upon Self-Refresh exit, DDR3 SDRAM will not perform an IO calibration without an explicit ZQ calibration
command. The earliest possible time for ZQ Calibration command (short or long) after self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper,
tZQinit, or tZQCS between the devices.
87
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
ZQCL
NOP
NOP
NOP
VALID
VALID
ZQCS
NOP
NOP
NOP
VALID
ADDRESS
VALID
VALID
VALID
A10
VALID
VALID
VALID
CK#
CK
COMMAND
CKE
(1)
VALID
VALID
(1)
VALID
ODT
(2)
VALID
VALID
(2)
VALID
DQ Bus
(3)
HI-Z
ACTIVITIES
(3)
tZQinit or tZQoper
HI-Z
ACTIVITIES
tZQCS
NOTES: 1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.
((
) ) TIME BREAK
((
))
DONT CARE
88
DDR3L-1333/1600
DDR3L-1866
Parameter
Unit Notes
Min
Max
Min
Max
Min
Max
VIH.CA(DC90)
Vref + 0.090
VDD
Vref + 0.090
VDD
Vref + 0.090
VDD
VIL.CA(DC90)
VSS
Vref - 0.090
VSS
Vref - 0.090
VSS
Vref - 0.090
VIH.CA(AC160)
Vref + 0.160
Note 2
Vref + 0.160
Note 2
1, 2, 5
VIL.CA(AC160)
Note 2
Vref - 0.160
Note 2
Vref - 0.160
1, 2, 5
VIH.CA(AC135)
Vref + 0.135
Note 2
Vref + 0.135
Note 2
Vref + 0.135
Note 2
1, 2, 5
VIL.CA(AC135)
Note 2
Vref - 0.135
Note 2
Vref - 0.135
Note 2
Vref - 0.135
1, 2, 5
VIH.CA(AC125)
Vref + 0.125
Note 2
1, 2, 5
Note 2
Vref - 0.125
1, 2, 5
Reference Voltage for 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD
ADD, CMD inputs
3, 4
VIL.CA(AC125)
VRefCA(DC)
89
DDR3L-1866
Unit Notes
Min
VIH.DQ(DC90)
VIL.DQ(DC90)
VIH.DQ(AC160)
DDR3L-1333/1600
Parameter
VSS
VIL.DQ(AC160)
VIH.DQ(AC135)
VIL.DQ(AC135)
VIH.DQ(AC130)
VIL.DQ(AC130)
VRefDQ(DC)
Reference Voltage
for DQ, DM inputs
Note 2
Note 2
Note 2
Max
Min
Max
Min
Max
VDD
Vref + 0.090
VDD
Vref + 0.090
VDD
Vref - 0.090
VSS
Vref - 0.090
VSS
Vref - 0.090
Note 2
1,2,5
Vref - 0.160
1,2,5
Note 2
Vref + 0.135
Note 2
1,2,5
Vref - 0.135
Note 2
Vref - 0.135
1,2,5
Note 2
Vref + 0.135
Note 2
Vref + 0.130
Note 2
mV
1,2,5
Vref - 0.135
Note 2
Vref - 0.135
Note 2
Vref - 0.130
mV
1,2,5
3, 4
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD
90
voltage
VDD
VRef ac-noise
VRef(DC)
VRef(t)
VRef(DC)max
VDD/2
VRef(DC)min
VSS
time
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent
on VRef.
VRef shall be understood as VRef(DC), as defined in Figure 87.
This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high
or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets
need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit
(+/-1% of VDD) are included in DRAM timings and their associated deratings.
91
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 88. Definition of differential ac-swing and time above ac-level tDVAC
4.3.2 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Table 21: Differential AC and DC Input Levelss
DDR3L-800,1066,1333,1600,1866
Symbol
Parameter
Min
Max
Unit
Notes
VIHdiff
+ 0.180
note 3
VILdiff
Note 3
- 0.180
VIHdiff(ac)
2 x (VIH(ac) - Vref)
Note 3
VILdiff(ac)
note 3
2 x (VIL(ac) - Vref)
Table 22: Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
DDR3L-800/1066/1333/1600
DDR3L-1866
Slew
tDVAC [ps]
tDVAC [ ps ]
tDVAC [ ps ]
DVAC [ ps ]
DVAC [ ps ]
Rate @ |VIH/Ldiff(AC)| = @ |VIH/Ldiff(AC)| = @ |VIH/Ldiff(AC)| = @ |VIH/Ldiff(AC)| = @ |VIH/Ldiff(AC)| =
[V/ns]
320mV
270mV
270mV
250mV
260mV
min
max
min
max
min
max
min
max
min
max
> 4.0
189
201
163
168
176
4.0
189
201
163
168
176
3.0
162
179
140
147
154
2.0
109
134
105
111
1.8
91
119
80
91
97
1.6
69
100
62
74
78
1.4
40
76
37
52
56
1.2
note
44
22
24
1.0
note
note
note
note
note
< 1.0
note
note
note
note
note
95
note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input
differential signal shall become equal to or less than VIL(ac) level.
93
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSEL
VSS or VSSQ
time
Parameter
Unit
Notes
note 3
1, 2
(VDD / 2) + 0.175
note 3
1, 2
note 3
(VDD / 2) - 0.175
1, 2
note 3
(VDD / 2) - 0.175
1, 2
Min
Max
(VDD / 2) + 0.175
NOTE 1 For CK, CK# use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQS#, DQSL, DQSL#, DQSU,
DQSU#) use VIH/VIL(ac) of DQs.
NOTE 2 VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on
VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced
level applies also here
NOTE 3 These values are not defined, however the single-ended signals CK, CK#, DQS, DQS#,
DQSL, DQSL#, DQSU, DQSU# need to be within the respective limits (VIH(dc) max,
VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Refer to ?$paratext>? on page 126
94
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe,
each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements
in Table 24. The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signals to the midlevel between of VDD and VSS
Parameter
Min
Max
Unit
Notes
1
VIX(CK)
- 150
150
mV
VIX(DQS)
- 150
150
mV
NOTE 1 The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL 25mV
VSEH - ((VDD/2) + Vix (Max)) 25mV
95
See "7.5 Address / Command Setup, Hold and Derating" on page 133 for single-ended slew rate definitions
for address and command signals.
See "7.6 Data Setup, Hold and Slew Rate Derating" on page 140 for single-ended slew rate definitions for
data signals.
IInput slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in
Table 25 and Figure 91.
Table 25: Differential Input Slew Rate Definition
Measured
Description
Defined by
from
to
VILdiffmax
VIHdiffmin
VIHdiffmin
VILdiffmax
NOTE: The differential signal (i.e., CK - CK# and DQS - DQS#) must be linear between these thresholds.
Figure 91. Differential Input Slew Rate Definition for DQS, DQS and CK, CK
96
Parameter
Unit
VOH(DC)
0.8 x VDDQ
VOM(DC)
0.5 x VDDQ
VOL(DC)
0.2 x VDDQ
VOH(AC)
VOL(AC)
Notes
NOTE 1 The swing of 0.1 VDDQ is based on approximately 50% of the static single-ended output
high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT =
VDDQ/2.
Parameter
Unit
Notes
VOHdiff(AC)
+ 0.2 x VDDQ
VOLdiff(AC)
- 0.2 x VDDQ
NOTE 1 The swing of 0.2 VDDQ is based on approximately 50% of the static single-ended output
high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT =
VDDQ/2 at each of the differential outputs.
97
Defined by
from
to
VOL(AC)
VOH(AC)
VOH(AC)
VOL(AC)
NOTE:
Output slew rate is verified by design and characterization, and may not be subject to production test.
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
1.75
51)
1.75
51)
1.75
51)
1.75
51)
1.75
51)
V/ns
98
Defined by
from
to
VOLdiff(AC)
VOHdiff(AC)
VOHdiff(AC)
VOLdiff(AC)
NOTE:
Output slew rate is verified by design and characterization, and may not be subject to production test.
Symbol
SRQdiff
12
3.5
12
3.5
12
3.5
12
3.5
12
V/ns
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
99
Figure 94. Reference Load for AC Timing and Output Slew Rate
100
0.4
0.4
0.4
0.4
0.4
Maximum peak amplitude allowed for undershoot area. (See Figure 95)
0.4
0.4
0.4
0.4
0.4
0.67
0.5
0.4
0.33
0.28
V-ns
0.67
0.5
0.4
0.33
0.28
V-ns
NOTE 1 The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed
absolute maximum DC ratings.
NOTE 2 The sum of applied voltage (VDD) and peak amplitude undershoot voltage is not to exceed
absolute maximum DC ratings.
Maximum Amplitude
Overshoot Area
VDD
Volts VSS
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
101
0.4
0.4
0.4
0.4
0.4
Maximum peak amplitude allowed for undershoot area. (See Figure 96)
0.4
0.4
0.4
0.4
0.4
0.25
0.19
0.15
0.13
0.11
V-ns
0.25
0.19
0.15
0.13
0.11
V-ns
NOTE 1 The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed
absolute maximum DC ratings.
NOTE 2 The sum of applied voltage (VDD) and peak amplitude undershoot voltage is not to exceed
absolute maximum DC ratings.
Maximum Amplitude
Overshoot Area
VDDQ
Volts VSSQ
(V)
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 96. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
102
V DDQ V Out
RON Pu = -------------------------------------I Out
(1)
V Out
RON Pd = --------------I Out
(2)
VDDQ
IPu
To
other
circuitry
like
RCV,
...
RONPu
DQ
RONPd
IPd
I Out
VOut
VSSQ
103
Table 34: Output Driver DC Electrical Characteristics, assuming RZQ = 240 W ; entire operating
temperature range; after proper ZQ calibration
RONNom
Resistor
VOut
min
nom
max
Unit
Notes
34
RON34Pd
0.6
1.0
1.15
RZQ/7
1, 2, 3
0.9
1.0
1.15
RZQ/7
1, 2, 3
0.9
1.0
1.45
RZQ/7
1, 2, 3
0.9
1.0
1.45
RZQ/7
1, 2, 3
0.9
1.0
1.15
RZQ/7
1, 2, 3
0.6
1.0
1.15
RZQ/7
1, 2, 3
0.6
1.0
1.15
RZQ/6
1, 2, 3
0.9
1.0
1.15
RZQ/6
1, 2, 3
0.9
1.0
1.45
RZQ/6
1, 2, 3
0.9
1.0
1.45
RZQ/6
1, 2, 3
0.9
1.0
1.15
RZQ/6
1, 2, 3
0.6
1.0
1.15
RZQ/6
1, 2, 3
-10
+10
1, 2, 4
RON34Pu
40
RON40Pd
RON40Pu
NOTE 1 The tolerance limits are specified after calibration with stable voltage and temperature. For the
behavior of the tolerance limits if temperature or voltage changes after calibration, see following
section on voltage and temperature sensitivity.
NOTE 2 The tolerance limits are specified under the condition that VDDQ VDD and that VSSQ = VSS.
NOTE 3 Pull-down and pull-up output driver impedances are recommended to be calibrated at
0.5 VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above,
e.g. calibration at 0.2 VDDQ and 0.8 VDDQ.
NOTE 4 Measurement definition for mismatch between pull-up and pull-down, MMPuPd:
Measure RONPu and RONPd, both at 0.5 * VDDQ:
RON Pu RON Pd
MM PuPd = -------------------------------------------------x100
RON Nom
104
max
unit
RONPU@ VOHdc
RZQ/7
RON@ VOMdc
RZQ/7
RONPD@ VOLdc
RZQ/7
1600
Speed Bin
unit
min
max
min
max
dRONdTM
1.5
1.5
%/oC
dRONdVM
0.15
0.13
%/mV
dRONdTL
1.5
1.5
%/oC
dRONdVL
0.15
0.13
%/mV
dRONdTH
1.5
1.5
%/oC
dRONdVH
0.15
0.13
%/mV
These parameters may not be subject to production test. They are verified by design and characterization.
105
V DDQ V Out
RTT Pu = -------------------------------- under the condition that RTTPd is turned off
I Out
(3)
V Out
RTT Pd = ------------ under the condition that RTTPu is turned off
I Out
(4)
VDDQ
IPu
To
other
circuitry
like
RCV,
...
RTT Pu
RTT Pd
IPd
I Out
VOut
VSSQ
IO_CTT_DEFINITION_01
106
RTT
Resistor
VOut
min
nom
max
Unit
Notes
VOLdc
0.2 VDDQ
0.6
1.00
1.15
RZQ
1, 2, 3, 4,
0.5 VDDQ
0.9
1.00
1.15
RZQ
1, 2, 3, 4,
VOHdc
0.8 VDDQ
0.9
1.00
1.45
RZQ
1, 2, 3, 4,
VOLdc
0.2 VDDQ
0.9
1.00
1.45
RZQ
1, 2, 3, 4,
0.5 VDDQ
0.9
1.00
1.15
RZQ
1, 2, 3, 4,
VOHdc
0.8 VDDQ
0.6
1.00
1.15
RZQ
1, 2, 3, 4,
RTT120
VIL(ac) to VIH(ac)
0.9
1.00
1.65
RZQ/2
1, 2, 5,
RTT60Pd120
VOLdc
0.2 VDDQ
0.6
1.00
1.15
RZQ/2
1, 2, 3, 4,
0.5 VDDQ
0.9
1.00
1.15
RZQ/2
1, 2, 3, 4,
VOHdc
0.8 VDDQ
0.9
1.00
1.45
RZQ/2
1, 2, 3, 4,
VOLdc
0.2 VDDQ
0.9
1.00
1.45
RZQ/2
1, 2, 3, 4,
0.5 VDDQ
0.9
1.00
1.15
RZQ/2
1, 2, 3, 4,
VOHdc
0.8 VDDQ
0.6
1.00
1.15
RZQ/2
1, 2, 3, 4,
RTT60
VIL(ac) to VIH(ac)
0.9
1.00
1.65
RZQ/4
1, 2, 5,
RTT40Pd80
VOLdc
0.2 VDDQ
0.6
1.00
1.15
RZQ/3
1, 2, 3, 4,
0.5 VDDQ
0.9
1.00
1.15
RZQ/3
1, 2, 3, 4,
VOHdc
0.8 VDDQ
0.9
1.00
1.45
RZQ/3
1, 2, 3, 4,
VOLdc
0.2 VDDQ
0.9
1.00
1.45
RZQ/3
1, 2, 3, 4,
0.5 VDDQ
0.9
1.00
1.15
RZQ/3
1, 2, 3, 4,
VOHdc
0.8 VDDQ
0.6
1.00
1.15
RZQ/3
1, 2, 3, 4,
VIL(ac) to VIH(ac)
0.9
1.00
1.65
RZQ/6
1, 2, 5,
120 RTT120Pd240
RTT120Pu240
0, 0, 1
60
RTT60Pu120
0, 1, 1
40
RTT40Pu80
RTT40
107
RTT
Resistor
1, 0, 1
30
RTT30Pd60
VOut
min
nom
max
VOLdc
0.6
1.00
1.15
RZQ/4 1, 2, 3, 4,
0.5 VDDQ
0.9
1.00
1.15
VOHdc
0.9
1.00
1.45
RZQ/4 1, 2, 3, 4,
RZQ/4 1, 2, 3, 4,
VOLdc
0.9
1.00
1.45
RZQ/4 1, 2, 3, 4,
0.5 VDDQ
0.9
1.00
1.15
VOHdc
0.8 VDDQ
VIL(ac) to VIH(ac)
VOLdc
0.2 VDDQ
0.5 VDDQ
VOHdc
0.8 VDDQ
VOLdc
0.2 VDDQ
0.5 VDDQ
VOHdc
0.8 VDDQ
VIL(ac) to VIH(ac)
0.6
1.00
1.15
RZQ/4 1, 2, 3, 4,
RZQ/4 1, 2, 3, 4,
0.9
1.00
1.65
0.6
1.00
1.15
0.9
1.00
1.15
0.9
1.00
1.45
RZQ/6 1, 2, 3, 4,
RZQ/6 1, 2, 3, 4,
0.9
1.00
1.45
RZQ/6 1, 2, 3, 4,
0.9
1.00
1.15
0.6
1.00
1.15
RZQ/6 1, 2, 3, 4,
RZQ/6 1, 2, 3, 4,
0.9
1.00
1.65
RZQ/1
0.2 VDDQ
0.8 VDDQ
RTT30Pu60
1, 0, 0
RTT30
20 RTT20Pd40
RTT20Pu40
RTT20
0.2 VDDQ
Unit
Notes
RZQ/8 1, 2, 5,
RZQ/6 1, 2, 3, 4,
1, 2, 5,
2
Deviation of VM w.r.t. VDDQ/2, DVM
-5
+5
%
1, 2, 5, 6,
NOTE 1 he tolerance limits are specified after calibration with stable voltage and temperature. For the
behavior of the tolerance limits if temperature or voltage changes after calibration, see following
section on voltage and temperature sensitivity.
NOTE 2 The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
NOTE 3 Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 VDDQ. Other
calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at
0.2 VDDQ and 0.8 VDDQ.
NOTE 4 Not a specification requirement, but a design guide line.
NOTE 5 Measurement definition for RTT:
Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test
and measure current I(VIL(ac)) respectively.
V IH(ac) V IL(ac)
RTT = -------------------------------------------------------I(VIH(ac)) I(VIL(ac))
NOTE 6 Measurement definition for VM and DVM:
Measure voltage (VM) at test pin (midpoint) with no load:
2 VM
V M = ------------------ 1 100
V DDQ
108
RTT
min
max
unit
RZQ/2,4,6,8,12
max
unit
dRTTdT
1.5
%/oC
dRTTdV
0.15
%/mV
These parameters may not be subject to production test. They are verified by design and characterization
DUT
CK, CK
DQ, DM
DQS, DQS
TDQS, TDQS
RTT
= 25
VTT =
VSSQ
VSSQ
Timing Reference Points
BD_REFLOAD_ODT
109
tAON
tAONPD
tAOF
tAOFPD
tADC
Figure
Figure 100
Rising edge of CK - CK# with ODT being first Extrapolated point at VSSQ
registered high
Figure 101
Figure 102
Rising edge of CK - CK# with ODT being first End point: Extrapolated point at VRTT_Nom
registered low
Figure 103
Rising edge of CK - CK# defined by the end End point: Extrapolated point at VRTT_Wr
point of ODTLcnw, ODTLcwn4 or ODTLcwn8 and VRTT_Nom respectively
Figure 104
RTT_Nom Setting
RTT_Wr Setting
VSW1 [V]
VSW2 [V]
tAON
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
tAONPD
tAOF
tAOFPD
tADC
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/12
RZQ/2
0.20
0.25
Note
110
CK
VTT
CK
t AON
TSW2
DQ, DM
DQS, DQS
TDQS, TDQS
T SW1
VSW2
VSW1
VSSQ
VSSQ
End point: Extrapolated point at VSSQ
CK
VTT
CK
t AONPD
T SW2
DQ, DM
DQS, DQS
TDQS, TDQS
T SW1
VSW2
VSSQ
VSW1
VSSQ
End point: Extrapolated point at VSSQ
TD TAONPD DEF
111
CK
VTT
CK
t AOF
End point: Extrapolated point at VRTT_Nom
VRTT_Nom
T SW2
DQ, DM
DQS, DQS
TDQS, TDQS
T SW1
VSW2
VSW1
VSSQ
CK
VTT
CK
t AOFPD
End point: Extrapolated point at VRTT_Nom
VRTT_Nom
T SW2
DQ, DM
DQS, DQS
TDQS, TDQS
T SW1
VSW2
VSW1
VSSQ
112
CK
VTT
CK
t ADC
VRTT_Nom
End point:
DQ, DM
Extrapolated
DQS, DQS
point at VRTT_Nom
TDQS, TDQS
tADC
VRTT_Nom
T SW21
TSW11
T SW22
VSW2
VSW1
T SW12
VRTT_Wr
VSSQ
113
tCK avg =
tCK j N
j = 1
where
N = 200
tCH avg =
tCH j N tCK avg
j = 1
where
N = 200
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
tCL avg =
tCL j N tCK avg
j = 1
where
N = 200
114
Symbol
512Mb
1Gb
2Gb
4Gb
8Gb
Units
tRFC
90
110
160
260
350
ns
0 C TCASE 85 C
7.8
7.8
7.8
7.8
7.8
85 C TCASE 95 C
3.9
3.9
3.9
3.9
3.9
Average periodic
refresh interval
tREFI
Notes
NOTE 1 Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3
SDRAM devices support the following options or requirements referred to in this material.
115
Symbol
Min
Max
DDR3L-1066
DDR3L-1333
DDR3L-1600
Min
Min
Min
Max
Max
Max
Units Notes
Clock Timing
Minimum Clock Cycle
tCK
8
8
8
8
ns
Time (DLL off mode) (DLL_OFF)
Average Clock Period tCK(avg)
Standard Speed Bins in product datasheet
ps
Average high pulse
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK
width
(avg)
Average low pulse
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK
width
(avg)
Absolute Clock
tCK(abs) tCK(avg)min tCK(avg) tCK(avg)min tCK(avg) tCK(avg)mi tCK(avg) tCK(avg)mi tCK(avg) ps
Period
+
max +
+
max +
n+
max +
n+
max +
tJIT(per)min tJIT(per) tJIT(per)min tJIT(per) tJIT(per)mi tJIT(per) tJIT(per)mi tJIT(per)
max
max
n
max
n
max
Absolute clock HIGH
tCH(abs)
0.43
0.43
0.43
0.43
tCK
pulse width
(avg)
Absolute clock LOW
tCL(abs)
0.43
0.43
0.43
0.43
tCK
pulse width
(avg)
Clock Period Jitter
JIT(per)
- 100
100
- 90
90
- 80
80
-70
70
ps
Clock Period Jitter
tJIT(per,
- 90
90
- 80
80
- 70
70
-60
60
ps
during DLL locking
lck)
period
Cycle to Cycle Period
tJIT(cc)
200
180
160
140
ps
Jitter
Cycle to Cycle Period tJIT(cc, lck)
180
160
140
120
ps
Jitter during DLL locking period
Duty Cycle Jitter
tJIT(duty)
ps
Cumulative error
tERR(2per)
- 147
147
- 132
132
- 118
118
- 103
103
ps
across 2 cycles
Cumulative error
tERR(3per)
- 175
175
- 157
157
- 140
140
- 122
122
ps
across 3 cycles
Cumulative error
tERR(4per)
- 194
194
- 175
175
- 155
155
- 136
136
ps
across 4 cycles
Cumulative error
tERR(5per)
- 209
209
- 188
188
- 168
168
- 147
147
ps
across 5 cycles
Cumulative error
tERR(6per)
- 222
222
- 200
200
- 177
177
- 155
155
ps
across 6 cycles
Cumulative error
tERR(7per)
- 232
232
- 209
209
- 186
186
- 163
163
ps
across 7 cycles
Cumulative error
tERR(8per)
- 241
241
- 217
217
- 193
193
- 169
169
ps
across 8 cycles
Cumulative error
tERR(9per)
- 249
249
- 224
224
- 200
200
- 175
175
ps
across 9 cycles
116
25
26
DDR3L-1066
DDR3L-1333
DDR3L-1600
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Cumulative error
across 10 cycles
Cumulative error
across 11 cycles
Cumulative error
across 12 cycles
Cumulative error
across n = 13, 14 . . .
49, 50 cycles
tERR
(10per)
tERR
(11per)
tERR
(12per)
tERR
(nper)
- 257
257
- 231
231
- 205
205
- 180
180
ps
- 263
263
- 237
237
- 210
210
- 184
184
ps
- 269
269
- 242
242
- 215
215
- 188
188
ps
tDQSQ
200
150
125
100
tQH
0.38
0.38
0.38
0.38
tLZ(DQ)
- 800
400
- 600
300
- 500
250
- 450
225
tHZ(DQ)
400
300
250
225
tDS(base)
AC160
SR =1V/ns
tDS(base)
AC135
SR =1V/ns
tDS(base)
AC130
SR =2V/ns
tDH(base)
DC190
SR = 1V/ns
tDH(base)
DC190
SR = 2V/ns
tDIPW
90
40
140
90
45
25
ps
d, 17
ps
160
110
75
55
ps
d, 17
ps
600
490
400
360
ps
28
tRPRE
0.9
Note 19
0.9
Note 19
0.9
Note 19
0.9
Note 19
tRPST
0.3
Note 11
0.3
Note 11
0.3
Note 11
0.3
tQSH
0.38
0.38
0.40
0.40
tQSL
0.38
0.38
0.40
0.40
tWPRE
0.9
0.9
0.9
0.9
tERR(nper)min
tERR(nper)max
Units Notes
= (1 + 0.68ln(n)) * tJIT(per)min
= (1 + 0.68ln(n)) * tJIT(per)max
ps
24
ps
13
Data Timing
DQS, DQS# to DQ
skew, per group, per
access
DQ output hold time
from DQS, DQS#
DQ low-impedance
time from CK, CK#
DQ high impedance
time from CK, CK#
Data setup time to
DQS, DQS# referenced to Vih(ac) /
Vil(ac) levels
DQ and DM Input
pulse width for each
input
tCK 13, g
(avg)
ps 13, 14,
f
ps 13, 14,
f
ps
d, 17
tCK
(avg)
Note 11 tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
117
13, 19,
g
11, 13,
g
13, g
13, g
1
Symbol
DDR3L-1066
DDR3L-1333
DDR3L-1600
Min
Max
Min
Max
Min
Max
Min
Max
0.3
0.3
0.3
0.3
- 400
400
- 300
300
- 255
255
- 225
225
tCK
(avg)
ps
- 800
400
- 600
300
- 500
250
- 450
225
ps
13, 14,
f
400
300
250
225
ps
13, 14,
f
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK 29, 31
(avg)
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK 30, 31
(avg)
- 0.25
0.25
- 0.25
0.25
- 0.25
0.25
- 0.27
0.27
tCK
(avg)
0.2
0.2
0.2
0.18
tCK
(avg)
c, 32
0.2
0.2
0.2
0.18
tCK
(avg)
c, 32
tDLLK
tRTP
512
max(4nCK,
7.5ns)
512
max(4nCK,
7.5ns)
512
max(4nCK,
7.5ns)
512
max(4nCK,
7.5ns)
nCK
tWTR
max(4nCK,
7.5ns)
max(4nCK,
7.5ns)
max(4nCK,
7.5ns)
max(4nCK,
7.5ns)
tWR
tMRD
15
4
15
4
15
4
15
4
tMOD
max(12nCK,
15ns)
max(12nCK,
15ns)
max(12nCK
, 15ns)
max(12nCK
, 15ns)
Units Notes
1
13, f
e, 18
ns
nCK
tRCD
tRP
tRC
e, 18
e
Refer to the individual data sheet for its frequencies supported & latencies.
e
e
118
Symbol
Min
Max
DDR3L-1066
DDR3L-1333
DDR3L-1600
Min
Min
Min
Max
Max
Max
-
Units Notes
nCK
nCK
nCK
22
e
ns
ns
ps
b, 16
ps
b, 16,
ps
b, 16,
ps
b, 16
ps
28
Calibration Timing
Power-up and
RESET calibration
time
Normal operation Full
calibration time
Normal operation
Short calibration time
tZQinit
max(512nCK
, 640ns)
max(512nCK
, 640ns)
max(512nC
K, 640ns)
max(512nC
K, 640ns)
tZQoper
max(256nCK
, 320ns)
max(64nCK,
80ns)
max(256nCK
, 320ns)
max(64nCK,
80ns)
max(256nC
K, 320ns)
max(64nCK
, 80ns)
max(256nC
K, 320ns)
max(64nCK
, 80ns)
max(5nCK,
tRFC(min) +
10ns)
max(5nCK,
tRFC(min) +
10ns)
max(5nCK,
tRFC(min)
+ 10ns)
max(5nCK,
tRFC(min)
+ 10ns)
tZQCS
23
Reset Timing
Exit Reset from CKE
HIGH to a valid command
tXPR
119
Symbol
DDR3L-1066
DDR3L-1333
DDR3L-1600
Min
Max
Min
Max
Min
Max
Min
Max
Units Notes
max(5nCK,
tRFC(min) +
10ns)
tDLLK(min)
max(5nCK,
tRFC(min) +
10ns)
tDLLK(min)
max(5nCK,
tRFC(min)
+ 10ns)
tDLLK(min)
max(5nCK,
tRFC(min)
+ 10ns)
tDLLK(min)
tCKESR
tCKE(min) +
1 nCK
tCKE(min) +
1 nCK
tCKE(min)
+ 1 nCK
tCKE(min)
+ 1 nCK
tCKSRE
max(5 nCK,
10 ns)
max(5 nCK,
10 ns)
max(5 nCK,
10 ns)
max(5 nCK,
10 ns)
tCKSRX
max(5 nCK,
10 ns)
max(5 nCK,
10 ns)
max(5 nCK,
10 ns)
max(5 nCK,
10 ns)
max(3nCK,
7.5ns)
max(3nCK,
6ns)
max(3nCK,
6ns)
max(10nCK,
24ns)
max(10nCK
, 24ns)
max(10nCK
, 24ns)
max(3nCK,
5.625ns)
1
max(3nCK,
5.625ns)
1
max(3nCK,
5ns)
1
9*
tREFI
-
tCKE(min)
tCKE(min)
1
9*
tREFI
-
tCKE(min)
9*
tREFI
-
9*
tREFI
-
nCK
20
nCK
20
RL + 4 + 1
RL + 4 + 1
RL + 4 + 1
tXS
tXSDLL
nCK
nCK
15
nCK
120
Symbol
Min
Timing of WR comtWRPDEN
WL + 4 +
mand to Power Down
(tWR /
entry (BL8OTF,
tCK(avg))
BL8MRS, BC4OTF)
Timing of WRA comtWRAPWL + 4 +
mand to Power Down
DEN
WR + 1
entry (BL8OTF,
BL8MRS, BC4OTF)
Timing of WR comtWRPDEN
WL + 2 +
mand to Power Down
(tWR /
entry (BC4MRS)
tCK(avg))
Timing of WRA comtWRAPWL + 2 +
mand to Power Down
DEN
WR + 1
entry (BC4MRS)
Timing of REF com- tREFPDEN
1
mand to Power Down
entry
Timing of MRS comtMRSPtMOD(min)
mand to Power Down
DEN
entry
DDR3L-1066
DDR3L-1333
DDR3L-1600
Max
Min
Max
Min
Max
Min
Max
WL + 4 +
(tWR /
tCK(avg))
WL + 4 +
(tWR /
tCK(avg))
WL + 4 +
(tWR /
tCK(avg))
nCK
WL + 4 +
WR + 1
WL + 4 +
WR + 1
WL + 4 +
WR + 1
nCK
10
WL + 2 +
(tWR /
tCK(avg))
WL + 2 +
WR + 1
WL + 2 +
(tWR /
tCK(avg))
WL + 2 +
WR + 1
WL + 2 +
(tWR /
tCK(avg))
WL + 2 +
WR + 1
nCK
nCK
10
nCK 20, 21
tMOD(min)
tMOD(min)
tMOD(min)
Units Notes
ODT Timings
ODT turn on Latency
ODT turn off Latency
ODT high time without write command or
with write command
and BC4
ODT high time with
Write command and
BL8
Asynchronous RTT
turn-on delay (PowerDown with DLL frozen)
Asynchronous RTT
turn-off delay (PowerDown with DLL frozen)
RTT turn-on
RTT_Nom and
RTT_WR turn-off time
from ODTLoff reference
RTT dynamic change
skew
ODTLon
ODTLoff
ODTH4
WL - 2 = CWL + AL - 2
WL - 2 = CWL + AL - 2
4
nCK
nCK
nCK
ODTH8
nCK
tAONPD
8.5
8.5
8.5
8.5
ns
tAOFPD
8.5
8.5
8.5
8.5
ns
tAON
tAOF
-400
0.3
400
0.7
-300
0.3
300
0.7
-250
0.3
250
0.7
-225
0.3
225
0.7
ps
tCK
(avg)
7, f
8, f
tADC
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
tCK
(avg)
121
DDR3L-1066
DDR3L-1333
DDR3L-1600
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units Notes
tWLMRD
40
40
40
40
nCK
tWLDQSEN
25
25
25
25
nCK
tWLS
325
245
195
165
ps
tWLH
325
245
195
165
ps
tWLO
7.5
ns
a The
setup and hole parameters in this table apply 1.35V (see Table Recommended DC Operating Conditions - DDR3L (1.35V) operation in
component datasheet) operation only. If the device is operated at 1.5V (see Table Recommended DC Operating Conditions - DDR3 (1.5V) operation in component datasheet) the respective parameters in JESD79-3 (tIS(base, AC175), tIS(base, AC150), tIH(base, DC100), tDS(base,
AC150), tDH(base, DC100), etc.) apply. The 1.5V setup/hold parameters (tIS(base, A175), tIS(base, AC150), tIH(base, DC100), tDS(base,
AC175), tDS(base, AC150), tDH(base, DC100), etc.) do not apply with the device is operated in the 1.35V voltage range.
NOTE 1 The general notes from JESD79-3E, 7.4, apply to Table 43.
NOTE 2 VDD = VDDQ = 1.35V + 0.100/-0.067V
122
Symbol
Min
Max
Units Notes
Clock Timing
Minimum Clock Cycle
tCK
Time (DLL off mode)
(DLL_OFF)
Average Clock Period
tCK(avg)
Average high pulse
tCH(avg)
width
Average low pulse
tCL(avg)
width
Absolute Clock
tCK(abs)
Period
0.53
tCK(avg)min
+
tJIT(per)min
tCK(avg)max
+
tJIT(per)max
tCH(abs)
0.43
tCL(abs)
0.43
JIT(per)
tJIT(per, lck)
-60
-50
60
50
ns
ps
tCK
(avg)
tCK
(avg)
ps
tCK
(avg)
tCK
(avg)
ps
ps
tJIT(cc)
120
ps
tJIT(cc, lck)
100
ps
tJIT(duty)
tERR(2per)
-88
88
ps
ps
tERR(3per)
-105
105
ps
tERR(4per)
-117
117
ps
tERR(5per)
-126
126
ps
tERR(6per)
-133
133
ps
tERR(7per)
-139
139
ps
tERR(8per)
-145
145
ps
tERR(9per)
-150
150
ps
tERR(10per)
-154
154
ps
tERR(11per)
-158
158
ps
25
26
123
Symbol
Cumulative error
tERR(12per)
across 12 cycles
Cumulative error
tERR(nper)
across n = 13, 14 . . .
49, 50 cycles
Min
Max
-161
161
Units Notes
ps
ps
24
ps
13
tERR(nper)max
Data Timing
DQS, DQS# to DQ
skew, per group, per
access
DQ output hold time
from DQS, DQS#
DQ low-impedance
time from CK, CK#
DQ high impedance
time from CK, CK#
Data setup time to
DQS, DQS# referenced to Vih(ac) /
Vil(ac) levels
DQ and DM Input
pulse width for each
input
Data Strobe Timing
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
tDQSQ
85
tQH
0.38
tLZ(DQ)
- 390
195
tHZ(DQ)
195
tDS(base)
AC160
SR = 1V/ns
tDS(base)
AC135
SR = 1V/ns
tDS(base)
AC130
SR = 1V/ns
tDH(base)
DC90
SR = 1V/ns
tDH(base)
DC90
SR = 2V/ns
tDIPW
ps
70
ps
d, 17
ps
d, 17
75
ps
320
ps
28
tRPRE
0.9
Note 19
tRPST
0.3
Note 11
tQSH
0.4
tQSL
0.4
tWPRE
0.9
tWPST
0.3
tCK
13, g
(avg)
ps 13, 14,
f
ps 13, 14,
f
ps
d, 17
124
Symbol
Min
Max
Units Notes
tDQSCK
- 195
195
ps
13, f
tLZ(DQS)
- 390
195
ps
13, 14,
f
tHZ(DQS)
195
ps
13, 14,
f
tDQSL
0.45
0.55
tCK 29, 31
(avg)
tDQSH
0.45
0.55
tCK 30, 31
(avg)
tDQSS
- 0.27
0.27
tCK
(avg)
tDSS
0.18
tCK
(avg)
c, 32
tDSH
0.18
tCK
(avg)
c, 32
tDLLK
tRTP
512
max(4nCK, 7.5ns)
nCK
tWTR
max(4nCK, 7.5ns)
tWR
tMRD
15
4
tMOD
max(12nCK, 15ns)
e, 18
ns
nCK
tRCD
tRP
tRC
tCCD
e, 18
e
Refer to the individual data sheet for its frequencies supported &
latencies.
e
e
nCK
125
Symbol
Min
Max
WR + roundup(tRP / tCK(avg))
Units Notes
nCK
nCK
22
e
Refer to the individual data sheet for its frequencies supported &
latencies.
max(4nCK, 5.0ns)
max(4nCK, 6.0ns)
27
ns
35
ns
ps
b, 16
65
ps
b, 16
150
ps
b, 16
110
ps
b, 16
535
ps
28
max(512nCK, 640ns)
max(256nCK, 320ns)
max(64nCK, 80ns)
23
Reset Timing
Exit Reset from CKE
HIGH to a valid command
tXPR
126
Symbol
Min
Max
Units Notes
tXS
tXSDLL
tDLLK(min)
tCKESR
tCKE(min) + 1 nCK
tCKSRE
tCKSRX
max(3nCK, 6ns)
max(10nCK, 24ns)
max(3nCK 5ns)
tCKE(min)
9 * tREFI
nCK
20
nCK
20
RL + 4 + 1
nCK
WL + 4 + (tWR / tCK(avg))
nCK
nCK
nCK
15
127
Symbol
Min
Max
Units Notes
WL + 4 + WR + 1
nCK
10
WL + 2 + (tWR / tCK(avg))
nCK
WL + 2 + WR + 1
nCK
10
nCK
20, 21
tMOD(min)
ODT Timings
ODT turn on Latency
ODT turn off Latency
ODT high time without write command or
with write command
and BC4
ODT high time with
Write command and
BL8
Asynchronous RTT
turn-on delay (PowerDown with DLL frozen)
Asynchronous RTT
turn-off delay (PowerDown with DLL frozen)
RTT turn-on
RTT_Nom and
RTT_WR turn-off time
from ODTLoff reference
RTT dynamic change
skew
ODTLon
ODTLoff
ODTH4
WL - 2 = CWL + AL - 2
WL - 2 = CWL + AL - 2
4
nCK
nCK
nCK
ODTH8
nCK
tAONPD
8.5
ns
tAOFPD
8.5
ns
tAON
tAOF
- 195
0.3
195
0.7
ps
tCK(a
vg)
7, f
8, f
tADC
0.3
0.7
tCK(a
vg)
tWLMRD
40
nCK
tWLDQSEN
25
nCK
128
Symbol
Min
Max
Units Notes
tWLS
140
ps
tWLH
140
ps
tWLO
7.5
ns
tWLOE
ns
The setup and hole parameters in this table apply 1.35V (see Table Recommended DC Operating Conditions - DDR3L
(1.35V) operation in component datasheet) operation only. If the device is operated at 1.5V (see Table Recommended
DC Operating Conditions - DDR3 (1.5V) operation in component datasheet) the respective parameters in JESD79-3
(tIS(base, AC175), tIS(base, AC150), tIH(base, DC100), tDS(base, AC150), tDH(base, DC100), etc.) apply. The 1.5V
setup/hold parameters (tIS(base, A175), tIS(base, AC150), tIH(base, DC100), tDS(base, AC175), tDS(base, AC150),
tDH(base, DC100), etc.) do not apply with the device is operated in the 1.35V voltage range.
NOTE 1 The general notes from JESD79-3E, 7.4, apply to Table 44.
VDD = VDDQ = 1.35V + 0.100/-0.067V
129
130
131
ZQCorrection
----------------------------------------------------------------------------------------------------------------------- TSens Tdriftrate + VSens Vdriftrate
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the
SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% / oC, VSens = 0.15% / mV, Tdriftrate = 1 oC / sec and Vdriftrate = 15
mV / sec, then the interval between ZQCS commands is calculated as:
0.5
--------------------------------------------------------- = 0.133 128ms
1.5 1 + 0.15 15
NOTE 24.n = from 13 cycles to 50 cycles. This row defines 38 parameters.
NOTE 25.tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge
to the following falling edge.
NOTE 26.tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to
the following rising edge.
NOTE 27.The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an
additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV and
another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
NOTE 28.Pulse width of a input signal is defined as the width between the first crossing of Vref(dc) and the
consecutive crossing of Vref(dc).
NOTE 29.tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured
from one falling edge to the next consecutive rising edge.
NOTE 30.tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured from one rising edge to the next consecutive falling edge.
NOTE 31.tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application.
NOTE 32.tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective
timing parameter in the application.
132
Reference
Note
tIS(base) AC160
VIH/L(ac)
215
140
80
60
ps
tIS(base) AC135
VIH/L(ac)
365
290
205
185
65
ps
1, 2
tIS(base) AC125
VIH/L(ac)
150
ps
1, 3
tIH(base) DC90
VIH/L(dc)
285
210
150
130
110
ps
NOTE 1 (ac/dc referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew
rate)
NOTE 2 The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by
adding an additional 125 ps for DDR3L-800/1066 or 100ps for DDR3L-1333/1600 of derating to
accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the
earlier reference point [(160 mv - 135 mV) / 1 V/ns].
NOTE 3 The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by
adding an additional 75 ps for DDR3L-1866 of derating to accommodate for the lower altemate
threshold of 135 mV and another 10 ps to account for the earlier reference point [(135 mv - 125
mV) / 1 V/ns].
133
Table 46: Derating values DDR3L-800/1066/1333/1600 tIS/tIH - AC/DC based AC160 Threshold
tIS, tIH derating in [ps] AC/DC based
AC175 Threshold -> VIH(AC)=VREF(DC)+160mV, VIL(AC)=VREF(DC)-160mV
CK,CK# Differential Slew Rate
4.0 V/ns
2.0
1.5
CMD/ 1.0
ADD 0.9
Slew 0.8
rate 0.7
V/ns 0.6
0.5
0.4
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
80
53
0
-1
-3
-5
-8
-20
-40
45
30
0
-3
-8
-13
-20
-30
-45
80
53
0
-1
-3
-5
-8
-20
-40
45
30
0
-3
-8
-13
-20
-30
-45
80
53
0
-1
-3
-5
-8
-20
-40
45
30
0
-3
-8
-13
-20
-30
-45
88
61
8
7
5
3
0
-12
-32
53
38
8
5
1
-5
-12
-22
-37
96
69
16
15
13
11
8
-4
-24
61
46
16
13
9
3
-4
-14
-39
104
77
24
23
21
19
16
4
-16
69
54
24
21
17
11
4
-6
-21
112
85
32
31
29
27
24
12
-8
79
64
34
31
27
21
14
4
-11
120
93
40
39
37
35
32
20
0
95
80
50
47
43
37
30
20
5
Table 47: Derating values DDR3L-800/1066/1333/1600 tIS/tIH - AC/DC based Alternate AC135
Threshold
tIS, tIH derating in [ps] AC/DC based
Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
CK,CK# Differential Slew Rate
4.0 V/ns
2.0
1.5
CMD/ 1.0
ADD 0.9
Slew 0.8
rate 0.7
V/ns 0.6
0.5
0.4
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
68
45
0
2
3
6
9
5
-3
45
30
0
-3
-8
-13
-20
-30
-45
68
45
0
2
3
6
9
5
-3
45
30
0
-3
-8
-13
-20
-30
-45
68
45
0
2
3
6
9
5
-3
45
30
0
-3
-8
-13
-20
-30
-45
76
53
8
10
11
14
17
13
6
53
38
8
5
1
-5
-12
-22
-37
84
61
16
18
19
22
25
21
14
61
46
16
13
9
3
-4
-14
-29
92
69
24
26
27
30
33
29
22
69
54
24
21
17
11
4
-6
-21
100
77
32
34
35
38
41
37
30
79
64
34
31
27
21
14
4
-11
108
85
40
42
43
46
49
45
38
95
80
50
47
43
37
30
20
5
134
Table 48: Derating values DDR3L-1866 tIS/tIH - AC/DC based Alternate AC125 Threshold
tIS, tIH derating in [ps] AC/DC based
Alternate AC125 Threshold -> VIH(AC)=VREF(DC)+125mV, VIL(AC)=VREF(DC)-125mV
CK,CK# Differential Slew Rate
4.0 V/ns
2.0
1.5
CMD/ 1.0
ADD 0.9
Slew 0.8
rate 0.7
V/ns 0.6
0.5
0.4
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
63
42
0
3
6
10
16
15
13
45
30
0
-3
-8
-13
-20
-30
-45
63
42
0
3
6
10
16
15
13
45
30
0
-3
-8
-13
-20
-30
-45
63
42
0
3
6
10
16
15
13
45
30
0
-3
-8
-13
-20
-30
-45
71
50
8
11
14
18
24
23
21
53
38
8
5
1
-5
-12
-22
-37
79
58
16
19
22
26
32
31
29
61
46
16
13
9
3
4
-14
-29
87
66
24
27
30
34
40
39
37
69
54
24
21
17
11
-4
-6
-21
95
74
32
35
38
42
48
47
45
79
64
34
31
27
21
14
4
-11
103
82
40
43
46
50
56
55
53
95
80
50
47
43
37
30
20
5
Table 49: Required time tVAC above VIH(AC) {below VIL(AC)} for valid ADD/CMD transition
DDR3L-800/1066/1333/1600
Slew Rate [V/ns]
> 2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
< 0.5
DDR3L-1866
tVAC @ 135mV[ps]
min
max
min
max
min
max
min
max
200
200
173
120
102
80
51
13
note
note
213
213
190
145
130
111
87
55
10
10
200
200
178
133
118
99
75
43
note
note
205
205
184
143
129
111
89
59
18
18
Note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall
become equal to or less than VIL(ac) level.
135
CK
CK#
tIS
tIH
tIS
tIH
VDDQ
tVAC
VIH(ac) min
VREF to ac
region
VIH(dc) min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc) max
VREF to ac
region
VIL(ac) max
tVAC
VSS
TF
TR
Figure 105. Illustration of nominal slew rate and tVAC for setup time tIS (for ADD/CMD with respect to
clock).
136
CK
CK#
tIS
tIH
tIS
tIH
VDDQ
VIH(ac) min
VIH(dc) min
dc to VREF
region
nominal
slew rate
VREF(dc)
nominal
slew rate
dc to VREF
region
VIL(dc) max
VIL(ac) max
VSS
TR
VREF(dc) - VIL(dc)max
Hold Slew Rate
=
Rising Signal
TR
TF
VIH(dc)min - VREF(dc)
Hold Slew Rate
=
Falling Signal
TF
Figure 106. Illustration of nominal slew rate for hold time tIH (for ADD/CMD with respect to clock).
137
CK
CK#
tIS
tIH
tIS
VDDQ
nominal
line
VIH(ac) min
tIH
tVAC
VREF to ac
region
VIH(dc) min
tangent
line
VREF(dc)
tangent
line
VIL(dc) max
VREF to ac
region
VIL(ac) max
nominal
line
tVAC
VSS
Setup Slew Rate
Rising Signal =
TF
TR
Figure 107. Illustration of tangent line for setup time tIS (for ADD/CMD with respect to clock)
138
CK
CK#
tIS
tIH
tIS
tIH
VDDQ
VIH(ac) min
nominal
line
VIH(dc) min
dc to VREF
region
tangent
line
VREF(dc)
dc to VREF
region
tangent
line
nominal
line
VIL(dc) max
VIL(ac) max
VSS
TR
TF
139
140
Reference
90
40
ps
140
90
45
20
ps
70
ps
75
ps
160
110
75
55
ps
NOTE 1 (AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate)
NOTE 2 (AC/DC referenced for 2V/ns DQ-slew rate and 4V/ns DQS slew rate)
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0
1.5
1.0
DQ 0.9
Slew
0.8
rate
V/ns 0.7
0.6
0.5
0.4
80
53
0
-
45
03
0
-
80
53
0
-1
-
45
30
0
-3
-
80
53
0
-1
-3
-
45
30
0
-3
-8
-
61
8
7
5
3
-
38
8
5
1
-5
-
16
15
13
11
8
-
16
13
9
3
-4
-
23
21
19
16
4
-
21
17
11
4
-6
-
29
27
24
12
-8
27
21
14
4
-11
35
32
20
0
37
30
20
5
141
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0
1.5
1.0
DQ 0.9
Slew
0.8
rate
V/ns 0.7
0.6
0.5
0.4
68
45
0
-
45
30
0
-
68
45
0
-1
-
45
30
0
-3
-
68
45
0
-1
-3
-
45
30
0
-3
-8
-
53
8
7
5
14
-
38
8
5
1
-5
-
16
15
13
22
25
-
16
13
9
3
-4
-
23
21
30
33
29
-
21
17
11
4
-6
-
29
38
41
37
30
27
21
14
4
-11
46
49
45
38
37
30
20
5
DQ
Slew
rate
V/ns
-29
-32
-37
-42
-49
-
-38
-37
-33
-29
-31
-
-24
-29
-34
-41
-51
-
-29
-24
-21
-23
-28
-19
-24
-31
-41
-56
-17
-13
-15
-20
-8
-15
-25
-40
142
Table 54: Required time tVAC above VIH(ac) {below VIL(ac)} for valid DQ transition
Slew Rate
[V/ns]
> 2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
< 0.5
DDR3L-800/1066
(AC160)
DDR3L-800/1066/ 1333/1600
(AC135)
DDR3L-1866
(AC130)
tVAC [ps]
tVAC [ps]
tVAC [ps]
min
max
min
max
min
max
165
165
138
85
67
45
16
note
note
note
113
113
90
45
30
11
note
note
note
note
95
95
73
30
16
note
-
note : Rising input sinnal shall become equal to or greater than VIH(ac) level and Falling input signal shall
become equal to or less than VIL(ac) level.
143
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
tVAC
VIH(ac) min
VREF to ac
region
VIH(dc) min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc) max
VREF to ac
region
VIL(ac) max
tVAC
VSS
TF
TR
Figure 109. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe)
144
DQS#
DQS
tDS
tDS
tDH
tDH
VDDQ
VIH(ac) min
VIH(dc) min
dc to VREF
region
nominal
slew rate
VREF(dc)
nominal
slew rate
dc to VREF
region
VIL(dc) max
VIL(ac) max
VSS
TR
VREF(dc) - VIL(dc)max
Hold Slew Rate
=
Rising Signal
TR
TF
VIH(dc)min - VREF(dc)
Hold Slew Rate
=
Falling Signal
TF
Figure 110. Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe)
145
DQS#
DQS
tDS
tDS
tDH
VDDQ
nominal
line
VIH(ac) min
tDH
tVAC
VREF to ac
region
VIH(dc) min
tangent
line
VREF(dc)
tangent
line
VIL(dc) max
VREF to ac
region
VIL(ac) max
nominal
line
tVAC
VSS
Setup Slew Rate
Rising Signal =
TF
TR
Figure 111. IIllustration of tangent line for setup time tDS (for DQ with respect to strobe)
146
DQS#
DQS
tDS
tDS
tDH
tDH
VDDQ
VIH(ac) min
nominal
line
VIH(dc) min
dc to VREF
region
tangent
line
VREF(dc)
dc to VREF
region
tangent
line
nominal
line
VIL(dc) max
VIL(ac) max
VSS
TR
TF
147