Catsw Arch Rst-2011

RST-2011
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2003, Cisco Systems, Inc. All rights reserved.
Catalyst Switch Architecture

and Operation
Session RST-2011
RST-2011
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Copyright 2003, Cisco Systems, Inc. All rights reserved. Printed in USA.
RST-2011 8174_05_2003_c2
Agenda
Components of a Switch Architecture

Packet Forwarding Mechanisms
Catalyst 3550 and 3750 Architecture and
Operation
Catalyst 4500 Architecture and Operation
Catalyst 6500 Architecture and Operation
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Components of a Switch
Architecture
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Multilayer Switch Components

Processors
Flash
ASICs
Switch
Fabric
DRAM
Uplinks
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Console
External
Flash

Processors
Processors
Processor supports critical

control plane functions and
system management
Spanning tree, routing protocols,
ARP, HSRP, etc.
Module and environmental
management
Upsidenew features easily

implemented in software,
allowing faster and more
flexible development
Downsidefeatures
processed in software, with
lower performance than ASICbased features
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ASICs
ASICs provide hardware-based
features providing very highspeed performance
ASICs
Forwarding Engine
Layer 2 and Layer 3 forwarding
Access Control Lists (ACLs), QoS
marking and policing, multicast
replication, port mirroring (SPAN)
Port ASICs
Buffering, port QoS, scheduling,
congestion avoidance, shaping
EtherChannel, VLAN tagging,
broadcast suppression
Upsidevery high performance

DownsideASIC development
cycles relatively long
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Architecture
Switch Fabrics
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Switch Fabric
Provides the Connection between Slots/Ports in a Switch
Slot 1
Slot 0
Slot 2
Slot 3
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Non-Blocking Switch Fabric

Non-BlockingThe Sum of All Inputs
Is LESS THAN or EQUAL TO the
Capacity of the Switch Fabric
10x 1
Gbps
Ports
10x 1 Gbps Ports
60 Gbps Fabric
10x 1
Gbps
Ports
10x 1 Gbps Ports

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Over-Subscribed Switch Fabric

BlockingThe Sum of All Inputs Is
GREATER THAN the Capacity of the
Switch Fabric
10x 1
Gbps
Ports
10x 1 Gbps Ports
10 Gbps Fabric
10x 1
Gbps
Ports
10x 1 Gbps Ports

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How Does Traffic Run in a

Real Network?
10Gb
10Gb
One or Two
Active Uplink Ports
Each at 10Gb
80 Gbps Fabric
Rarely Do
Networks
Implement Fully
Non-Blocking
Designs
End User Ports

60 10/100/1000 Ports
Potential Upstream Traffic Load Is 60Gbps!
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Understanding Bandwidth
Bandwidth is the
capacity of the switch
fabricGbps
1 Gbps
1 Gbps
Exampleeach fabric
interface is capable of
1 Gbps TX and 1 Gbps
RX; therefore, in full
duplex, the bandwidth
is 2 Gbps
1 Gbps
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1 Gbps
13
Calculating Bandwidth
Local switching,
in theory, makes additional
bandwidth available
to the system
128 Gbps Central Fabric
However, a single stream of

traffic can consume
bandwidth on multiple
different fabrics
Additive numbers
often unrealistically high
Also, datasheet numbers are
always in full duplex
Marketing math numbers
are the de facto bandwidth
measurement in the industry
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32 Gbps
Local
Fabric
32 Gbps
Local
Fabric
32 Gbps
Local
Fabric
128 Gbps + 6 x 32 Gbps = 320 Gbps
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Understanding Throughput
Abuse of bandwidth
numbers means that
throughput values can be
more important
Switch Fabric
Throughput is the highest

rate at which packets can
be sent without packet loss
Measures capacity of
forwarding engine(s)
Measured in packets per
second (pps)
Local
Fabric
Local
Fabric
Local
Fabric
Only applicable at 64 byte

packetsdoes not
represent realistic
network traffic
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Calculating Throughput
Throughput numbers
can be abused as well
64 Gbps Switch Fabric
Keeping traffic local to

line card means that
you can add up the
local switching values
Not considered nonblocking to the
switch fabric
Does measure
maximum forwarding
capacity but does not
necessarily reflect realworld traffic flows
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32 Gbps
Local
Fabric
32 Gbps
Local
Fabric
32 Gbps
Local
Fabric
6 x 32 Gbps x 1.488 Mpps = 286 Mpps!
vs. 64 Gbps x 1.488 = 96 Mpps
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Shared Bus/Ring Switch Fabrics

Forwarding
Engine
Shared Ring
Fabric
Shared Bus
Fabric
Forwarding
Engine
Switching
Module
Switching
Module
Switching
Module
Switching
Module
Forwarding
Engine
Switching
Module
Switching
Module
Switching
Module
Forwarding
Engine
Typically oversubscribed architecture

Only one module/port can access the fabric at
any given time
Buffering typically implemented at module level,
not in fabric itself
Well-suited for multicast and broadcast traffic
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Switches Using
a Shared Fabric
Architecture
Catalyst 6500
Catalyst 3750
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Shared Memory Switch Fabrics

Switches Using
a Shared Memory
Architecture
Forwarding Engine
Shared Memory
Fabric
Switching
Module
Switching
Module
Switching
Module
Catalyst 3550
Buffering occurs on the switch fabric

Packets stored in shared memory
buffer while forwarding decision
is made
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Catalyst 4500
18
Crossbar Switch Fabrics

Forwarding
Engine
Switching
Module
Switching
Module
Crossbar
Fabric
Switching
Module
Switches Using
a Crossbar Fabric
Architecture
Switching
Module
Switching
Module
Multiple conflict free paths between modules

Very high bandwidth capacity, with dedicated
bandwidth per slot/interface
Signaling and scheduling more complex
Catalyst 6500
Handles HOLB, broadcast, and multicast with

internal overspeed
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Architecture:
Buffering and Queuing
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Why Do We Need to Buffer Traffic?

A
Contention
To A
To A
Buffering normalizes bursts from the network to an
outbound port
Buffering is required when
Multiple input ports are contending for bandwidth on the same output port
Speed mismatch exists between input and output ports (1000 Mbps to 100
Mbps port)
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Buffer AllocationContiguous Buffers

One 64-Byte
Frame Uses One
1500-Byte Buffer
Packet Buffer
One 256-Byte
Frame Uses One
1500-Byte Buffer
Wasted Memory
1500 Bytes
Buffer length fixed in size (typically to MTU)

Tradeoffs
Less expensive to implement than particle buffering
architectures
Inefficient use of overall buffer space
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Buffer AllocationParticle Buffers

Three 64-Byte
Frames Use 192
Bytes of Memory
Unused Memory
Packet Buffer
One 256 Byte

Frame Uses 256
Bytes of Memory
320 Bytes
Buffer length fixed in small increments (for example, 64 bytes each)

Tradeoffs
Allows for most efficient use of buffer space
More expensive to implement than contiguous buffering architectures
Cat 6500 writes to buffer in 32-byte increments; Cat 4000 in 256-byte

increments; Cat 3550 in 64-byte increments
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Where Does Buffering Happen

in a Switch?
Rx Buffering
Tx Buffering
Switching
Module
Receive Buffering
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Switching
Module
Transmit Buffering
Store-and-forward operation
Most efficient buffering point
Hold packet just long enough to

make a forwarding decision
Deeper buffers and queuing

structures on transmit
In shared memory architecture,

fabric itself is the first buffer
Helps to relieve HOLB
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Prevents congestion on output

interfaces
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Architecture:
Lookup Table Architectures
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Table Architectures
When building bridging, routing, or ACL lookup
tables, how is information stored and found?
Catalyst switches store this information in highspeed table memory
Table lookups use efficient search algorithms
and lookup keys
Catalyst switches implement two main table
architectures
CAM tables
TCAM tables
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CAM Tables
Content Addressable
Memory (CAM)
CAM
CAM
Very high speed lookup in

large tables
Binary operation
matches based on
0 or 1 values
Exact match returns hit
Useful for lookups where
lookup key must exactly
match a table entry (VLAN
+ MAC in bridge table)
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000
000
0101010101010101
0101010101010101
001
001
0101010101010111
0101010101010111
002
002
0101010101010001
0101010101010001
003
003
0101010101011101
0101010101011101
004
004
0101010101000101
0101010101000101
005
005
0101010101110101
0101010101110101
006
006
0101010100010101
0101010100010101
007
007
0101011101010101
0101011101010101
008
008
0101000101010101
0101000101010101
009
009
0101110101010101
0101110101010101
27
CAM Table ExampleCatalyst 6500

MAC Address Table
Bridge table
lookup requires
DMAC and
VLAN ID
Values fed into
hashing function
to generate
lookup key
Key is a pointer
to a specific
row in the CAM
Packet
VLAN
DMAC
Hash
Hash Function
Function
Row 006
Hit returns a
result (output port)
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CAM
CAM
000
000
0101010101010101
0101010101010101
001
001
0101010101010111
0101010101010111
002
002
0101010101010001
0101010101010001
003
003
0101010101011101
0101010101011101
004
004
0101010101000101
0101010101000101
005
005
0101010101110101
0101010101110101
006
006
0101010100010101
0101010100010101
007
007
0101011101010101
0101011101010101
008
008
0101000101010101
0101000101010101
009
009
0101110101010101
0101110101010101
8 Pages X
16,384 Entries
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Port 3/1
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TCAM Tables
Ternary Content Addressable
Memory (TCAM)
Mask 1
Very high-speed, fixed latency

lookups with wildcarding
Ternary operationmatches
based on 0, 1 or X (dont care)
Longest match returns hit
Memory structure broken into
groups of patterns and
associated masks
Mask 2
Masks used to wildcard some

bits in the patterns
Useful for lookups where not all
fields of lookup key must match
(CEF, ACL lookups)
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Masks
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 7
Pattern 8
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 7
Pattern 8
Patterns
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TCAM Table Example

CEF Prefix Lookup
Packet
Lookup
DIP
Key
Address
10.1.1.1
Key32-bit IP
Address
CEF prefix lookup requires

destination IP address
Destination IP used to create
32-bit lookup key
Key compared to all TCAM
entries in parallelas key is
compared, associated mask
is applied
Longest match hit returns
adjacency info
1=Compare
0=Mask
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10.1.1.2
10.1.1.2
10.1.1.3
10.1.1.3
255.255.255.255
255.255.255.255
172.45.33.1
172.45.33.1
192.168.1.191
192.168.1.191
10.10.10.10
10.10.10.10
10.9.8.7
10.9.8.7
172.16.199.12
172.16.199.12
192.168.1.1
192.168.1.1
172.45.33.
172.45.33.00
255.255.255.
255.255.255.00
10.1.1.
10.1.1.00
HIT!
192.168.1.
192.168.1.00
172.45.33.0
172.45.33.0
Masks
Wildcard Masks
Patterns
IP Prefixes
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Architecture:
Forwarding Architectures
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Centralized Forwarding
Single, central forwarding
engine for the system
Central engine performs all
forwarding operations for
the systemL2, L3, QoS,
ACLs, etc.
System performance gated
by performance of the
central forwarding engine
Forwarding
Engine
Switching
Module
Switching
Module
Switching
Module
Switching
Module
Switching
Module
Examples
Catalyst 4500
Catalyst 6500
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Distributed Forwarding
Switching decisions made
at port or module level
Forwarding tables
are synchronized across
engines for consistent
forwarding decisions
System performance is
equal to aggregate
performance of all
forwarding engines
This is how switches
achieve very high
forwarding performance
numbers
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Primary
Forwarding
Engine
Switching
Module with
Forwarding
Engine
Switching
Module with
Forwarding
Engine
Switching
Module with
Forwarding
Engine
ExamplesCatalyst
ExamplesCatalyst 3550/3750
3550/3750
Catalyst
Catalyst 6500
6500 with
with DFCs
DFCs
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Demand-Based Switching
Forwarding based on
traffic flows
First packet switched in
software by route
processor
Route
Processor
ASICs
Subsequent packets
switched in hardware
by ASICs
Flow consists of source
address, source/
destination addresses, or
full Layer 3 and Layer 4
information
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Routing Table
IP Prefix
10.44/16
10.99/16
0/0
Next Hop
10.4.1.1 via Gig6/1
10.1.2.1 via VLAN10
10.1.1.1 via Gig1/1
Hardware
Forwarding Table
SIP
10.3.3.3
10.4.4.4
10.5.5.5
DIP
10.44.1.1
10.99.1.1
172.1.1.1
Rewrite Info
SMAC DMAC Gig6/1
SMAC DMAC VLAN10
SMAC DMAC Gig1/1
Switching
Module
Switching
Module
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Switching
Module
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Demand-Based Switching Scalability

Processor Switching Speeds:
Thousands of Packets per Second
Route
Processor
Routing Table
IP Prefix
10.44/16
10.99/16
0/0
ASIC Switching Speeds:

Millions of Packets per Second
Hardware
Forwarding Table
ASICs
SIP
10.3.3.3
10.4.4.4
10.5.5.5
Next Hop
10.4.1.1 via Gig6/1
10.1.2.1 via VLAN10
10.1.1.1 via Gig1/1
DIP
10.44.1.1
10.99.1.1
172.1.1.1
Rewrite Info
SMAC DMAC Gig6/1
SMAC DMAC VLAN10
SMAC DMAC Gig1/1
Scalability of switch dependant on control plane performance

How fast can the system set up new flows in hardware?
How are network topology changes managed (route flaps etc.)?
What other tasks is the control plane responsible for (routing protocols,
ARP, spanning tree, etc.)?
How stable are critical control plane functions while flows are being
established?
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Topology-Based Switching
FIB Derived
from Routing
Table
Adjacencies
Derived from
ARP Table
Leverages and extends CEF model
Route
Processor
ASICs
IP forwarding tables (FIB and

Adjacency) built on control plane
FIB lookup based on destination

prefix (longest-match)
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ADJ
10.4.1.1 (DMAC) via Gig6/1
10.1.2.1 (DMAC) via VLAN10
10.1.1.1 (DMAC) via Gig1/1
Hardware CEF
FIB
10.44/16
10.99/16
0/0
Tables installed in ASIC hardware
FIB hit returns Adjacency,

Adjacency contains rewrite
information
CEF
FIB
10.44/16
10.99/16
0/0
ADJ
10.4.1.1 (DMAC) via Gig6/1
10.1.1.1 (DMAC) via Gig1/1
Switching
Module
Switching
Module
Switching
Module
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Topology-Based Switching Scalability

Route
Processor
CEF
FIB
10.44/16
10.99/16
0/0
ASICs
ADJ
10.4.1.1 (DMAC) via Gig6/1
10.1.1.1 (DMAC) via Gig1/1
Hardware CEF
FIB
10.44/16
10.99/16
0/0
ADJ
10.4.1.1 (DMAC) via Gig6/1
10.1.1.1 (DMAC) via Gig1/1
Scalability of switch dependant on forwarding engine performance

Not flow-basedhardware forwarding of first packet in each flow,
whether there are one or one million new flows
Hardware tables are identical to software tables
Hardware tables updated by software as network topology changes
Control plane unburdened by traffic forwardingdedicated to protocol
processing (routing protocols, ARP, spanning tree, etc.)
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Catalyst 3550 and 3750

Architecture and Operation
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Catalyst 3550 Architecture Overview

Fixed configuration
stackable switches
Employs distributed sharedmemory switch fabric
architecture
All forwarding decisions
implemented in Satellite
ASICsL2/L3/L4 forwarding
including CEF switching
Satellite ASICs manage a
port (GE) or group of
ports (FE)
Central CPU for system and
table management
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Catalyst 3550 Architecture

CPU
CPU Subsystem
Subsystem
Notify
Notify
Ring
Ring
SRAM
SRAM
TCAM
Shared
Shared
Memory
Memory
Fabric
Fabric
SRAM
SRAM
Switch
Channels
SRAM
SRAM
Satellite
Satellite
Satellite
Satellite
Fast
Ethernet
Interfaces
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Gigabit
Ethernet
Interface
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Satellite
Satellite
SRAM
SRAM
Satellite
Satellite
Fast
Ethernet
Interfaces
Gigabit
Ethernet
Interface
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Catalyst 3550 Packet Flow
Shared
Memory
Fabric
Switch
Channel
Payload Data Path
1
Packet
Satellite
1.
2.
3.
3 Headers
Satellite
Control Path
Packet arrives at the Satellite from port

Ingress Satellite ASIC makes forwarding decision (L2, L3,
policing, marking, etc.)
Satellite parses packet and
Sends header info on ring to egress portsControl Path
Sends packet payload to the shared memory switch fabric for temporary
storageData Path
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Shared
Memory
Fabric
Switch
Channel
Satellite
Data Path Payload 5

Headers
Control Path
4.
5.
6.
7.
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4 Satellite
6
Packet
Egress Satellite receives control info on ringRecognizing the

destination port(s)
Egress Satellite retrieves the packet from the shared
buffer for all destination ports
Egress Satellite performs packet rewrite, output ACL and policing,
and multicast expansion
Satellite sends packet out egress port(s)
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Catalyst 3750 Architecture Overview

Fixed configuration stackable
switches using StackWise
technology
Stacked switches function as a
single switch
Employs extensible shared-ring
switch fabric architecture
32 Gbps fault-tolerant
bidirectional rings interconnect
stacked devices
All forwarding decisions
implemented in Ethernet port
ASICsL2/L3/L4 forwarding
including CEF switching
Ethernet port ASICs manage
groups of Fast or Gigabit
Ethernet ports
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Catalyst 3750 StackWise Architecture
TCAM
TCAM
TCAM
TCAM
Ethernet
Ethernet
Port
Port ASIC
ASIC
TCAM
TCAM
Ethernet
Ethernet
Port
Port ASIC
ASIC
Ethernet
Ethernet
Port
Port ASIC
ASIC
Stack
Interface
CPU
Switch 1
Fast or
Gigabit
Ethernet
Interfaces
Fast or
Gigabit
Ethernet
Interfaces
Fast or
Gigabit
Ethernet
Interfaces
Stack
Rings
Switch 2
Switch 3
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Catalyst 3550 and 3750 TCAM

Architecture
The TCAM is used for storing
information required for
forwarding traffic
The available TCAM space is
shared amongst all entries
Sharing of these entries is
based on pre-defined
templates selected with the
sdm prefer command
Templates carve the TCAM
to suit the network
environmentrouting,
VLAN, etc.
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TCAM
Layer 2
Layer 3
ACL Table
QoS
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Catalyst 3550 and 3750 Security

ACL Support
Catalyst 3550 and 3750 series switches support

Router -based Access Control Lists (RACLs)
VLAN -based ACL (VACLs)
Identical support for 256 security ACLs on 10/100 configurations

Identical support for 1K security ACEs on 10/100 configurations
Security ACLs programmed in TCAM for hardware enforcement of
security policy
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Catalyst 3550 and 3750 QoS

Crosses
Fabric
QoS Actions
at Ingress Satellite/Port ASIC
QoS Actions
at Egress
Satellite/Port ASIC
Enters
Port
Rx
Classify
Ingress
Police
Rewrite
Egress
Police
WRR/SRR
Schedule
with
WRED/
WTD
Tx
Scheduling
Ingress (3750 only) and egress scheduling
Strict priority queuing (3750 available via
future software upgrade)
Egress Weighted Round Robin (WRR) with
WRED on 3550
Egress Shaped Round Robin (SRR) with
weighted tail-drop on 3750
Ingress
Schedule
with WTD
Policer support
128 ingress policers per GE on 3550
8 ingress policers per FE on 3550
8 egress policers per GE/FE on 3550
Traffic Classification and Marking
64 ingress policers per port on 3750
Based on default port CoS or L2/L3/L4

ACL policy
512 QoS ACEs for all 10/100 3550 and 3750
configurations
802.1p (CoS), ISL, DSCP, or IP ToS marking
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Rate Policing
Support per-interface and shared

aggregate policers
47
Catalyst 3550 and 3750 Performance
Catalyst 3550
Catalyst 3750
Catalyst 3550-12T/12G
17 Mpps throughput
24 Gbps capacity
35.7 Mpps throughput

Catalyst 3750G-24TS
Catalyst 3550-24
6.6 Mpps throughput
8.8 Gbps capacity

Catalyst 3750-24- TS
6.6 Mpps throughput
Catalyst 3550-48
Catalyst 3750-48TS
13.6 Gbps capacity

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Catalyst 3750G-24T
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32 Gbps StackWise capacity for all

Catalyst 3750 switches
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Catalyst 4500 Architecture and

Operation
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Catalyst 4500 Architecture

6-slot chassisone supervisor
with five module slots
7-slot chassisone or two
supervisors with five
module slots
Forwarding Engine (FFE)

Shared Memory
Fabric (PPE)
Supervisor 3 and 4 provide
Switching
Module
6 Gbps
Modules are transparent
Switching
Module
6 Gbps
Switching
Module
6 Gbps
6 Gbps bandwidth provided

to each module slot across
passive backplane
6 Gbps
Buffering and 64 Gbps fabric (Packet

Processing Engine, PPE)
6 Gbps
Central forwarding engine (Fast

Forwarding Engine, FFE)
Switching
Module
Switching
Module
Contain simple stub ASICs, PHYs

No buffering or local switching
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Catalyst 4500 Supervisor

Engine 3 and 4
Supervisor Engine
TCAMs
Shared Memory
Fabric (PPE)
Packet
Buffer
Switching Modules
Shared Memory Fabric ASIC (PPE)

Responsible for receiving, buffering, and transmitting packets, as
well as queuing, scheduling and rewriting
Forwarding Engine ASIC (FFE)

Responsible for Layer 2/3 forwarding, access control,
policing/marking, and packet replication
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Catalyst 4500 Packet Forwarding

Supervisor Engine
PLD
Forwarding
Engine (FFE)
2
Shared Memory
Fabric (PPE)
TCAMs
Packet
Packet
Buffer
1
Packet
Switching Modules
1. Frame arrives from switching module

2. PPE parses packet header and builds Packet
Lookup Descriptor (PLD) for the FFE
3. PPE stores packet in packet-buffer memory
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Supervisor Engine
4
PTD
6
Shared Memory
Fabric
PTD(PPE)
PLD
TCAMs
Packet
Packet
Buffer
Switching Modules
4. FFE performs forwarding table lookups based

on contents of PLD (packet headers)
5. FFE generates a lookup result in the format
of a Packet Transmit Descriptor (PTD)
6. PTD (lookup result) is sent to PPE
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Supervisor Engine
7
Shared
Memory
PTD
Fabric (PPE)
TCAMs
Packet
Packet
Packet
Buffer
9
Switching Modules
Packet
7. Based on PTD, PPE rewrites the packet headers, selects

transmit queue, and schedules packet for transmission
8. PPE retrieves packet from the packet-buffer memory
9. PPE transmits the rewritten frame to the egress
switching module
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Catalyst 4500 FFE Architecture

MAC Table
ACL/QoS
TCAM
Forwarding
Engine (FFE)
Layer 3
TCAM
To PPE
FFE uses several lookup tables to return forwarding result

Packet Lookup Descriptors (PLDs) are pipelined through the
FFE lookup engines
MAC addresses, FIB/Adjacencies, and ACL/QoS each have
dedicated memory
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Catalyst 4500 Security ACLs
Catalyst 4500 series switches support

Router -based Access Control Lists (RACLs)
VLAN -based ACL (VACLs)
Support for 1024 security ACLs (combination of security and

QoS ACLs)
Support for 16,384 input and 16,384 output security ACL ACEs
Security ACLs programmed in TCAM for hardware enforcement of
security policy
ACL entries installed in dedicated security ACL TCAM
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Catalyst 4500 QoS

Result
From FFE
Enters
Fabric
Rx
QoS Actions
at PPE
QoS Actions at FFE
Classify
Ingress/
Egress
Police
Leaves
Fabric
Dynamic
Buffer
Limiting
Rewrite
Shaping/
Sharing,
RR Schedule
Tx

Based on default port CoS or Layer 2/3/4
ACL policy
16K input/16K output QoS ACEs
802.1p (CoS), ISL, DSCP, or IP ToS marking
Rate Policing
1022 ingress and 1022 egress policers
Support per-interface and shared aggregate
policers
Scheduling
Egress scheduling (4 queues)
Shaping and sharing per queue
Strict priority queuing
Round robin scheduling
Dynamic buffer limiting for fair buffer

allocation
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Catalyst 4500 Supervisor Redundancy

Supervisor redundancy
only with Supervisor 4 in
4507R chassis
Route Processor
Redundancy (RPR)
Config is synched
Failover is non-stateful
Config must be parsed and
modules are reset
Failover in 2040 seconds
One uplink per supervisor

active in redundant
configuration
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Catalyst 4500 Supervisor 3 and 4

Performance
Catalyst 4500 Supervisor 3 and 4

48 Mpps throughput
64 Gbps capacity
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59
Catalyst 6500
Architecture
and Operation
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Catalyst 6500 Supervisor 2

Optional Multilayer Switch Feature
Card 2 (MSFC2) Daughter Card
Housing an Cisco IOS-Based
Routing Engine for Layer 3 Services
Policy Feature Card 2 (PFC2)

Daughter Card Housing ASIC
Complex for Hardware-Based
Forwarding and Features
The Supervisor Baseboard Contains the SP

CPU, SP DRAM/Flash, Backplane
Connectors, Rewrite Engine and Uplink Ports
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Supervisor 2 Architecture
32 Gbps
Bus
32 Gbps
Bus
8 Gbps
Crossbar
Supervisor 2
L2 Table
(CAM)
Fabric/Bus
Interface
NetFlow
MSFC2 DC
L2/L4 Engine
L3 Engine
Rewrite
Engine
MSFC2
CPU
Port ASIC
ACL
TCAM
QoS
TCAM
L3 FIB
TCAM
ADJ
PFC2 DC
NMP
CPU
GE
GE
GBIC GBIC
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Catalyst 6500 Supervisor 720

CPU Daughter Card Contains
the MSFC3 (Cisco IOS-Based
Routing Engine) and the Switch
Processor (L2 Engine)
Policy Feature Card 3A (PFC3A)

Daughter Card Housing ASIC
Complex for Hardware-Based
Forwarding and Features
Supervisor Baseboard Contains the

720Gbps Switch Fabric, Backplane
Connectors, Rewrite Engine and
Uplink Ports
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63
Supervisor 720 Architecture

32 Gbps
Bus
20 Gbps
Channels
Supervisor 720
PFC3 DC
L2 Table
(CAM)
FIB TCAM
and SSRAM
L2 Engine
ADJ
Table
Switch Fabric
Fabric/Bus
Interface and
Rewrite
Engine
CPU DC
Layer 3/Layer 4 Engine
ACL
TCAM
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QoS
TCAM
NetFlow
TCAM
NetFlow
Table
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MSFC3
CPU
Port ASIC
NMP
CPU
GE
SFP
GE
SFP
10/100/
1000 64
Switch Fabric Module and SFM2

Fabric module occupies
separate slot
6506/6509Slots 5/6
6513Slots 7/8
Fabric channels run at 8

Gbps FDX (8 Gbps in/
8 Gbps out)
Two fabric channels per
slot (except in 6513)
SFM6506 and 6509
SFM26506, 6509,
and 6513
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Supervisor 720 Switch Fabric
Fabric integrated on Supervisor

720 baseboard
6503Supervisor goes in slot 1/2
6506/6509 Supervisor goes in slot 5/6
6513Supervisor goes in slot 7/8
Fabric channels run at 20 Gbps

FDX (20 Gbps in/20 Gbps out)
Two fabric channels per slot
(except in 6513)
Fabric channels will each
independently auto-sync to
8 Gbps or 20 Gbps
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Catalyst 6500 Module Terminology

Old Style
ClassicModules that connect to the 32 Gbps switching bus. Use centralized CEF
Engine on PFCx for forwarding of 15 Mpps/system.
Fabric EnabledModules that connect to both the 256 Gbps fabric and the 32
Gbps Bus. Use centralized CEF Engine on PFCx for forwarding of 30 Mpps/system.
Fabric OnlyModules that connect to the 256 Gbps fabric only. Use the
distributed CEF Engine on the DFC for forwarding of 24 Mpps/slot.
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New Style
dCEF720
Forwarding
Architecture
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Fabric
Connection
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68

New Style
ClassicModules that connect to the 32 Gbps switching bus. Use centralized CEF
Engine on PFCx for forwarding of 15 Mpps/system.
CEF256Modules that connect to both the 256 Gbps fabric and the 32 Gbps Bus.
dCEF720
Use centralized CEF Engine on PFCx for forwarding of 30 Mpps/system.
dCEF256Modules that connect to the 256 Gbps fabric only. Use the distributed
CEF Engine on the DFC for forwarding of 12 or 24 Mpps/slot.
Forwarding
CEF720Modules
that take full advantage of 720 Fabric
Gbps fabric. These cards use
centralized CEF Engine on PFC3 for forwarding of 30 Mpps/system.
Architecture
Connection
aCEF720Modules that take full advantage of 720 Gbps fabric. These cards use an
accelerated CEF Engine for forwarding, with 48 Mpps/slot peak performance.
dCEF720Modules that take full advantage of 720 Gbps fabric. These cards use
the distributed CEF Engine on the DFC3 for forwarding of 48 Mpps/slot sustained.
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Catalyst 6500 Classic Modules

Support Catalyst 6500 32 Gbps
bus connection onlyno fabric
connection
Always use the central
forwarding engine on the
Supervisorno distributed
forwarding
Always place entire packet
payload on the 32 Gbps bus
Variety of interface types
10/100 Fast Ethernet
Gigabit Ethernet
Campus ATM
Services Modules
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Catalyst 6500 Classic Gigabit

Ethernet Module Architecture
32 Gbps Switch Fabric

WS-X6416-GBIC
16-Port Gigabit
Ethernet Module
Port ASIC
4 Ports
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Port ASIC
4 Ports
Port ASIC
Port ASIC
4 Ports
4 Ports
71
Catalyst 6500 CEF256 Modules

Support both 32 Gbps bus connection
and single 8 Gbps connection to 256
Gbps or 720 Gbps fabric
Use central forwarding engine on the
Supervisor by default, but Ethernet
cards can be upgraded to DFC/DFC3 for
distributed forwarding
Place only packet headers on bus in
central lookup systempayload always
passed over fabric
Variety of interface types
10/100 and 100Mb Fast Ethernet
Gigabit Ethernet
10 Gigabit Ethernet
Services Modules
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Catalyst 6500 CEF256 Gigabit

32 Gbps
Bus
WS-X6516-GBIC
16-Port Gigabit
Ethernet Module
Optional
DFC
L3
Engine
L2/L4
Engine
Dedicated 8 Gbps
Fabric Connection
Fabric
Interface
32 Gbps Local Switch Fabric
Rewrite
Engine
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Port ASIC
Port ASIC
4 Ports
4 Ports
Port ASIC
4 Ports
Port ASIC
4 Ports
73
Catalyst 6500 dCEF256 Gigabit

Ethernet
Supports dual 8 Gbps
connections to 256 Gbps or
720 Gbps fabricno 32 Gbps
bus connection
Uses onboard DFC/DFC3 for
Never uses the 32 Gbps bus
ingress lookups always on
module, and payload always
passed over fabric
Only one module falls in this
categoryWS-X6816-GBIC,
16-port Gigabit Ethernet GBIC
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Catalyst 6500 dCEF256 Gigabit

Dedicated 8 Gbps
Fabric Connection
Dedicated 8 Gbps
Fabric Connection
W S-X6816-GBIC
16-Port Gigabit
Ethernet Module
Fabric
Interface
Integrated
DFC
L3
Engine
Rewrite
Engine
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Port ASIC
Port ASIC
4 Ports
4 Ports
L2/L4
Engine
Fabric
Interface
Rewrite
Engine
Port ASIC
4 Ports
Port ASIC
4 Ports
75
Catalyst 6500 CEF720 10 Gigabit

Ethernet
connections to 720 Gbps fabric
Supports central CEF
forwarding and upgrade option
to dCEF (DFC3) at FCS
Upgrade option to aCEF (AFC3)
in future
Uses 32 Gbps bus for
CEF/aCEF lookupspayload
always passed over fabric
With DFC3, ingress lookups
always on modulebus is
not used
WS-X6704-10GE4-port
10GbE Xenpak
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Catalyst 6500 CEF720 10 Gigabit

Dedicated 20 Gbps
Fabric Connection
32 Gbps
Bus
32 Gbps
Bus
Dedicated 20 Gbps EOBC

Fabric Connection
W S-X6704-10GE
4-Port 10 Gigabit
Ethernet Module
LC CPU
CFC/AFC
TCAM
TCAM
ACEF Engine
Fabric Interface
and
Rewrite Engine
Port ASIC
1 10GbE Port
L2
Engine
ACEF Engine
L2
Engine
Port ASIC
1 10GbE Port
L3/L4
Engine
Fabric Interface
and
Rewrite Engine
Port ASIC
Port ASIC
1 10GbE Port
1 10GbE Port
Optional DFC3
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Catalyst 6500 dCEF720 10 Gigabit

Ethernet
connections to 720
Gbps fabric
Uses onboard DFC3 for
Never uses the 32 Gbps
busingress lookups
always on module, and
payload always passed
over fabric
WS-X6802-10GENonblocking 2-port
10GbE Xenpak
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Catalyst 6500 dCEF720 10 Gigabit

Dedicated 20 Gbps
Fabric Connection
W S-X6802-10GE
2-Port 10 Gigabit
Ethernet Module
Dedicated 20 Gbps EOBC

Fabric Connection
LC CPU
Integrated
DFC3 Layer 3/Layer 4
Engine
L2 Engine
Fabric
Interface
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Rewrite
Engine
L2 Engine
Rewrite
Engine
Fabric
Interface
Port ASIC
Port ASIC
1 10GbE Port
1 10GbE Port
79

Hardware-Based CEF Forwarding
Leverages and extends the existing Cisco
Express Forwarding (CEF) model
IP Forwarding Tables (FIB and Adjacency) built
on control plane
FIB and Adjacency tables downloaded to
hardware
Hardware FIB lookup based on destination prefix
(longest-match)
Hardware FIB hit returns Adjacency, Adjacency
contains rewrite information
Packet forwarded to next hop in hardware
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Supervisor 720 and Distributed

Forwarding Performance Summary
dCEF720400
dCEF720400 Mpps
Mpps Sustained
Sustained Performance
Performance
400+
Mpps
Accelerated
Accelerated CEF
CEF
400
400 Mpps
Mpps Peak
Peak
Performance
Performance
dCEF256210
dCEF256210 Mpps
Mpps Sustained
Performance
Throughput
(Mpps)
Centralized
Centralized CEF
CEF 30
30 Mpps
Mpps Sustained
Performance
30
Mpps
Infinite
Short
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Flow
Flow Duration
Duration
(Average
(Average ## Packets
Packets per
per Flow)
Flow)
81
CEF Forwarding with Supervisor 2

Central Forwarding
Supervisor 2
6548 Module
MSFC2
Routing Table
PFC2
Hardware FIB
6516 Module
3
256Gbps
Switch Fabric
Port ASIC
Fabric
Interface
8Gbps
8Gbps
8Gbps
8Gbps
Fabric 6
Interface
Port ASIC
Catalyst 6500 32 Gbps Switch Fabric

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Catalyst 6500 Distributed Forwarding

One or more modules have local
forwarding engine
Central engine and distributed engines all
perform different lookups independently
and simultaneously
Two methods of hardware-based
distributed forwarding in Catalyst 6500
Accelerated CEF (aCEF)
Distributed CEF (dCEF)
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Distributed Forwarding
Accelerated CEF vs. Distributed CEF
aCEF (Demand-Based)
dCEF (Topology-Based)
Advantages of distributed
forwarding at a lower cost
Fully hardware-basedno
CPU in the forwarding path
Central lookup engine on
Supervisor performs
first lookup
Ingress aCEF engine
performs subsequent
lookups locally
Performance varies
depending on traffic mix
aCEF720 module architecture
blocking at small
packet sizes
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Fully distributed forwarding

Highest performance
possible
FIB, Adjacencies, ACL/QOS
info downloaded from
Supervisor
Ingress DFC performs all
lookups locally
Highly scalablenot
flow-based
Deterministic performance
dCEF720 module architecture
non-blocking at small
packet sizes
84

Distributed Forwarding with aCEF
Supervisor 720
6704 Module
Fabric IF
and RW
Engine
Port ASIC
MSFC3
Routing Table
PFC3A
Hardware FIB
6802 Module
DFC3A
Hardware
Hardware FIB
FIB
Rewrite
Engine
20Gbps
20Gbps
720Gbps
Switch Fabric
20Gbps
20Gbps
ACEF ASIC
Port ASIC
Fabric IF
and RW
Engine
ACEF ASIC
Fabric
Interface
Port ASIC
Rewrite
Engine
20Gbps
20Gbps
6
20Gbps
20Gbps
Fabric
Interface
Port ASIC
Miss!
5

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Distributed Forwarding with aCEF
Supervisor 720
6704 Module
Fabric IF
and RW
Engine
Port ASIC
MSFC3
Routing Table
PFC3A
Hardware FIB
20Gbps
20Gbps
720Gbps
Switch Fabric
6802 Module
DFC3A
Hardware
Hardware FIB
FIB
Rewrite
Engine
20Gbps
20Gbps
ACEF ASIC
Port ASIC
Fabric IF
and RW
Engine
ACEF ASIC
Fabric
Interface
Port ASIC
Rewrite
Engine
20Gbps
20Gbps
4
20Gbps
20Gbps
Fabric
Interface
Port ASIC
Hit!

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86

Distributed Forwarding with dCEF
Supervisor 720
6704 Module
Port ASIC
Fabric IF
and RW
Engine
MSFC3
Routing Table
PFC3A
Hardware FIB
6802 Module
DFC3A
Hardware
Hardware FIB
FIB
Rewrite
Engine
3
20Gbps
20Gbps
720Gbps
20Gbps
20Gbps
Switch Fabric 4
ACEF ASIC
Port ASIC
Fabric IF
and RW
Engine
Fabric
Interface
Port ASIC
Rewrite
Engine
20Gbps
20Gbps
20Gbps
20Gbps
ACEF ASIC
Fabric
Interface
Port ASIC

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Catalyst 6500 Security ACLs

Security ACLs enforced in
hardware with no
performance penalty
Dedicated ACL TCAM ensures
ACL configuration does not
affect L2 or L3 forwarding
entry capacity
Sophisticated feature merge
algorithm allows multiple
ACL features to be applied
to a single interface
Dual-bank TCAM architecture
in Supervisor 720 reduces
requirement for merge
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Catalyst 6500 Security ACL Summary
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ACL Feature
Supervisor 2
Supervisor 720
RACLs
VACLs
Yes
Yes
ACEs
32K/4K
Entries/Masks
32K/4K
Entries/Masks
Dual-Bank TCAM
No
Yes
ACL Labels
512
512
LOUs
32
64
89
Catalyst 6500 QoS

Enters Forwarding
Engine
Enters
Port
Rx
QoS Actions
at Ingress
Port ASIC
Schedule
Crosses
Fabric
QoS Actions
at PFC/DFC
Classify
Ingress
Police
QoS Actions
at Egress
Port ASIC
Egress
Police
Rewrite
WRR
Schedule
and WRED
Leaves
Port
Tx
Scheduling
Ingress and egress scheduling
Rate Policing
Strict priority queuing

WRR with tail-drop or WRED
Queues per port varies by module

Based on default port CoS or
L2/L3/L4 ACL policy
32K QoS ACEs
802.1p (CoS), ISL, DSCP, or
IP ToS marking
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1024 aggregate ingress policers

on Sup2
1024 aggregate ingress/egress
policers on Sup720
Per-interface and shared
aggregate policers
63 microflow policers
User -based rate limiting (selectable
flow mask) on Sup720
90
Catalyst 6500 Supervisor Redundancy

Supervisor redundancy in
any chassis, any supervisor
CatOS High Availability
redundancy
Config is synced
Protocol state is synced,
including hardware L2/L3/L4
information
Stateful failover in 13 seconds
Cisco IOS RPR+

redundancy
Config is synched
Failover is non-stateful
Config preparsed and modules
are not reset
Failover in 30+ seconds
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91
Supervisor 2 Throughput and Bandwidth

Sup 2
Config
Sup2 supports
Classic, CEF256,
and dCEF256
modules
Any
w/o SFM
Throughput Bandwidth
(Mpps)
(Gbps)
15
*
Central
32
Shared
CEF256 Only
w/SFM
30
Central
16 per Slot
Classic +
CEF256
w/SFM
15
Central
32 Shared
16 per Slot
dCEF256
w/SFM
15 or 24
per Slot
16 or 32 per
Slot
*Also Applies to Sup1A

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Supervisor Engine 720 Performance

Important Points to Remember
Sup720 does not increase the performance of any

existing modules for L2/IPv4 forwarding; Sup720
does enable new features on all existing modules
The same principles for mixing classic and CEF256

modules apply to Sup720 as they do for Sup2+SFM
Mixing xCEF256 and xCEF720 modules does not

affect the performance of either series of module
RST-2011
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xCEF720 always uses 20Gbps/fabric channel, xCEF256

always uses 8 Gbps/fabric channel
93
Supervisor 720 Throughput and

Bandwidth with Next-Generation Modules
New modules leverage
high-speed channel
capacity of Sup720
2 x 20Gbps channels
per slot and higher
throughput numbers
in distributed system
Classic cards do affect
aCEF720 throughput,
but distributed
forwarding is still
possible!
RST-2011
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Sup 720
Config
Throughput Bandwidth
(Mpps)
(Gbps)
CEF720
Only
30 Central
80 per Slot
Classic +
CEF720
15 Central
32 Shared
80 per Slot
aCEF720
Only
Up to 48
per Slot
80 per Slot
Classic +
aCEF720
15
15 Central
Central
Up
Up to
to 48
48
per
per Slot
Slot
32 Shared
80 per Slot
dCEF720
48
per Slot
80 per Slot
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94
Summary
Cisco Catalyst switches

combine the latest and greatest
in processor and ASIC
technology
Leverage the processor to make
the system scale better
Leverage the ASICs to achieve
high performance with a rich
feature set
RST-2011
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Cisco Catalyst switches deliver

wide range of options at
different price points for
different networks
Stackables provide low-cost,
high-function switches for small
networks
Modular switches provide
additional functionality,
redundancy, interface types, and
features as well as a smooth,
flexible upgrade path
Architectures always evolving to
bring advanced new hardwareenabled features to market
95
LAN Switching
More Information @ Networkers
RST-2031/2032Designing Campus
Networks: Part 1 and Part 2
RST-3031Troubleshooting LAN
Protocols
RST-3041Catalyst 2900 and Catalyst
3500 Troubleshooting
RST-3042Catalyst 4000 and Catalyst
4500 Troubleshooting
RST-3043Catalyst 6500 Troubleshooting
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96
Recommended Reading
Cisco Field Manual:
Catalyst Switch
Configuration
ISBN: 1587050439
Building Cisco Multilayer

Switched Networks
ISBN: 1578700930
Cisco LAN Switching

ISBN: 1578700949
Available on-site at the Cisco Company Store
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97
Recommended Reading
Cisco Catalyst QoS: Quality
of Service in Campus
Networks
ISBN: 1587051206
Available in June 2003.
Available on-site at the Cisco Company Store

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Evaluation Form
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RST-2011

2003, Cisco Systems, Inc. All rights reserved.

Catalyst Switch Architecture

2003, Cisco Systems, Inc. All rights reserved.

Components of a Switch Architecture

2003, Cisco Systems, Inc. All rights reserved.

2003, Cisco Systems, Inc. All rights reserved.

Multilayer Switch Components

2003, Cisco Systems, Inc. All rights reserved.

Multilayer Switch Components

Processor supports critical

Upsidenew features easily

2003, Cisco Systems, Inc. All rights reserved.

Multilayer Switch Components

Upsidevery high performance

2003, Cisco Systems, Inc. All rights reserved.

2003, Cisco Systems, Inc. All rights reserved.

2003, Cisco Systems, Inc. All rights reserved.

Non-Blocking Switch Fabric

10x 1 Gbps Ports

10x 1 Gbps Ports

2003, Cisco Systems, Inc. All rights reserved.

Over-Subscribed Switch Fabric

10x 1 Gbps Ports

10x 1 Gbps Ports

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How Does Traffic Run in a

End User Ports

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2003, Cisco Systems, Inc. All rights reserved.

128 Gbps Central Fabric

However, a single stream of

128 Gbps + 6 x 32 Gbps = 320 Gbps

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Throughput is the highest

Only applicable at 64 byte

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64 Gbps Switch Fabric

Keeping traffic local to

6 x 32 Gbps x 1.488 Mpps = 286 Mpps!

vs. 64 Gbps x 1.488 = 96 Mpps

2003, Cisco Systems, Inc. All rights reserved.

Shared Bus/Ring Switch Fabrics

Typically oversubscribed architecture

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Shared Memory Switch Fabrics

Buffering occurs on the switch fabric

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Crossbar Switch Fabrics

Multiple conflict free paths between modules

Handles HOLB, broadcast, and multicast with

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2003, Cisco Systems, Inc. All rights reserved.

Why Do We Need to Buffer Traffic?

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Buffer AllocationContiguous Buffers

Buffer length fixed in size (typically to MTU)

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Buffer AllocationParticle Buffers

One 256 Byte

Buffer length fixed in small increments (for example, 64 bytes each)

Cat 6500 writes to buffer in 32-byte increments; Cat 4000 in 256-byte

2003, Cisco Systems, Inc. All rights reserved.

Where Does Buffering Happen