AAME Syllabus

ARM Accredited MCU Engineer
AA
AAME
Syllabus
Document number: ARM AEG 0073B
Copyright ARM Limited 2013 - 2014
ARM Accredited MCU Engineer

AAME Syllabus
Copyright 2013 - 2014 ARM Limited. All rights reserved.
Release information
The Change history table lists the changes made to this document.
Table 1 Change history

Date
Issue
Confidentiality
Change
28 August 2013
Non-Confidential
First release
10 January 2014
Non-Confidential
Minor updates and corrections
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Confidentiality status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject
to license restrictions in accordance with the terms of the agreement entered into by ARM and the
party that ARM delivered this document to.
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Copyright 2013 - 2014 ARM. All rights reserved.

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ARM AEG 0073B
Table of Contents
Table of Contents
ARM AEG 0073B
Introduction ................................................................................................................ 4
1.1 Scope .................................................................................................................. 4
1.2 Related documentation ....................................................................................... 4
1.3 Disclaimer ........................................................................................................... 4
Syllabus structure ..................................................................................................... 5

2.1 Difficulty Levels ................................................................................................... 5
2.2 Architecture and Product Applicability ................................................................ 5
2.3 Subject Area Weighting ...................................................................................... 6
Detailed Syllabus ....................................................................................................... 7

3.1 Architectural ........................................................................................................ 7
3.2 Software Development ..................................................................................... 15
3.3 Software Optimization ...................................................................................... 20
3.4 Software Debug ................................................................................................ 21
3.5 System Start-up ................................................................................................ 22
3.6 Implementation ................................................................................................. 23

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Introduction
Introduction
The ARM Accredited Engineer program provides a series of examinations which may be
taken by engineers and developers all over the world, in any company, giving them the
opportunity to become ARM Accredited Engineers.
We have defined a range of different exams, covering various different subject areas and
difficulty levels. This document is related to the second of those exams the ARM
Accredited MCU Engineer (AAME) exam which is focused on software aspects of
ARMv6-M and ARMv7-M architecture profiles or Cortex-M series microcontroller
technology.
1.1
Scope
This document provides full details of the exam syllabus for the standard-level exam. This
syllabus was developed during a two-day workshop held at the ARM headquarters in
Cambridge in early 2013. It is based on a top-down analysis of the job functions of a typical
ARM Accredited MCU Engineer, and the tasks and knowledge of ARM-based
microcontroller technology that would be required to successfully perform that job.
As well as the required knowledge areas for the standard-level exam, this document
indicates further areas which will be the subject of future advanced-level exams.
Note that this document describes the knowledge areas which will be covered by the exam
but does not fully specify the knowledge itself. The information which candidates will need
to study prior to sitting the examination is detailed in further standard and publicallyavailable reference documentation. See the list in the next section.
1.2
Related documentation
Learning resources for AAME Accreditation are available to download for free on the ARM
website.
Download learning resources for AAME Accreditation
1.3
Disclaimer
This syllabus is provided for information purposes only. ARM Ltd reserves the right
to update the syllabus and the corresponding exam content for any reason at any
time to maintain the validity and relevance of our certifications. In the event of any
changes to this syllabus, the updated syllabus will be posted on ARMs website in
advance of changes to the examination.

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Syllabus structure
2
2.1
Syllabus structure
Difficulty Levels
Each subject area in the detailed syllabus below is allocated a Difficulty Level. This is
indicated via a colored key next to each area. For the purposes of the standard-level
examination, candidates should ensure a detailed knowledge of all green subject areas
and should have a good awareness of those colored yellow. A red item is one about which
no knowledge is required in the standard-level examination.
Difficulty level key:
The candidate is expected to demonstrate a good knowledge of this subject.
Detailed questions will be included.
The candidate is expected to demonstrate an awareness or high-level
understanding of this subject. High (or overview) level questions may be
included.
The candidate is not expected to demonstrate knowledge of this subject at this
level. No questions will be included.
Note that this key only applies to the standard-level examination. Areas which are marked
as not applicable in this document may be graded differently in the context of future, more
advanced examinations.
2.2
Architecture and Product Applicability

This standard-level exam relates primarily to the ARMv6-M and ARMv7-M architectural
profiles together with the processor cores available from ARM which conform to these
architectures. Earlier versions of the architecture and earlier processor cores also form part
of the syllabus. Knowledge of products prior to ARM7TDMI and architectures prior to
ARMv4T are not required.
Only a basic awareness of ARMv7-A, ARMv7-R and conforming processors is required
e.g. the ability to classify application and real-time products according to architecture.
Familiarity with ARMs own software development tools is assumed.
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Syllabus structure
2.3
Subject Area Weighting

Each subject area is allocated a weighting which determines the approximate number of
questions which may be asked on that area in any one examination session. This should
be used as a guideline only when studying the syllabus. In particular, candidates should
not attempt to use this information to deduce how many questions will be presented on a
particular subject area.
Subject Area
1. Architectural
a. Exception model
b. MPU
c. CPU Registers
d. Modes and stacks
e. Instruction set
f. SYSTICK Timer
g. Memory model
h. Power modes
i. FPU
2. Software Development
a. Standards
b. Barrier usage scenarios
c. Determinism
d. Fault tolerance
e. Code generation
f. Image generation
g. RTOS
3. Software Optimization
4. Debug
a. Debug techniques
b. Debug facilities
5. Software Optimization
6. Debug
Total

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35%
7%
2%
5%
4%
6%
2%
4%
3%
2%
30%
5%
3%
6%
1%
8%
3%
4%
10%
13%
7%
6%
5%
7%
100%
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Detailed Syllabus
Detailed Syllabus
This section lists the detailed requirements under each subject area. Where necessary,
examples are given of typical knowledge required. These are examples intended to
illustrate the level of detail required of the minimally-competent candidate. Knowing these
items alone will not be sufficient to pass the examination. In some areas, examples are
also given of knowledge which a more capable candidate is likely to have.
For clarity, items which are not required knowledge for this examination (those which are
coded red) are grayed out in the table.
3.1
3.1.1
Architectural
Exception model
a) Core exceptions
How to enable faults
Candidates should know how the FAULTMASK register is used to enable and
disable exceptions including HardFaults, except NMI. They should also know how to
use PRIMASK to disable all except HardFault and NMI.
NMI
Candidates should know what NMI is typically used for; that it cannot be disabled;
what distinguishes it from other interrupts and why it is important to have NMI in
addition to other interrupts.
More advanced candidates will know that it has priority -2; that its vector address is
at offset 0x8 in the vector table; the circumstances in which NMI will not be taken
immediately.
Fault Handlers
Candidates should know which faults are defined by the ARMv7-M and ARMv6-M
architectures; what causes these faults; that all faults except HardFault can be
disabled.
More advanced candidates will be aware of the circumstances under which a hard
fault is generated; the differences between the set of faults defined by ARMv7-M and
ARMv6-M.
SVC
Candidates should know what SVC is typically used for; what causes an
SVCallexception and how to use the SVC instruction.
More advanced candidates should know that SVC is a precise exception.
Debug
Candidates are not expected to demonstrate knowledge of this subject.
SysTick
Candidates should know that the SysTick timer is part of the architectural definition
of the NVIC. They should also know how to program it to generate a simple
repeating downcounter.
More advanced candidates would know that it can be driven either by the internal
processor clock or by the external reference clock input.
Fault escalation
Candidates should know under what circumstances faults are escalated.
More advanced candidates would know how to determine the original fault that
caused the escalation.
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Imprecise and precise faults

Candidates are not expected to demonstrate knowledge of this subject..
Synchronous and asynchronous faults

Candidates are not expected to demonstrate knowledge of this subject...
Exception handling
Candidates should know the sequence of actions that the processor takes when
handling an exception; at what point the pending status is cleared and how to clear a
pending interrupt before it is taken.
Advanced candidates would know what happens if an interrupt is pended while
disabled, or reasserted while active.
PendSV
Candidates should know the PendSV exception exists and have an understanding
of why it might be used.
Advanced candidates would know, for example, that defining PendSV with the
lowest priority in the system can be used to avoid significant OS overhead while
IRQs are being executed.
Reset
Candidates should know that Reset cannot be masked or disabled; that it has the
highest priority in the system; that the initial SP and execution address are the first
two words in the vector table and that self-reset can be triggered under software
control.
More advanced candidates would know that it has priority -3.
b. Interrupt handling
Level or edge sensitive interrupt channel
Candidates should know the difference between level and edge sensitive interrupts
and understand the importance of clearing a level-sensitive interrupt before exiting
the exception handler.
More advanced candidates would know that multiple pulses on an edge-sensitive
input cause the interrupt to be pended only once.
Re-entrant interrupt handler

Candidates should know that re-entrant interrupts are not supported.
More advanced candidates should know how to generate deferred system services
from within an exception handler using PendSV exception.
Enable and disable interrupts

Candidates should know how to enable and disable interrupts using PRIMASK; how
to enable and disable individual interrupts in the NVIC and how to clear or set
pending status for an individual interrupt.
More advanced candidates will know how to disable interrupts below a certain
priority using BASEPRI.
Vector table relocation

Candidates should know that the vector table can be relocated under software
control.
Advanced candidates would be aware of common reasons for relocating the vector
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Register stacking
Candidates should know what registers are stacked automatically by the processor
and how to stack further registers if they are required by the interrupt handler.
Advanced candidates should know in which order the registers are laid out in
memory; how much space to allow for this; that the stack must be aligned properly
and understand how STKALIGN does this.
Exception return value

Candidates should know that there is no special return-from-interrupt instruction but
that it is triggered by a special value in LR.
Advanced candidates will know what form the EXC_RETURN value takes; how this
is used to control mode and stack on return and which instructions can be used to
return from an exception handler.
Vector table
Candidates will know the default location of the vector table; the contents of the first
four words; that entries 16 and upwards are used for IRQ vectors and that the vector
table is relocated to 0x00000000 after a reset.
More advanced candidates will be able to calculate the address of an individual
vector from the exception number; that all entries must have LSB set to 1 (apart
from the initial stack pointer value).
Lazy stacking
Candidates will be aware of the potential impact of stacking FPU registers; that lazy
stacking helps with this and that the available options are always/never/lazy.
More advanced candidates will know how many extra registers need to be stacked
when using an FPU; the circumstances under which they will be stacked (lazy or
otherwise) and how to configure the lazy stacking mode.
SVC
Candidates should know what happens to the comment field; how to pass
parameters to an SVC handler and how to return results.
More advanced candidates will know how to retrieve the comment field from the
SVC instruction.
Interrupt priority levels and groups

Candidates will know that priority values are split into two variable-sized fields; how
these fields are used; that the size of the fields is programmable and that the total
size of the priority field registers is synthesis-configurable.
Advanced candidates will know that lower bits are removed when the number of
priority bits is reduced; how to configure the size of the priority group field; what its
reset value is.
Runtime interrupt configuration (BASEPRI, PRIMASK, FAULTMASK)

Candidates should know what the function of each of these is; how they interact with
interrupt priorities.
More advanced candidates will know that FAULTMASK is automatically cleared on
exception exit except in the case of NMI.
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3.1.2
MPU
a)
MPU initialization
Candidates should know how to setup the MPU to provide a single region with full
access.
More advanced candidates should know how to check whether the MPU is present.
b)
Memory attributes
Candidates should be aware of the three basic memory types; the intended use of
each and understand the importance of configuring peripheral regions as Device
memory.
Advanced candidates should be aware of the XN attribute and what it might be used
for.
c)
Region overlap
Candidates should know that there are up to eight regions; what happens when
regions overlap; and the background region feature.
More advanced candidates should know about sub-region disable and what this
might be used for.
d)
Region priority
Candidates should know that each region has a fixed priority.

More advanced candidates should know that it is important to write and enable an
appropriate fault handler before enabling the MPU.
e)
Region alignment
Candidates should know that regions must be aligned according to their size.
f)
How to enable and disable the MPU
Candidates should know how to enable and disable the MPU

More advanced candidates should know that it is important to write and enable an
appropriate fault handler before enabling the MPU.
g)
Differences between ARMv6-M MPU and ARMv7-M MPU
Candidates should be aware of the main differences between the ARMv6-M and
ARMv7-M MPUs. For example, some attributes are not supported on ARMv6-M,
while ARMv7-M supports smaller regions.
h)
Aliased MPU registers
Candidates should know that aliased registers allow multiple regions to be

programmed in faster operations.
3.1.3
CPU Registers
a)
Special registers
Candidates will be aware of PSRs, PRIMASK, FAULTMASK, BASEPRI, CONTROL

and will understand the basic function of each.
Advanced candidates will be able to name the fields in the PSRs and be aware of
their function.
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b)
Register bank
Candidates will be aware that the core has 13 general purpose registers (r0-r12),
stack pointer (r13), link register (r14) and program counter (r15).
Advanced candidates will know that r0-r7 are accessible by more instructions than
r8-r12; that the value of PC is 4 ahead of the current instruction; that the LSB of the
value loaded into PC should always be set to 1 and that the LSB of PC will always
be 0.
3.1.4
Modes and stacks
a)
Stack alignment
Candidates should know that the stack pointer should always be aligned to a
doubleword boundary at public interfaces and that a full descending stack model is
used..
Advanced candidates should be aware of the STKALIGN feature and why it is
necessary to write code which is AAPCS-compliant.
b)
MSP, PSP
Candidates should be aware that there are two stack pointers; that MSP is selected
at reset and that it is initialized from the first word of the vector table.
More advanced candidates will know how to configure for PSP use
c)
Privilege
Candidates will know that there are two privilege levels; that handler mode is always
privileged; that thread mode can be configured to be unprivileged; that certain
operations (e.g. NVIC configuration) can only be carried out in privileged mode and
that unprivileged programs need to use SVC to access privileged features.
Advanced candidates will know how to set the privilege configuration and what
happens if a privileged operation is attempted in unprivileged mode.
3.1.5
Instruction Set
a)
SIMD
Candidates should know that ARMv7E-M adds SIMD instructions and is currently
implemented in the Cortex-M4 processor; that these instructions are capable of
carrying out parallel operations on vectors of data items and that they are aimed at
accelerating common signal and video processing algorithms.
b)
Addressing modes
Candidates should be aware of pre-index and post-index addressing and optional

base register auto-update
More advanced candidates will know that the offset can be shifted left by a
maximum of 3 bits; that the offset can be positive or negative and that 32-bit
instructions allow a larger offset than 16-bit instructions.
c)
Data processing instructions
Candidates should be familiar with the basic set of data processing instructions, their
syntax and operation.
Advanced candidates will be familiar with more unusual instructions such as CMN,
SX??, UX??, RSB, CLZ, BF?.
d)
Multiply and divide
Candidates will be aware that some of these processors support hardware division;
be familiar with the syntax and operation of SDIV/UDIV, MUL, MLA.
More advanced candidates will be familiar with more unusual instructions such as
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UMULL, SMULL, SMLAL, UMLAL.
e)
Multiple load/store
Candidates will be familiar with POP, PUSH, LDM, STM, that IA and DB are the only
distinct addressing modes; with base register auto-update.
Advanced candidates will be familiar with the order in memory in which registers are
placed by these instructions.
f)
Saturated arithmetic instructions
Candidates will be familiar with the concept of saturated arithmetic and saturation
and understand what these instructions might be used for.
More advanced candidates will understand the syntax and operation of the USAT
and SSAT instructions, the function of the Q flag.
g)
Load/store instructions
Candidates will know the data sizes support by LDR and STR (doubleword, word,
halfword, byte); that LDR supports signed and unsigned data; the alignment
restrictions on addresses and that ARMv6-M does not support unaligned accesses.
More advanced candidates will be aware of the consequences of using unaligned
addresses.
h)
Differences between subsets
Candidates will know that ARMv6-M, ARMv7-M, ARMv7E-M support differing

subsets of the Thumb instruction set; that ARMv6-M supports the smallest subset
and ARMv7E-M the largest; that ARMv7E-M introduces SIMD instructions; that
floating point support is an optional extension to ARMv7E-M.
More advanced candidates will know that ARMv6-M only supports 16-bit instructions
with a small number of 32-bit system instructions.
i)
Conditional execution
Candidates will know that Cortex-M processors support conditional branches; that
other instructions can be made conditional using IT; that for most 32-bit data
processing instructions the S bit indicates whether the flags are changed or not and
that with 16-bit instructions there is no choice.
Advanced candidates will know how to construct a syntactically correct IT block of
up to four instructions containing opposite conditions; that IT is not available on
ARMv6-M and that IT progress is recorded in reserved bits in EPSR.
j)
Exclusive operations
Candidates will be aware that LDREX and STREX are used to construct lock/unlock
sequences.
More advanced candidates will know that these instructions rely on a lock flag in the
memory system and be familiar with the syntax of the instructions.
k)
Barriers
Candidates should know that barrier instructions enforce memory access ordering
and be familiar with the differences between DMB, DSB and ISB.
More advanced candidates would be able to insert DMB/DSB instructions in simple
example sequences to ensure correct operation.
l)
Special Register Access Instructions
Candidates will know that MSR/MRS instructions are used to access special
registers.
More advanced candidates will know that only the APSR can be changed when in
unprivileged mode.
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3.1.6
SYSTICK Timer
a)
SYSTICK calibration
Candidates will be aware of the SYSTICK TENMS calibration register and its
purpose.
More advanced candidates will know about the SKEW register and what it means.
b)
Correct sequence to initialize SYSTICK timer
Candidates will know the sequence required to initialize the timer.

3.1.7
Memory Model
a)
Memory types
Candidates will be aware of the supported memory types and their respective
properties.
More advanced candidates will know that bufferable transfers can complete
immediately in the write buffer and that external memory will be updated at some
later time; that instruction execution can continue immediately.
b)
Default memory types
Candidates should know that there is a default, fixed address map consisting of 8 x
0.5GB regions, which defines memory attributes and access permissions. They
should also know what can be located in each defined area of that map. The
memory attributes and access permissions can be changed by programming the
optional Memory Protection Unit (MPU) under software control.
More advanced candidates will know which regions carry the XN attribute .
c)
System control space (SCS)
Candidates should be aware that SCS access is privileged, little-endian, aligned

accesses only; that it contains registers for configuring e.g. MPU, SYSTICK, NVIC,
debug and that it contains the System Control Block.
More advanced candidates will know that the SCS region is classed as Stronglyordered memory and know where it appears in the address map
d)
Endianness
Candidates should know that instruction accesses are always little-endian; that
endianness of data accesses on ARMv7-M is configurable at reset-time by a
hardware signal; that instructions are available to support mixed-endian operations
in software. For example, REV, REV16 and others; that the compiler must be
configured to match the hardware.
More advanced candidates should be aware of the syntax and operation of REV,
REV16 etc.
e)
Alignment
Candidates should be aware of the situations in which unaligned accesses might be

generated; that some peripherals may not handle unaligned access correctly
f)
Peripheral control space
Candidates should be aware that there is a specific region of memory which is

reserved for memory-mapped peripherals and that this region is non-cacheable but
bufferable.
More advanced candidates will know where in the address map this region appears.
g)
Vendor specific space
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h)
Code space
i)
Architectural/implementation requirement for barriers
Candidates should know that certain system operations architecturally require use of
barriers to ensure correct operation.
Advanced candidates should be able to indicate, given a selection of barriers, which
of them are architectural requirements. They should also be aware that some
processor implementations will function correctly without the barriers but the barriers
should still be inserted as required by the architecture for portability.
3.1.8
Power modes
a)
WFE
Candidates should be aware of the WFE instruction; what events can cause
execution to resume after a WFE instruction and that resuming execution clears any
pending events.
More advanced candidates should know that WFE will not cause entry to sleep
mode if an event is already pending..
b)
WFI
Candidates should be aware of the WFI instruction and know what events can cause
execution to resume after a WFI instruction.
More advanced candidates should know that an interrupt which is currently disabled
will not cause execution to resume but that if the interrupt is enabled and PRIMASK
is set to 1, execution will resume but the interrupt will not be taken..
c)
SEV
Candidates should be aware that the SEV instruction can be used to send an event
to another processor in the system or to set the internal event pending status.
d)
WIC
Candidates should be aware that the WIC is an optional component and that it
enables interrupts to be detected when the processor is in power down mode or
clock-gated.
e)
Power modes (e.g. Awake, Sleep, Deep Sleep, Sleep on Exit etc.)
Candidates should be aware of available modes; the relative power saving of each
mode; the relative cost of entry and exit for each mode; how to configure the sleep
on exit feature and how to configure entry to deep sleep.
More advanced candidates should be aware that, in some devices, the SYSTICK
timer may stop in deep sleep mode.
f)
Debug and power
Candidates should be aware that when a debugger is attached, some power-saving

features may not be available.
3.1.9
FPU
a)
Floating point data types
Candidates should know that single precision floating point may be supported in
hardware but double precision is handled by a runtime library.
b)
Compiler options
Candidates should know that a suitable target processor must be specified in order
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for the compiler to use VFP instructions and that it is possible to compile software
which includes floating point operations so that the FPU, even if present, is not used.
c)
ABI
Candidates should know that there are hard (parameters passed in VFP registers)
and soft (parameters passed in core registers) options for the ABI and that the hard
option can provide lower performance than the soft option when many double
precision operations are performed, even when there is an FPU present.
d)
Hard and soft linkage
Candidates should know that hard linkage passes parameters in VFP registers and
soft linkage passes parameters in core registers and that there is a hybrid linkage
which passes parameters in core registers even when the FPU is present. They
should also know that this model allows for FPU support to be included at link time
rather than compile time.
e)
How to enable the FPU
Candidates should know how to enable the FPU via CPACR and that this can only
be carried out in privileged mode.
Advanced candidates should know that the FPU may be enabled for full or
privileged-only access.
f)
Lazy stacking
Candidates should know that lazy stacking is a means of reducing the impact of the
FPU register set on exception latency. They should know that an extra 17 registers
(S0-S15, FPSCR) must be stacked if FPU context has to be saved and that lazy
stacking is enabled by default.
g)
Rounding modes
Candidates should know that Round to Nearest, Round towards Plus Infinity, Round
towards Minus Infinity and Round towards Zero are supported and that Round to
Nearest is the default.
h)
How to detect floating point exceptions
i)
NaNs
3.2
Software Development
3.2.1
Standards
a)
ARM ABI (AAPCS, C++ ABI)
Candidates should be aware of the ARM ABI, specifically the Procedure Call
Standard for the ARM Architecture (AAPCS). They should know that it specifies
register usage across function calls; that R0-R3 are designated for input parameters;
that R0-R1 are used for return values; that the stack pointer must be set to a
doubleword aligned address at public boundaries.
More advanced candidates would know the difference between caller-saved and
callee-saved registers and that S0-S15 are caller-saved registers if FPU is present.
b)
MISRA
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c)
UAL.( Unified Assembly Language)
Candidates should know that UAL is a common syntax used for all subsets of
instructions i.e. Thumb, Thumb-2, 16-bit only Thumb etc and that 2-operand
instructions should be written in 3-operand form.
More advanced candidates will know that .N. and .W suffixes can be used to specify
instruction width..
d)
CMSIS-DSP
Candidates should know that CMSIS-DSP is a library of common signal processing

and mathematical functions; that it is targeted and optimized at the Cortex-M4
processor; and is available for the Cortex-M3, Cortex-M0 and Cortex-M0+
processors, and that it is freely available.
e)
CMSIS-CORE
Candidates should know that CMSIS-CORE is a standard set of APIs for application
and middleware; that it supports all available Cortex-M microcontrollers and that it
provides toolchain-agnostic access to machine-specific features (e.g. instructions
like WFI).
More advanced candidates will know that the standard initialization function in
CMSIS-CORE is called SystemInit().
f)
CMSIS-RTOS

3.2.2
Barrier Usage Scenarios
a)
Barrier usage scenarios (Application Note 321)
Candidates should be aware of the situations in which barriers may be required and
that some of these requirements are architectural. They should be aware that an ISB
is required after changes to the CONTROL register and that a DSB instruction
should be executed immediately prior to WFI or WFE.
3.2.3
Determinism
a)
Interrupt latencies
Candidates should know the standard interrupt latencies of different Cortex-M

processors, with zero wait state memory and that the latency may be extended if the
processor is already servicing another exception of equal or higher priority.
Advanced candidates would know that interrupts occurring during an unaligned
memory access or bit band access may have slightly longer latency.
b)
Tail chaining
Candidates should know that tail-chaining takes place when the processor finishes
an exception handler and immediately services an already pending exception and
that this avoids the need to unstack and restack context.
c)
Preemption
Candidates should know that an exception of higher priority may interrupt a currently
executing exception handler; that this process is called preemption; that
preemption depends only on the preempt priority field in the Priority Level Register.
More advanced candidates should know that a new exception can interrupt the
unstacking operation of a previous exception and that this is called pop
preemption.
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d)
Late arrival
Candidates should know that a processor can accept a new exception request after
the stacking process has started for a prior exception; that this process is called late
arrival.
e)
Cycle counts
f)
Interruption of multi-cycle instructions
Candidates should know that multiple cycle instructions may be interrupted and
restarted following completion of the exception handler and that Cortex-M3 and
Cortex-M4 processors permit LDM/STM to be interrupted and resumed.
Advanced candidates will know that the Interrupt-Continuable Instruction status
information is stored in EPSR and that this shares the same space as IT execution
status, meaning that LDM/STM in an IT block will be abandoned and restarted rather
than interrupted and resumed.
g)
Pre-fetching
Candidates should know that due to the pipeline nature of the processor, by the time
an instruction is being executed, some of the subsequent instructions have already
been fetched by the processor.
Advanced candidates should know that executing an ISB instruction can flush the
fetch buffer.
h)
Division algorithm

3.2.4
Fault Tolerance
a)
Stack overflow detection
Candidates should know common techniques for detecting stack overflow e.g.
locating stack near the bottom of SRAM; setting watchpoint below stack.
Advanced candidates would know how to use the MPU to configure an inaccessible
(or read-only) region below the stack area.
3.2.5
Code generation
a)
Thumb instruction set (16-bit and 32-bit)
Candidates should know 32-bit instructions can be positioned in unaligned

addresses; most of the 16-bit instructions cannot access high registers; some of the
operations can be carried out by either 16-bit instruction or 32-bit instructions; and
most of the 16-bit data processing instructions update APSR (apart from the special
case of inside an IT instruction block).
b)
Candidates should know C compilers can put local variables in stack or in registers
and that typically data structures are used for peripheral registers definitions.
c)
Unaligned data access
Candidates should be aware that unaligned data accesses are slower than aligned
accesses; that they are not supported by the Cortex-M0 and Cortex-M0+
processors; that they are not supported for load/store multiple instructions.
More advanced candidates should know that the Cortex-M3 and Cortex-M4
processors can be configured to generate a fault on unaligned accesses; and
unaligned exclusive transfers are not permitted.
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d)
Packed
Candidates should be aware that potentially unaligned data items can be declared
as packed; that this can also be used to remove padding from structures or arrays
of structures.
e)
Literal pools
Candidates should know what a literal pool is; that the compiler will place literal data
in the code section and that this data is accessed using PC relative instructions
Advanced candidates should be aware of the need to use the LTORG/.pool directive
to place literal pools when writing assembler and be aware that ALIGN statements
might be required before and after literal pool definitions.
f)
Veneers
Candidates should be aware that a veneer is a small piece of code inserted by the
linker to extend the range of a branch instruction by becoming the intermediate
target of the instruction and then setting the PC to the destination address.
More advanced candidates will know that this enables the veneer to branch
anywhere in the 4 GB address space
g)
Interworking
Candidates should know that the system must always execute in Thumb state and
that transitions to ARM state are not permitted.
More advanced candidates will know that the T bit in EPSR is always set to 1 and
that the LSB of function and return addresses must always be set to 1.
h)
NOP Insertions/Wide instructions
i)
Branch limitations
Candidates should know that for ARMv7-M branch instructions can be 16-bit or 32bit, and 32-bit version offers a larger branch offset than the 16-bit version. They
should also know that the BL instruction in ARMv6-M is 32-bit (the same as ARMv7M).
Advanced candidates should know that CBZ and CBNZ instructions are forward
branch only.
j)
Position independent code/data
Candidates should know that ARM processors support Position Independent

code/data, but additional compiler switches are required; and position independent
code can have a small additional code size and execution cycle overhead.
k)
Differences between CMSIS intrinsic and compiler intrinsic
l)
Use of volatile
Candidates should know that variables corresponding to memory-mapped registers

and those which can be changed by exception handlers should always be declared
with the volatile keyword and should understand why this is necessary.
Advanced candidates will know that bit band locations should be declared as
volatile; also variables used as locks with LDREX/STREX
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3.2.6
Image generation
a)
C Library Variants
Candidates should know that many C functions require C runtime library code to be
inserted to the program image by the linker; and various choices of C runtime
libraries can be available.
b)
Weak definitions and reference
Candidates are not expected to demonstrate knowledge of this subject
c)
Compiler and linker options
Candidates should know that in most cases maximum speed optimization will result
in larger code size.
d)
Techniques for estimating stack requirements
Candidates should know common techniques for estimating stack requirements

e.g. filling with a pre-defined pattern, static output from compiler/linker.
Advanced candidates will be aware of the limitations of these techniques e.g. need
for worst-case run, not taking account of exception stack usage etc
3.2.7
RTOS
a)
Timers and RTOS
Candidates should know that an RTOS requires hardware timer interrupts, and the
SysTick is designed for this. They should know that when an RTOS is used, the
application code should not use SysTick directly; if an RTOS is not used, the
application code can use the SysTick for periodic exception generation or for timing
measurement/time keeping.
b)
Support of MPU
Candidates should know that some RTOS can utilize MPU to isolate memories for
different tasks.
Advanced candidates should know that an RTOS can reprogram the MPU
configuration for each context switch.
c)
Use of privilege model
Candidates should know that some RTOS can run application tasks in unprivileged
mode to maximize memory protection.
d)
Lazy stacking support
Candidates should know that some RTOS may require lazy stacking to be enabled
during context switching.
e)
Use of architectural support for RTOS
f)
OS aware debugging (ITM channel 31)
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3.3
Software Optimization
3.3.1
Code generation
a)
Restrict keyword
Candidates should know that the restrict keyword helps avoid pointer aliasing issues
in C and that this is important when writing loops which the compiler can unroll
effectively.
b)
Which features affect performance (e.g. memory Wait States)
c)
Vectorization
Candidates should be aware that certain algorithms and loop structures can be
accelerated by simple transformations which make use of SIMD instructions. They
should know the compiler switches which enable this and should be aware of how to
facilitate this in C code.
More advanced candidates would be aware of the SIMD instructions involved.
d)
Parameter passing
Candidates should know that the parameter passing mechanism is defined by the
AAPCS and that in simple cases input parameters are passed using R0 to R3, and
return values are passed using R0 (or R0+R1 for 64-bit results)
Advanced candidates would know that passing of lots of parameters to functions can
result in slower performance, and that this can be avoided by placing the parameters
in a data structure and just passing a pointer to the data structure. They should also
know that when using C++ a this pointer may also be passed, reducing the number
of registers available for passing other parameters.
e)
Code inlining
f)
Loop unrolling
g)
Data types and alignment
Candidates should know that word-sized variables are more effective in looping and
indexing; that items should be naturally aligned in memory for best performance.
h)
Memory types
Candidates should know that peripherals can be defined as having memory type of
Device or Strongly-ordered, but Device is better for performance reasons.
Advanced candidates should know that architecturally the processor can
reorder/resize accesses to, or speculatively read a location with Normal memory
type.
i)
Code placement
Candidates should know that it is essential for address 0x0 to contain MSP and
address 0x4 to contain the reset vector in order for the system to boot up (though
this location can be aliased at reset), but that the boot code pointed to by the reset
vector can be in any executable region. Candidates should also know that program
code can be executed from SRAM.
j)
Branch target alignment
Advanced candidates should know that a branch target that is an unaligned 32-bit
instruction might take an extra cycle to execute.
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3.4
Software Debug
3.4.1
Standard debug techniques
a)
Debug monitor vs. halt mode
b)
Vector catching
Candidates should know that the vector catch feature can be used to cause a debug
event when reset or fault exceptions occur.
Advanced students should know how to program the vector catch feature (via the
DEMCR register).
c)
Determining exception cause using DFSR, xPSR, Link Register
d)
Call stack
Candidates should know what a call stack is and how the information it contains
might be interpreted when debugging.
e)
Run control
Candidates should know that processors can be started and stopped under
debugger control; that various types of single-step are usually available (e.g. stepover, step-into etc).
f)
Printf
Candidates should know that printf-style debugging is a common technique and that
it can be used without a debugger connected (provided that a suitable output device
is available).
Advanced candidates should know printf can increase code size, SRAM
requirements and can result in timing and program behavior being affected
g)
Exception trace event
Candidates should know that exception event trace is available on Cortex-M3 and
Cortex-M4 devices, and this enables users to examine a history of exception events
via the trace interface.
h)
Software triggering of exceptions
Candidates should know that exceptions can be triggered under software control;
that this is done via the ISPR or STIR registers in the NVIC and that only the STIR
method can be made available to unprivileged code.
More advanced candidates will know that the STIR register is not available in
ARMv6-M and that unprivileged access to STIR can be granted via the
USERSETMPEND bit.
i)
Semihosting
Candidates should know that some development suites support semihosting, which
enables the application running on a target board to interact with a debug host using
the debug connection and that one typical usage of semihosting is to route printf
output to the host.
j)
Using SYSTICK for timing analysis
Candidates should know that the SYSTICK timer can be used for timing
measurement and that the SYSTICK timer is a down counter, limited to 24-bit and
can only be accessed by privileged code.
Advanced candidates should know that to measure longer durations of time, the
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SysTick exception can be used to record how many times it has underflowed
3.4.2
Standard Debug Facilities
a)
Types of debug sockets/connectors
Candidates should know that there are several standard debug connector
arrangements: 20 pin IDC connector, 10 pin Cortex/CoreSight debug connector, 20
pin Cortex/CoreSight debug+trace connector, 38-pin Mictor debug and trace
connector.
b)
Cross-triggering
c)
Difference between hardware and software breakpoints
Candidates should know that the number of hardware breakpoints is limited,

whereas the number of software breakpoints is unlimited.
Advanced candidates should know that when a breakpoint is hit, the processor stops
at the breakpoint instruction and that two of the eight breakpoint comparators in
Cortex-M3 and M4 processors are for literal data and cannot be used to halt the
processor upon instruction execution.
d)
DFSR, xPSR, Link register
Candidates should know that a debugger can determine the cause of Halting by
examining the contents of the DFSR.
e)
DWT, ITM, ETM, DAP, TPIU, MTB, ETB, FPB, Trace port
Candidates should know that DWT, ITM and ETM trace features require trace
interface; that the trace interface can be single pin Serial Wire Viewer mode, or
multi-pin trace port mode; when ETM instruction trace is used a multiple-pin trace
port interface is needed due to bandwidth. Candidates should be aware that the
number of DWT/FPB comparators is architecturally limited and implementation
defined.
Advanced candidates should know before using any trace feature the TRCENA bit in
DEMCR must be set to 1.
f)
Physical debug connection (SWO, SWD, JTAG)
Candidates should know that it is possible to share TDO pin with Serial Wire Viewer
when using Serial Wire Debug; 20 pin Cortex/CoreSight debug+trace connector has
4 trace data pin + 1 trace clock pin.
g)
Event counters
Candidates should know that the DWT can be programmed for generating profiling
trace information.
h)
Cycle counter
Candidates should know that the DWT contains a 32-bit cycle counter.
i)
PC Sampling
Candidates should know that the DWT can be programmed for generating PC
sampling trace information for basic profiling; if without trace connection, the
debugger can also periodically sample PC via a PC sampling register for basic
profiling.
3.5
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a)
How to set up stacks (MSP/ PSP)
Candidates should know that MSP is selected as the stack pointer at reset; that it
takes its initial value from the first word in the vector table (0x0); how to select PSP
for Thread mode via the CONTROL register and that this can only be done when in
privileged mode.
Advanced students would know that the architecture requires an ISB to be
performed after modification of the CONTROL register (even though current
implementations may function correctly without the barrier).
b)
Heap memory
Candidates should know that some of the C runtime functions require heap memory.
c)
SP and PC initialization
Candidates should know that MSP takes its initial value from the first word of the
vector table; that this must be a doubleword-aligned address; that PC takes its initial
value from the second word of the vector table; that the initial value of PC in the
vector table must have LSB set to 1. The Process Stack Pointer (PSP) needs to be
initialized by software if it is used.
d)
CMSIS-Core SystemInit
Candidates should know that the SystemInit() function is typically provided in a

CMSIS driver package from the microcontroller vendor and that the SystemInit()
typically provides clock and PLL initialization.
Advanced candidates should know that SystemInit() is typically called from the reset
handler.
3.6
Implementation
a)
Bit-banding
Candidates should know that bit band operation is optional on Cortex-M3 and
Cortex-M4 processors; that it provides a means of accessing individual bits in a two
fixed bit band regions via alias regions; that these accesses are atomic and how to
construct macros to simplify bit band accesses when programming in C.
Advanced students will know that bit banding cannot be used on the Private
Peripheral Bus ; that unaligned access are not supported in bit band alias regions
and that sub-word accesses are permitted in the alias region.
b)
SYSTICK options
Candidates should know that SYSTICK is a synthesis-time option in ARMv6-M.
c)
Additional fetch latency above 0x20000000
d)
Differences across cores
Candidates should know that vector table relocation is not available in Cortex-M0
and is a synthesis-time option in Cortex-M0+; that privileged mode is not available
on Cortex-M0 and is a synthesis-time option in Cortex-M0+ and that Cortex-M0 and
Cortex-M0+ do not support hardware divide.
e)
Hardware multiply options
Candidates will know that the Cortex-M0 and Cortex-M0+ processors support only
basic multiply; that the Cortex-M3 and Cortex-M4 processors support multiplyaccumulate and that Cortex-M4 processor supports an extended range of halfword
multiply and multiply-accumulate.
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Detailed Syllabus
f)
MPU
Candidates should know that MPU support is available on Cortex-M0+, Cortex-M3,

Cortex-M4 only and that this is a synthesis-time option.
g)
FPU
Candidates should be aware that the FPU is an option on Cortex-M4 only and that
the decision to include it is made at synthesis time.
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Table 1 Change history

Minor updates and corrections

ARM web address

Copyright 2013 - 2014 ARM. All rights reserved.

ARM AEG 0073B

ARM AEG 0073B

Syllabus structure ..................................................................................................... 5

Detailed Syllabus ....................................................................................................... 7

Copyright 2013 - 2014 ARM. All rights reserved.

Copyright 2013 - 2014 ARM. All rights reserved.

ARM AEG 0073B

Architecture and Product Applicability

ARM AEG 0073B

Copyright 2013 - 2014 ARM. All rights reserved.

Subject Area Weighting

Copyright 2013 - 2014 ARM. All rights reserved.

ARM AEG 0073B

Copyright 2013 - 2014 ARM. All rights reserved.

Imprecise and precise faults

Synchronous and asynchronous faults

Re-entrant interrupt handler

Enable and disable interrupts

Vector table relocation

Copyright 2013 - 2014 ARM. All rights reserved.

ARM AEG 0073B

Exception return value

Interrupt priority levels and groups

Runtime interrupt configuration (BASEPRI, PRIMASK, FAULTMASK)

ARM AEG 0073B

Copyright 2013 - 2014 ARM. All rights reserved.

Candidates should know that each region has a fixed priority.

How to enable and disable the MPU

Candidates should know how to enable and disable the MPU

Differences between ARMv6-M MPU and ARMv7-M MPU

Aliased MPU registers

Candidates should know that aliased registers allow multiple regions to be

Candidates will be aware of PSRs, PRIMASK, FAULTMASK, BASEPRI, CONTROL

Copyright 2013 - 2014 ARM. All rights reserved.

ARM AEG 0073B

Modes and stacks

Candidates should be aware of pre-index and post-index addressing and optional

Data processing instructions

Multiply and divide

Copyright 2013 - 2014 ARM. All rights reserved.

UMULL, SMULL, SMLAL, UMLAL.

Saturated arithmetic instructions

Differences between subsets

Candidates will know that ARMv6-M, ARMv7-M, ARMv7E-M support differing

Special Register Access Instructions

Copyright 2013 - 2014 ARM. All rights reserved.

ARM AEG 0073B

Correct sequence to initialize SYSTICK timer

Candidates will know the sequence required to initialize the timer.

Default memory types

System control space (SCS)

Candidates should be aware that SCS access is privileged, little-endian, aligned

Candidates should be aware of the situations in which unaligned accesses might be

Peripheral control space

Candidates should be aware that there is a specific region of memory which is

Vendor specific space

Candidates are not expected to demonstrate knowledge of this subject.

ARM AEG 0073B