A Wide Frequency Range and Adjustable Duty Cycle

CMOS Ring Voltage Controlled Oscillator

Minh-Hai Nguyen, Cong-Kha Pham
Department of Electronics Engineering
The University of Electro-Communications, Tokyo, Japan
minhhai.loto@gmail.com, pham@ee.uec.ac.jp
Abstract This paper presents a voltage controlled
ring oscillator (VCO) with wide tuning range and
adjustable duty cycle. The circuit was designed
using Rohm 0.18m technology with 1.5V supply
voltage. The simulation results show that the VCO
oscillates from 300Hz up to 1.4GHz, while the duty
cycle can be adjusted 20-80% independently from
the oscillating frequency.
Keywords:
voltage-controlled oscillator, VCO,
transmission gate, wide frequency range, adjustable duty cycle

Figure 2: Three stage VCO using transmission gates

3

PROPOSED INPUT CIRCUIT

The diculty of applying two voltages on transmission
1 INTRODUCTION
gates while maintain their sum unchanged can be solved by
Voltage-controlled oscillators (VCOs) are widely used a simple input circuit with two identical pMOS transistors
in communication systems as an important block. The (gure 3). Supposed all transistors operate in saturate recritical development of digital processing demands VCOs gion and neglect 2-dimension eects, the gate-source voltto be entirely integrated on a chip, respond to high fre- age dierences of M13 and M14 must be the same, refer to
quency, low power and accurate duty cycle need. Some VP = VDD VCT RL .
researches on high frequency, wide tuning range and low
power supply Ring VCOs were introduced [1]-[3]. In most
cases, the duty cycle of the VCO is depend on the oscillating frequency, become unsuitable in many clock generation
applications that need both positive and negative transitions [4].
This paper presents a design of a CMOS ring VCO
based on transmission gates with wide tuning range 300Hz1.4GHz at low power supply 1.5V. The duty cycle can be
adjusted linearly 20-80% independently from the oscillating frequency by a surplus control voltage.
2

THREE STAGE VCO USING TRANSMISSION GATES

As described in [5], a transmission gate (gure 1) with

an nMOS and a pMOS transistors are parallel connected
can work as an adjustable resistance. The resistance of the
transmission gate can be adjusted by the two voltages applying on the transistors gates whose sum should be xed
as VDD.

Figure 3: Input circuit

The condition for both transistors to operate in saturate region is VCT RL VDD VT Hp > VP VDD . Using
the result above VP = VDD VCT RL , we have VCT RL >
1
2 (VDD + VT Hp ). Suppose VDD = 1.5[V ] and VT Hp =
0.5[V ], the condition is estimated as VCT RL > 0.5[V ].
Because when VCT RL < 0.5[V ] the transmission gates will
be OFF and the circuit will stop oscillating, therefore the
condition that VCT RL must be larger than 0.5[V] does not
narrow the oscillate circuits range of use.
4

Figure 1: Transmission gate

Transmission gates can be applied to form a VCO as
depicted in Figure 2. The voltage VCT RL controls the resistance of transmission gates and therefore changes the
delay time of each stage. Thus the frequency of output
signal can be adjusted.
978-1-4244-7057-0/10/$26.00 2010 IEEE

PROPOSED DUTY CYCLE CONTROL CIRCUIT

The method of controlling the duty cycle of the output
signal is described as in gure 4. The output square pulse
signal from the oscillator is rst changed into a triangle signal. Then by an inverter which has movable reverse point
the triangle signal will be transformed back into square
signal. The duty cycle of the nal square signal can be
controlled by moving the position of the reverse point of
the previous inverter.

a) Signal from oscillate circuit

SIMULATION RESULTS

The whole system as depicted in gure 7 was simulated

by HSPICE using Rohm 0.18m technology. Figure 8 show
the oscillating frequency versus the control voltage VCT RL .
Figure 9 show the duty cycle adjusted result at 3 representative frequencies. The duty cycle of output signal was
adjusted linearly from 20 - 80%. Other simulation results
are summarized in Table 1.

b) Transform into triangle signal

c) Transform back to square signal

Figure 4: Duty cycle controlling method
a) Simple model
The square-to-triangle signal transform circuit is depicted in gure 5, consists of an inverter connected in series with a transmission gate. The transmission gate is designed to have large resistance so that the charge-decharge
process from the inverter will be damped to nearly linear. The using of a transmission gate instead of a xed
resistor makes sure that the square signal will always be
transformed into triangle signal independently with its frequency. When we decrease the voltage VCT RL , the period
of the output signal increases, at the same time, the resistance of the transmission gate becomes larger, then the
charge-decharge process will be more damped. The situation when VCT RL increases is similar. In sum, the resistance of the transmission gate always responds to the
change of frequency and keeps the triangle signal in stable
shape.
b) The circuit
Figure 6: Triangle-to-Square signal transform circuit

Figure 5: Square-to-Triangle signal transform circuit

Finally, the triangle-to-square signal transform circuit,
works as an inverter with movable reverse point, consists
of 2 inverters connected in parallel with two inputs, one
as the triangle signal and the other as duty cycle control
voltage VDU T Y . Another inverter is added to rene the
signal after the transformation. The circuitry is depicted
in gure 6.
Supposed all transistors operate in saturate region, the
voltage VBU F F can be calculated as
VBU F F = VDD

Figure 7: Block diagram of the whole system

r20//r22
r19//r21 + r20//r22

(where r is ON resistance of MOS transistor)

The voltage VBU F F depends on the ON resistances of M21
and M22 which are controlled by VDU T Y . That means the
duty cycle control voltage VDU T Y can move the reverse
point of the inverter formed by M19 and M20 and therefore can adjust the duty cycle of the output signal.

Figure 8: VCO oscillating frequency vs frequency control

voltage

Table 1: Summary results of the proposed VCO

[5]
this work
Technology
TSMC 0.35m
Rohm 0.18m
Power supply
3.3V
1.5V
Max. frequency 260MHz@Vc=3.3V 1.4GHz@Vctrl=1.5V
Min. frequency
17Hz@Vc=0V
300Hz@Vctrl=0V
KV CO
105.27MHz/V
1.38GHz/V

Acknowledgment
This work is supported by VLSI Design and Education
Center (VDEC), the University of Tokyo in collaboration
with Cadence Design Systems, Inc.
References
[1] Mahdi Parvizi, Amir Khodabakhsh, A. Nabavi, LowPower High-Tuning Range CMOS Ring Oscillator
VCOs, Proc. of 2008 IEEE International Conference
on Semiconductor Electronics, ICSE2008, pp. 40-44,
Nov. 2008.

Figure 9: Output signals duty cycle adjustment

6

[2] Luciano Severino de Paula, Sergio Bampi, Eric Fabris, Altaniro Amadeu Susin, A Wide Band CMOS
Dierential Voltage-Controlled Ring Oscillator, Proc.
of 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference,
NEWCAS-TAISA2008, pp. 9-12, June 2008.

CONCLUSION
A voltage controlled ring oscillator with wide frequency
tuning range and adjustable duty cycle has been described.
The simulation results using CMOS 0.18m technology [3] Narasi Reddy, Manisha Pattanaik, S. S. Rajput, 0.4V
show that the frequency can be tuned up to 1.4GHz and
CMOS based Low Power Voltage Controlled Ring Osthe duty cycle can be adjusted in wide range 20-80% indecillator for Medical Applications, Proc. of 2008 IEEE
pendently from the oscillating frequency.
Region 10 Conference, TENCON2008, pp.1-5, Nov.
The layout of the whole circuit, as shown in gure
2008.
10, was designed on Rohm 0.18m technology using CADENCE Virtuoso design tool.
[4] T. Gawa, K. Taniguchi, A 50% duty-cycle correction circuit for PLL output, Proc. of 2002 IEEE International Symposium on Circuits and Systems, ISCAS2002, pp. 26-29, May 2002.

Figure 10: Layout of the proposed circuit

[5] Meng-Lieh Sheu, Ta-Wei Lin, and Wei-Hung Hsu,

Wide Frequency Range Voltage Controlled Ring Oscillators based on Transmission Gates , Proc. of 2005
IEEE International Symposium on Circuits and Systems, ISCAS2005, vol.3, pp.2731-2734, May 2005.