Cours Nios Altera

Designing with Nios II and SOPC Builder
Designing with Nios II

and SOPC Builder
Copyright 2005 Altera Corporation
Objectives
Students
will be able to:
Describe the Nios II softcore processor

Use the SOPC Builder tool to create complex systems
Create and debug software for Nios II
Program the development board
Perform an RTL Simulation in ModelSim
Tie in custom peripherals to the Avalon Switch Fabric
and utilize its multi-mastering capabilities
Append a custom instruction to the Nios II instruction set
Agenda
Nios II Hardware Development

Nios II Software Development
Nios II Software Debug
RTL Simulation
Avalon Switch Fabric
Custom Peripherals
Custom Instructions
Multi-Masters and Direct Memory Access (DMA)
Configuring the Development Board
A-MNL-NIOSII-04
The Programmable Solutions Company
Devices
Intellectual Property (IP)
Mercury Devices
ACEX Devices
FLEX Devices
MAX Devices
Tools
Signal Processing
Communications
Embedded Processors
z
Devices (continued)
Stratix II
Stratix
Stratix GX
Cyclone II
Cyclone
MAX II
Nios, Nios II
Quartus II Software
Quartus II Web Edition
SOPC Builder
DSP Builder
Nios II IDE
Nios II Hardware
Development
What is Nios II?
Alteras Second Generation Soft-Core 32 Bit RISC Microprocessor
Debug
Cache
Nios II
CPU
On-Chip
ROM
On-Chip
RAM
- Nios
Developed
By Altera
II Plus Internally
All Peripherals
Written In HDL
- Can
Harvard
Architecture
Be Targeted
For All Altera FPGAs
- Synthesis
Royalty-Free
Using Quartus II Integrated Synthesis
UART
GPIO
Timer
SPI
SDRAM
Controller
FPGA
6
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Problem: Reduce Cost, Complexity & Power
Flash
I/O
CPU
SDRAM
I/O
I/O
I/O
I/O
I/O
DSP
FPGA
CPU
DSP
Solution: Replace External Devices

with Programmable Logic
7
Reduce
Cost, Complexity
& Power
Problem:On
System
A Programmable
Chip
(SOPC)
Flash
FPGA
SDRAM
CPU is a Critical
Function
Solution:
ReplaceControl
External
Devices
Required
forProgrammable
System-Level Logic
Integration
with
8
FPGA Hardware Design Flow

Design Entry/RTL Coding
Design Specification
SOPC Builder
- Behavioral or Structural Description of Design
RTL Simulation
Functional Simulation (Modelsim,
- Functional
Simulation (Modelsim,
Quartus II)
Quartus II)
Verify Logic Model & Data Flow
- Verify Logic Model & Data Flow
(No Timing Delays)
(No Timing Delays)
LE
M512
M4K
I/O
Synthesis
- Translate Design into Device Specific Primitives
- Optimization to Meet Required Area & Performance Constraints
- Spectrum, Synplify, Quartus II
Place & Route

- Map Primitives to Specific Locations Inside
Target Technology with Reference to Area &
Performance Constraints
- Specify Routing Resources to Be Used
9
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FPGA Hardware Design Flow

Timing Analysis
tclk
- Verify Performance Specifications Were Met

- Static Timing Analysis
Gate Level Simulation

- Timing Simulation
- Verify Design Will Work in Target Technology
Test FPGA on PC Board

- Program & Test Device on Board
- Use SignalTap II for Debugging
10
Development Kits, Stratix & Cyclone Edition

Download /JTAG
Debug Connector
Serial RS-232
Connectors
Power Connector
10/100 Ethernet
MAC/PHY &
RJ-45 Connector
Expansion
Prototype
Connectors
CPU Reset
8 MB Flash
(40 I/O pins each)
16 MB SDRAM
1MB SRAM
Compact Flash
(Connector Mounted on Back)
11
Buttons
LEDs
7 Segment
Configuration Controller
(MAX 7128AE)
Configuration Control
Standard Design Block Diagram

Ethernet
MAC/PHY
1MB
SRAM
8MB
FLASH
16MB Compact
FLASH
32MB
SDRAM
Address (32)
Read
Write
Data In (32)
Data Out (32)
IRQ
IRQ #(6)
On-Chip
12
Off-Chip
32-Bit
Nios II
Processor
Tri-State
Bridge
Tri-State
Bridge
Compact
Flash
PIOs
ROM
General
Purpose
Timer
Periodic
Timer
LED PIO
LCD PIO
7-Segment
LED PIO
Button PIO
8 LEDs
Expansion
Header
J12
2 Digit
Display
4
Momentary
buttons
(with Monitor)
SDRAM
Controller
UART
Level Shifter
Nios II Processor
Reconfig
PIO
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Nios II System Architecture

Avalon
Master/
Slave
Port
Interfaces
Address
Decoder
Instr.
Nios II
CPU
Data
Interrupt
Controller
On-Chip
Debug Core
UART 0
Timer 0
SPI 0
Wait State
Generation
GPIO 0
Data in
Multiplexer
Off-Chip
Software Trace
Memory
DMA 0
Master
Arbitration
Timer n
SPI n
GPIO n
DMA n
Memory
Interface Memory
Interface
Dynamic
Bus Sizing

13
UART n
User-Defined
InterfaceUser-Defined
Interface
Nios II Block Diagram

Nios II Processor Core
reset
clock
JTAG interface
to Software
Debugger
HardwareAssisted
Debug Module
Program
Controller
&
Address
Generation
General
Purpose
Registers
r0 to r31
Instruction
Master
Port
Instruction
Cache
Exception
Controller
Interrupt
Controller
irq[31..0]
Custom
I/O Signals
14
Custom
Instruction
Logic
Control
Registers
ctl0 to ctl4
Arithmetic
Logic Unit
Data
Cache
Data
Master
Port
Nios II Processor Architecture

Classic
Pipelined RISC Machine
32 General Purpose Registers

3 Instruction Formats
32-Bit Instructions
32-Bit Data Path
Flat Register File
Separate Instruction and Data Cache (configurable sizes)
Branch Prediction
32 Prioritized Interrupts
Custom Instructions
JTAG-Based Hardware Debug Unit
15
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Nios II Versions
Nios
II Processor Comes In Three ISA Compatible

Versions
FAST: Optimized for Speed
STANDARD: Balanced for Speed and

Size
ECONOMY: Optimized for Size
Software
Code is Binary Compatible
z
16
No Changes Required When CPU is Changed
Binary Compatibility / Flexible Performance
Pipeline
Nios II /f
Fast
Nios II /s
Standard
6 Stage
5 Stage
None
H/W Multiplier &

Barrel Shifter
1 Cycle
3 Cycle
Emulated
In Software
Branch Prediction
Dynamic
Static
None
Instruction Cache
Configurable
Configurable
None
Data Cache
Configurable
None
None
1400 - 1800
1200 1400
600 700
Logic Usage
(Logic Elements)
Custom
Instructions
17
Nios II /e
Economy
Up to 256
Hardware Multiplier Acceleration
Nios II Economy version - No Multiply Hardware
Nios II Standard - Full Hardware Multiplier
Uses GNUPro Math Library to Implement Multiplier

32 x 32 32 in 3 Clock Cycles if DSP block present, else uses software
only multiplier
Nios II Fast - Full Hardware Multiplier

32 x 32 32 in 1 Clock Cycles if DSP block present, else uses software
only multiplier
Acceleration Clock Cycles
Hardware
(32 x 32 32)
None
18
250
Standard
MUL in Stratix
Fast
MUL in Stratix
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Hardware Multiplier Support
Stratix and Stratix II DSP Blocks
Cyclone II Multiplier Blocks
Optional LE Implementation
Multiplication using 18 x 18 Multiplier Block

Enables HW multiplier support for Cyclone Device Family
Can also use in Stratix and Stratix II instead of DSP Blocks
Mul, Shift, Rotate (~ 8 Clocks Per Mul)
Eliminates need for DSP blocks for Nios II MUL
19
Licensing
Nios II Delivered As Encrypted Megacore
Licensed Via Feature Line In Existing Quartus II License File

Consistent With General Altera Megacore Delivery Mechanism
Enables Detection Of Nios II In Customer Designs (Talkback)
No Nios II Feature Line (OpenCore Plus Mode)

System Runs If Tethered To Host PC
System Times Out If Disconnected from PC After ~ 1 hr
Nios II Feature Line (Active Subscriber)
Subscription and New Dev Kit Customers Obtain Licenses From

www.altera.com
Nios II CPU RTL Remains Encrypted
Nios II Source License
Available Upon Request On Case-By-Case Basis

Included With Purchase Of Nios II ASIC License
20
Requirements for Nios II Designs

Quartus
II 4.0 SP1 or higher

Note: Quartus II now 4.2 available
Required for Nios II 1.1
No
spaces in Quartus II project pathname

Nios II license or a programming cable
tethered to PC to run the OpenCore Plus
version of Nios II
21
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Nios II: Faster & Smaller

250
Fast
4X Faster
Performance
(DMIPS)
200
150
Standard
10% Smaller
Over 2X Faster
100
50
Economy
50% Smaller
0
0
500
1000
Results Based on Stratix II FPGA
22
1500
2000
CPU Core Size

(Logic Elements)
Variation with FPGA Device

250
Fast
DMIPS
200
150
Standard
100
Economy
50
0
0
500
1000
1500
2000
Logic Elements
Stratix II
23
Stratix
Cyclone
HC-Stratix
Processor Cost vs. Performance

300
250
Performance
(DMIPS)
Stratix II
200
f
150
Cyclone II
100
50
Cyclone
e
e e
0
$0.00
Stratix
$1.00
$2.00
$3.00
$4.00
$5.00
Cost of CPU Logic
24
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Nios II: Hard Numbers

Nios II/f
Stratix II
Stratix
Cyclone
Nios II/s
Nios II/e
200 DMIPS @ 175MHz

1180 LEs
1 of 8 DSP
4K Icache, 2K Dcache
Stratix 2S10-C5
150 DMIPS @ 135MHz
1800 LEs
1 of 8 DSP
Stratix 1S10-C5
100 DMIPS @ 125MHz
1800 LEs
90 DMIPS @ 175MHz
800 LEs
28 DMIPS @ 190MHz
400 LEs
4K Icache, No Dcache
Stratix 2S10-C5
67 DMIPS @ 135MHz
1200 LEs
No Icache, No Dcache
Stratix 2S10-C5
22 DMIPS @ 150MHz
550 LEs
Stratix 1S10-C5
62 DMIPS @ 125MHz
1200 LEs
Stratix 1S10-C5
20 DMIPS @ 140MHz
550 LEs
Cyclone 1C4-C6
Cyclone 1C4-C6
Cyclone 1C4-C6
* FMax Numbers Based Reference Design Running From On-Chip Memory (Nios II/f 1.15 DMIPS / MHz)
25
SOPC Builder System Contents Page
Over 60
Cores Available
Today
26
Altera, Partner & User

Cores
Processors
Memory Interfaces
Peripherals
Bridges
Hardware Accelerators
Import User Logic
(ie. custom peripherals)
Web-Based IP Deployment
Clock-Domain Crossing
New in
4.2
Auto-Insertion of Clock-Domain Crossing Logic

FIFO Where Posted-Reads Are Supported
Simple Metastability-Hardening Otherwise
Unlimited Number of Clock Domains

Added, Named & Managed Through GUI
27
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Nios II Exceptions
All
exceptions processed by code at

exception location
Provided by HAL system library
Supported
Exception Types
z Software
Exceptions
Software Traps (currently, not implemented)

Unimplemented instructions
Maintains compatibility between Nios II cores
z Hardware
Interrupts
32 Level-sensitive interrupts are supported.

z More
exceptions will be supported as features are

added.
28
Nios II CPU Configured in SOPC Builder
29
Hardware designer selects which Nios II version to use when

creating system
Selecting JTAG Debug Core
30
Configuration is chosen when hardware designer selects

appropriate Nios II processor core
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10
SOPC Builder More cpu Settings Page
31
SOPC Builder System Generation Page
32
SOPC Builder Produces a .PTF File
33
Text file that records SOPC Builder edits

Describes Nios II System
Used by software development tools
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11
Integrate SOPC Builder O/P in Quartus II
Integrate SOPC Builder block symbol to Quartus II schematic

(as shown below) and compile design
Or, instantiate top module into your HDL design and compile
34
New Peripherals for Nios II
System ID Peripheral
Memory Interfaces
EPCS Serial Flash
Controller
On-Chip
Used to Ensure Hardware/

Software Version Synchronization
Simple 2 read-only register
peripheral containing hardware ID
tags.
z
z
RAM, ROM
Off-Chip
Register 1 contains random

number
Register 2 contains time and date
when system was generated in
SOPC Builder
z
z
Can be checked at runtime to

ensure that the software to be
downloaded matches the
hardware image
SRAM
CFI Flash
LCD Display
35
New Peripherals for Nios II
JTAG UART
Single JTAG
Connection For:
z
z
z
z
z
Device Configuration
Flash Programming
Code Download
Debug
Target STDIO (printing)
Compact Flash Interface

Mass Storage Support
z
z
True IDE Mode

Compact Flash Mode
Software Supports
z
z
z
Low-Level API
MicroC/OS-II File System
Support
CLinux File System
Support
Supported through
www.niosforum.com
36
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12
Project Directories
Hardware
HDL Source & Netlist
db - Quartus project
database
Software
Application source code
Library files
Simulation
Testbench
Automatically generated
test memory and vectors
37
Exercise 1
A Basic Nios II Design
35 mins
Nios II Software
Development
A-MNL-NIOSII-04
13
SOPC Builder Flow

SOPC Builder GUI
Processor Library
Configure Processor
Peripheral Library
Select & Configure

Peripherals, IP
Hardware Development
Custom Instructions
IP Modules
Software Development
Nios II IDE
Connect Blocks
HDL Source Files
C Header files
Testbench
Custom Library
Peripheral Drivers
Synthesis &
Fitter
User Design
Other IP Blocks
Generate
Hardware
Configuration
File
Quartus II
40
Executable
Code
Verification
& Debug
JTAG,
Serial, or
Ethernet
Altera
PLD
On-Chip
Debug
Software Trace
Hard Breakpoints
SignalTap II
Compiler,
Linker, Debugger
User Code
Libraries
RTOS
GNU Tools
Nios II IDE (Integrated Development Environment)*
Leading Edge Software

Development Tool
Target Connections
Hardware (JTAG)
Instruction Set Simulator
ModelSim-Altera Software
Advanced Hardware
Debug Features
Software and Hardware
Break Points, Data Triggers,
Trace
Flash Memory
Programming Support
* Based on Eclipse Project

41
Opening the Nios II IDE

Launch the Nios II IDE from
the SOPC Builder or from
the Windows Start menu
42
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14
Nios II IDE
File Viewer
Window
List of Open
Projects
(for C code,
C++, and
assembly*)
Terminal
window
43
Note: C++ files must have extension .cpp

In-line assembly code offset by asm();
Nios II IDE C/C++ Projects/Navigator
44
Lists all
open
projects
Displays
source files
associated
with project
List all
open and
closed
projects
Allows you
to drag and
drop new
files into
existing
projects
Creating a C/C++ Application

File > New > Project
45
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15
Creating a C/C++ Application

Link to a System Library
- Select a pre-existing library
- Or create a new library
46
This Creates Two Software Projects

- Application and System Library Project
Application Project
- contains application
source code
System Library Project

- contains system
header file, etc.
Drivers Directory
- contains all device drivers
DO NOT DELETE !
47
Application and System Library Projects
Application Projects build executables

System Library Projects contain interface to the
hardware
Nios II device drivers (Hardware Abstraction
Layer)
Optional RTOS (MicroC/OS-II)
Optional software components (Lightweight
TCP/IP stack, Read Only Zip File System)
48
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16
Other New Project Options
System Library
Only creates system library project
Build C applications upon this later
Advanced C/C++ Project

Disable automatic tool features like
makefile and linker script generation
User defines own instead
Managed Library Project

Facilitates software library
development
Enables you to associate precompiled code into an Application
Project
Tool writes makefile for included files
49
Importing Projects into the IDE
50
Project Properties
51
Both Application and System Library have

Properties pages
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17
System Library Options

Select
Specify
stdio
devicesmap
Partition
theRTOS
memory
52
Software Compilation
To compile a software application, highlight your project

and select Build Project from the Projects menu
53
Directory Structure After Compilation
54
Application Project
System Library Project
A-MNL-NIOSII-04
18
Nios II Host Platform Support

Windows
XP
Linux Host Support (RedHat 7.3, 8.0,
Enterprise 3)
Nios II GNU Toolchain (Compiler, Binary Utilities)
Nios II Instruction Set Simulator
Nios II Debugger
Nios II IDE
USB Blaster Linux driver
55
Hardware Abstraction Layer
A lightweight runtime environment for Nios II software

Provides a level of abstraction between application code and
low level hardware
HAL libraries are generated by Nios II IDE

A HAL contains:
56
device drivers
initialization software
file system
stdio, stderr
Provides generic device models for classes of

peripherals common in embedded systems
eg. timers, I/O peripherals, etc.
Gives a consistent POSIX-like API, regardless of

underlying hardware
Make programming as familiar as possible to
software engineers who may not be familiar with the
specific peripheral architectures
z
z
z
57
ANSI C (through the Newlib library)

UNIX style interface (i.e. POSIX like)
Altera extensions where standards dont exist or were
inappropriate (watch for the alt_* extension)
A-MNL-NIOSII-04
19
Key features of the HAL

Uses standard interfaces where appropriate
Close integration with the Newlib ANSI C library
z http://sources.redhat.com/newlib/
Device drivers automatically configured to match the PTF
Drivers initialised before main()
Scalable (i.e. packs down small)
Clear distinction between system and application software
58
Nios II HAL: Runtime Library

The HAL UNIX Style Functions are the glue
between the C library and the device drivers
HAL API
User Program
_exit()
close()
closedir()
fstat()
getpid()
gettimeofday()
ioctl()
isatty()
kill()
lseek()
C
C Standard
Standard Library
Library
HAL API
Device
Driver
Device
Driver
Device
Driver
open()
opendir
read()
readdir()
rewinddir()
sbrk()
settimeofday()
stat()
usleep()
wait()
write()
Nios II Processor System Hardware
59
HAL File System

/
/dev
/dev/jtag_uart0
/mnt
/dev/lcd0
/mnt/rozipfs
/mnt/rozipfs/myfile1
Device names match those set in SOPC

builder.
Can only access nodes, not directories.
All paths must be absolute (no current
directory)
60
/mnt/rozips/myfile21
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20
Familiar File/Device Access

ANSI
C:
fp = fopen (/dev/lcd0, w); fprintf (fp, %s, msg);
UNIX
Style:
fd = open (/dev/lcd0, O_WRONLY); write (fd, msg, strlen(msg));
Newlib
also supports C++ streams:
ofstream ofp(/dev/lcd0, ios::out); ofp << msg;
Existing
code (outside the Nios world) uses

these interfaces. Porting is now much
easier.
Use of existing standards means theres
nothing new to learn.
61
HAL System Header File

SOPC Builder System Contents
system.h
System Library Settings

62
system.h
Contains macro definitions for system parameters,

including peripheral configuration, for instance:
Hardware configuration of the peripheral

Base address
IRQ priority (if any)
Symbolic name for peripheral
Does not include: static information, function

prototypes, or device structures (unlike the old
excalibur.h)
Located in the syslib project directory
Rarely necessary to include it explicitly in your
application code, which improves rebuild time
63
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21
system.h - example
Defines system settings and peripheral configurations:

Replaces excalibur.h (from Nios)
/*
* system configuration
*
*/
.
.
.
#define ALT_SYSTEM_NAME "std_1s10ES"

#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "STRATIX"
#define ALTERA_NIOS_DEV_BOARD_STRATIX_1S10_ES
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_CPU_FREQ 50000000
#define ALT_CPP_CONSTRUCTORS
#define ALT_IRQ_BASE NULL
.
.
.
64
/*
* button_pio configuration
*
*/
#define BUTTON_PIO_NAME "/dev/button_pio"
#define BUTTON_PIO_TYPE "altera_avalon_pio"
#define BUTTON_PIO_BASE 0x00920830
#define BUTTON_PIO_IRQ 2
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_EDGE_TYPE "ANY"
#define BUTTON_PIO_IRQ_TYPE "EDGE"
#define BUTTON_PIO_FREQ 50000000
HAL References
65
Each HAL project references library routines and drivers for the
components included in your Nios II system
Reading/Writing Hardware in Nios

Nios
Classic used volatile pointers to

access hardware e.g.
volatile *my_led_pointer = (int *) LED_BASE;
Volatiles
will no longer provide access to

hardware registers in Nios II
They are still used to tell the compiler not to
optimize code
No longer disable cache access
66
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22
Reading/Writing Hardware in Nios II
Instead use I/O macros to access hardware

I/O macros bypass the cache for hardware accesses
They set bit 31 of address bus high (ie. control bit)
IORD(BASE, REGNUM)
z Reads value at register
REGNUM offset from base
address BASE
BASE
REGNUM = 0
BASE+2
REGNUM = 2
REGNUM = 1
REGNUM = 3
IOWR(BASE,REGNUM,DATA)
z Writes DATA to register
REGNUM offset from base
address BASE
67
BASE+4
REGNUM = 4
Header Files for Nios II Peripherals
Each Nios II peripheral has specific read/write

macros for each register
Example: UART (altera_avalon_uart_regs.h)
68
#define IORD_ALTERA_AVALON_UART_RXDATA(base)
IORD(base, 0)
#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data)
IOWR(base, 0, data)
#define IORD_ALTERA_AVALON_UART_TXDATA(base)
IORD(base, 1)
#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data)
IOWR(base, 1, data)
#define IORD_ALTERA_AVALON_UART_STATUS(base)
IORD(base, 2)
#define IOWR_ALTERA_AVALON_UART_STATUS(base, data)
IOWR(base, 2, data)
Data Cache
Memory
space is mirrored (e.g. 2GB

addressable space)
Upper half is uncacheable
Lower half is cacheable
All
data variables are cached by default
This can cause memory coherency issues if

you are using a DMA controller in your design.
69
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23
Data Cache
70
To bypass the cache and maintain coherency

Flush before any DMA transfers using
alt_dcache_flush()
Allocate uncacheable regions on the heap
using alt_uncached_malloc()
Remap an existing area of memory using
alt_remap_uncached()
Use ldio or stio instructions in assembly
Interrupts
HAL API for ISRs - Functions

alt_irq_register()
z
Associates interrupt with your ISR function.
alt_irq_disable_all()
z
Disables all IRQs
alt_irq_enable_all()
z
Enables all IRQs
alt_irq_interruptible()
z
Used in ISR function body. Allows ISR to be interrupted by

higher priority IRQs.
alt_irq_non_interruptible()
z
71
Used to make ISRs uninterruptible (default behavior).
HAL API for ISRs - Useful Info

sample_isr ( void* context, alt_u32 id);
Write your ISR

(Follow prototype)
id == irq number (0 to 31)

context == void pointer to data produced by or
consumed by ISR.
alt_irq_register ( alt_u32 id, void* context,

void (*irq_handler) (void*, alt_u32));
Register your ISR

Using alt_irq_register()
72
Sample Usage:
alt_irq_register ( 3, &some_data,
sample_isr);
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24
HAL API for ISRs - Useful Info
Creating interruptible code blocks in ISR

Use alt_irq_interruptible() & alt_irq_non_interruptible()
Do not use standard C library or RTOS software functions inside

ISR that may pend for any reason
Keep it simple.
Use ISR to trigger execution of slow processing tasks outside of
interrupt context
Do NOT perform these tasks within ISR
References:
Exception Handling Chapter in Nios II Software Developers
Handbook
Eg. printf()
73
Nios II OS / RTOS Support

Product
* MicroC/OS-II
Provider
Micrium
Source
Code
Standards
TCP/IP
Stack
File
System
Yes
RTCA/DO-178B
Opt.
Opt.
* Lightweight IP
TCP/IP Stack
Open Source
Yes
** Nucleus Plus
ATI/Mentor
Yes
CLinux
Open Source
(GPL)
Yes
KROS
KROS
Technologies
Yes
POSIX
GUI
Flash
C/OS-II
Support
Sockets API
IP, ICMP, UDP,
TCP
OSEK
ITRON
Other
Opt.
Opt.
GUI, SNMP
RMON,
SPAN
Incl.
Many,
inc.
FAT
and
JFFS2
Extensive
drivers and
middlewear,
inc USB,
IPSec, etc.
Opt.
Opt.
<continued on next slide>

* Included in Nios II Development Kits
** Evaluation Version Included in Nios II Development Kits
74
Nios II OS / RTOS Support (cont)

Product
Provider
Source
Code
Standards
TCP/IP
Stack
File
System
Other
NORTi
MiSPO
Yes
ITRON
Opt.
Opt.
PPP,
SNMP,
HTTP
PrKERNELv4
eSOL
Yes
ITRON
Opt.
Opt.
USB, Mail
HTTP
ThreadX
Express Logic
Yes
Opt.
Opt.
USB
FAT,
JFFS2,
ROMFS,
RAMFS
Extensive
drivers and
middleware
, inc. USB,
IPSec, etc.
eCos
Open Source
(GPL with
excpetion)
Yes
POSIZ, uITRON,
EL/IX
Incl.

75
A-MNL-NIOSII-04
25
Nios II MicroC/OS-II
76
Single-seat developers license included for free with

Nios II kits
Licensing fee reqd when you productize your system
Full source code included
Preemptive operating system
Small footprint
Code Size (min 5KB, max 20KB)
Data Space (min 1KB, max 5KB)
Supports Semaphores, and Mailboxes for task
synchronization
Nios II MicroC/OS-II
77
Lightweight IP for MicroC/OS-II

Plugs
is being replaced with the

Lightweight IP TCP/IP stack in Nios II
Open source TCP/IP Stack
Supports TCP, UDP, IP, DHCP and ARP

Optimised for size (Very simple web server < 500k)
LWIP supports IPv4 and IPv6, but we support IPv4 ONLY
Based on version 0.6.3
Integrated into Nios II IDE

Used in conjunction with uC/OS-II
Sockets API available
Free Licensing
Modified BSD License, must keep the copyright notice and display it in the
product documentation
78
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26
LWIP - Instantiation
Available
79
as a Software Component
LWIP Configuration
80
Nios to Nios II Conversion

Hardware
Must be Ported
Add Nios II processor and connections in

SOPC Builder
Software
can be Used in Legacy SDK

Mode or Ported to HAL
See AN350 for full details
81
A-MNL-NIOSII-04
27

Legacy
Software Support
Minimal if any Code Changes Required

No Access to Nios II IDE
Only supported for Standard and Economy
cores
New peripherals (CFI flash, sysid, etc) not
supported
New software components (uC/OSII, LWIP)
not supported
82

Full
Port from Nios to Nios II
Requires C code changes

No GERMS support
Provides access HAL, uC/OSII, LWIP
83

Porting
Process:
Replace header files

z
Example: system.h for excalibur.h
Change API calls from SDK to HAL syntax

z
Example: nr_delay() is replaced with usleep()
Replace data types (int, char, etc..) with Nios II data

types (alt_u32, alt_u8, etc)
Replace hardware access pointers with macros
z
Example: my_pio->data = 1 is replaced with

IOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE,1)
Take into account that *volatile pointers no longer

prevent data from being cached
84
A-MNL-NIOSII-04
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Software Run & Debug
Software Run and Debug

Nios
II Run
Nios II IDE JTAG Debugger
Nios II ISS
Nios II Console
Third Party tools
86
Running Code On A Target
87
Nios II IDE can be used to download code to target board
A-MNL-NIOSII-04
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Running Code On A Target
88
Download messages, stdout and stdin appear in console

window
Nios II IDE Run Options
89
Nios II IDE > Run > Run
System ID Peripheral Revisited
When downloading code to a target, Nios II IDE computes

expected System ID peripheral values from PTF file
If computed ID values do not match System ID variables stored on
the target board then an error is flagged
Generally, to fix this you should recompile your hardware
90
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Nios II IDE JTAG Debugger
Requirements
Must have JTAG
Debug Core enabled
in CPU
91
Nios II IDE Debug Perspective
Basic Debug
Run Controls
Stack View
Active Debug
Sessions
DoubleDouble-click to
add breakpoints
Memory View
Variables
Registers
Signals
92
Nios II IDE Debugger

Step Return
Step Over
Step Into
Step with Filters
Disconnect
Terminate
Suspend
Resume
Run last Configuration
Debug last Configuration
93
A-MNL-NIOSII-04
31
Nios II IDE Debugger
Standard debug
windows
94
memory
registers
Variables
breakpoints
expressions
signals
Nios II IDE Multi-Processor Launch
Mechanism to Quickly Launch Multiple Debuggers and

Connect Them to Multiple Nios II Processors
Run > Debug > Nios II Multiprocessor Collection
Accelerates Debug Cycle for Multi-Processor Systems

95
Nios II IDE: Debugger
96
Debug each CPU by selecting its program thread
A-MNL-NIOSII-04
32

Instruction
Set Simulators are software

models of an Instruction Set Architecture
Generally used to debug code if a target board
is unavailable.
Provides limited models of a few hardware
peripherals.
z Timer
z UART
z Memory
97
(flash, SDRAM, on-chip, etc)
98
Launch an ISS Debug session from the

Run Menu
Targets .elf file to ISS and opens debugger

Application can then be debugged as normal
99
A-MNL-NIOSII-04
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Customizing Views in the IDE GUI
100
You can turn windows on or off in either the

Run or Debug Perspective
Nios II SDK Shell
SDK shell is still provided with Nios II

Used to support legacy SDK flow (eg.. n2b, n2c) as
well as other general commands
Can launch terminal to interface to JTAG UARTs
nios2-terminal
And compile code
nios2-elf-gcc
101
Nios II / FS2 Console

Command
102
line debugger
A-MNL-NIOSII-04
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Nios II Console Launch

FS2
103
Console Launches then minimizes
Nios II Console
Allows for hardware

breakpoints and trace data
2 HWBPs and 16 Frames of OnChip Trace Included
104
Displays C Source,
Assembly, Mixed
Nios II Debug Solutions

Product
Provider
Description
Features
* Nios II IDE
Altera
IDE / Debugger JTAG Target Connection, H/W

Breakpoints, Data Triggers,
On-Chip Trace, FS2 Trace
Probe
** code|lab
ATI Mentor
IDE / Debugger JTAG Target Connection, H/W

Breakpoints, Data Triggers,
On-Chip Trace , FS2 Trace
Probe
Watchpoint
Sophia
Systems
Debugger
Supports FS2 ISA-Nios/T
ISA-Nios/T
First Silicon
Solution
(FS2)
JTAG Trace
Probe
External Trace Capture,

Timestamp, Complex Data
Triggers

105
A-MNL-NIOSII-04
35
Upgrades from FS2

(see www.fs2.com for details)
Feature
Nios II IDE
FS2 S/W
Upgrade
FS2 H/W
Upgrade
Hardware Execution
Breakpoints
Data Triggers
On-Chip
16 Frames
On-Chip
128 Frames
Off-Chip
128K Frames
Trace (Load / Store)
No
Yes
Yes
Trace (Timestamp)
No
No
Yes
Target Connection
Altera
USB/B Blaster
Altera
USB/B Blaster
FS2 Black Box

(USB, Ethernet)
Included
See FS2
See FS2
Trace (PC)
Cost
106
FS2 System Analyzer Upgrade
ISA-Nios II System Analyzer
10-pin JTAG Target Connection

Unlimited Software Breakpoints
2 Hardware Breakpoints (upgradable to 4)
Supports On-Chip Trace (upgrades available for
deeper trace)
ISA-Nios II/T System Analyzer

38-pin Mictor Connection
Blackbox probe
Supports 128k frames Off-Chip Trace
in addition to Unlimited On-Chip Trace
107
Lab 2
Software Flow
45 mins
A-MNL-NIOSII-04
36
RTL Simulation
RTL Simulation
Nios II SOPC Builder Automatically Creates

Simulation Models Plus:
ModelSim Project
Testbench
Simulation Scripts
Set Simulation Option

110
Simulation TestBench
Ethernet
MAC/PHY
Dev board
SRAM
Dev board
FLASH
Compact FLASH
SDRAM
Nios II Processor
Write
Data In (32)
Data Out (32)
IRQ
Read
IRQ #(6)
Clock
111
Reset
Tri-State
Bridge
Tri-State
Bridge
Compact
Flash
PIOs
On Chip
ROM)
On Chip
RAM
Custom
Instruction
User
Defined
Peripheral
User
Defined
Interface
User Device
User
Peripheral
SDRAM
Controller
UART
User Device
Address (32)
32-Bit
Nios II
Processor
Included
Not Included
A-MNL-NIOSII-04
37
User Additions to Nios II TestBench
112
SOPC Builder creates

testbench embedded in
top level file eg NiosII.v
Sections within this file

are reserved to add user
files and code
These sections are

preserved if the SOPC
builder is used to regenerate the Nios II
system
Running an RTL Simulation
Modify Nios II IDE System Library For Simulation:

Specify Program Memory
Set Up As Simulation Only
113
Checking the ModelSim only, no hardware support

button:
Leaves caches uninitialized
Does not initialize the .bss section
114
As a result simulation speeds are increased
You can still simulate with this button unchecked but

simulation time will be much longer
A-MNL-NIOSII-04
38
Launch ModelSim from Nios II IDE:

Highlight Software Project In C/C++ Projects panel
Right click
Run As Nios II ModelSim
115
116
Simulation Scripts
When ModelSim is started from the Nios II IDE a set-up

script is run automatically which creates aliases for
simulation scripts
The set up script can also be run independently as follows:
do setup_sim.do
Simulation Scripts
s Compiles HDL source code and loads design
c Rebuilds memory contents based on software code
z
w
l
h
117
Includes changes since Nios II generation
Opens Wave window with useful signals

Opens List window with useful signals
Displays help message describing scripts
A-MNL-NIOSII-04
39
Memory Device Simulation Models
Applies To The Following Nios II Memories

On Chip Memory (ROM or RAM)
SRAM
Flash Memory and now SDRAM
Include SDRAM Model

for Simulation
118
Memory Device Simulation Models
You can no longer initialize memories in the

SOPC Builder.
Memory init file are created by the Nios II IDE.
ext_ram will be initialized for simulation
with the ext_ram.dat file
You must compile your software in the
Nios II IDE to generate this file
Onchip memories are initialized with
<component_name>.hex
Onchip memory init files can be created
by an editor or by the Nios II IDE
119
UART Simulation
Text is transmitted to
UART during simulation
Creates and saves txt file
containing UART tx
stream
Creates window to input
text at simulation run time
Note: ModelSim Options are mutually exclusive
120
A-MNL-NIOSII-04
40
UART Simulation
121
Input is interactive or predefined

Output is shown and saved independently for
multiple UARTs
JTAG_UART Simulation
New
Text is transmitted to the

new JTAG_UART
peripheral during
simulation
Creates and saves txt file
containing UART tx
stream
Creates window to input
text at simulation run time
Note: ModelSim Options are mutually exclusive
122
Wave Window
123
Adds UART and CPU signals by default
A-MNL-NIOSII-04
41
SignalTap II Logic Analyzer
Up to 200 MHz
Multi-Analyzer Support
1,024 Channels
128K Samples
10 Trigger Levels
No Probes!
Can be used
simultaneously with the
Nios II IDE debugger and
the FS2 console!
Capture the state of internal nodes

In-system, at full system speeds
124
125
Lab 3
RTL Simulation
30 mins
A-MNL-NIOSII-04
42
Proprietary interconnect specification used with Nios II
Principal design goals

Low resource utilization for
bus logic
Simplicity
Synchronous operation
Transfer Types
128
Slave Transfers
Master Transfers
Streaming Transfers
Latency-Aware Transfers
Burst Transfers
Switch
PIO
Address (32)
32-Bit
Nios II
Processor
Read
Write
Data In (32)
Data Out (32)
IRQ
IRQ #(6)
ROM
(with Monitor)
UART
Timer
Nios II Processor
LED PIO
7-Segment
LED PIO
PIO-32
UserDefined
Interface
Custom-Generated for Peripherals

Contingencies are on a Per-Peripheral Basis
System is Not Burdened by Bus Complexity
SOPC Builder Automatically Generates
129
Arbitration
Address Decoding
Data Path Multiplexing
Bus Sizing
Wait-State Generation
Interrupts
A-MNL-NIOSII-04
43
Avalon Master Ports
Initiate Transfers with Avalon Switch Fabric

Transfer Types
Fundamental Read
Fundamental Write
All Avalon Masters Must Honor a waitrequest

signal
Transfer Properties
Latency
Streaming
Burst
130
Avalon Slave Ports
Respond to Transfer Requests from Avalon

Switch Fabric
Transfer Types
Fundamental Read
Fundamental Write
Transfer Properties
131
Wait States
Latency
Streaming
Burst
Slave Read Transfer
0 Setup
Cycles
0 Wait Cycles
clk
address,be_n
address, be_n
readn
chipselect
readdata
132
readdata
A-MNL-NIOSII-04
44
Slave Read Transfer with Wait States
1 Setup Cycle
1 Wait Cycle
B C
clk
address,be_n
address, be_n
chipselect
Tsu
readn
readdata
133
readdata
Slave Write Transfer
0 Setup
Cycles
0 Wait Cycles
0 Hold Cycles
clk
address,be_n
address, be_n
writedata
writedata
writen
chipselect
134
Slave Write Transfer with Wait States
1 Setup Cycle
0 Wait Cycles
1 Hold Cycle
B C
clk
address,be_n
writedata
address, be_n
writedata
writen
chipselect
135
A-MNL-NIOSII-04
45
Multiple Clock Domains Supported

Master
Clock Domain 1
Master
Clock Domain 2
Master
Clock Domain 1
CDX
CDX
CDX
CDX
Arbiter
Arbiter

Slave
Slave
Clock
Clock Domain
Domain 22
Slave
Slave
Clock
Clock Domain
Domain 22
Slave
Slave
Clock
Clock Domain
Domain 22
Slave
Slave
Clock
Clock Domain
Domain 22
CDX = Clock Domain Crossing Logic (inserted automatically by SOPC Builder)

136
Multi-Clock Domain Support

Master
Clock
Domain 2
Master
Clock
Domain 1
Master
Clock
Domain 1
CDX
CDX
CDX
CDX
Arbiter
Arbiter
CDX
CDX
Arbiter
Arbiter
Slave
Slave
Clock
Clock Domain
Domain 33
Master
Clock
Domain 1
Slave
Slave
Clock
Clock Domain
Domain 22
CDX = Clock Domain Crossing Logic

137
User-Defined Custom Peripherals
What if I need to add a peripheral not included with the

Nios II system?
user wants to add own peripheral to perform some kind of
proprietary function or perhaps a standard function that is
not yet included as part of the Nios kit
Expand or accelerate system capabilities
We are now going learn how to connect our own design

directly to the Nios II system via Avalon
As many peripherals contain registers we could also have
chosen to connect to a PIO rather than directly to the bus
138
A-MNL-NIOSII-04
46
Creating Avalon Slave
No Need to Worry about Bus Interface

Implement Only Signals Needed
Peripherals Adapted to by
Timing Handled Automatically
Register File
Fabric Created for You
User
Arbiters Generated for You
Logic
Concentrate Effort on
Peripheral Functionality!
139
New Component Editor
140
Creates Interface
Connect to Existing HDL or board component

Map into Nios II Memory Space
Can be Inside or Outside Nios II System
I/O
I/O
Nios II
CPU
Nios II
CPU
I/O
Nios II System
Module
141
I/O
I/O
I/O
Interface
to User
Logic
I/O
Avalon
Avalon
I/O
External
User
Peripheral
Nios II System
Module
Internal
User
Peripheral
A-MNL-NIOSII-04
47
Create External Component Interface
142
AMD29LV065AD CFI Flash Chip
To communicate with
off-chip peripherals
Base interface type
on data sheet
Or Add HDL Files
143
For peripheral that has been encoded for FPGA
Tri-State Peripherals
Require Tri-State Bridge
Interface to
User Logic
Tri-State
Bridge
Nios II
Processor
Avalon
Available as an SOPC Builder component

Off Chip
Peripheral
FPGA
144
Tri-State peripheral is defined by the presence of

a bi-direction data port
Off-chip peripherals do not have to be tri-state
A-MNL-NIOSII-04
48
Define Component Signals
Automatically populates port

table from design files
Enter port type here
Can also define ports manually
145
Define Interface for Each Signal Type
Choose interface type

Register Slave uses native
alignment, Memory Slave uses
dynamic alignment
Control Read and Write Timing

Add wait and hold states View
waveforms
146
Address Alignment Narrow Slave

Peripheral Registers
147
32
Avalon
32-Bit
Nios II
Processor
8 Bit
Peripheral
Base
aa
Base + 0x1
bb
Base + 0x2
cc
Base + 0x3
dd
Base + 0x4
ee
Dynamic Address Alignment (set as Memory Slave)

LD from Base + 0x0:
dd cc bb aa
LD from Base + 0x4:
uu uu uu ee
Native Address Alignment

LD from Base + 0x0:
LD from Base + 0x4:
LD from Base + 0x8:
(set as Avalon Register Slave)

uu uu uu aa
uu uu uu bb
uu uu uu cc
A-MNL-NIOSII-04
49
Address Alignment Narrow Master
148
Memory Contents
32
Avalon
32-Bit
Nios II
Processor
64
64 Bit
Memory
Base
77 66 55 44 33 22 11 00
Base + 0x8
ff ee dd cc bb aa 99 88
Base + 0x16
?? ?? ?? ?? ?? ?? ?? ??
Dynamic Address Alignment

LD from Base + 0x0:
33 22 11 00
LD from Base + 0x4:
77 66 55 44
LD from Base + 0x8:
bb aa 99 88
Native Address Alignment

LD from Base + 0x0:
33 22 11 00
LD from Base + 0x4:
bb aa 99 88
LD from Base + 0x8:
?? ?? ?? ??
High bytes are unobtainable warning issued
Add Software Files
149
ie. Header files and drivers
Add Software Files
150
Header file and drivers can also be added directly to

Application Project
A-MNL-NIOSII-04
50
Create Component Wizard
Publish and create a wizard for your component
Fill in fields
Add component to
SOPC Builder portfolio
Can add parameterizing
capability to component
151
Add Component to SOPC System
152
Default location is the User Logic folder
Eg. Add User-Defined PWM to System
HDL for PWM already exists with standard microprocessor type interface
This will be added to our Nios II system in the next Lab
Avalon
Nios II System
153
A-MNL-NIOSII-04
51
PWM Memory Map

Pre-scale
factor divides Nios II clock to

produce PWM operating frequency
On Period should be less than or equal to
Pre-scale
Base Addr
PWM Pre-scale
+ 0x04
PWM On Period
31
154
PWM Duty Cycle =
On Period
Pre-scale
Lab 4
Adding A User Peripheral
30 mins
Custom Instructions
A-MNL-NIOSII-04
52
Custom Instructions
Add custom functionality to the Nios II design

To take full advantage of the flexibility of FPGA
Dramatically Boost Processing Performance

With no Increase in fMAX required
Application Examples
Data Stream Processing (eg. Network Applications)
Application Specific Processing (eg. MP3 Audio Decode)
Software Inner Loop Optimization
157
Custom Instructions
Augment Nios II Instruction Set

Mux User Logic Into ALU Path of Processor Pipeline
158
Several Levels of Customization

Optional Interface to FIFO, Memory, Other Logic
dataa
datab
32
result
Combinatorial
32
clk
32
clk_en
Multi-Cycle
reset
done
start
n
Extended
8
readra
Internal
Register File
readrb
writerc
5
159
A-MNL-NIOSII-04
53
Custom Instructions
Integrated Into Nios II Development Tools

SOPC Builder design tool handles op-code assignment
Generates C and assembly-language macros
Similar to Nios Custom Instructions Except

Up to 256 different custom instructions possible
Multi-cycle instructions can have variable duration
Parameterization of custom instructions has changed
160
Custom Instructions Tab
Enabled from the Custom Instructions tab in the

Nios II CPU settings in SOPC Builder
161
Custom Instructions Tab
Import logic for the custom instruction

Custom Instruction module can be of following
formats:
162
VHDL
Verilog HDL
EDIF
Quartus Block Diagram (.bdf)
A-MNL-NIOSII-04
54
Combinatorial Custom Instructions
Port list
All Custom Instruction Modules need these ports
z
163
Port names must match exactly
Multi-Cycle Custom Instructions
Port list for Multi-Cycle Custom Instructions

Must have all of these ports with exact names
164
Extended Custom Instructions
165
Uses n[7..0] port to select an operation to perform.
A-MNL-NIOSII-04
55
Register File Custom Instructions
Custom instructions can select inputs from internal

registers or dataa, datab ports
Custom instructions can write results to an internal
register file
dataa[31..0]
result[31..0]
Custom
Logic
reada
writec
c[4..0]
a[4..0]
166
Software Interface - C
NIOS II IDE generates macros automatically during build process
Macros defined in system.h file
Example of user C-code that references Bitswap custom instruction:
#define ALT_CI_<your instruction_name>(instruction arguments)
#include "system.h"
int main (void)
{
int a = 0x12345678;
int a_swap = 0;
a_swap = ALT_CI_BSWAP(a);
return 0;
}
167
Assembly Language Interface
Assembler syntax for the custom instruction:

custom N, rC, rA, rB
Custom
instruction
opcode
number
Destination
register
for result
Operand 2
Two Examples:
custom 0, r6, r7, r8
custom 3, c1, r2, c4
168
Operand 1
r = Nios II processor
register
c = Custom instruction
internal register
A-MNL-NIOSII-04
56
Why Custom Instruction?
Reduce Complex Sequence of Instructions to One Instruction

Example: Floating Point Multiply
float
float a,
a, b,
b, result_slow,
result_slow, result_fast;
result_fast;
result_slow
/*
result_slow == aa ** b;
b;
/* Takes
Takes 266
266 clock
clock cycles
cycles */
*/
result_fast
result_fast == ALT_CI_fpmult(a,b);
ALT_CI_fpmult(a,b); /*
/* Takes
Takes 66 clock
clock cycles*/
cycles*/
Significantly
SignificantlyFaster!
Faster!
Typical Flow
Profile Code
Identify Critical Inner Loop
Create Custom Instruction Logic
z
Replace One or All Instructions in Inner Loop
Import Custom Instruction Logic into Design

Call Custom Instruction from C or Assembly
169
Custom Instruction vs Peripheral
Custom Instruction can execute in a single cycle

No overhead for call to custom Hardware
L0
L1
Custom
Instruction
L0
Access to same hardware as peripheral takes

multiple cycles
Write DataA, then write DataB, and finally read Result
Peripheral memory map
0x408
0x404
0x400
L0
L1
170
Result
DataB
DataA
Custom
Peripheral
L0
Multi-Cycle Custom Instructions

stalls while awaiting result
Nios Clock Cycles
Clock cycles = 3
custom
DataA
DataB
REG
----Next Instr
REG
Custom Instruction
Processor
Result
171
A-MNL-NIOSII-04
57
Pipelined Custom Instructions

not always needed for each input
Clock Cycles = 1
Route start sig to reg clk_en
DataA
REG
custom
Nios Clock Cycles
DataB
Custom Instruction
Result
custom
custom
REG
custom
custom
Next Instr
Result
172
Accelerating CRC
Implementing
the shift and XOR for each

bit takes many clock cycles ~50
Software algorithms tend to use look up
tables to pre-compute each byte
Parallel Hardware is fastest
173
xor/shift
in(0)
xor/shift
reg
in(14)
xor/shift
in(15)
CRC Custom Instruction
CRC16-CCITT needs to be preset to 0xFFFF at

the start of each computation
Can use the Data B input to select between run
and load
Use of prefix would waste a clock cycle
////reset
resetcrc
crc
ALT_CI_CRC(0xFFFF,1);
ALT_CI_CRC(0xFFFF,1);
////run
runcrc
crc
ALT_CI_CRC(word,0);
ALT_CI_CRC(word,0);
Control
DataA(31-0)
Data in
CRC Reg
DataB(0)
174
CRC
Custom Instruction
Result(15-0)
Init / nRun
A-MNL-NIOSII-04
58
Multi-Masters and Direct

Memory Access (DMA)
Traditional Multi-Masters
Direct
Memory Access (DMA)
Processor Waits For Bus During DMA

Masters
System CPU
(Master 1)
System
System
Bottleneck
Bottleneck
Control
direction
100Base-T
(Master 2)
Arbiter Determines
Which Master Has
Access To Shared
Bus
DMA
Bus
Arbiter
DMA
Bus
Arbiter
DMA
Arbitor
System Bus
Slaves
176
Program
Memory
I/O
1
I/O
2
Data
Memory
Avalon Simultaneous Multi-Mastering Bus
Has Benefits of a Switch Fabric and Slave-Side Arbitration

Shared Bus & Share Arbiter are No Longer the Bottleneck
Multiple Master Transactions Can Operate Simultaneously
z
As long as they dont access the same slave in the same bus bycle
I/O Devices Can be Grouped Based on Bandwidth Requirement
Trade-Off
Hardware Resource Usage Increases
Uses Fairness
Arbitration
automatically
generated by
SOPC Builder
CPU
CPU 00
Masters
DMA
DMA
CPU
CPU 11
System
Switch
Fabric
Arbiter
Arbiter
Slaves
177
Program
Program
Memory
Memory 00
I/O
I/O
Data
Data
Memory
Memory 00
Arbiter
Arbiter
Display
Display
Control
Control
Data
Data
Memory
Memory 11
Custom
Custom
Function
Function
Program
Program
Memory
Memory 11
A-MNL-NIOSII-04
59
DMA Peripheral
Provides Bus Master Capability to Any Nios II

Peripheral
FIFO Depth = 2
DMA Peripheral
FIFO
Master Port
1
Master Port
2
Start Addr
Start Addr
# Bytes
# Bytes
Addr Incr
Addr Incr
Direction
Control Port
178
Data Flow with DMA Peripheral

Master 2
DMA
Master 1
(Nios II CPU)
I
SPI
Avalon
Avalon
Arbiter
Program
Memory
179
I/O
1
I/O
2
Data
Memory
1
Accelerate Software Execution
Use custom hardware peripheral with DMA
Avalon
Switch
Fabric
Program
Memory
180
DMA
DMA
Processor
DMA
DMA
Processor & Accelerator Run Concurrently

More Work Per Clock
Lower fMAX, Power, Cost
Arbiter
Arbiter
Arbiter
Arbiter
Data
Memory
Data
Memory
Accelerator
A-MNL-NIOSII-04
60
Accelerate Software Execution
Example: CRC Algorithm (64 Kbytes)

25,000,000
Clock Cycles
20,000,000
15,000,000
10,000,000
27 Times
Faster
5,000,000
530
Times
Faster
0
Software Only
181
Custom
Instruction
Hardware
Accelerator
Custom Streaming Slave Peripherals

For
using DMA with other slow peripherals
Example: UART
up to three outputs to Avalon Slave
dataavailable
readyfordata
endofpacket
adress
control
Custom
Streaming
Slave
Peripheral
writedata
readdata
Avalon
Adds
dataavailable
Readyfordata
endofpacket
182
Streaming Slave Peripheral Signals
dataavailable
Indicates that the peripheral has data available to be read
by DMA or other master
ie, there is data in the rx buffer or register
readyfordata
Indicates that the peripheral is able to receive data written
by DMA or other master
Ie. the tx buffer or register is not full
endofpacket
Usage not defined
DMA can be optionally set to end transfer
183
A-MNL-NIOSII-04
61
Custom Master Peripherals
Can integrate DMA function
Simpler than Slave peripherals
Transaction are between Master and Avalon,

not Slave
Eg. VGA that takes data from memory directly

Assert outputs until waitrequest is low
address
writedata
readdata
Avalon
control
Custom
Master
Peripheral
waitrequest
184
Master Read Transfer

Assert
addr, be, read

Wait for waitrequest = 0
Read in Data
End of transfer
185
Master Write Transfer

Assert
addr, be, read

Assert Write Data
Wait for waitrequest = 0
End of transfer
186
A-MNL-NIOSII-04
62
Avalon Burst Support

New
Signals for Bursting Masters, Slaves
Burstcount, beginbursttransfer
Several
Bursting Styles Exist
Wrapping, Off-Boundary, Interleaved

Maximum Burst Size
Tool
Automatically Reconciles:
Data Width, Burst Size,

Bursting-to-non-bursting Transfers
187
Avalon Master-Slave Connections
188
View => Show Master Connections

Observe and configure Avalon connections
Master Arbitration Scheme
Nios II Multi-Master Avalon Switch Fabric Utilises

Fairness Arbitration Scheme
Each Master/Slave pair is assign an integer shares
Upon conflict Master with most shares takes bus until all
shares are used
Master with least shares then takes bus until all shares are
used
Assuming all Masters continuously request the bus, they will
each be granted the bus for a percentage of time equal to the
percentage of total master shares that they own
CPU
7 Shares
SPI DMA
1 share
189
A-MNL-NIOSII-04
PCI DMA
2 shares
63
Set Arbitration Priority
190
View => Show Arbitration Priorities
Avalon Arbitration Behavior

Master A Shares = 4
Master A
Master B
Master B Shares = 2
Arbiter
Slave
Arbiter (continuous accesses)
Master A
Master B
191
Lab 5
Custom Instruction and
(optional) DMA Controller
45 mins
A-MNL-NIOSII-04
64
Working with the

Development Board
Ensure Unused I/O are Tri-State
The FPGA may connect to components on the board not

used by your design
There is a connection between FPGA and MAX device to
force reconfiguration
Active low, pulled high
194
Assignments -> Device

For Stratix devices, be sure to set Dual Purpose pins to
Use as Regular IO
Clock Distribution
PLL
SDRAM
Nios II
PLL
Zero Skew
Buffer
CLK in
(50 MHz)
Zero Skew
Buffer
FPGA
required to meet SDRAM I/O timing
Introduces -60 phase shift relative to Nios II

CLK
in is socket crystal or external input
Resistor changes required for external

See
195
board schematic and ref design
A-MNL-NIOSII-04
65
Hardware Configuration Process

8 MB Flash
Flash Configuration
Two FPGA images
z
0x600000
Safe FPGA
Image
Stratix
User FPGA
Image
MAX EPM7128 Configures FPGA from

Flash
Upon power up or press of Reset Config
z
Data
Address
Safe Image
User Image
0x700000
MAX
MAX Device Loads User Image into FPGA

If This Fails MAX Device Loads Safe Image
Failure includes no user image present
Upon press of Safe Config

z
196
MAX Device Loads Safe Image into FPGA
Flash Memory Configuration

8 MB Flash
0x700000
0x600000
Safe FPGA
Image & S/W
User FPGA
Image
Data
Stratix
0x500000
Address
0x400000
SRAM
0x300000
User
Software
0x200000
0x100000
0x000000
197
Boot Copier
Use
Flash for Program

Storage
Running from Flash is slow
Data
II IDE Automatically
Prepends Boot Copier to
Program Code
For Custom Boards:

(see again Nios II Flash
Programmer User Guide)
Must create your own flash

programmer design to transport data
to the flash on your board
198
Address
Nios
if Reset Address is in Flash and

Program Memory is in RAM
Stratix
User
Software
SRAM
8 MB Flash
Boot Copier
my_sw.flash
my_sw.elf
A-MNL-NIOSII-04
66
Nios II Flash Programmer
Downloads flash content to CFI flash device

Communication is over JTAG interface
Can also download to any Altera EPCS Serial Configuration
Device connected to FPGA
Two-step process:
Send Flash Programmer Design
Send Flash Content
Flash Content
199
Flash Programmer Design contains
Nios II CPU
JTAG UART
Active serial memory interface
Tri-state bridge
CFI-compatible flash interface
System ID peripheral on-chip memory for firmware and buffers
Flash Content can include:

FPGA hardware configuration image
Software content
Arbitrary content
200
Can program Flash from Nios II IDE or command line

Nios II IDE is recommended method
201
A-MNL-NIOSII-04
67
Command Line Utilities

elf2flash
sof2flash
bin2flash
nios2-flash-programmer
(see Nios II Flash Programmer User Guide for details)
202
Instantiating Flash in Target System
203
Must set target board to appropriate development kit
Need CFI (Common Flash Interface) Flash Memory
EPCS Serial Flash Controller reqd if booting from EPCS device
Flash Programmer Design
What if I Have a Custom Board?

Import board settings into the SOPC Builder using
mk_target_board script
z
Specify flash devices and designator numbers
Clock frequency
Device family
Create flash programming design in SOPC Builder

based on .PTF generated from above script
Generate .SOF file for flash design
204
See Nios II Flash Programmer User Guide for details
A-MNL-NIOSII-04
68
What If Safe Flash Image Overwritten?
Open Nios II SDK Shell

Start > Programs > Altera > Nios II Development Kit
<installed version> > Nios II SDKShell
Change to factory-recovery directory for your

development kit
Run flash-restoration script
cd examples/factory_recovery/niosII_cyclone_1c20
./restore_my_flash
205
Follow the scripts instructions
Diverse Portfolio of Nios Development Kits
eg. Stratix and Cyclone

Altera
Microtronix
Daughter Cards
Microtronix: VGA / PS2

SLS: USB 2.0
El Camino GmbH: RF A/D D/A
EasyFPGA: USB 2.0
The List Keeps Growing

206
Lab 6
The Flash Programmer
10 mins
A-MNL-NIOSII-04
69
Summary
Nios II - Leads The Industry

Highest
Highest
Performance
Performance
Multi-Processor
Hardware Acceleration
Custom Instructions
Greatest
Greatest
Flexibility
Flexibility
Processors
Peripherals
Optimized Interconnect
Most
MostPowerful
Powerful
Design
DesignTools
Tools
Fastest
FastestTime
Time
to
toMarket
Market
209
SOPC Builder
Nios II IDE
On-Chip Processor Debug
Concept to System in Minutes

FPGA > HardCopy Structured
ASIC
Altera Technical Support
210
Reference Quartus II On-Line Help

Consult Altera Applications (Factory Applications Engineers)
MySupport: http://www.altera.com/mysupport
Hotline: (800) 800-EPLD (7:00 a.m. - 5:00 p.m. PST)
World-Wide Web: http://www.altera.com
Use Solutions to Search for Answers to Technical Problems
View Design Examples
Field Applications Engineers: Contact Your Local Altera Sales Office
Receive Literature by Mail: (888) 3-ALTERA
FTP: ftp.altera.com
A-MNL-NIOSII-04
70
Learn More Through Technical Training

Instructor-Led Training
On-Line Training
With Altera's instructor-led training courses, you can:
With Altera's on-line training courses, you can:
Listen to a lecture from an Altera technical training

engineer (instructor)
Take a course at any time that is convenient for you
Take a course from the comfort of your home or

Complete hands-on exercises with guidance from an office (no need to travel as with instructor-led courses)
Altera instructor
Each on-line course will take approximately 2-3
hours to complete.
Ask questions and receive real-time answers from
an Altera instructor
Each instructor-led class is one day in length (8
working hours).
www.altera.com/training
View Training Class Schedule & Register for a Class
211
Thank You
Appendix
A-MNL-NIOSII-04
71
Introduction to Altera Devices
Programmable Logic Families

High & Medium Density FPGAs
z
Stratix II, Stratix, APEX II,

APEX 20K, & FLEX 10K
Low-Cost FPGAs
z
Cyclone II, Cyclone & ACEX 1K
FPGAs with Clock Data Recovery

z
Stratix GX & Mercury
CPLDs
z
MAX II, MAX 7000 & MAX 3000
Embedded Processor Solutions

z
Nios, Nios II
Configuration Devices
z
214
EPC
Introduction to Altera Design Software

Software
& Development Tools:
Quartus II
z Stratix
II, Stratix GX, Cyclone II, HardCopy Stratix,

MAX II, APEX 20K/E/C, Excalibur, & Mercury
Devices
z FLEX 10K/A/E, ACEX 1K, FLEX 6000, MAX 3000A,
MAX 7000S/AE/B Devices
Quartus II Web Edition

z Free
z Not
version
all features & devices included
MAX+PLUS II
z All
215
FLEX, ACEX, & MAX Devices
Nios II vs Nios
Nios II
216
Pipelined RISC Architecture

32-Bit Instructions
Flat Register File
32-Bit Data Path
Optional Instruction & Data Cache
Custom Instructions
Branch Prediction
Nios

16-Bit Instructions
Windowed Register File
16-bit or 32-Bit Data Path
Optional Instruction & Data Cache
Custom Instructions
A-MNL-NIOSII-04
72
Nios II/f Fast version
217

32-Bit Instruction and Data Paths
6 Stage Pipeline
32 External Interrupt Sources
Configurable Size Instruction Cache
Dynamic Branch Prediction
Hardware Multiply
Barrel Shifter
Custom Instructions
Configurable Size Data Cache
Hardware Breakpoints
Optional Hardware Divide
135MHz
1.2 DMIPS/MHz
<1800 LEs and <900 ALMs
Nios II/s Standard version
218

5 Stage Pipeline
Configurable Size Instruction Cache
Branch Prediction
Hardware Multiply
Barrel Shifter
Custom Instructions
135MHz
0.75 DMIPS/MHz
Nios II/e Economy version
219

5 Stage Single Instruction Pipeline
Custom Instructions
150 MHz
0.16 DMIPS/MHz
A-MNL-NIOSII-04
73
Clock Domain Crossing - Clock Adapters

D1
D2
D3
D4
CLK 1
CLK 2
CLK 1
D2
CLK2 samples D2
while it is changing
CLK 2
D4 is synchronized and valid
D3
D4
220
Note: Can Compile Code Right Into Quartus II .sof File
Target on-chip memory => .hex

file containing Nios II program
Smart Compilation must have been

on in first Quartus II compile to
incrementally include .hex file into .sof
221
What is Trace Data?

Collection
of instructions executed by CPU

JTAG Console will display it as load/store
operations or in disassembled instructions
(eg. Nios II CPU instructions)
15.28: 008032BC 0xe0809d17 ldw r2, 628(fp)
15.28: 008032C0 0xe1809d17 ldw r6, 628(fp)
15.28: 008032C4 0x10800017 ldw r2, 0(r2)
15.28: 008032C8 0x31800104 addi r6, r6, 4
15.28: 008032CC 0xe1809d15 stw r6, 628(fp)
15.28: 008032D0 0x003fde06 br 0x80324c
15.30: 0080324C 0x11000015 stw r4, 0(r2)
15.30: 00803250 0x003fe006 br 0x8031d4
222
A-MNL-NIOSII-04
74
What is a Software Breakpoint?

Implemented
by inserting an interrupt into

the code (TRAP instruction)
Program memory must be writable (not
ROM)
Flash wont work either due to write sequence
Used
to break at a line of code
223
What is a Hardware Breakpoint?
Implemented by triggering a dedicated hardware

interrupt
Used to break on hardware conditions:
Specified data address and/or data value
Can also break on instruction (similar to software
breakpoint) for code stored in ROM
Option to halt the processor, gather trace data or
trigger out
Doesnt matter whether program memory is

writable since it doesnt touch the code, so you
can debug code stored in ROM or Flash
224
Micrium uC/OS-II Licensing:
There are actually three licenses available for MicroC/OS-II:
1. A developers license - Included with every copy of MicroC/OS-II shipped with an Altera development
kit. This enables customers to develop applications using the RTOS which are targeted for the Altera
development board.
2. Annual MicroC/OS-II subscription . Customers writing application code for their own board (or any
board other than Altera development boards) must purchase an annual subscription from which entitles
them to the following:
License for 3 developers to create as many designs as they wish for 1 year using MicroC/OS-II
Perpetual license to support designs created during the subscription period (i.e. fix bugs, minor
modifications).
Additional subscription license seats may be purchased per developer.
225
3. Project License . Customers who require licenses for more than 10 developers should purchase a
Project license which enables an unlimited number of designers to develop for that project using
MicroC/OS-II.
A-MNL-NIOSII-04
75
Arbitration with MURL Length Set to 3

Master A Shares = 4
Master A
Master B
Master B Shares = 2
Arbiter
Slave MURL = 3
Slave
Minimum unun-interrupted run length
(hidden feature that is set in .PTF file)
Arbiter (continuous accesses)
Master A
Master B
226
A-MNL-NIOSII-04
76

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Designing with Nios II and SOPC Builder

Designing with Nios II

will be able to:

Describe the Nios II softcore processor

Copyright 2005 Altera Corporation

Nios II Hardware Development

Copyright 2005 Altera Corporation

Designing with Nios II and SOPC Builder

The Programmable Solutions Company

Intellectual Property (IP)

Copyright 2005 Altera Corporation

What is Nios II?

Alteras Second Generation Soft-Core 32 Bit RISC Microprocessor

Avalon Switch Fabric

Copyright 2005 Altera Corporation

Designing with Nios II and SOPC Builder

Problem: Reduce Cost, Complexity & Power

Solution: Replace External Devices

Copyright 2005 Altera Corporation

Copyright 2005 Altera Corporation

FPGA Hardware Design Flow

- Behavioral or Structural Description of Design

Place & Route

Copyright 2005 Altera Corporation

Designing with Nios II and SOPC Builder

FPGA Hardware Design Flow

- Verify Performance Specifications Were Met

Gate Level Simulation

Test FPGA on PC Board

Copyright 2005 Altera Corporation

Development Kits, Stratix & Cyclone Edition

(40 I/O pins each)

Copyright 2005 Altera Corporation

Standard Design Block Diagram

Avalon Switch Fabric

Copyright 2005 Altera Corporation

Designing with Nios II and SOPC Builder

Nios II System Architecture

Avalon Switch Fabric

Copyright 2005 Altera Corporation

Nios II Block Diagram

Copyright 2005 Altera Corporation

Nios II Processor Architecture

Pipelined RISC Machine

32 General Purpose Registers

Copyright 2005 Altera Corporation

Designing with Nios II and SOPC Builder

II Processor Comes In Three ISA Compatible

STANDARD: Balanced for Speed and

No Changes Required When CPU is Changed

Copyright 2005 Altera Corporation

Binary Compatibility / Flexible Performance

H/W Multiplier &

Copyright 2005 Altera Corporation

Hardware Multiplier Acceleration

Nios II Economy version - No Multiply Hardware

Nios II Standard - Full Hardware Multiplier

Uses GNUPro Math Library to Implement Multiplier

Nios II Fast - Full Hardware Multiplier

Copyright 2005 Altera Corporation

Designing with Nios II and SOPC Builder

Hardware Multiplier Support

Stratix and Stratix II DSP Blocks