INDEX

Sr.
No

Title of the Experiment

Page
No.

Study of BASIC Gates: AND, OR, NOT

NAND and NOR GATES

To verify universal gates NAND and NOR

10

Study of Full & Half Adder & Subtractor using

Gates

17

To implement circuit that converts binary to

gray and gray to binary

20

(A) To implement 3 X 8 Decoder.

(B) Using 3 X 8 Decoder, implement 4 X 16
Decoder.

24

To implement 8X1 Multiplexer.

30

Study of Demultiplexer

33

(A) To implement 4-bit comparator.

(B) Using 4-bit comparator implements 8-bit
comparator.

35

9
10
11
12

To verify various flip-flops like D, T, and JK.

Study of Shift Register
To implement 3-bit and 4-bit binary counters.
To implement BCD counter.

39
45
47
50

Date

Sign.

Experiment 1
Aim: -

Study of BASIC Gates:

AND, OR, NOT, NAND and NOR GATES

Apparatus: -

IC 7404, IC 7432, IC 7408, IC 7400, IC 7402, IC 7486, IC 74266,Power supply,

connecting wires, Multimeter, Bread Board etc.

Standard Procedures:Analyzing the Problem:Logic gates are the basic components in digital electronics. They are used to create digital circuits
and even complex integrated circuits. For example, complex integrated circui may bring already a
complete circuit ready to be used microprocessors and microcontrollers are the best example but inside
them they were projected using several logic gates.
A gate is a digital electronic circuit having only one output but one or more inputs. The output or a
signal will appear at the output of the gate only for certain input-signal combinations. There are many
types of logic gates; such as AND, OR and NOT, which are usually called the three basic gates. Other
popular gates are the NAND and the NOR gates; which are simply combinations of an AND or an OR
gate with a NOT gate inserted just before the output signal. Other gates include the XOR Exclusive-OR
and the XNOR "Exclusive NOR" gates.
All the logic gates used in the exercises below are known as TTL (transistor-to-transistor) Logic.
These have the convenient property that the output of any gate can be used directly as input to another
gate. All these TTL circuits are operated from a 5 V power supply, and the binary digits 0 and 1 are
represented by low and high voltages on the gate terminals.
AND gate
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. X.Y. Bear in mind that this dot is sometimes
omitted i.e. XY
Logic eqn. Y = A.B

3-input AND gate

OR gate
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs
are high. A plus (+) is used to show the OR operation.
Logic eqn. Y = A+B.

3-input OR gate

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It
is also known as an inverter. If the input variable is A, the inverted output is known as NOT A.
This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below
show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be
done using NOR logic gates in the same way.
Logic eqn. Y =A.

NAND gate
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a
small circle on the output. The small circle represents inversion.
Logic eqn. Y = A. B

3 Input NAND gate:

NOR gate
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs
of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small
circle on the output. The small circle represents inversion.
Logic eqn. Y =A + B.

3 input NOR gate

EXOR gate
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of
its two inputs are high. An encircled plus sign ( ) is used to + show the EOR operation.
Logic eqn. Y= A B or AB + AB .

EXNOR gate
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low
output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small
circle on the output. The small circle represents inversion.

Designing the Solution:Pin diagram of all the above gates are:

Fig Pin Diagrams of IC 7404, 7402, 7400,7486,74266

Implementing the Solution:

Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the
chip package).
Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
Make the connections as per the circuit diagram.
Switch on VCC and apply various combinations of input according to truth table.
Note down the output readings for half/full adder and sum and the carry bit for different
combinations of inputs in following Tables where S & V indicating logic value of the output.
And fill your result in S (V) and C (V) in voltage. Where 5V indicating logic 1 and 0V
indicating logic 0.

Testing the Solution:-

Conclusion:All the truth tables are verified.

Experiment 2
Aim: -

To verify universal gates NAND and NOR

Apparatus: -

IC 7402, IC 7400, Power supply, Connecting wires, Multimeter, Breadboard etc.

Standard Procedures:Analyzing the Problem:NAND GATE:

NAND is the contraction of AND NOT gates.

It has two or more inputs and only one output i.e. Y = A B.
When all the inputs are HIGH, the output is LOW. If any one or both the inputs are LOW, then the
output is HIGH.
The Logic symbol and the truth table of NAND gate is as shown here.
The small circle (or bubble) represents the operation of inversion.
The NAND gate is equivalent to an OR gate with the bubble at its inputs which are as shown.

NOR GATE:

NOR is the contraction of OR NOT gates.

It has two or more inputs and only one output i.e. Y = A + B.
When all the inputs are LOW, the output is HIGH. If any one or both the inputs are HIGH, then the
output is LOW.
The Logic symbol and the truth table of NOR gate is as shown here.
The small circle (or bubble) represents the operation of inversion.
The NOR gate is equivalent to an AND gate with the bubble at its inputs which are as shown.

A universal gate is a gate which can implement any Boolean function without need to use any
other gate type.
The NAND and NOR gates are universal gates.
In practice, this is advantageous since NAND and NOR gates are economical and easier to
fabricate and are the basic gates used in all IC digital logic families.

Designing the Solution:

NAND GATE AS A UNIVERSAL GATE :
To prove that any Boolean function can be implemented using only NAND gates, we will show
that the AND, OR, and NOT operations can be performed using only these gates.

IMPLEMENTING INVERTER USING NAND GATE :

The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).
1. All NAND input pins connect to the input signal A gives an output A.
2. One NAND input pin is connected to the input signal A while all other input pins are
connected to logic 1. The output will be A.

IMPLEMENTING AND USING NAND GATE :

An AND gate can be replaced by NAND gates as shown in the figure (The AND is
replaced by a NAND gate with its output complemented by a NAND gate inverter).

IMPLEMENTING OR USING NAND GATE:

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is
replaced by a NAND gate with all its inputs complemented by NAND gate inverters).

NOR GATE AS A UNIVERSAL GATE:

To prove that any Boolean function can be implemented using only NOR gates, we will show that
the AND, OR, and NOT operations can be performed using only these gates.

IMPLEMENTING INVERTER USING NOR GATE :

The figure shows two ways in which a NOR gate can be used as an inverter (NOT
gate).
o
All NOR input pins connect to the input signal A gives an output A.
o
One NOR input pin is connected to the input signal A while all other input pins are
connected to logic 0. The output will be A.
o

IMPLEMENTING OR USING NOR GATE :

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by
a NOR gate with its output complemented by a NOR gate inverter).

IMPLEMENTING AND USING NOR GATE :

An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is
replaced by a NOR gate with all its inputs complemented by NOR gate inverters).

Basic IC needed are NAND gate and NOR gate.

IC diagram are given as below

Fig Pin Diagram of NAND & NOR GATES

Implementing the Solution:

Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the
chip package).
Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard.
Make the connections as per the circuit diagram.
Switch on VCC and apply various combinations of input according to truth table.
Note down the output readings for half/full adder and sum and the carry bit for different
combinations of inputs in following Tables where S & V indicating logic value of the output.
And fill your result in S (V) and C (V) in voltage. Where 5V indicating logic 1 and 0V
indicating logic 0.

Testing the Solution:Truth Tables:

NAND Gate

Inverter Using Nand Gate

NOR Gate

And Using Nand Gate

Or Using Nand Gate

Inverter Using Nor Gate

Or Using Nor Gate

And Using Nor Gate

Conclusion:A universal gate is a gate which can implement any Boolean function without need to use any
other gate type. The NAND and NOR gates are universal gates.

Digital Logic Design (130701)

Lab Manual

Experiment 3
Aim: -

Study of Full & Half Adder & Subtractor using Gates

Apparatus: -

IC 7402, IC 7400, Power supply, Connecting wires, Multimeter, Breadboard etc.

Standard Procedures:Analyzing the Problem:To implement half and full adder we require X-OR gates, AND gates, OR Gate. Pin Diagrams of
these gates are as below.

Derive the Equation for Sum and Carry.

Pin Diagrams of Basic gates ICs used in experiment:-

XOR Gate(IC 7486)

AND Gate(IC 7408)

OR Gate(IC 7432)

Truth Tables of Basic gates used in experiment:-

E.C Dept, GEC-DAHOD

Page 17

Digital Logic Design (130701)

Lab Manual

Designing the Solution:-

Half adder and Full adder circuits

Half Subtractor using basic gates:-

Full Subtractor using basic gates:-

Fig Half Subtractor and Full Subtractor circuits

E.C Dept, GEC-DAHOD

Page 18

Digital Logic Design (130701)

Lab Manual

Implementing the Solution:

Plug the chips you will be using into the breadboard. Point all the chips in the same direction with
pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip
package).
Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard.
Make the connections as per the circuit diagram.
Switch on VCC and apply various combinations of input according to truth table.
Note down the output readings for half/full adder and sum and the carry bit for different
combinations of inputs in following Tables where S & V indicating logic value of the output. And
fill your result in S (V) and C (V) in voltage. Where 5V indicating logic 1 and 0V indicating logic
0.

Testing the Solution:

Write Observations in following tables and check the output:
Truth Table:-

Half Adder

Half Subtractor

Full Adder

Full Subtractor

Conclusion:By using various logic gate Ics we can perform the full or half adder and check the truth table.

E.C Dept, GEC-DAHOD

Page 19

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

2. DECADE COUNTER 74LS90

Aim: To construct and verify the working of a single digit decade counter using IC 7490.
Apparatus: 1) IC7490 Decade counter kit
2) Connecting patch cards.
Circuit Diagram:-

FIGURE 1

Procedure:
1. Wire the circuit diagram shown in figure 1.
2. Connect the 1Hz clock to pin CPO.(14)
3. Connect the reset terminals (MR1 & MR2) to high and set terminals (MS1 & MS2) to zero
and observe the output.
4. Now connect set and reset inputs to zero and observe the outputs.
5. Record the counter states for each clock pulse.
6. Design mod 6 counter using IC 7490 as shown in fig 2.
7. Record the counter states for each clock pulse.
8. Now Construct decade counter using J K F/Fs and record the counter states

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

MOD 6 COUNTERS:

Truth Table:-

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

Result: - Verified the working of a single digit decade counter using IC 7490.

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

3. UNIVERSAL SHIFT REGISTER-74LS194

Aim: - To study the following applications of the Universal shift register using IC 74194.
a. Shift Right Logic
b. Shift Left Logic
c. Parallel Load

Apparatus:1. Universal Shift Register using IC 74194 Trainer boards.

2. 5v fixed DC power supply.

Circuit Diagram:-

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

Procedure:STEP: 1. MASTER RESET

Set the inputs as below and observe the out puts as per table 1

A logic 0 on MR resets all outputs to logic 0 irrespective of other inputs.

STEP: 2 PARALLEL LOAD
In this step we load the data parallel. Set the inputs as below and observe the outputs.

Here when S1 & S0 are both logic 1 the input data is transferred parallely to output at the
clock positive transition change the input data and observe the change at the output .
STEP: 3. SHIFT LEFT LOGIC 0 .
Set Q0, Q1, Q2, Q3 to 1 1 1 1 by putting DSL to Logic 1 .
While running the above step, change the logic input DSL to logic 0 And S0 to logic 0 in
the same sequence .Observe the following outputs after each clock pulse and verify .

In the sequence 4 clock pulses logic o s are shifted left successively with each clock pulse .
STEP: 4. SHIFT LEFT LOGIC 1 S
Set the Q0 Q1 Q2 Q3 to 0 0 0 0 by setting DSL input to logic 0 .
Prepared By SURESH BABU M
Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

Now switch DSL input to logic 1 and observe the shifting of logic 1 s to left as below .
Observe the following outputs after each clock pulse and verify.

STEP: 5 . SHIFT RIGHT LOGIC 0

Set the Q0 Q1 Q2 Q3 to 1 1 1 1 by setting DSR input to logic 1 . Repeat step 4 and parallel
load logic 1s in all the 4 outputs. Change the logic inputs of DSR to logic 0 and then of S1 to
logic 0 in the same sequence. Observe the following outputs after each clock pulse and verify.

STEP: 6 SHIFT RIGHT LOGIC 1s

Now at this condition of all 0 at the outputs switch DSR to logic 1 this will enable all logic
as serial data and logic 1 s will be shifted successively with each clock pulse as shown below .
Observe the following table and verify the outputs .

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

STEP: 7. In the above steps for shift left or shift right operation ,(step 3 4 5 6 ) if both the S0
&S1 switches are forced to logic 0 , then shifting operation will cease and whatever is the
output data it will freeze or hold. Observe this condition and verify.

Result:- Verified the applications of the Universal shift register using IC 74194

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

6. 8:1 Multiplexer 74151

Aim: To verify the truth table of a given 8 to 1 Multiplexer and 1 to 8 De-Multiplexer using IC
74151 and 74138 .
Apparatus:
1. 8 to 1 Multiplexer Trainer kit .
2. Connecting patch chords.
Theory:
Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one output.
By using control signals (select lines ) we can select any input to the output. Multiplexer is also
called as data selector because the output bit depends on the input data bit that is selected. The
general idea about the multiplexing the circuit has N input signals, M control signals and 1
output signal.8 X 1 Multiplexer has 8 input signals and one output signal, three data control or
select lines. These data control lines are nothing but 3-bit binary code on the data control signal
inputs which will allow the data on the corresponding data input to pass through to the data
output.

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

IC Applications LAB

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

Logic Diagram:

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

Procedure:
1. Switch on the trainer by connecting power chord to the AC mains
2. By using pulsar switch reset the control signals (Q2 Q1 Q0 ) to 0 0 0
3. Connect the output terminals (pin 5) to the output LEC indicator.
4. Apply logic 1 to I0 input (pin 4) by using the switch. The output LED indicator glows
5. Apply logic 0 to I0 input (pin 4) by using the switch. The output LEC indicator is off.
6. Verify the truth table by changing the control 3 signal states using pulsar switch from 000 to
111

Result: The truth table of 8 to 1 multiplexer has been verified.

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

7. RAM (164) - IC 7489

Aim: -To study the operation of the RAM Ic7489.
Apparatus: 1. RAM IC 7489 Trainer kits.
2. Connecting wires.
Pin Diagram: -

Operation: RAM IC 7489 is 16 words x 4-bit Read/WriteMemory.

The Truth Table for the RAM IC 7489 is given below.

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

IC Applications LAB

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

The memory Enable pin is used to select 1- of-n ICs i.e. like a Chip Select signal. For simply
city, the memory enable pin is permanently held low.
The address lines are given through an up /down counter with preset capability.
The set address switch is held high to allow the user choose any location in the RAM, using the
address bits.
The address and data bits are used to set an address and enter the data.
The Read/Write switch is used to write data on to the RAM.
Procedure:
This experiment has 3 stages Clearing the memory, data entry (Write operation) and
data verification (Read operation).
Clearing the Memory: -The RAM IC 7489 is a volatile memory. This means that it will lose the
data stored in it, on loss of power. However, this dose not means that the content of the memory
becomes 0h, but not always. The RAM IC 7489 does not come with a Clear Memory signal.
The memory has to be cleared manually.
1. Position the Stack/Queue switch in the Queue position.
2. Position the Set Address switch in the 1 position.
3. Set the address bits to 0h (first byte in the memory)
4. Position the Set Address switch in the 0 position to disable random access and enable the
counter.
5. Position the Read/Write switch in the Write position to write data on to the memory.
6. Set the data bits to 0h (clearing the content)
7. Observe that the LEDs (D3 to D0) glow. This is to indicate that the content is 0h. Refer the
truth table above and observe that the data outputs of the RAM will be compliments of the data
inputs.
8. Position the Increment/Decrement switch in the Increment position.
9. Press the Clock to increment the counter to the next address. As the Read /Write switch is
already in the Write position, and the data bits are set to the 0h, the content in the new location
is also replaced with 0h.

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

Write Operation: 1. Assume that the following data has to be written on to the RAM. The address and data are
given in the hexadecimal format.

2. Position the Stack/Queue switch in the Queueposition.

3. Position the Read/Write switch in the Write position to enable the entry of data in to the
RAM.
4. Position the Set Address switch in the 1 position to allow random access of memory.
5. Set the desired address (any address at random) using the address bit switches.
6. Set the desired data (refer table for the data to be entered in each location) using the data bit
switches.
7. Observe that the data is indicated by the LEDs (D3 toD0). This is because the data is written
on to the RAM.
8. Also observe that the data is indicated by the data outputs is the compliment of the data input
(refer truth table condition ME =L and WE=L) .
Prepared By SURESH BABU M
Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

ANNAMACHARYA INSTITUTE OF SCIENCE AND TECHNOLOGY

IC Applications LAB

9. After each data entry, make a note of the location where data is entered. This is to make sure
that we are not re entering data in the same location.
10. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the above table
11. Position the Read/Write switch in the Read position, to disable data entry.
12. This completes data entry.
Read Operation: 1. Position the Stack/Queue switch in the Queue position.
2. Position the Set Address switch in the 0 position to allow random access of memory.
3. Position Read/Write switches in the Read position, to disable unauthorized entry of data.
4. Set the desired address (any address at random).
5. Observe that the data entered in the location is indicated by the LEDs (D3 toD0). This is
because the data was written during the data entry procedure.
6. Also observe that the data indicated by the data out puts is the compliment of the data input
(refer truth table condition ME=L and WE=H).

Result: - Operation of the RAM Ic7489 has been verified.

Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH,

Cont No.+91-80992 28247

Logic Design Laboratory Manual

39

___________________________________________________________________________

EXPERIMENT: 12

FLIP FLOPS

AIM: Truth Table verification of

RS Flip Flop
1)
2)
T type Flip Flop.
D type Flip Flop.
3)
4)
JK Flip Flop.
5)
JK Master Slave Flip Flop.
LEARNING OBJECTIVE:
 To learn about various Flip-Flops
 To learn and understand the working of Master slave FF
 To learn about applications of FFs
 Conversion of one type of Flip flop to another
COMPONENTS REQUIRED:
IC 7408, IC 7404, IC 7402, IC 7400, Patch Cords & IC Trainer Kit.
THEORY:
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation.
The latch (flip-flop) is a basic bi-stable memory element widely used in sequential logic
circuits. Usually there are two outputs, Q and its complementary value.
Some of the most widely used latches are listed below.
SR LATCH:
An S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design
using cross-coupled NAND gates as shown. The truth tables of the circuits are shown below.
A clocked S-R flip-flop has an additional clock input so that the S and R inputs are
active only when the clock is high. When the clock goes low, the state of flip-flop is latched
and cannot change until the clock goes high again. Therefore, the clocked S-R flip-flop
is also called enabled S-R flip-flop.
A D latch combines the S and R inputs of an S-R latch into one input by adding an
inverter. When the clock is high, the output follows the D input, and when the clock
goes low, the state is latched.
A S-R flip-flop can be converted to T-flip flop by connecting S input to Qb and R to Q.

1)

S-R LATCH:

(A) LOGIC DIAGRAM

(B) SYMBOL

Logic Design Laboratory Manual

40

___________________________________________________________________________

TRUTH TABLE
S

Q+

Q b+

0
1

1
0

0
1

Qb
1
0

0*

0*

S R LATCH:

TRUTH TABLE
S
0
0
1
1

2)

R
0
1
0
1

Q+
1*
1
0
Q

Q b+
1*
0
1
Qb

SR FLIP FLOP:

CIRCUIT DIAGRAM:

(A) LOGIC DIAGRAM

S

(B) SYMBOL
TRUTH TABLE
R
Q+

Q b+

Qb

0*

0*

Logic Design Laboratory Manual

41

___________________________________________________________________________

3) CONVERSION OF SR-FLIP FLOP TO T-FLIP FLOP (Toggle)

LOGIC DIAGRAM

T FLIP FLOP USING IC 7476

SYMBOL

TRUTH TABLE

Qn + 1

Qn

Qn

4) CONVERSION OF SR-FLIP FLOP TO D-FLIP FLOP :

LOGIC DIAGRAM

D FLIP FLOP USING IC 7476

SYMBOL

TRUTH TABLE
CLOCK
0

D
X

Q+
Q

Q+
Q

Logic Design Laboratory Manual

42

___________________________________________________________________________

5. CONVERSION OF SR-FLIP FLOP TO JK-FLIP FLOP

LOGIC DIAGRAM
TRUTH TABLE
Clock J K Q+ Q+ Comment
1

No
Change

Reset

Set

Toggle

LOGIC DIAGRAM

TRUTH TABLE
SD RD Clock J

Comment

Not Allowed

X X

Set

X X

Reset

Reset

Set

Toggle

6. JK MASTER SLAVE FLIP FLOP

LOGIC DIAGRAM

NC NC

Memory

Logic Design Laboratory Manual

43

___________________________________________________________________________

TRUTH TABLE
PRE = CLR = 1
Clock J K Q+ Q+ Comment
1

No
Change

Reset

Set

Race Around

PROCEDURE:
Check all the components for their working.
Insert the appropriate IC into the IC base.
Make connections as shown in the circuit diagram.
Verify the Truth Table and observe the outputs.
VIVA QUESTIONS:
1. What is the difference between Flip-Flop & latch?
2. Give examples for synchronous & asynchronous inputs?
3. What are the applications of different Flip-Flops?
4. What is the advantage of Edge triggering over level triggering?
5. What is the relation between propagation delay & clock frequency of flip-flop?
6. What is race around in flip-flop & how to over come it?
7. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
8. List the functions of asynchronous inputs?