1) a) Design and simulate a 8-bit ripple carry adder using Verilog and verify its

functionality using a test bench.

(50)
b) Design and simulate a CMOS inverter using a layout tool and extract its parasitic.(50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100

2) a) Design and simulate a 4-bit array multiplier using Verilog and verify its functionality
using a test bench.
(50)
b) Design and simulate a 4-bit up counter using Verilog.
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

(50)
Results
25

Viva
10

Total
100

3) a) Design and simulate a 3 to 8 decoder using Verilog and verify its functionality
using a test bench.
(50)
b) Design and simulate a Mod-10 up counter using Verilog. (50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100

4) a) Design and simulate a 4 to 1 multiplexer using Verilog and verify its functionality
using a test bench.
(50)
b) Design and synthesize a 4-bit adder using Verilog and show the synthesize report
for a
Virtex series FPGA.
(50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100

Viva
10

Total
100

5) a) Design and simulate a 4-bit PRBS generator using Verilog.(50)

b) Design and simulate a CMOS inverter using a layout tool and extract its
parasitics.50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

6) a) Design and simulate a 8-bit accumulator using Verilog.

Results
25

(50)

b) Design and simulate a MOS differential amplifier using SPICE and determine its
gain.50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100

7) a) Design and simulate a Mod-12 up counter using Verilog.

(50)

b) Design and simulate a MOS differential amplifier using SPICE and determine its
bandwith(50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100

10) a) Design and simulate a 2 to 4 decoder using Verilog and verify its functionality using a
test bench.
(50)
b) Design and simulate a CMOS inverter from its schematic representation and generate
its layout.
(50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

11) a)Design and simulate a 3 to 8 decoder using Verilog.

b) Realize the same 3 to 8 decoder on a FPGA.
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Results 25

Viva
10

Total
100

Results
25

Viva
10

Total
100

(50)

(50)

Connections/
execution
15

12) a) Design and simulate a 1 to 4 de-multiplexer using Verilog.

b) Realize the same 1 to 4 de-multiplexer on a FPGA.
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

(50)

(50)
Results
25

Viva
10

Total
100

14) a)Design and simulate a MOS differential amplifier using SPICE and determine
its CMRR. (50)
b) Design and simulate a 1 to 4 de-multiplexer using Verilog. Generate the Synthesis
report for a Virtex FPGA.(50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100

15) a) Design and simulate a 8-bit ripple carry adder using Verilog and verify its functionality
using a test bench. (50)
b) Design a 2 to 4 decoder using Verilog and generate its synthesis report for a Virtex FPGA.
(50)
Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100

16)

a) Design and simulate a MOS differential amplifier using SPICE and determine
its gain and bandwidth.

(50)

b) Design and simulate a 4 to 1 multiplexer using Verilog.

Aim/procedure/
Algorithm
25

16)

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100

a) Design and simulate a MOS differential amplifier using SPICE and determine
its gain and bandwidth.

(50)

b) Design and simulate a 4 to 1 multiplexer using Verilog.

Aim/procedure/
Algorithm
25

16)

(50)

Circuit
diagram/program
25

Connections/
execution
15

(50)
Results
25

Viva
10

a) Design and simulate a MOS differential amplifier using SPICE and determine
its gain and bandwidth.

(50)

b) Design and simulate a 4 to 1 multiplexer using Verilog.

(50)

Total
100

Aim/procedure/
Algorithm
25

Circuit
diagram/program
25

Connections/
execution
15

Results
25

Viva
10

Total
100