About the Instructor

Kwang-Ting (Tim) Cheng

PhD, 1988, Univ. of California, Berkeley
1988-1993: AT&T Bell Labs
1993-Present: Professor, Dept. of ECE, Univ. of California,
Santa Barbara
1999-2002: Director, Computer Engineering Program, UCSB
2005-2008: Chair, Dept. of ECE, UCSB
July-Dec. 2008: Visiting Professor, Univ. of Tokyo
Research areas: VLSI test, validation and verification;
multimedia computing (image and video content analysis)

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UCSBs SoC Design and Test Lab

z

Research directions:
Test techniques for heterogeneous SOC
Functional and timing verification
Post-silicon debug and validation
Current projects:
Models and coverage metrics for effective post-silicon validation
Low-cost on-line checking for consumer electronics
Self-test and error resilience for high-speed IO and RF systems
Test, yield and reliability analysis for multi-core systems with
spares
Design and test for flexible electronics

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Class Website
z

http://www.cad.t.u-tokyo.ac.jp/~timcheng/index.html

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 K.T. Tim Cheng

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Outline - Overview
Overview of IC Testing

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Types of Testing at IC level

IC Production Test Process

Burn-in

Board, System and Field Testing

Costs of Testing

The Testing Problems

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Verification vs. Testing

Verification
Testing
z Verifies correctness of
z Verifies correctness of
manufactured hardware.
design.
z Two-part process:
z Performed by
simulation, hardware
1. Test generation: software
process executed once during
emulation, or formal
design
methods.
2. Test application: electrical
z Performed once prior
tests applied to hardware
to manufacturing.
z Test application performed on
z Responsible for quality
every manufactured device.
of design.
z Responsible for quality of
devices.
*from M. Bushnell/V. Agrawal
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Testing Process Is Never Perfect

z
z
z

Based on analyzable fault models, which

may not map on real defects.
Incomplete coverage of modeled faults due
to high complexity.
Some good chips are rejected. The
fraction (or percentage) of such chips is
called the yield loss.
Some bad chips pass tests. The fraction
(or percentage) of bad chips among all
passing chips is called the defect level.

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Testing as Filter Process

Good chips
Prob(pass test) = high
Prob(good) = y
w
Pr
lo
ob
(fa
)=
il est
tt
Fabricated
es
s
s
t)
chips
a
=
p
(
lo
b
o
w
Pr
Defective chips
Prob(bad) = 1- y Prob(fail test) = high

Mostly
good
chips

Mostly
bad
chips

Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000

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Types of Testing
z

Characterization testing, or design debug

Verifies correctness of design & of test procedure
data will be used for final spec.
data can be used to identify area in which
processing can be helped for increased yield
test time is not important

Manufacturing testing/Production testing

Factory testing of all manufactured chips for
parametric faults and for random defects
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000

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Characterization Test
z

Worst-case test

Choose test that passes/fails chips

Select statistically significant sample of chips
Repeat test for every combination of 2+
environmental variables
Plot results in Shmoo plot
Diagnose and correct design errors

Continue throughout production life of chips

to improve design and process to increase
yield
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000

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Shmoo Plot

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Types of Manufacturing Tests

Wafer sort or probe test done before wafer is

Packaged device tests

scribed and cut into chips

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Where Does Probe Fit In?

Design

Wafer
Test

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Photomask

Package

Wafer
Fabrication

Final
Test

14

Bad Die Inker

Reservoir of ink
Plunger or fish line
dispenses one drop
onto each bad die
Plunger is electromagnetically or
pneumatically
driven
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Inked Wafer

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Typical Probe Test Cell

Stimulus,
Response

Load Board

Automatic

Spring Assy

Test
Equipment

Test
Head

Wafer
Good/Bad

Probe Card
Prober

X & Y Location
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Probe Test Cell

ATE

Prober
Interface
Board

Spring
Contactor
Assembly

Probe
Card

Prober
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Production IC Probe Floor

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Probe Card
z
z

z
z

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Provides the primary electrical contact between the

tester and each device-under-test (DUT) on the wafer
Needles on the probe card contact the device I/O
pads on the die (same pads are used for package
interconnects; often called bond pads)
There is usually a different, custom probe card for
every circuit design
The cards are delicate and fragile

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Cantilever Needle, Epoxy Ring Probe

Card Technology
Printed Circuit Board (Probe Card)

Needle
Epoxy Ring

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Needle soldered
to PCB

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Cantilever Needle Card

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Multi Level Cantilever Needles

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Vertical Cards for Area Array

Space Transform

DUT Board

DUT Board

Vertical Needles

Insulator
WAFER

IBM Buckling Beam Cobra, Patented in 1978

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Vertical Card (3500 Needles)

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Where Does Final Test Fit In?

Design

Wafer
Test

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Photomask

Package

Wafer
Fabrication

Final
Test

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Production Testing for Packaged

Devices
To screen out assembly related failures.
ContactTest

To insure that the tester interface is in

contact with the device.

Burn-In Test

To screen out infant mortalities

Functional Test

DC Parametric Test

Steady state tests

AC Parametric Test

To ensure that state changes

occur at the right time

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Why Do We Burn-In?

Burn-in stress required to meet IM induces early

wearout for die size >400 mils
Source: Intel

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Burn-in Testing
z

Correlations have been made between life span at room

temperature & life span at elevated temperature.
Charts of these correlations have been made for each
technology
Put the device in a furnace for a certain length of time
at an elevated temperature and voltage
By applying high voltage to the ICs pins, burn-in accelerates
the time-to-failure of oxide defects (weak oxide, pin holes,
uneven layer growth, etc) typically found in MOS devices
High temperature accelerates these and other defects, such
as ionic contamination and silicon defects

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An Example of IC Failure Rate vs. System

Operating Time With and Without Burn-in
100,000
10,000
1,000

No burn-in
125C burn-in

100
10

150C burn-in

101

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102

103
104
Time (hr)

105

106

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Problem of Burn-In: Leakage

Dominates Burn-In Power

Thermal runaway
A destructive positive feedback
condition during BI
Test sockets can be destroyed
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Functional Testing for Digital Circuits

.
. 00 10
. 0 1

True
True
Response
Response

Circuit
Response
Digital
Digital
Circuit
Circuit

10
11

.
.

.
.

Test
Vectors

01

Comparator
Comparator
Test
Result

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DC Parametric Testing
z

Tests are done by Parametric

Measurement Unit (PMU)

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Leakage test
Threshold ViL & ViH test
Output drive current test
Power consumption test
Output short current test

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AC Parametric Testing
To ensure that value/state changes occur at
the right time
Some of AC parametric tests are mainly for
characterization and may not be necessary
for production test.

Test for rise and fall times of an output signal

Tests for setup and hold times
Tests for time to tri-state
Tests for measuring delay times
E.g. tests for memory access time
Functional at-speed tests (speed sorting)

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Mov00100.mpg
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Board Level Testing

Shorts testing
In-circuit testing
Check devices already mounted on a board
An external tester applies patterns directly to the
inputs of the device & observe the outputs
The tester must be capable of electronically
isolating the IC under test from the board
environment

Functional Board Testing

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System Testing

Final test in the manufacturing process

Checking the right assembly of components
such as boards, backplanes, cables and
peripherals
It also involves checking of component
interactions and HW/SW functionality
Very long test times required

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Field Testing

Necessary for commissioning and faultfinding the system as a whole in a fieldservice environment
Both analog and digital test equipment is
needed, issues of
Portability
Ease of use
Range of functions

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Testing Costs are Composed of:

Test equipment costs

Analog & digital signal and measuring instrumentation

Test head (pin electronics, drivers and cables)
Test controller (computer & storage)

Test development costs

Test planning, test program development and

debugging

Testing-time costs

time using the equipment to support testing

Test personnel costs

training
working time

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Types of ATE
z

IC Device ATE

Memory, Logic, Mixed-signal, Analog

Environmental Test - Burn-In

Board-Level ATE

z
z
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Bare-Board Testers (Assembly Fault Testers)

Manufacturing Defects Analyzers
In-circuit Testers
Functional Board Testers
Combinational Board Testers

Systems Testers
Field Service Testers
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Cost of Manufacturing
Testing in 2000AD
0.5-1.0GHz, analog instruments, 1,024 digital
pins: ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation)

= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/year

Test cost (24 hour ATE operation)

= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second

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Tremendous Cost Pressure

z

The price to performance ratio of

semiconductors continues to decline
$ per MIP or $ per bit follow Moores Law

Test equipment cost increases

Tester cost increase 10 X in 30 years
Prober cost increase 20 X in 30 years

Test costs dont scale with geometry

We must test all the individual parts
We must test them more thoroughly

And
And the
the parts
parts get
get more
more complicated!
complicated!
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Summary Types of IC Testing

Characterization testing vs. Production testing

Production testing: Wafer probe vs. Packaged
device testing

Production testing for packaged devices:

Contact test
Burn-in
Functional testing
DC & AC parametric testing

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Cost Of Testing - The Rule of Tens

1000
Cost
Per
Fault
(Dollars)

100

500

10

50
1

5.0
0.5

IC
Test

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Board
Test

System
Test

Warranty
Repair

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In-Field Failures are Common

and Costly
z
z

Xbox:16.4% failure rate

Additional warranty and
refund will cost Microsoft
$1.15B ($86 per $300-item)
More than financial cost:
reputation and market loss
Non-trivial failure rate
15% in average

http://arstechnica.com/news.ars/post/20080214-xbox-360failure-rates-worse-than-most-consumer-electornics.html

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The Testing Problems

z

Q1: Which faults to target?

Fault Modeling
Q2: How is test derived?
Manually
Automatic Test Pattern Generation (ATPG)
Q3: How is test quality measured?
Fault coverage vs. product quality
Fault simulation
Q4: How are tests applied?
Test Engineering, Test programming
Automatic test equipment (ATE)
Wafer probe

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The Testing Problems (Contd)

z

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Q5: How to make sure high quality test can be

derived and applied?
Design for testability
Built-in self-test
Q6: How to identify the source of errors, if any?
Fault Diagnosis

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