TDA7339

3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR

PRODUCT PREVIEW

THREE STEREO INPUT

ONE RECORD OUTPUT
ONE STEREO OUTPUT
TWO INDEPENDENT VOLUME CONTROL IN
1.0dB STEPS
TREBLE, MIDDLE AND BASS CONTROL IN
1.0dB STEPS
ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS

DIP28

DESCRIPTION
The TDA7339 is a volume and tone (bass , middle and treble) processor for quality audio application in car radio and Hi-Fi system.
Control is accomplished by serial I2C bus microprocessor interface.
The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.

ORDERING NUMBER: TDA7339

Thanks to the used BIPOLAR/MOS Technology,

Low Distortion, Low Noise and Low DC stepping
are obtained.

BLOCK DIAGRAM

R1
2.7K
C7
5.6nF

IN1(L)
IN2(L)
IN3(L)

3x
2.2F
C1

C2

C3

REC OUT(L) TREBLE(L)

8

C9
18nF

C10
22nF

M IN(L)

R3
2.7K
C13
100nF

M OUT(L)

C14
100nF

B IN(L)

B OUT(L)
10

1st VOL

2nd VOL
TREBLE

MIDDLE

BASS

SOFTMUTE

MUTE

12

14
13
SERIAL BUS DECODE & LATCHES

18

MULTIPLEXER

IN1(R)
IN2(R)
IN3(R)

C4

27

C5

25

C6

24

15
1st VOL

11
TREBLE

MIDDLE

BASS
2nd VOL

MUTE

3x
2.2F

SOFTMUTE

OUT L

SCL
SDA

BUS

ADDR
DIG.GND
CMUTE
CSM 22nF

17

OUT R

1
VS

SUPPLY
16

ANAL.GND

CREF

28

21

26

REC OUT(R) TREBLE(R)

CREF
10F

C8
5.6nF

M IN(R)
C11
18nF

23

22

M OUT(R)
C12
22nF
R2
2.7K

20

19

B IN(R)

B OUT(R)

C15
100nF

D94AU067C

C16
100nF
R4
5.6K

July 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.

1/12

TDA7339
ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Value
10.5

Tamb

Operating Ambient Temperature

-40 to 85

Tstg

Storage Temperature Range

-55 to 150

VS

Operating Supply Voltage

Unit

PIN CONNECTION

VS

28

CREF

IN1L

27

IN1R

TREBLE L

26

TREBLE R

IN2L

25

IN2R

IN3L

24

IN3R

M IN L

23

M IN R

M OUT L

22

M OUT R

REC OUT L

21

REC OUT R

B IN L

20

B IN R

B OUT L

10

19

B OUT R

CMUTE

11

18

ADDR

OUT L

12

17

OUT R

SDA

13

16

AGND

SCL

14

15

DIG GND

D95AU217A

THERMAL DATA
Symbol
Rth j-amb

Parameter
Thermal Resistance Junction-pins

Value

Unit

65

C/W

Unit

QUICK REFERENCE DATA

Symbol

Min.

Typ.

Max.

VS

Supply Voltage

Parameter

10

VCL

Max. input signal handling

V
Vrms

THD

Total Harmonic Distortion V = 1Vrms f = 1KHz

0.01

S/N

Signal to Noise Ratio

106

dB

SC

Channel Separation f = 1KHz

100

dB

1st and 2nd Volume Control 1dB step

-47

dB

Bass, Middle and Treble Control 1dB step

-14

+14

dB

Mute Attenuation

2/12

0.08

100

dB

TDA7339
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K; f = 1KHz; all control = flat (G = 0); Tamb =
25C Refer to the test circuit, unless otherwise specified.)
Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

35

50

65

INPUTS
R in

Input Resistance

1st VOLUME CONTROL

C RANGE

Control Range

45

47

49

dB

AVMAX
Astep
EA

Maximum Attenuation
Step Resolution
Attenuation Set Error

45
0.5
-1.0

47
1.0

49
1.5
1.0

dB
dB
dB

1.5
1
2

dB
dB
dB

100
0
0.5

3
5

dB
mV
mV

47
47
1.0

49
49
1.5

dB
dB
dB

1.0
1.5
1

dB
dB
dB

Et
Amute
VDC

Tracking Error
Mute Attenuation
DC Steps

G = 0 to -24dB
G = -24 to -47dB
G = 0 to -24dB
G = 24 to -47dB

-1.5

80
Adiacent Attenuation Steps
From 0dB to AVMAX

2nd VOLUME CONTROL

C RANGE
AVMAX
Astep

Control Range
Maximum Attenuation
Step Resolution

EA

Attenuation Set Error

Et

Tracking Error

45
45
0.5
G = 0 to -24dB
G = -24 to -47dB
G = 0 to -24dB

-1.0
-1.5

G = 24 to -47dB
AMUTE
VDC

Mute Attenuation
DC Steps

Adiacent Attenuation Steps

100
0

dB
dB
mV

From 0dB to AVMAX

0.5

mV

80

BASS
Rb
C RANGE
Astep

Internal Feedback Resistance

Control Range
Step Resolution

32
11.5
0.5

44
14
1

56
16
1.5

K
dB
dB

Internal Feedback Resistance

Control Range

18
11.5

25
14

32
16

K
dB

Step Resolution

0.5

1.5

dB

Control Range

13
0.5

14
1

15
1.5

dB

Step Resolution

Supply Voltage (note1)

Supply Current
Ripple Rejection

6
4
60

9
7
90

10.5
10

V
mA
dB

2
45

ms
ms

MIDDLE
Rb
C RANGE
Astep

TREBLE
C RANGE
Astep

dB

SUPPLY
VS
IS
SVR

SOFT MUTE
AMUTE
tD

Mute Attenuation
Delay Time

C SM = 22F; 0 to 20dB; I = IMAX

C SM = 22F; 0 to 20dB; I = IMIN

45

60

0.8
15

1.5
25

dB

3/12

TDA7339
ELECTRICAL CHARACTERISTICS (continued)
Symbol

Parameter

Test Condition

Min.

Typ.

2.6

Max.

Unit

AUDIO OUTPUT
Vclip

Clipping Level

R Ol

Output Load Resistance

RO

Output Impedance

VDC

DC Voltage Level

d = 0.3%

Vrms

2
100

K
180

300

3.8

GENERAL
eNO
Et

Output Noise

All Gains 0dB (B = 20 to 20kHz flat)

15

Total Tracking Error

AV = 0 to -24dB

dB

AV = -24 to -47dB

dB

S/N

Signal to Noise Ratio

SC

Channel Separation

Distortion

All Gains = 0dB; VO = 1Vrms

106
80

AV = 0; V in = 1Vrms

dB

100
0.01

dB
0.08

0.8

BUS INPUTS
V il

Input Low Voltage

Vih

Input High Voltage

Iin

Input Current

Vin = 0.4V

VO

Output Voltage SDA

Acknowledge

IO = 1.6mA

NOTE 1: the device is functionally good at Vs = 5V. A step down, on V S, to 4V doest reset the device.

4/12

-5
0.4

TDA7339
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7319 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.

Acknowledge
The master (P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it generates the 9th clock pulse without checking the slave acknowledging, and then
sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.

Data Validity on the I 2CBUS

Timing Diagram of I2CBUS

Acknowledge on the I2CBUS

5/12

TDA7339
address (the 8th bit of the byte must be 0). The
TDA7339 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)

SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7339

TDA7339 ADDRESS

first byte

MSB
S

LSB

MSB

LSB

0 ACK

DATA

MSB

LSB
DATA

ACK

ACK P

Data Transferred (N-bytes + Acknowledge)

ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s

SOFTWARE SPECIFICATION
Chip address
1
MSB

0
LSB

A = Logic level ON pin ADDR

FUNCTION CODES
MSB

F6

F5

F4

F3

F2

F1

LSB
0

1st VOLUME

F6

F5

F4

F3

F2

F1

2nd VOLUME

F6

F5

F4

F3

F2

F1

TREBLE

F4

F3

F2

F1

F0

MIDDLE

F4

F3

F2

F1

F0

BASS

F4

F3

F2

F1

F0

MUTMUX

F4

F3

F2

F1

F0

POWER ON RESET:
1st volume = 2nd volume = Mute
Treble = Middle = Bass = -14dB
Mutmux = Active Input IN 1

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TDA7339
1st VOLUME CODES
MSB

F6

F5

F4

F3

F2

F1

LSB

FUNCTION

step 1dB

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

step 8dB

0dB

-8dB

-16dB

-24dB

-32dB

-40dB

MUTE

F5

F4

2nd VOLUME CODES

MSB

F6

F3

F2

F1

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

LSB

FUNCTION

step 1dB

-7dB
1

step 8dB

0dB

-8dB

-16dB

-24dB

-32dB

-40dB

MUTE

7/12

TDA7339
TREBLE CODES
MSB

F6

F5

8/12

F4

F3

F2

F1

LSB

FUNCTION
TREBLE BOOST

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

13dB

14dB

14dB

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

-8dB

-9dB

-10dB

-11dB

-12dB

-13dB

-14dB

-14dB

TREBLE CUT

TDA7339
MIDDLE CODES
MSB

F6

F5

F4

F3

F2

F1

LSB

FUNCTION
MIDDLE BOOST

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

13dB

14dB

14dB

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

-8dB

-9dB

-10dB

-11dB

-12dB

-13dB

-14dB

-14dB

MIDDLE CUT

9/12

TDA7339
BASS CODES
MSB

F6

F5

F4

F3

F2

F1

LSB

FUNCTION
BASS BOOST

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

13dB

14dB

14dB

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

-8dB

-9dB

-10dB

-11dB

-12dB

-13dB

-14dB

-14dB

BASS CUT

MUTMUX CODES
MSB

F6

F5

10/12

F4

F3

F2

F1

LSB

FUNCTION

SLOW SOFT MUTE SLOPE (I=IMIN)

FAST SOFT MUTE SLOPE (I=IMAN)

SOFT MUTE OFF

NOT ALLOWED

IN3

IN2

IN1

INPUTS

TDA7339
mm

DIM.
MIN.

TYP.

inch
MAX.

MIN.

TYP.

a1

0.63

0.025

0.45

0.018

b1

0.23

b2

0.31
1.27

D
E

0.009

0.012
0.050

37.34
15.2

16.68

1.470
0.598

0.657

2.54

0.100

e3

33.02

1.300

MAX.

OUTLINE AND
MECHANICAL DATA

14.1

0.555

4.445

0.175

3.3

0.130

DIP28

11/12

TDA7339

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics Printed in Italy All Rights Reserved
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