Conclusion

After conducting the experiment, the following conclusions were gathered.

* The three FET terminals are source, drain and gate.
* The gate voltage controls the output drain current. The controlled drain
current flows from drain to source and thee controlling gate voltage is applied
between the gate and source.
* A channel is passage in which the carriers pass through from the drain to the
source.
* The JFET operates with a reverse-biased pn junction (gate-to-source)
* Due to the reverse-biased gate-source junction, a JFET has high input
resistance.
* There are two types of BJT, the NPN and PNP transistors; meanwhile, FET has
two types as well, the junction field-effect transistors (JFET) and the metaloxide-semiconductor field-effect transistors (MOSFET).
* Reverse bias of a JFET produces a depletion region within the channel, thus
increasing channel resistance.
* The gate voltage controls the output drain current.
* Controlling gate voltage is applied between the gate and source terminal.

Interpretation of Results
The main objective of Experiment 4 entitled JFET Fundamentals is to
demonstrate the biasing circuit for a Junction Field Effect Transistor. In the
previous experiments we have studied the characteristics of BJT, in this case we
would be studying the characteristics of Field Effect Transistor (FET). FETs are
unipolar devices unlike BJTs that both use hole and electron carriers, they
operate using only one type of charge carrier, either a hole or an electron.
There are two types of FET: JFET (Junction Field Effect Transistor) and MOSFET

(Metal Oxide Semiconductor Field Transistor). In this experiment, we would

specifically be studying the characteristics of JFETs.
The first part of this experiment demonstrates the JFET drain
characteristics. We observed the effect of drain voltage on drain current at zero
gate bias. Drain voltage supply affects the operation of the circuit. Based on the
data gathered, as drain voltage supply increases, the current I D flowing through
R3 also increases. But when it reaches the pinch-off voltage of 3V the drain
current becomes constant because this is the maximum drain current that a
JFET can produce. Thus, it has entered the active region. Since there is voltage
applied between the gate and the source, the channel is a wide open path for
electrons to flow.
Another supply is added which is the gate supply. Looking at the circuit the
negative polarity of the gate supply is connected to the p-type material of the
JFET and the positive supply to the n-type material. From this, we can say that
the gate-source junction is reverse-biased. It should be noted that JFET is
always operated with the gate-source PN junction in reverse-biased condition.
With a gate supply of -0.5V with increasing drain supply, the drain current
would increases until it reaches the pinch-off voltage and even much greater,
giving an essentially constant value of drain current. Because of the increase in
gate-source voltage, narrowing of the channel happens. We have observed that
the current flowing between the source and drain is now limited. Having a gate
supply of 3V it was observed that at maximum gate source voltage, it pinched
off all current through source and drain, forcing JFET into cut-off mode. With
that, the channel completely closed resulting to a zero drain current.
Second part of the experiment leads to the effect of gate bias on drain
current. Increasing the value of gate supply voltage (V GG) also increases the
gate-to-source voltage (VGS). In this set-up, gate supply voltage is varied while
keeping the drain supply constant. Having a fixed drain supply voltage with a
negatively increasing gate supply voltage, there came to a point that they are
almost equal. In this case drain current decreases until it reaches a zero drain
current. Thus, the cut-off voltage is observed to be at -2.5 gate supply because
at this value the drain current is from maximum to its minimum caused by the
widening of the depletion region until the channel completely closes.
Considering the graph obtained from the data gathered, the relationship
between the voltage to source and the drain current is not linear, hence, its
exponential.

Graphs and Curves

VGG = 0V
4
3.5
3
2.5

ID(mA)

2
1.5
1
0.5
0
0

VGG = -0.5V
2.5
2
1.5

ID(mA)

1
0.5
0
0

VGG = -3V
1
0.9
0.8
0.7
0.6

ID(mA)

0.5
0.4
0.3
0.2
0.1
0
0

Graph 4-1. JFET Drain Characteristic Curve

VDD = 4V
4
3.5
3
2.5

ID(mA)

2
1.5
1
0.5
0
-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

VDD = 8V
4
3.5
3
2.5

ID(mA)

2
1.5
1
0.5
0
-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

Graph 4-2. JFET Transfer Characteristic Curve