"Latch" Vs "Flip Flop"

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http://blog.digitalelectronics.co.in/2004/12/latch-vs-flip-flop.html

"Latch" Vs "Flip Flop"

Welcome to the most popular title on this Blog ;-))))) !!!

A flip-flop is Edge sensitive: Output only changes on rising (or falling) edge of clock.
A latch is Level sensitive: Output changes whenever clock/Enable is high (or low)
A common implementation of a flip-flop is a pair of latches (Master/Slave flop).
Latches are sometimes called transparent latches, because they are transparent (input directly connected to output) when the clock is high.
The clock to a latch is primarily called the enable.
For more information have a look at the picture below.

Deprecated Hardware:
Latches:
1. Use flops, not latches
2. Latch-based designs are susceptible to timing problems
3. The transparent phase of a latch can let a signal leak through a latch causing the signal to affect the output one clock cycle too early
4. Its possible for a latch-based circuit to simulate correctly, but not work in real hardware, because the timing delays on the real hardware dont match those
predicted in synthesis
Flip-flops:
1. Limit yourself to D-type flip-flops
2. Some FPGA and ASIC cell libraries include only D-type flip flops. Others, such as Alteras APEX FPGAs, can be configured as D, T, JK, or SR flip-flops.

For every signal in your design, know whether it should be a flip-flop or combinational. Examine the log file e.g. dc shell.log to see if the flip-flops in your
circuit match your expectations, and to check that you dont have any latches in your design.
Do not assign a signal to itself (e.g. a <= a; is bad). If the signal is a flop, use an enable to cause the signal to hold its value. If the signal is combinational,
then assigning a signal to itself will cause combinational loops, which are very bad.
If you are looking for code snippets for following types of harware, please leave a comment.
1. Flops with Waits and Ifs
2. Flops with Synchronous Reset
3. Flops with Chip-Enable
4. Flops with Chip-Enable and Mux on Input
5. Flops with Chip-Enable, Mux's, and Reset

This article is Tagged in: Design , Flipflop , Latch , RTL

Written By One Nanometer (Name changed) on 18 December 2004 at 8:39 PM

6/9/2015 12:24 PM

"Latch" Vs "Flip Flop"

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http://blog.digitalelectronics.co.in/2004/12/latch-vs-flip-flop.html

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6/9/2015 12:24 PM