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Multiplexers
2:1 multiplexer chooses between two inputs
S
S
0
D1
D0
Compiled
Balpande
X
0 by: 0Suresh S.D0
0
@BALPANDECircuits and
Layout
Y
contact:sbalpande@yahoo.com
1
1
D1 1
X
Slide 2
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D1
S
D0
@BALPANDECircuits and
Layout
2
4
Slide 3
D0
S
D1
S
@BALPANDECircuits and
Layout
Slide 4
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two
selects
S1S0 S1S0 S1S0 S1S0
Two levels of 2:1 muxes
by: Suresh S. Balpande
OrCompiled
four tristates
D0
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S1
S0
D0
0
D1
D1
0
Y
Y
D2
D3
1
D2
D3
@BALPANDECircuits and
Layout
Slide 5
D Latch
When CLK = 1, latch is transparent
D flows through to Q like a buffer
D
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Layout
Latch
CLK
Q
Q
Slide 6
D Latch Design
Multiplexer chooses D or old Q
CLK
D
CLK
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CLK CLK
CLK
@BALPANDECircuits and
Layout
Slide 7
D Latch Operation
Q
D
CLK = 1
Q
D
CLK = 0
Slide 8
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, masterCompiled
by:
Suresh
S.
Balpande
slave flip-flop
contact:sbalpande@yahoo.com
CLK
CLK
D
Flop
Q
Q
@BALPANDECircuits and
Layout
Slide 9
D Flip-flop Design
Built from master and slave D latches
CLK
CLK
CLK
QM
CLK
CLK Suresh
Compiled by:
S. Balpande
CLK CLK
QM
Latch
Latch
CLK
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Q
CLK
@BALPANDECircuits and
Layout
Slide 10
CLK
D Flip-flop Operation
QM
CLK = 0
QM
Q
Compiled by: Suresh S. Balpande
contact:sbalpande@yahoo.com
CLK = 1
CLK
D
Q
@BALPANDECircuits and
Layout
Slide 11
state indefinitely
If both Set and Reset go high, both Q and Q
are pulled low, giving an indefinite state.
Therefore, R=S=1 is not allowed
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R=0 Q = 1 (if S = 1)
R. W. Knepper
SC571, page 5-32
R. W. Knepper
SC571, page 5-35
R. W. Knepper
SC571, page 5-37
R. W. Knepper
SC571, page 5-39