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QN902x Hardware Application Note

Version 0.7

Copyright 2012-2014 by Quintic Corporation


Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA)

QN902x Hardware Application Note

v 0.7

Table of Contents
1

Introduction.................................................................................................................................... 1
Purpose ...................................................................................................................................... 1
2
Hardware design ............................................................................................................................ 2
2.1
Power supply ............................................................................................................................. 2
2.1.1 Using external power supply directly ................................................................................ 2
2.1.2 Using internal DC-DC converter ....................................................................................... 2
2.2
Clocks ........................................................................................................................................ 2
2.2.1 High frequency clock ........................................................................................................ 3
2.2.2 Low frequency clock ......................................................................................................... 4
2.3
Reset circuit ............................................................................................................................... 5
2.4
GPIOs define ............................................................................................................................ 6
2.5
RF matching circuit ................................................................................................................... 7
2.6
AN Hardware reference design ................................................................................................. 9
2.7
QN9020 typical application design schematic ..........................................................................11
2.8
Bill of material ..........................................................................................................................12
3
PCB layout for QN902x ...............................................................................................................16
3.1
PCB Stack-up ...........................................................................................................................16
3.2
RF interface ..............................................................................................................................17
3.3
Clock ........................................................................................................................................18
3.4
With DC-DC converter .............................................................................................................18
3.5
AN Example of PCB layout .....................................................................................................19
Release History..............................................................................................................................................23
1.1

QN902x Hardware Application Note

v 0.7

1 Introduction
QN902x is an ultra low power, high performance and highly integrated Bluetooth Low Energy
(BLE) SOC with few external components.

1.1 Purpose
This document is the application note for hardware design with QN902x.

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QN902x Hardware Application Note

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2 Hardware design
2.1 Power supply
The QN902x has integrated a voltage regulator. So there are two typical solutions for QN902x
power supply connection.

2.1.1 Using external power supply directly


If using external power supply directly, all the QN902x power pins should be connected to the
external power supply source. Please refer to schematic in figure10 or figure12. And the voltage
range should be between 2.4V~3.6V. To keep the best performance the 100nF decupling
capacitors should be connected to the power supply pins and suggested a 10uF capacitor to be
connected to pin1 of QN9020 to filter ripple of power supply pin.

2.1.2 Using internal DC-DC converter


Using internal integrated DC-DC converter can be utilized to further reduce the current
consumption. The DC-DC converter generates the internal required voltage from VCC (pin1 in
QN902x) and output the voltage at the DCC pin (pin48 in QN9020 or pin32 in QN9021). The
DCC pin connects the DCDC converter circuit to supply the voltage for QN9020 three power
pins (VDD1VDD2VDD3). The figure1 shows the DCC pin (pin48 in QN9020 or pin32 in
QN9021) connection in schematic.
The DCC pin needs a 10uH inductor and a 15nH inductor in series then a 1uF decupling capacitor
in parallel. The 15nH inductor and the 1uF decupling capacitor are used to filtering the noise
from DC-DC converter. All the three components should place close to the DCC pin.

VCC

VCC
L4

10uH

L5

15nH

DCC

Vout

QN902x

C11
1uF

VDD1
VDD2
VDD3

Filter

From External
power supply
source
DC-DC converter
output voltage
for QN9020 all
inner supply

Figure 1 Using internal integrated DC-DC converter reference schematic

2.2 Clocks
Two clocks are required by the QN902x, there are the 16/32 MHz high frequency clock and
32.768 KHz low frequency clock (RTC).

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2.2.1 High frequency clock


A high frequency crystal is utilized to provide the system clock, which accepts16/32-MHz
external crystal with 50ppm accuracy. Higher accuracy can easier successfully to send or
receive packets. If possible, suggested using the 20ppm accuracy crystal. The QN902x has
integrated crystal load capacitances. The parameters for selecting the crystals show in the table
below.

Frequency
16/32MHz

Table 1 High Frequency Crystal Selection


Accuracy
Load capacitance
<50ppm
12pF

QN902x also accepts external clock inputs.


Square clock. For Square wave as clock input, the voltage range is between 0~VCC.
Sin wave. For sin wave as clock input, the voltage should be larger than 350mVpeak and it
should be AC coupling.

XTAL1
Y1
16/32MHz
XTAL2

Figure 2 Crystal input interface with no external load capacitance


U/v

XTAL1

VCC

XTAL2
0

T/s

Figure 3 External square wave clock input interface

XTAL1

350mVp-p

XTAL2

Figure 4 External sin wave clock input interface

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2.2.2 Low frequency clock

The external 32.768-kHz crystal is used when the accurate timing is needed.
The 32-kHz internal RC oscillator can be used in order to reduce the cost and the power
consumption in case it neednt the accurate timing.

The parameters for selecting external 32.768 KHz crystal are shown in follows table2. The
recommend accuracy is 20ppm.
Table 2 Low Frequency Crystal Selection

Frequency
32.768KHz

XTAL2_32K

XTAL1_32K

Accuracy
<100ppm

C9
Y2
32.768KHz
C10

22pF

22pF

Figure 5 32.768 KHz crystal circuit

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QN902x Hardware Application Note

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2.3 Reset circuit


The reset pin of QN902x is RSTN. It is logic low for reset, for normal using it should be
connected to logic high. This pin is suggested to connect with an RC reset circuit for power on
reset. The recommended values for the resistor(Rres) and the capacitor(Cres) should be 100k
and 1uF.
VCC

QN9020/1

Rres

RSTN
Cres

Figure 6 RC reset circuit

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QN902x Hardware Application Note

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2.4 GPIOs define


Pin_ctrl
[1:0]
[3:2]
[5:4]
[7:6]
[9:8]
[11:10]
[13:12]
[15:14]
[17:16]
[19:18]
[21:20]
[23:22]
[25:24]
[27:26]
[29:28]
[31:30]
[33:32]
[35:34]
[37:36]
[39:35]
[41:40]
[43:42]
[44:43]
[46:45]
[48:47]
[50:49]
[52:51]
[54:53]
[56:55]
[58:57]
[60:59]

0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
SW_DAT
SW_CLK
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30

1
UART0_TXD
RSVD
I2C_SDA
RSVD
RSVD
I2C_SCL
GPIO6
GPIO7
SPI1_DIN
SPI1_DAT
SPI1_CS0
SPI1_CLK
RSVD
RSVD
SPI0_CS1
UART0_RXD
SPI1_DIN
SPI1_DAT
SPI1_CLK
I2C_SDA
I2C_SCL
SPI1_CS1
RSVD
ACMP1
TIMER2_1
TIMER0_2
SPI0_DIN
SPI0_DAT
SPI0_CLK
SPI0_CS0
SPI1_CS0

2
SPI0_DAT
SPI0_CS0
SPI0_CLK
CLKOUT0
CLKOUT1
ADC Trig
AIN2
AIN3
UART1_RXD
UART1_TXD
UART1_CTSn
UART1_RTSn
RSVD
PWM1
PWM0
SPI0_DIN
UART1_RXD
UART1_TXD
UART1_RTSn
ACMP0_out
PWM1
RSVD
PWM1
PWM0
AIN0
AIN1
RSVD
CLKOUT0
RSVD
RSVD
UART1_CTSn

3
RSVD
UART0_CTSn
UART0_RTSn
TIMER0_eclk
RSVD
ACMP1_out
ACMP1ACMP1+
TIMER2_eclk
TIMER1_0_out
ADC Trig
CLKOUT1
TIMER1_3
TIMER1_2
TIMER0_3
TIMER0_O
TIMER3_2
TIMER3_1
TIMER2_3
TIMER3_0
TIMER3_eclk
TIMER2_2
TIMER2_0
TIMER1_eclk
ACMP0ACMP0+
ACMP0_out
RSVD
RSVD
TIMER0_0
RSVD

pin num
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6

Most of the GPIOs have four defined function and swap using registers control.
Only P0_0 to P1_7 can be used as wakeup source.
From the table it can see only the red part are shared with QN9021 QFN5x5 package.

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2.5 RF matching circuit


The QN902x radio transceiver requires a matching network to match the 50 ohm impedance. The
structure of the matching network shows as figure 7 and figure 8. All the values on the matching
network, please follows the BOM list Table 3 and Table 4.
The components of the matching network should place to the pins as close as possible.
The 50ohm RF trace between the antennas or SMA connectors and matching circuit should be as
short as possible

RF matching
circuit
50 RF Trace
RFP

RFP

L2

2.0nH C1

1.5pF

L1
1.1nH

QN9020

C2

to connect 50
impedance antenna
or SMA connector

1pF
RFN

RFN

L3

6.2nH C4

8.2pF

VDD_PA VDD_PA
C3
2.2nF

Figure 7 QN9020 RF matching circuit


Table 3 QN9020 RF matching components value

Part name
Inductor L1
Inductor L2
Inductor L3
Capacitor C1
Capacitor C2
Capacitor C4
Capacitor C3

Part number
LQP15MN1N1B02
LQP15MN2N0B02
LQP15MN6N2B02
GRM1555C1H1R5CA01
GRM1555C1H1R0CA01
GRM1555C1H8R2DA01
GRM155R71H222KA01

Value
1.1nH
2.0nH
6.2nH
1.5pF
1.0pF
8.2pF
2.2nF

Size
0402
0402
0402
0402
0402
0402
0402

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QN902x Hardware Application Note

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RF matching
circuit
50 RF Trace
RFP

RFP

L2

1.8nH C1

1.8pF

L1
1.3nH

QN9021

C2

to connect 50
impedance antenna
or SMA connector

1pF
RFN

RFN

L3

6.2nH C4

8.2pF

VDD_PA VDD_PA
C3
2.2nF

Figure 8 QN9021 RF matching circuit


Table 4 QN9021 RF matching components value

Part name
Inductor L1
Inductor L2
Inductor L3
Capacitor C1
Capacitor C2
Capacitor C4
Capacitor C3

Part number
LQP15MN1N3B02
LQP15MN1N8B02
LQP15MN6N2B02
GRM1555C1H1R8CA01
GRM1555C1H1R0CA01
GRM1555C1H8R2DA01
GRM155R71H222KA01

Value
1.3nH
1.8nH
6.2nH
1.8pF
1.0pF
8.2pF
2.2nF

Size
0402
0402
0402
0402
0402
0402
0402

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QN902x Hardware Application Note

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2.6 AN Hardware reference design


VCC

C11

1uF

Y 1 16M

P3_5

P3_4

P3_3

P3_2

P3_0

15nH

P3_1

L4

L5

C6

100nF

R1

56K

C8

38

39

36

C7

24
P2_5

100nF

L2

35

2.0nH

C1

1.5pF
antenna

L1
1.1nH

34

C2

33

L3

6.2nH
1.0pF

32
31

RESET

30

P3_6

29

P2_0

28

R2

C3
2.2nF

C4
8.2pF

100K

P2_1

27

P2_2

26

P2_3

25

C12
1uF

P2_4

P2_5

23

P2_6

22

21
P1_0

P2_6

20
P1_1

P2_7

19
P1_2

P2_7

P2_4

P1_0

P2_3

VSS1

P1_1

P0_0

P1_2

P2_2

P1_3

P2_1

P0_1

P1_3

A1

37
REXT

VDD3

XTAL2

40
XTAL1

41
P3_5

P3_4

42

P3_3

43

44
P3_2

46

45
P3_1

P3_0

DCC
P0_2

13

12

P2_0

P1_4

11

P0_0

P3_6

P0_3

18

10

P0_1

RSTN

QN9020

P0_4

17

P0_2

P0_5

P1_4

P0_3

RVDD

U1

P1_5

P0_4

RFN

XTAL1_32K

P1_6

P0_5

XTAL2_32K

16

RFP

15

32.768KHz

P0_6

P1_5

Y2

VSS2

P1_6

22pF

VSS3

48
22pF

C10

VDD2

P0_7

P1_7

C9

SWDIO_IN/P0_6

VCC

VDD1

14

100nF

P1_7

C5

SWDCLK/P0_7

47

10uH

100nF

Figure 9 QN9020 with DC-DC converter reference design schematic

C8

REXT

P2_1

21

22

23

24

P1_0

P2_7

P2_6

P2_5

P2_5

20
P1_1

P2_6

19

P2_7

P2_4

P1_0

P2_3

VSS1

P1_1

P2_2

P0_0

P1_2

P0_1

P1_3

C6

100nF

R1

56K

A1

37

39

38
VDD3

XTAL2

XTAL1

40

P3_5
P3_5

P3_4

41

P3_4

P3_2

P3_3

42

P3_3

43

P3_1

44
P3_2

46

45
P3_1

P3_0

DCC
P0_2

13

12

P2_0

P1_2

11

P0_0

P3_6

P0_3

P1_3

10

P0_1

RSTN

QN9020

P0_4

P1_4

P0_2

P0_5

18

P0_3

RVDD

U1

17

P0_4

XTAL1_32K

P1_4

P0_5

RFN

XTAL2_32K

P1_5

P1_6

16

4
32.768KHz

RFP

15

Y2

P0_6

P1_5

22pF

VSS2

P1_6

C10

SWDIO_IN/P0_6

VSS3

48
22pF

VDD2

P0_7

P1_7

C9

VCC

VDD1

14

100nF

Y 1 16M

P1_7

C5

SWDCLK/P0_7

47

P3_0

VCC

36

C7

100nF

L2

35

2.0nH

C1

34

antenna

C2

33

L3

6.2nH
1.0pF

32
31
30
29
28
27
26
25

1.5pF

L1
1.1nH

RESET
P3_6
P2_0

R2

C3
2.2nF

C4
8.2pF

100K

P2_1
P2_2
P2_3

C12
1uF

P2_4

100nF

Figure 10 QN9020 without DC-DC converter reference design schematic

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QN902x Hardware Application Note

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VCC
C11

1uF

15nH

P3_1

P3_0

L4
Y 1 16M
C6

100nF

R1

56K

L5
10uH

26

27

25
REXT

VDD3

28
XTAL1

30

29
P3_1

XTAL2

RVDD
RSTN

INT0/P0_3

10

P2_3

MISO1/P1_0

C7

100nF

L2

23

1.8nH

C1

1.8pF
antenna

L1
1.3nH
C2

21

L3

6.2nH
1.0pF

20
19

RESET

18

P2_3

17

P2_4

R2

C3
2.2nF

C4
8.2pF

100K

P2_6

P2_4

P2_7

TXD0/P0_0
VSS1

VDD1

RFN

QN9021

24

22

C12

16

P0_0

U1

XTAL2_32K
XTAL1_32K

15

P0_3

RFP

14

P0_6

MOSI1/P1_1

4
32.768KHz

VSS2

13

Y2

VDD2

nCS1/P1_2

22pF

22pF

SWDIO_IN/P0_6

VCC
P0_7

SPICLK1/P1_3

C9

C10

12

11

100nF
SWDCLK/P0_7

RXD0/P1_7

C5

P3_0

32
DCC

VSS3

31

A1

C8

P2_6

P2_7

P1_0

P1_1

P1_2

P1_3

P1_7

1uF

100nF

Figure 11 QN9021 with DC-DC converter reference design schematic

P3_1

P3_0

VCC

Y 1 16M
C6

100nF

R1

56K

REXT

25

27

26
VDD3

XTAL2

28
XTAL1

30

29
P3_1

INT0/P0_3

RSTN

P2_3
P2_4

24

C7

100nF

L2

23

1.8nH

C1

1.8pF
antenna

L1
1.3nH

22

C2

21

L3

6.2nH
1.0pF

20
19
18
17

RESET
P2_3
P2_4

R2

C3
2.2nF

C4
8.2pF

100K

P2_6

VSS1

P2_7

TXD0/P0_0

VDD1

RVDD

MISO1/P1_0

P0_0

RFN

QN9021

XTAL1_32K

16

P0_3

XTAL2_32K

15

14

4
32.768KHz

MOSI1/P1_1

Y2

RFP

U1

13

22pF

P0_6

nCS1/P1_2

C10

SWDIO_IN/P0_6

VSS2

SPICLK1/P1_3

22pF

VDD2

P0_7

12

C9

VCC

11

RXD0/P1_7

100nF
SWDCLK/P0_7

10

C5

P3_0

32
DCC

VSS3

31

A1

C12

C8

P2_6

P2_7

P1_0

P1_1

P1_2

P1_3

P1_7

1uF

100nF

Figure 12 QN9021 without DC-DC converter reference design schematic

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QN902x Hardware Application Note

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2.7 QN9020 typical application design schematic

L4

15nH

L5

P3_5

P3_4

P3_3

P3_2

P3_0

DC-DC
converter
circuit

P3_1

Y 1 16M

C6 100nF

10uH
R1 56K

C11

38

37
REXT

VDD3

XTAL2

39

36

C7 100nF
L2

35

2.0nH

C1

antenna

C2

33

L3

6.2nH
1.0pF

32
31
30
29
28
27
26
25

1.5pF

L1
1.1nH

34

R2
100K
P3_6

C12 1uF

C3
2.2nF

C4
8.2pF

P2_0
P2_1
P2_2
P2_3

RESET

Reset pin

P2_4

23

24

P2_7

P2_6

P2_5

P2_5

22

P1_0

P2_6

21

P2_7

P2_4

20

C8

XTAL1

VSS1

P1_0

P2_3

P1_1

P2_2

P0_0

P1_2

P0_1

13

UART0 interface

40

41
P3_5

42
P3_4

P3_3

43

45

44
P3_2

46

P2_1

VDD1

12

P0_2

P1_1

11

P2_0

P1_3

10

P0_1
P0_0

P3_6

P0_3

19

P0_2

QN9020

P0_4

P1_2

RSTN

P0_5

P1_3

P0_3

RVDD

18

P0_4

RFN

XTAL1_32K

P1_4

P0_5

XTAL2_32K

17

P1_5

P1_6

4
Y2
32.768KHz

16

22pF

RFP

P0_6

P1_5

22pF

VSS2

P1_6

SWDIO_IN/P0_6

VDD2

P0_7

P1_7

A1

VCC

15

14

1
SWDCLK/P0_7

C10

P3_1

100nF

SWD interface

C9

P3_0

48
DCC

C5

VSS3

U1
VCC

47

1uF

Power Supply

100nF

P1_7

P1_4

Test mode control pin

Figure 13 QN9020 Typical application design schematic


Note
VCC (pin1) must connect external power supply source.
Reset pin (pin21) as an input pin used for QN9020 hardware reset. When it inputs logical
low can force Qn9020 to reset.
When GPIO P1.4 (pin17) is configured as an input and inputs logical low, it can force
QN9020 enter into test mode.

UART0 or SWD interface together with Reset used for Qn9020 to download program.

Please make sure you connect these pins out to interface pads for your production testing and
debug purpose.

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QN902x Hardware Application Note

v 0.7

2.8 Bill of material


Table 5 Bill of materials for QN9020 with DCDC converter reference design

QN9020_48 with DC converter Reference Design Bom


Item

Part Description

Footprint

Reference

Qty

part No.

Capacitor
1

C_SMD, 100nF, X7R, 10%, 16V, 0402

0402

C5,C6,C7,C8

GRM155R71C104KA88

C_SMD,1uF, X5R, 10%, 6.3V, 0402

0402

C11,C12

GRM155R60J105KE19

C_SMD, 22pF, NP0, 5%, 50V, 0402

0402

C9,C10

GRM1555C1H220JA01

Resistor
4

R_SMD,56K, 1%, 0402

0402

R1

R_SMD,100K, 5%, 0402

0402

R2

Inductor
6

L_SMD,15nH,5%,0402

0402

L4

LQG15HN15NJ02

L_SMD,10uH,5%,0603

0603

L5

LQM18FN100M00D

SMD_2520

Y1

FA-20H

SMD_2012

Y2

FC-12M

QFN48

U1

QN9020

Oscillator
8
9

Crystal, 16MHz, 20ppm, 12pF,


2.5x2.0x0.55 mm
Crystal, 32.768K, 20ppm, 15pF,
2.0x1.2x0.6 mm

IC
10

IC, 2.4G SOC, 64KB system memory,


QFN48,QN9020

RF circuit
11

L_SMD, 6.2nH, 0.1nH,0402

0402

L3

LQP15MN6N2B02

12

L_SMD, 2.0nH, 0.1nH,0402

0402

L2

LQP15MN2N0B02

13

L_SMD, 1.1nH, 0.1nH,0402

0402

L1

LQP15MN1N1B02

14

C_SMD, 2.2nF, X7R, 10%, 50V, 0402

0402

C3

GRM155R71H222KA01

15

C_SMD, 8.2pF, COG, 0.5pF, 50V, 0402

0402

C4

GRM1555C1H8R2DA01

16

C_SMD, 1.5pF, COG, 0.25pF, 50V, 0402

0402

C1

GRM1555C1H1R5CA01

17

C_SMD, 1.0pF, COG, 0.25pF, 50V, 0402

0402

C2

GRM1555C1H1R0CA01

A1

Others
18

Antenna

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QN902x Hardware Application Note

v 0.7

Table 6 Bill of materials for QN9020 without DCDC converter reference design

QN9020_48 without DC converter Reference Design Bom


Item

Part Description

Footprint

Reference

Qty

part No.

Capacitor
1

C_SMD, 100nF, X7R, 10%, 16V, 0402

0402

C5,C6,C7,C8

GRM155R71C104KA88

C_SMD,1uF, X5R, 10%, 6.3V, 0402

0402

C11

GRM155R60J105KE19

C_SMD, 22pF, NP0, 5%, 50V, 0402

0402

C9,C10

GRM1555C1H220JA01

Resistor
4

R_SMD,56K, 1%, 0402

0402

R1

R_SMD,100K, 5%, 0402

0402

R2

SMD_2520

Y1

FA-20H

SMD_2012

Y2

FC-12M

QFN48

U1

QN9020

Oscillator
6
7

Crystal, 16MHz, 20ppm, 12pF,


2.5x2.0x0.55 mm
Crystal, 32.768K, 20ppm, 15pF,
2.0x1.2x0.6 mm

IC
8

IC, 2.4G SOC, 64KB system memory,


QFN48,QN9020

RF circuit
9

L_SMD, 6.2nH, 0.1nH,0402

0402

L3

LQP15MN6N2B02

10

L_SMD, 2.0nH, 0.1nH,0402

0402

L2

LQP15MN2N0B02

11

L_SMD, 1.1nH, 0.1nH,0402

0402

L1

LQP15MN1N1B02

12

C_SMD, 2.2nF, X7R, 10%, 50V, 0402

0402

C3

GRM155R71H222KA01

13

C_SMD, 8.2pF, COG, 0.5pF, 50V, 0402

0402

C4

GRM1555C1H8R2DA01

14

C_SMD, 1.5pF, COG, 0.25pF, 50V, 0402

0402

C1

GRM1555C1H1R5CA01

15

C_SMD, 1.0pF, COG, 0.25pF, 50V, 0402

0402

C2

GRM1555C1H1R0CA01

A1

Others
16

Antenna

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Table 7 Bill of materials for QN9021 with DCDC converter reference design

QN9021_32 with DC converter Reference Design Bom


Item

Part Description

Footprint

Reference

Qty

part No.

Capacitor
1

C_SMD, 100nF, X7R, 10%, 16V, 0402

0402

C5,C6,C7,C8

GRM155R71C104KA88

C_SMD,1uF, X5R, 10%, 6.3V, 0402

0402

C11,C12

GRM155R60J105KE19

C_SMD, 22pF, NP0, 5%, 50V, 0402

0402

C9,C10

GRM1555C1H220JA01

Resistor
4

R_SMD,56K, 1%, 0402

0402

R1

R_SMD,100K, 5%, 0402

0402

R2

Inductor
6

L_SMD,15nH,5%,0402

0402

L4

LQG15HN15NJ02

L_SMD,10uH,5%,0603

0603

L5

LQM18FN100M00D

SMD_2520

Y1

FA-20H

SMD_2012

Y2

FC-12M

QFN32

U1

QN9021

Oscillator
8
9

Crystal, 16MHz, 20ppm, 12pF,


2.5x2.0x0.55 mm
Crystal, 32.768K, 20ppm, 15pF,
2.0x1.2x0.6 mm

IC
10

IC, 2.4G SOC, 64KB system memory,


QFN32,QN9021

RF circuit
11

L_SMD, 6.2nH, 0.1nH,0402

0402

L3

LQP15MN6N2B02

12

L_SMD, 1.8nH, 0.1nH,0402

0402

L2

LQP15MN1N8B02

13

L_SMD, 1.3nH, 0.1nH,0402

0402

L1

LQP15MN1N3B02

14

C_SMD, 2.2nF, X7R, 10%, 50V, 0402

0402

C3

GRM155R71H222KA01

15

C_SMD, 8.2pF, COG, 0.5pF, 50V, 0402

0402

C4

GRM1555C1H8R2DA01

16

C_SMD, 1.8pF, COG, 0.25pF, 50V, 0402

0402

C1

GRM1555C1H1R8CA01

17

C_SMD, 1.0pF, COG, 0.25pF, 50V, 0402

0402

C2

GRM1555C1H1R0CA01

A1

Others
18

Antenna

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Table 8 Bill of materials for QN9021 without DCDC converter reference design

QN9021_32 without DC converter Reference Design Bom


Item

Part Description

Footprint

Reference

Qty

part No.

Capacitor
1

C_SMD, 100nF, X7R, 10%, 16V, 0402

0402

C5,C6,C7,C8

GRM155R71C104KA88

C_SMD,1uF, X5R, 10%, 6.3V, 0402

0402

C11

GRM155R60J105KE19

C_SMD, 22pF, NP0, 5%, 50V, 0402

0402

C9,C10

GRM1555C1H220JA01

Resistor
4

R_SMD,56K, 1%, 0402

0402

R1

R_SMD,100K, 5%, 0402

0402

R2

SMD_2520

Y1

FA-20H

SMD_2012

Y2

FC-12M

QFN32

U1

QN9021

Oscillator
6
7

Crystal, 16MHz, 20ppm, 12pF,


2.5x2.0x0.55 mm
Crystal, 32.768K, 20ppm, 15pF,
2.0x1.2x0.6 mm

IC
8

IC, 2.4G SOC, 64KB system memory,


QFN32,QN9021

RF circuit
9

L_SMD, 6.2nH, 0.1nH,0402

0402

L3

LQP15MN6N2B02

10

L_SMD, 1.8nH, 0.1nH,0402

0402

L2

LQP15MN1N8B02

11

L_SMD, 1.3nH, 0.1nH,0402

0402

L1

LQP15MN1N3B02

12

C_SMD, 2.2nF, X7R, 10%, 50V, 0402

0402

C3

GRM155R71H222KA01

13

C_SMD, 8.2pF, COG, 0.5pF, 50V, 0402

0402

C4

GRM1555C1H8R2DA01

14

C_SMD, 1.8pF, COG, 0.25pF, 50V, 0402

0402

C1

GRM1555C1H1R8CA01

15

C_SMD, 1.0pF, COG, 0.25pF, 50V, 0402

0402

C2

GRM1555C1H1R0CA01

A1

Others
16

Antenna

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3 PCB layout for QN902x


3.1 PCB Stack-up
The recommend PCB Stack-up for QN902x application shows as follows.
layer1

layer2

Copper

1oz +plating

Prepreq

FR-4 0.28mm

Copper

1oz 35um

Core
layer3

Copper

FR-4 0.7mm
1oz 35um

Prepreq FR-4 0.28mm


Copper

layer4

1oz +plating

Figure 14 PCB stack up


The PCB board is 1.5 millimeter thick based on standard flame retardant (FR4) material.

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3.2 RF interface
Since the QN902x works at 2.4GHz frequency, the parasitic parameters from printed circuit
board (PCB) layout will affect the RF parameters and it is very sensitive. So we should pay
attention to some details.

Route the RF traces on the top layer and keep traces as short as possible no via is allowed on
the trace.
The impedance of the RF trace between matching network and antenna (or the SMA
connector) must be 50-. Under this RF trace there should be a large, unbroken solid ground.
There should be via around the RF trace with high density.
When the PCB is multi-layers (more than 2 layers) it should remove the ground plane on the
internal layers under the RF components. Just keep the bottom layers ground plane for
shielding.
On the top layer, it should make a distance between the components and the ground plane.
Under the RF components and the RF traces no other signal trace is allowed.
L1 should be placed as close as possible to QN902x RF port for reduce parasitic capacitance.

50 RF trace

L1 should be
placed as close as
possible to
QN9020 RF port

Figure 15 QN902x RF layout

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3.3 Clock
If a crystal is used, the parasitic characteristics of the clock trace will influence the circuit. The
trace must be kept as short as possible. Keep the ground plane under the crystal trace to improve
the return path. We should avoid crossing the crystal trace between the layers.

Figure 16 QN902x 16/32M clock layout

3.4 With DC-DC converter


The DC-DC converter will generate noise. It should place the DC-DC converter components to
QN902x device as close as possible. Ensure the DC-DC converter output trace is wide enough.
Trace must be kept as short as possible. Keep the useful signal trace far away from the DC-DC
converter routing area.

Figure 17 QN902x with DC-DC converter layout


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3.5 AN Example of PCB layout


Qn9020 EVB layout

Figure 18 QN902x Layer1

Figure 19 QN902x Layer2

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QN902x Hardware Application Note

Figure 20 QN902x Layer3

v 0.7

Figure 21 QN902x Layer4

Figure22 QN902x SILK TOP

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QN9021 EVB layout

Figure23 QN9021 Layer1

Figure24 QN9021 Layer2

Figure25 QN9021 Layer3

Figure26 QN9021 Layer4

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Figure27 QN9021 SILK TOP

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Release History
REVISION

CHANGE DESCRIPTION

DATE

0.1

Initial release

2013-04-18

0.2

Add QN9021 reference design;

2013-05-22

0.3

Add QN9020 typical application design schematic

2013-06-06

0.4

Modify the pin name IDC to DCC in figure 9,10,11,12,13

2013-07-08

0.5

Update the RF matching net components value

2013-07-15

0.51

Update the parameters with crystal


Add GPIO description

2013-07-29

0.52

Update load capacitor value of 32.768 kHz crystal

2013-08-12

0.6

Update the Bill Of Material

2013-08-27

0.7

Suggest a 10uF capacitor to be connected to the pin1 of QN9020

2014-01-16

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