CC Man

REAL TIME DIGITAL SIMULATOR
CONTROLS LIBRARY MANUAL

(RSCAD VERSION)
Technologies
RTDS
JULY 2013
TABLE OF CONTENTS
1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
1.1 Introducing the RealTime Digital Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
1.2 Control System Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2
1.3 List of Controls Library Function Blocks (by Group) . . . . . . . . . . . . . . . . . . . . . . 1.3
2 GENERAL USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1
2.1 Creating a Control System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1
2.2 Running a Control System Model Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9
2.3 Interfacing External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10
2.4 Numerical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13
2.5 Signal Time Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.16
2.6 Execution & Communication Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.18
2.7 Interconnection to Power System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.19
3 FUNCTION BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1
MATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2
LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.22
SELECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.32
LIMITER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.38
DATA CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.45
INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.52
METERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.74
TRANSFER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.80
TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.85
SIGNAL PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.94
SIGNAL GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.117
LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.122
MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.128
4 GENERATOR CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1
4.1 Connection of Generator Controls to RTDS Generator Model . . . . . . . . . . . . . . . 4.2
4.2 Automatic Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5
4.3 Internal Variable Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6
4.4 PSCAD/RunTime Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7
4.5 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8
IEE2ST PSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10
IEEEST PSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12
PSS2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14
EXAC1 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16
EXAC1A AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18
ii
EXAC2 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20

EXAC3 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22
EXAC4 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24
EXDC2 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26
EXST1 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28
EXST1A AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.30
EXST2 (A) AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.34
EXST3 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.37
EXPIC1 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.39
IEEET1 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.42
IEEET2 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.44
IEEET3 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.46
IEEET4 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.48
IEEET5 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.50
IEEEX1 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.52
IEEEX2 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.54
IEEEX2A AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.56
DC1 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.58
DC2 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.60
REXS AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.62
AC7B AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.64
GAST GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.66
HYGOV GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.68
IEESGO GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.71
IEEEG1 GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.73
IEEEG2 GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.76
IEEEG3 GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.78
TGOV1 GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.81
WEHGOV GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.83
HYGOV4 GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.86
GGOV1 GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.89
TGOV5 GOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.92
5 COMPLEX NUMBER MATH FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1

6 SEQUENCER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1
6.2 Parameter Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1
6.3 Sample Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8
7 GTNET Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7A.1
7A GTNET GSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7A.1
7A.1 GOOSE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7A.1
iii
7A.2 GSSE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7A.2

7A.3 RSCAD Draft Component and Parameter Entries . . . . . . . . . . . . . . . 7A.3
7B GTNET Comtrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7B.1
7B.1 Comtrade Files and Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7B.1
7B.2 RTDS Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7B.2
7B.3 Linear Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7B.3
7B.4 Data Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7B.3
7B.5 Operating in PreTransient (prefault) and PostTtransient (postfault) data
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7B.4
7B.6 Playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7B.5
7B.7 RSCAD Draft Component and Parameter Entries . . . . . . . . . . . . . . . 7B.6
7B.8 Sending Comtrade Signals to a Peripheral Device . . . . . . . . . . . . . . 7B.11
7C GTNET DNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7C.1
7C.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7C.2
7C.2 DNP<>RTDS Point Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7C.4
7C.3 RSCAD Draft Component and Parameter Entries . . . . . . . . . . . . . . . 7C.8
7C.4 MultiRack Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7C.10
7D GTNET PLAYBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7D.1
7D.1 Model Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7D.1
7D.2 Playback Data File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7D.2
7D.3 Playback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7D.2
7D.4 RSCAD Draft Component and Parameter Entries . . . . . . . . . . . . . . . 7D.3
7D.5 GTNET Playback Example Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . 7D.10
7E GTNET SV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7E.1
7E.1 Sampled Values Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7E.1
7E.2 RSCAD Draft Component and Parameter Entries . . . . . . . . . . . . . . . 7E.2
7Ex GTNET SV se
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Ex.1
7Ex.1 Sampled Values Special Edition Communication . . . . . . . . . . . . . . 7Ex.1
7F GTNET PMU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7F.1
7F.1 Model Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7F.1
7F.4 Calibration of PMU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7F.4
7F.6 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7F.6
7G GTNET104
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7G.1
7G.0 Minimum Version Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7G.2
7G.1 Model Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7G.2
7G.2 IEC 608705104<>RTDS Point Mapping . . . . . . . . . . . . . . . . . . . 7G.4
7G.3 RSCAD Draft Component and Parameter Entries . . . . . . . . . . . . . . . 7G.8
7G.4 MultiRack Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7G.10
8 MultiFunction Relay Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1
8.2 MultiThreaded Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1
8.3 Creating A Protection System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2
8.4 MultiFunction Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3
8.5 MultiFunction Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.24
iv
8.6 MultiFunction Differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.36

8.7 MultiFunction Sequence Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.45
8.8 MultiFunction Impedance Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.48
8A MultiFunction Control Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8A.1
8A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8A.1
8A.2 MultiFunction Breaker Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8A.2
8A.3 MultiFunction Tap Changer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8A.10
8B MultiFunction Meter Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8B.1
8B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8B.1
8B.2 MultiFunction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8B.2
8B.3 MultiFunction Impedance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8B.5
8B.3 MultiFunction Phasor Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8B.10
Rev. 02: Oct 04
OVERVIEW
This manual provides information regarding the control system component models
which are available for use with the RealTime Digital Simulator (RTDS). Specifically, the general usage, capabilities and limitations of the individual models are
presented, as well as how to interconnect the individual components to form control
system models for simulation. Documentation regarding the interconnection of control system signals to power system components and exporting power system signals
for use in control systems is also given.
The RTDS Tutorial Manual may be referenced for fully documented example cases
illustrating the use of the RTDS. One of the ways in which the user can gain confidence with a specific component model is to stimulate the component in isolation,
and observe its response. It is especially useful to perform tests where the components observed response is directly proportional to its user specified parameters. For
example, applying basic input signals such as a step or ramp and observing the output
the user can gain confidence with that control system function block.
Before introducing the individual control system component models available for
use on the RTDS, some fundamental concepts pertaining to the RTDS technology as
a whole will be presented. The remainder of this chapter is dedicated to a brief discussion of RTDS hardware and software. This discussion is intended to give the user a
general overview of the technology and to introduce some of the terminology which
is commonly used when referring to the RTDS.
1.1 INTRODUCING THE REALTIME DIGITAL SIMULATOR ( RTDS )

The RealTime Digital Simulator ( RTDS ) is a special purpose computer initially
designed to study Electromagnetic Transient Phenomena in realtime. The RTDS is
comprised of both specially designed hardware and software. RTDS hardware is
Digital Signal Processor ( DSP ) based and utilizes advanced parallel processing
techniques in order to achieve the computation speeds required to maintain continuous realtime operation.
3PC PROCESSOR CARDS

Power and control system component software is executed using RTDS Processor
cards labelled 3PC or RPC. At the present time, October 2004, the 3PC and the RPC
RTDS TECHNOLOGIES INC.
1.1
CC OVERVIEW
are the only type of processor card which may be used with the RTDS. Controls models execute only on the 3PC.
3PCs use Analog Devices 21064 processors, commonly referred to as SHARCs (Super Harvard Architecture). SHARC processors use the IEEE Floating Point standard
for representation of floating point numbers and execute a single instruction every
25 nanoseconds
RTDS SOFTWARE
RTDS software includes extensive libraries of power system and control system
components. Power system and control system components may be interconnected
to form the overall system for simulation.
This Manual describes the SHARC based control system components available in
the RSCAD/Draft library named 3PC_Controls. All SHARC control components
include an double line at the bottom of their outline.
G
1 + sT
SHARC Component
(rtds_sharc_ctl_REALPL)
SHARC Control Component Representation
The naming convention of SHARC controls components is rtds_sharc_ctl_COMPONENTNAME. It is possible to see a components name by putting the cursor
over the ungrouped component in RSCAD/Draft and then hitting the d key. The
components name will be displayed in the message area near the bottom of the
RSCAD/Draft screen. Only SHARC control components are included in the default
3PC_Controls library.
1.2 CONTROL SYSTEM MODELLING
Although it is possible to interface physical control systems to the RTDS, indeed this
is one of the main features of the RTDS, it is not practical to interface all of the various
controls systems required for a given power system model. Controllers such as automatic voltage regulators, stabilizers and speed governors are required to operate each
generator included in the power system. Physical controllers for power electronic
1.2
CC OVERVIEW
based equipment such as HVDC, SVC, TCSC and GTO based bridges are also rarely
available to the power system engineer. The operation of such controllers play an
important role in the steadystate and dynamic performance of the power system.
The controls component library permits the RTDS user to construct models of control systems using individually function blocks. These function blocks may be interconnected to each other, as well as, to power system components.
As a simple example consider the voltage regulation function illustrated below. In
this case control system function blocks are used to compute the difference between
the measured bus voltage and a setpoint and dynamically adjust the generator field
voltage to minimize the error. Node voltages, as sine waves, are read from the power
system and the controllers output, field voltage, is provided to the generator model.
Simple Automatic Voltage Regulator
1.3 LIST OF CONTROLS LIBRARY FUNCTION BLOCKS (BY GROUP)

The graphical libraries included in the DRAFT program include only the most commonly used controls and power system components. There are many other specialized components that can be added by right clicking with the mouse in the library
window and following the indicated path. If the users library is customized, it may
be saved with a unique name for quick recall in future sessions of DRAFT.
The following list does not include all of the specialized components in the controls
library. It is intended only to provide an overview of the main functions available.
Furthermore, several varieties of some of the listed components exist. If a specialized
component is required that does not exist in the supplied libraries, it can be created
with the User Defined Component facility.
1.3
CC OVERVIEW
MATH GROUP
Summing Junction
Gain,
Absolute Value
ex
Arctrig(arcsin,arccos,arctan)
F(X)
modulo div
Multiplication Junction
xN, KxN, xy
Square Root
Log
3 Phase Sine
Table Lookup
Divide Junction
x
y
Inverse Square Root
Trig (sin,cos,tan)
ATan2
Random
NOT
Word2Bit
Edge Detector
BitShift
SR FlipFlop
Bitmapper
IfThenElse
Signal Switch
Range Check
Compare c/w Fraction
Dynamic Limits
DeadBand
High Limit
Fixed Rate Limits

Low Limit
Hysteresis
IEEE>NEC
RAD<>DEG
INT>REAL
Digital Output
DAC16
FDAC
Analogue Output
DITS
DDAC
Frequency
Full Wave Rectifier
Angle Difference
LOGIC GROUP
Boolean (AND,OR,XOR)
Bit2Word
Ring Counter
SELECTOR GROUP
Selectmin/Max
Signal Select
LIMITER GROUP
Fixed Limits
Dynamic Rate Limits
Fixed Output Deadband
Hystersis with time out
DATA CONVERSION GROUP
NEC>IEEE
REAL>INT
INPUT/OUTPUT GROUP
Digital Input
Analogue Input
Front Panel LEDs
DOPTO
METERS GROUP
RMS
3 Phase P & Q
1.4
CC OVERVIEW
TRANSFER FUNCTION GROUP
Integrator
Washout
Lag
2nd Order
LeadLag
Elapsed Time
1 T Delay
Clock
2
Counter
Sampled Delay
Up/Down Counter
TIMER AND COUNTER GROUP

Time
Scheduler
Pulse Generator
Variable Delay
SIGNAL PROCESSING GROUP
Zero Crossing Detector
Phase Locked Loop (type 2)
3 Phase Transformation
3 Phase DQ0 Transformation
Down Sampler
Synchronous Buffer
FIR Filter
Phase Locked Loop (type1)

Discrete Fourier Transform (DFT)
Butterworth Filter
DQ0 3 Phase Transformation
Moving Average Filter
Synchronous Counter
Sample/Hold
SIGNAL GENERATOR GROUP

Source
Firing Pulse
Fixed Ramp
Variable Ramp
Plot Update
Pst
Set Flag 0
EXAC1A AVR
EXAC4 AVR
EXST2 AVR
IEEET1 AVR
IEEET4 AVR
IEEEX2 AVR
HYGOV GOV
IEEEG2 GOV
EXAC2 AVR
EXDC2 AVR
EXST3 AVR
IEEET2 AVR
IEEET5 AVR
IEEEX2A AVR
IEESGO GOV
IEEEG3 GOV
MISCELLANEOUS GROUP
Stop
SendT0
GENERATOR CONTROLS GROUP
IEE2ST PSS
EXAC1 AVR
EXAC3 AVR
EXST1 AVR
EXPIC1 AVR
IEEET3 AVR
IEEEX1 AVR
GAST GOV
IEEEG1 GOV
TGOV1 GOV
LOAD GROUP
Load Model
ZIP Calculation
Exponential Load Calculation

1.5
Rev. 02: Oct. 04
CONTROLS COMPILER USAGE
Control system models for simulation using the RTDS can be constructed using basic
control system function blocks. This Chapter documents the general features of the
Controls Compiler software.
2.1 CREATING A CONTROL SYSTEM MODEL
RSCAD/DRAFT
Control system component function blocks can be accessed from RSCAD/Draft by
loading the library named 3PC_Controls. The same stretchable wire component
and jumper components that are used to interconnect power system components are
used to interconnect control system components. Inputs to a component are identified by an arrow and outputs by a line. All component inputs must be connected to
an output signal. A compile time error will be generated if an input signal is left floating. Component output signals need not be connected to anything.
N1
|X|
N2
|X|
N3
|X|
Va
max
max
Vmax
Vb
Vc
input signals are identified by

an arrow.
PROCESSOR ASSIGNMENT
Since most control components require only a relatively small amount of executable
code, many control system components can be assigned to the same SHARC processor. Controls components are assigned to a processor by setting their Proc parameter in RSCAD/Draft. The assigned processor will be allocated in the rack correRTDS TECHNOLOGIES INC.
2.1
CC USAGE
sponding to the RSCAD/Draft subsystem page in which the component is placed.
Assignment of the actual processor within the rack will usually not match the number
entered for the Proc parameter, however. In other words, the processor referred to
in the Proc parameter is a virtual processor. The RTDS Controls Compiler will assign controls processors to the first available non dual 3PC unit in the rack. Since
control components do not make use of the features available in a dual 3PC unit, the
dual units are left for other components which may be assigned later in the compile
process. If a nondual unit cannot be found within the rack the controls components
will be assigned to a dual 3PC.
The user is able override the search for the first nondualunit and to force assignment
of control components to a specific processor by using the ASSIGN CONTROLS
PROCESSOR block. This block (rtds_sharc_ctl_PROCASN) forces the assignment of all control function blocks with the same value of Proc to a specified
SHARC processor.
N1
abs
gain
inverse
|X|
5.0
1
X
Proc=1
Proc=5
Proc=8
If the circuit above represents the only control system components on a given
RSCAD/Draft page, then the abs function block will be assigned to the first available
processor residing on a nondual3PC card, the gain block on the next available processor and the inverse function on the next after that. For example, if the rack to which
the subsystem was assigned contained a total of five 3PC cards with the first and second arranged as dual and the third and fourth arranged as dual and the fifth as a single
then the abs block would be assigned to 3PC #5A, the gain block to 3PC #5B and the
inverse block to #5C. If the rack contained only four 3PC cards, again with the first
and second and third and fourth arranged as dual then the abs block would be assigned to 3PC #1A, the gain to 3PC #1B and the inverse to 3PC #1C.
By placing ASSIGN CONTROLS PROCESSOR blocks onto the RSCAD/Draft
page, virtual control processors can be forced onto actual 3PC processors. The ASSIGN block must not be used to assign more than one virtual controls processor to
an actual processor or a compile time error will result.
In this example, delays between the execution of each block have been introduced
by forcing each component to run in a separate processor. The consequences of this
are discussed in Section 2.5.
2.2
CC USAGE
abs
gain
inverse
|X|
5.0
1
X
Proc=1
Proc=5
Proc=8
N1
ASSIGN
CONTROLS
PROCESSOR #1
ASSIGN
CONTROLS
PROCESSOR #5
ASSIGN
CONTROLS
PROCESSOR #8
to 3PC 1A
to 3PC 1B
to 3PC 1C
abs block
gain block
inverse block
> 3PC 1A
> 3PC 1B
> 3PC 1C
PRIORITY ASSIGNMENT
The order in which control function blocks assigned to the same processor are executed can be very important. Assignment of blocks in the non optimum order may
result in unnecessary signal time delays. The Pri parameter associated with control
system function blocks can be used to manually set the order of execution for function blocks assigned to the same processor. A component with Pri= 1 will be executed before a component with Pri= 2. The user may leave gaps when assigning values
to the Pri parameter. For example, assigning values of 1, 5, 10, 15 ... to function
blocks is acceptable. It is probably a good idea to leave gaps between Pri values so
as to allow blocks to be inserted at a later time. Blocks assigned the same Pri value
will be executed in random order. For example, a set of blocks assigned the following
Pri values
Block #1
Block #2
Block #3
Block #4
Pri= 1
Pri= 5
Pri= 5
Pri= 10
may be executed in the order Block #1, Block #2, Block #3 and Block #4, or in the
order Block #1, Block #3, Block #2 and Block #4.
Automatic priority assignment by the Controls Compiler software is available and
usually preferable. In this case the Pri value should be set to 1 for each controls function block and the automatic ordering option should be turned on in RSCAD/Draft.
2.3
CC USAGE
To access the Auto/Manual ordering option select the OPTIONS button with a right
click and hold in the circuit area of RSCAD/Draft. The following popup menu will
appear.
Processor number and priority can be displayed in RSCAD/Draft by a left clickand

hold on the File label in upper left hand corner of the screen and sliding down to Options. The following menu will appear. Select the Show controls priority & processor
# box. The box can be deselected by clicking on it again if it is already selected.
Once the simulation case has been compiled, the order in which the components have
been allocated, as well as, the actual processor to which they have been allocated can
be seen by reading the MAP file. The actual processor and the order of execution
are listed here.
2.4
CC USAGE
Alternatively, a graphical display of the component order for each processor may be
seen by selecting the box with the vertical bars at the top of the Draft screen.
Note that the graphical display will only show the correct component order after the
case has been compiled. In addition to ordering, this display provides information
about the total length of time taken to complete execution of all components allocated
to a particular processor. This information is useful for ensuring that the longest controls processor execution time is not impacting the length of the overall time step in
a case. It is also useful for balancing the execution load on controls processors when
more than one is required in a case. Note that the processor numbers shown refer to
the virtual controls processor number and not the actual one.
In many cases, it is useful to have selected portions of a large control system running
on separate controls processors. The user can arrange the allocation of different parts
of the control to different processors so that the resultant time delays do not degrade
performance. To guarantee that particular controls components are given the same
processor number, the selected controls can be Grouped in Draft and then all changed
with an Edit Common command. Edit Common is available only on grouped components and changes all variables with the same name in the Group. It is performed by
a right clickandhold on the Group, sliding down to Edit and across to Common.
In this case, the variable Proc must be entered, followed by the desired processor
number.
IMPORT/EXPORT COMPONENTS
IMPORT and EXPORT components are used to exchange control signals between
control blocks assigned on different subsystems. An EXPORT component
(rtds_sharc_ctl_EXPORT) must be assigned a unique name (ie. a control signal may
only be exported once). One or more IMPORT components (rtds_sharc_ctl_IMPORT) given the same name as the corresponding export component may be connected to input wires for components on different RSCAD/Draft subsystem pages.
An IMPORT/EXPORT pair which spans RTDS racks which are not directly connected by an InterRack Communication (IRC) channel will result in a compile time
error. The IMPORT component requires that the signal type be specified (FLOAT
or INT). Only upper case letters may be used.
2.5
CC USAGE
1
X
5.0
|X|
SIG1
export
circuit in subsystem #1
SIG1
import
|X|
circuit in subsystem #2
Import/Export component pairs must also be used to bring monitored signals produced by power system components into control system components. In the case of
node voltages and monitored outputs there is no wire to which the EXPORT component may be attached. In this case an EXPORT component with a name matching
the power signal may be placed anywhere on the RSCAD/Draft page which also includes the relevant power system component. Alternatively, an IMPORT/EXPORT
combination component (rtds_sharc_ctl_IMPEXP) may be used. This component is
simply a single component which represents both the IMPORT and EXPORT components together.
N2
N1
10.0
N2
export
N1
import/export
I12
export
V12
N2
import
I12
import
I12
0.1453
Node Voltage N2 and Branch Current I12

are exported from the power system and
imported to controls using separate IMPORT and EXPORT components. Node
Voltage N1 uses a combined IMPORT/
EXPORT component.
I12PU
2.6
CC USAGE
SHARC
AC Type
A
IMPORT/EXPORT components are

used to bring monitored signals from
power system components into control
system components.
B
C
src
230.0 kV
SOURCE MODEL: MONITORING SUBMENU
PSRC
import/export
0.01
QSRC
import/export
0.01
PPU
QPU
HIERARCHY COMPONENT
The Hierarchy Component may be used to schematically separate circuit diagrams
into a number of blocks. Separate Hierarchy components may be allocated for each
major control function and may be nested so that the controls component structure
reflects the actual controls.
Control signals which are common between separate Hierarchy components or between the DRAFT main page and a Hierarchy component should be identified with
wire labels.
A Hierarchy component may be made to appear as an actual control block as shown
below. The Hierarchy component may be shaped as desired and given a color including white. Labeled wires can be drawn to the edge of the box as shown.
2.7
CC USAGE
If several components of the same type are needed, the Hierarchy box can be copied
and placed repeatedly in the circuit. However, wire labels must be changed in each
instance to match the correct external signals.
Controls components within the Hierarchy run on the same rack as any other controls
on the main page. They may be grouped to run in a seperate processor, if desired.
COMPILING
Once the control system circuit has been completely drawn, the case must be compiled. This done in the same manner as compiling a power system or mixed power
and controls case. If the case has not been compiled before, the user is required to
enter a file name. Note that the size of the time step and the starting rack number are
given default values.
The compiling procedure is done in two steps. Firstly, the RSCAD/Draft software
creates data files (case.dta and case.dtp). The case.dtp file is used as input by the
RTDS compiler (rtdspc) which in turn generates the following text (ASCII) files
case.map
Information regarding the allocation and ordering

of components to processors. The minimum time
step is listed at the end of the .map file.
case.inf
A list of all input and output variables and their

internal RTDS addresses.
case.sib
The default Batch file for RSCAD/RunTime. This

file is updated when SAVE is selected in RSCAD/
RunTime.
case_r1 ...
One such file for each subsystem. The _r# refers

to the rack number. Each file contains the data
and executable code for the RTDS processors.
Although all of the files are readable, the .map file is the only one which contains
information pertinent to the user.
2.8
CC USAGE
2.2 RUNNING A CONTROL SYSTEM MODEL SIMULATION
Once the circuit for simulation has been successfully compiled (no errors) in
RSCAD/Draft the case is ready for simulation. Running cases which include controls is not much different than running power system simulation cases. An empty
.sib file, which can be loaded using the File>Open command in RSCAD/RunTime,
is created by the compile process.
MONITORING CONTROL SIGNALS (WIRE LABELS)
In order for control signals to be viewable using meter or plot components in
RSCAD/RunTime, the wire must be labelled using a wire label component (wirelabel).
Any control signal thus labelled will appear under the Subsystem#>CTLs>Vars group when an output component is created. The created component will automatically display FLOAT or INT depending upon the type of signal
being monitored.
|X|
S1
5.0
1
X
S2
Signals S1 and S2 may be monitored using RSCAD/RunTime
Create > Plot
2.9
CC USAGE
RSCAD/RUNTIME INPUT COMPONENTS
Control system input signals may be connected to RSCAD/RunTime input devices
such as sliders, switches, push buttons and dials. The input components are placed
in RSCAD/Draft and assigned a unique names. Corresponding components may
then be placed in RSCAD/RunTime in order to dynamically set values to the control
signals.
switch
slider
1
button
dial
0
5.0
RSCAD/Draft Input Components
Right clickandhold
And select
OR
Select one of these
Initial values for each input component may be set from within RSCAD/Draft. The
specified initial value will be assigned to the control signal to which the input component is connected even if the corresponding input component is not created in
RSCAD/RunTime. Switches and Push Buttons may be specified to produce REAL
or INTEGER type data. Dial components can be configured as REAL, INTEGER
or HEX. Sliders only produce REAL values.
2.3 INTERFACING EXTERNAL SIGNALS
ANALOG I/O
The following control function blocks are available to write control signals to analogue output ports available on the RTDS.
2.10
CC USAGE
rtds_sharc_ctl_AOUT
rtds_sharc_ctl_DAC16
rtds_sharc_ctl_FDAC
rtds_sharc_ctl_DDAC
front panel analogue output port

3 channel 16 bit D/A output board
Optically isolated 6 channel 16 bit D/A
Optically isolated 12 channel 16 bit D/A
3PC cards do not include onboard analogue input capability. As such an external
optical analoguedigital converter board (OADC) is required. The following component can be used to read in external analogue signals from the OADC board
rtds_sharc_ctl_OADC
6 channel 16 bit A/D input board
Note: the OADC, FDAC and DDAC communicate with the 3PC card via the optical
port which is only available to the C processor on the 3PC.
The
rtds_sharc_ctl_OADC, rtds_sharc_ctl_FDAC and rtds_sharc_ctl_DDAC function
blocks may thus only be assigned to a C processor.
DIGITAL I/O
The A and B processors on 3PC cards each have direct access to a digital I/O port.
Sixteen digital input and sixteen digital output signals are available at each port. The
following components may be used to read/write control signal data to the digital I/O
port.
2.11
CC USAGE
rtds_sharc_ctl_DIGINP
rtds_sharc_ctl_DIGOUT
rtds_sharc_ctl_DITS
rtds_sharc_ctl_DOPTO
Read signal from digital input port

Write signal to digital input port
Digital Input Time Stamp Card
Digital Optical Isolated I/O
The DITS card is used to acquire digital inputs from external firing pulse generators.
It not only signals the arrival of a firing pulse, it also generates a signal called Frac
that records the arrival time of the firing pulse within a time step.
The DOPTO card is used to optically isolate digital inputs and outputs. It connects
via ribbon cable to the DOPTO CC and the DOPTO OC for convenient connection
to terminal blocks. Also, the DOPTO communicates with the 3PC card with link
ports to processor C and leaves the Digital I/O ports free for use with the A and
B processors.
2.12
CC USAGE
2.4 NUMERICAL CONSIDERATIONS
Sharc control component input and output signals may be either REAL (IEEE Floating Point) or INTEGER. A control components input or output wire may be of a
fixed type or may be changed by the setting of a parameter associated with the component. Connection of a REAL signal to an INTEGER signal results in a compile
time error.
TPC & 3PC MIXED MODE OPERATION
The processors used on TPC cards (NEC 77240) and on 3PC cards (ADSP21062)
within RTDS racks use a different format for representation of floating point numbers. In order to permit simulation cases to run when both TPC and 3PC cards are
used in the same simulation case, 3PC cards are equipped with NEC>IEEE and
IEEE>NEC format conversion hardware. NEC processors are not able to convert
floating point data to and from IEEE format.
If the RTDS compiler recognizes that a simulation case will run on racks which include both TPC and 3PC cards the floating point mode is automatically set to NEC.
This results in all power system components running on SHARC processors to convert their output and input from NEC to IEEE format. In this way all external power
system floating point data is in NEC format.
Control system components running on TPC cards also read and write floating point
data only in NEC format. Control system components running on 3PC cards, however, read and write only IEEE format data. In order to exchange floating point data
between SHARC control components and power system components or NEC control components the user must place IEEE>NEC (rtds_sharc_ctl_IEEE2NEC) and
NEC>IEEE (rtds_sharc_ctl_NEC2IEEE) conversion function blocks. These conversion blocks are only available in the SHARC controls library. NEC>IEEE conversion blocks should be allocated the highest priority (lowest Pri values) so that they
are executed before any other control blocks. NEC>IEEE conversion blocks
should be given the lowest priority (highest Pri value) so that they are executed after
all of the other control blocks.
2.13
CC USAGE
N2
N1
Simulation Case run
on RTDS racks with
no TPC Cards.
10.0
N1
...
...
N2
EFIELD
5.0
to generator model
N2
N1
10.0
N1
NEC
N2
NEC
IEEE
...
IEEE
NEC Format
...
Same case as above run

on RTDS racks with a
combination of TPC and
3PC racks.
IEEE Format
5.0
IEEE Format
IEEE
NEC
EFIELD
to generator model
NEC Format
FLOATING POINT RESOLUTION

Sharc processors use 40 bit extended precision floating point format with 32 bits allocated to the mantissa and 8 bits to the exponent. Floating point registers within the
Sharc processor, as well as, Sharc internal memory and 3PC external memory are all
able to store 40 bit data. Communication between processor cards, however, uses the
RTDS rack backplane which is 32 bits. Any data transferred between processor cards
is truncated from 40 bits to 32 bits.
2.14
CC USAGE
RTDS RACK BACKPLANE

32 BIT DATA
32 BIT DATA
BACKPLANE
QUAD PORT
ADSP
21062
40 BIT DATA
ADSP
21062
40 BIT DATA
SHARC C
40 BIT DATA
SHARC A
MEMORY
ADSP
21062
SHARC B
3PC CARD
There are circumstances where the 40 bit floating point representation does not provide enough accuracy. Consider the case where an integrator takes as input the difference between a measured quantity and a setpoint. Applying trapezoidal rule integration, the integrator output is computed as follows
Y(t)= t / 2T * [X(t) + X(tt)] + Y(tt)
X(t)= new input
X(tt)= input from previous timestep
Y(tt)= output from previous timestep
T= integrator time constant
t= integration timestep
The fraction t/2T can be very small since t is usually on the order of s and T can
be on the order of seconds. It is possible that the magnitude difference between the
output term (y(tt)) and the input term (t / 2T * [x(t) + x(tt)] ) is greater than
the processors floating point precision. In such circumstances the integrator output
remains at the initial output value even thought its input is nonzero.
The Integrator controls component includes an extended precision mode which detects that a nonzero input resulted in no change to the output and accumulates the
input term until the value of y(t) changes.
2.15
CC USAGE
2.5 SIGNAL TIME DELAYS
Due to the parallel processing aspects of the RTDS, there are circumstances where
there may be delays between the time when a signal is written out from a component
and when that signal is read in by another component. Timestep delays will also
be introduced when control system circuits include feedback paths.
All RTDS processors used for a particular simulation case operate in lock step. Each
processor receives the same timestep signal and starts its computations at the same
time. Once all processors have completed their computations for the given time
step, data is communicated from each processor to all others. For example, data computed by Processor A on 3PC #1 will be transferred so that in the next timestep all
processors on the same rack will have access to that data. In cases where the computed signal is required as input on other racks the data will be transferred and made
available to all processors on the other rack as well. Only named control signals are
transferred. Signal wires not labelled with a wire label are stored in the processors
internal memory and are not available for input by other processors, nor are those
signals available for metering in RSCAD/RunTime.
Controls components are solved sequentially on each processor. Time is only incremented at the start of each new timestep. There are no timedelays when an output signal from a component which is executed prior to the component which receives the signal as input when the two components are assigned to the same
processor.
|X|
S1
Pri=1
5.0
S2
Pri=2
1
X
S3
Pri=3
Signal S3 based on S2(t), S2(t) based on S1(t)
|X|
Pri=3
S1
5.0
Pri=1
S2
1
X
S3
Pri=2
Signal S3 based on S2(t), S2(t) based on S1(tt)
In the case where components are executed on processors residing on different 3PC
cards, the input signal will be based on the output computed from the previous time
step. Outputs computed on one processor card are communicated to other processor
cards at the end of each time step. Using the example above, consider the case when
the abs and gain (*5.0) blocks are executed on 3PC 1A and the 1/X block on 3PC 2A.
In this case signal S2(t) is computed based on input S1(t). Signal S2, however, is not
available to processors on card 3PC 2A until the next timestep. Signal S3 is comRTDS TECHNOLOGIES INC.
2.16
CC USAGE
puted one timestep after signal S2. If signals S2 and S3 are plotted on a common
grid in a RSCAD/RunTime plot, it will be observed that signal S3 changes one time
step later than S2.
|X|
S1
5.0
S2
Proc=1 (3PC 1A) Proc=1 (3PC 1A)

Pri=1
Pri=2
Proc #1 (3PC 1A)
|X| Block
1
X
S3
Proc=4 (3PC 2A)

Pri=3
Proc #1 (3PC 1A)

1/X Block
S1(t)
timestep #1
Gain *5 Block
S2(t)
...
communication interval
S2(tt)
1/X Block
timestep #2
The situation is somewhat more complex for the case when controls components are
assigned to blocks which are executed on processors residing on the same 3PC processor. Since all three processors residing on a 3PC share a single block of external
memory, signals written to external memory by one processor may be accessed by
the other processors on that card during the same timestep. However, only control
blocks which are executed after completion of the block producing the output will
read the (t) value. Blocks which use the signal as input, but are executed before the
block producing the output has completed will receive the (tt) signal. The shared
memory will not permit reading and writing at the same time thus preventing invalid
data from being read as input.
2.17
CC USAGE
Synchronized communication between processors residing on a 3PC card is possible
using link ports. Each of the A, B and C processors can communicated to the
other two using link ports. A control components named rtds_sharc_ctl_LPWR will
write a signal to the designated link port channel and the rtds_sharc_ctl_LPRD component is used to read the data. The link port hardware will cause the reading processor to wait until the data has been received from the writing processor.
3PC cards arranged as dual units are able to use link port communication between
processors on the two cards. Only AA, BB and CC link port communication is
possible between processors which are part of a dual 3PC unit.
2.6 EXECUTION & COMMUNICATION TIME
All computation and communication must be complete within the specified time
step. As the number of control components allocated to a processor increases the
computation time required by that processor increases. The processor whose computation time is longer than all others determines the minimum timestep that can
be used to maintain realtime operation of the RTDS. The computation time associated with each control component is given by the _SHINST_ variable in the COMPUTATION section within the components definition. The _SHINST_ variable is
equal to the number of instructions required to execute the longest path through the
components code. Since some components include ifthenelsestructures the time
taken to execute the code may vary from timestep to timestep. Since the Sharc
processor executes an instruction every 25 nanoseconds the time required to complete a block is equal to _SHINST_* 0.025 s.
Once all processors participating in a simulation case have completed their executable code, data is communicated from one processor card to all others on the rack.
0.125 s is required to transfer each data word. Each control signal identified with
a wire label must be transferred. Signals not identified with a wire label, but required
as input on another 3PC card, signals exchanged between racks and signals exchanged between control system and power system components must also be transferred.
The longest computation time, as well as, communication time are listed at the bottome of the .map file produced by the RTDS compiler. Processor loading can be seen
by opening the processor usage window in RSCAD/Draft (see Section 2.1 above).
HIDDEN TRANSFERS
Control signals that are not required as input by any other control system block or
power system component and are required only for monitoring in RSCAD/RunTime
are transferred as hidden transfers. Such transfers are only allocated if the RTDS is
equipped with WIF cards (not WIC cards). Hidden transfers occur after the normal
communication period when the processors have begun the next timestep. Since
these transfers occur in parallel with a computation interval they do not add to the
time step. For every 8 signals allocated as hidden in a single rack simulation case,
the timestep may be reduced by 1 s. Signals allocated as hidden are identified in
.map file produced by the RTDS compiler.
2.18
CC USAGE
2.7 INTERCONNECTION TO POWER SYSTEM COMPONENTS
Interconnection of signals between control system components and power system
components can be done using IMPORT/EXPORT components, by signal name or
by direct connection using wire components. The method to be used depends on the
type of power system component to which the control signals are to be interfaced.
Named signals computed by power system components can be attached to control
signal wires using an IMPORT/EXPORT component pair. The name given to the
IMPORT/EXPORT components must be upper case and must match the name assigned to the variable in the power system component menu. Signals such as monitored branch or breaker currents, node voltages and monitored signals produced by
power system components can all be attached to control signal wires using IMPORT/
EXPORT component pairs. A timestep delay is introduced when a signal is processed through a control circuit. For example, if node voltage N1 is Imported into
a control system gain (*1.0) block and both the node voltage and the gain block outputs are plotted on the same grid in PSCAD/RunTime the control signal will be
delayed by one timestep.
The connection between control signals that are used as input to power system components can be made using a control signal wire label component. The wire label
name must be the same as the name specified for the signal in the power system component menu. If the control component producing the signal resides on another subsystem then an IMPORT/EXPORT pair must be used. The EXPORT component
should be attached to the control signal wire and the IMPORT component placed in
the same subsystem as the power system component.
2.19
CC USAGE
2.20
Rev. 03: Aug 07
CONTROL BLOCKS
Control components are accessed from RSCAD/Draft 3PC_Controls library. The

library window may be customized and saved as a user library using SAVE TAB AS
function. Individual components may be added to a library by using the
COMPONENT>ADD function. The library must be saved in order for the newly
added component to be stored in the library.
A components name can be displayed by highlighting the component (put the cursor
over the component) and pressing the d key. The components name is displayed
as part of a message shown in the message window near the bottom of the
RSCAD/Draft window.
3.1
CC BLOCKS
SUMMING JUNCTION
MATH
CLASS:
MATH FUNCTION
FUNCTION:
2 or 3 Input Summing Junction
RSCAD/Draft ICON:
rtds_sharc_ctl_SUM3
Num= 3
Num= 2
Description:
2 or 3 input summing junction. Inputs may be individually set to add to or subtract
from the output. INTEGER or REAL operation may be specified.
See Also:
Execution Time: 0.375 s
3.2
CC BLOCKS
MATH
MULTIPLICATION JUNCTION
CLASS:
MATH FUNCTION
FUNCTION:
2 or 3 Input Multiplication Junction
RSCAD/Draft ICON:
rtds_sharc_ctl_MUL
Num= 3
Num= 2
Description:
2 or 3 input multiplication junction. INTEGER or REAL operation may be specified.
See Also: GAIN
3.3
CC BLOCKS
MATH
DIVIDE JUNCTION
CLASS:
MATH FUNCTION
FUNCTION:
2 Input Divide Junction
RSCAD/Draft ICON:
rtds_sharc_ctl_XDIVY
X/Y
Description:
2 input divide junction. Inputs and output are REAL. The user may specify the result
of a divide by zero (ie. Y input = 0.0) as either HALT or SET OUTPUT.
In halt mode, a divide by zero causes the simulation to stop with RSCAD/RunTime
issuing the error message Floating point invalid. In halt mode the output X/Y is
set equal to 0.0 for the first timestep after starting the simulation case.
In setoutputmode, a denominator value less than 1.0e12results in the output being
set to the user specified value (Val). No error or warning message is issued in
RSCAD/RunTime.
See Also: INVERSE
3.4
CC BLOCKS
MATH
GAIN
CLASS:
MATH FUNCTION
FUNCTION:
Gain
RSCAD/Draft ICON:
rtds_sharc_ctl_GAIN
1.0
Description:
Gain block, output= gain * input. Input and Output are REAL.
See Also: MULTIPLICATION JUNCTION
3.5
CC BLOCKS
MATH
kX
kX X
CLASS:
MATH FUNCTION
FUNCTION:
X raised to power N (2 =< N >= 99)
RSCAD/Draft ICON:
rtds_sharc_ctl_XPOWN
rtds_sharc_ctl_KXPOWN
kX
X= Input
N= Integer Constant
k= Real Constant
Description:
output= input raised to power N or input raised to power N multiplied by k. Input,
k and Output are REAL, power is an integer greater than or equal to 2 and less than
or equal to 99.
See Also: rtds_sharc_ctl_EXP
Execution Time: 5+N s
3.6
CC BLOCKS
Xy
MATH
CLASS:
MATH FUNCTION
FUNCTION:
X raised to power y
RSCAD/Draft ICON:
rtds_sharc_ctl_XPOWY
X
Y
Description:
output= input raised to power y. Inputs X and Y, and Output are REAL.
See Also:
rtds_sharc_ctl_EXP
rtds_sharc_ctl_KXPOWN
rtds_sharc_ctl_XPOWN
3.7
CC BLOCKS
K X
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Inverse K/X
RSCAD/Draft ICON:
rtds_sharc_ctl_INV
K
X
X= Input
K= Constant
Description:
output= K/input. Input, K and Output are REAL. The user may specify the initial
input signal value which will be used to compute the output for the first timestep
after start of the simulation. The operation mode for a divide by zero (ie. Input = 0.0)
may be specified as either HALT or SET OUTPUT.
In halt mode, a divide by zero causes the simulation to stop with RSCAD/RunTime
issuing the error message Floating point invalid. In halt mode the output X/Y is
set equal to 0.0 for the first timestep after starting the simulation case.
In setoutputmode, a denominator value less than 1.0e12results in the output being
set to the user specified value (Val). No error or warning message is issued in
RSCAD/RunTime.
See Also: DIVIDE JUNCTION
Execution Time:
Halt mode= 0.55 s

Set output mode= 0.7 s
3.8
CC BLOCKS
ABSOLUTE VALUE
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Absolute Value
RSCAD/Draft ICON:
rtds_sharc_ctl_ABS
|X|
Description:
output= abs(input). Input and Output are REAL.
See Also:
3.9
CC BLOCKS
SQUARE ROOT
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Square root
RSCAD/Draft ICON:
rtds_sharc_ctl_SQRT
Description:
output= sqrt(input). Input and Output are REAL. The operation mode for a negative
square root (ie. Input < 0.0) may be specified as either HALT or SET
OUTPUT=0.
In halt mode, a negative input causes the simulation to stop with RSCAD/RunTime
issuing the error message Negative Square Root Error.
In setoutput=0 mode, a negative input results in the output being set to 0.0. No error
or warning message is issued in RSCAD/RunTime.
See Also:
3.10
CC BLOCKS
INVERSE SQUARE ROOT
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Inverse Square root
RSCAD/Draft ICON:
rtds_sharc_ctl_INVSQRT
1
X
Description:
output= 1.0/sqrt(input). Input and Output are REAL. The operation mode for a
negative square root or zero input (ie. Input =< 0.0) will cause the block output to be
0.0. No error or warning message is issued in RSCAD/RunTime.
See Also:
3.11
CC BLOCKS
x
e
MATH
CLASS:
MATH FUNCTION
FUNCTION:
e raised to power X
RSCAD/Draft ICON:
rtds_sharc_ctl_EXP
X= Input
e= 2.71828183
Description:
output= e raised to power input. Input and Output are REAL.
See Also:
3.12
CC BLOCKS
LOG
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Natural Log, Log base 10 or Log base 2
RSCAD/Draft ICON:
rtds_sharc_ctl_LOGS
LOG e
LOG 10
LOG 2
Func= LN
Func= Log10
Func= Log2
Description:
output= Natural Log, Log base 10 or Log base 2 of the input. Input and Output are
REAL.
See Also:
3.13
CC BLOCKS
TRIG
MATH
CLASS:
MATH FUNCTION
FUNCTION:
sine, cosine, tangent
RSCAD/Draft ICON:
rtds_sharc_ctl_SINE
sin
(rad)
cos
(rad)
tan
(rad)
FT= sin
FT= cos
FT= tan
Description:
output= Sine, Cosine or Tangent of the input. The input signal may be specified as
radian or degree by setting the Mode parameter. Input and Output are REAL.
See Also:
3.14
CC BLOCKS
ARCTRIG
MATH
CLASS:
MATH FUNCTION
FUNCTION:
arcsine, arccosine, arctangent
RSCAD/Draft ICON:
rtds_sharc_ctl_ARCTRIG
arcsin
(rad)
Fun= arcsin
arccos
(rad)
Fun= arccos
arctan
(rad)
Fun= arctan
Description:
output= ArcSine, ArcCosine or ArcTangent of the input. The output signal may be
specified as radian or degree by setting the Osig parameter. Input and Output are
REAL. Input signals for the arcsin and arccos functions are limited to the range
1.0 <= X <= +1.0
See Also:
3.15
CC BLOCKS
3 PHASE SINE
MATH
CLASS:
MATH FUNCTION
FUNCTION:
3 Phase Sine
RSCAD/Draft ICON:
rtds_sharc_ctl_SINE3
3 Phase
Sine
Ph
(rad)
A
B
C
3 Phase
Sine
Ph
(rad)
(pk)
A
B
C
G
Gain= Yes
Gain= No
Description: Three phase sine wave generator. The input signal is phase in either
radians or degrees depending on the Mode parameter setting (rad or deg). The output
is a three phase sine wave with phase rotation ABC and with outputs
A= sine(Ph)
B= sine(Ph 120_)
C= sine(Ph + 120_)
With the Gain parameter set to No, the output magnitude is limited to +/1.0. With
the Gain parameter set to Yes the output magnitude is controlled using the G input
signal.
All input and output signals are REAL.
See Also:
Execution Time:
Gain=No 3.55 s
Gain=Yes 3.7 s
3.16
CC BLOCKS
ATAN2
MATH
CLASS:
MATH FUNCTION
FUNCTION:
2 input arctangent
RSCAD/Draft ICON:
rtds_sharc_ctl_ATAN2
R
I
ATAN2
(rad)
Input R= Real Component Input
Input I= Imaginary Component Input
Description:
output= ArcTangent of the input. By specifying both the real and imaginary
components of the input, the output can be computed in the range =
180_ < Y <= 180_
See Also:
3.17
CC BLOCKS
F(X)
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Nonlinear gain function
RSCAD/Draft ICON:
rtds_sharc_ctl_NLINEAR
rtds_sharc_ctl_NLG32
Y
Yn1
Y=F(X)
Xn1
Description: NLINEAR
A nonlinear gain is specified by entering up to 10 pairs of X,Y points. The output
(Y) is computed given the input (X) and the specified data points. The first and last
line segments are extended so that an input greater than Xn or less than X1 will have
a computed output. The entered values of X1, X2 ... Xn must be monotonically
increasing (ie. Xn+1 > Xn).
Description: NLG32
The same as above except that 32 pairs of points can be entered.
See Also:
3.18
CC BLOCKS
TABLE LOOKUP
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Table Lookup
RSCAD/Draft ICON:
rtds_sharc_ctl_TABLE
20
Description:
Input is an index into a table of predefined numbers. The number of entries in the
table is limited to 48 and may be specified as REAL or INTEGER (IorF parameter).
The input is INTEGER and must be in the range of 1 .. N where N is the number of
entries in the table. An input of 2, for example, results in the value associated with
the second table entry to be sent to the output signal. An input value less than 1 results
in the first table entry to be sent to the output and an input value greater than N results
in the last table entry to be sent to the output.
See Also:
3.19
CC BLOCKS
RANDOM
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Random Number Generator
RSCAD/Draft ICON:
rtds_sharc_ctl_RAND
RAND
(white)
RAND
(Gaussian)
Description:
output= Random Number. For white noise, a random number in the range 1 <= Y
<= 0 is generated in each time step. For Gaussian noise, a random number centered
about zero with a user selectable standard deviation is generated in each time step.
The seed input parameter is used to generate a new pseudo random number sequence.
Note that two RAND functions with the same seed value will generate the same
random number sequence. The sequence is computed using the following algorithm.
The initial value of seed is provided by setting the seed parameter.
k= float(seed) * 1/127773.0 + 0.5
ik= int(k)
seed= 16807.0 * (seed ik * 127773.0) 2836.0 * ik
if (seed < 0) seed= seed + 0x7FFFFFFF
rand= seed
See Also:
3.20
CC BLOCKS
MODULO DIVISION
MATH
CLASS:
MATH FUNCTION
FUNCTION:
Modulo Division
RSCAD/Draft ICON:
_rtds_MODULO.def
MOD
2
Description:
This component calculates the modulo operation. It finds the remainer of the
division of the input by a user specified divisor. The input, divisor and output are all
floating point numbers. The calculation carried out by this component is expressed
mathematically below.
Y MOD
MOD
Y = X trunc
where X is the input, MOD is the divisor and Y is the output.

Example:
For an input of 25.5 and a modulo divisor value of 5, the output will be 0.1.
3.21
CC BLOCKS
BOOLEAN
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
AND, OR, XOR
RSCAD/Draft ICON:
rtds_sharc_ctl_LOGIC
Type= AND
Type= XOR
Type= OR
Description:
output= AND, OR, XOR of the inputs. The number of inputs may be specified
between 2 and 6 and the output may be inverted or noninverted. The logic operation
may be performed on a Least Significant Bit (LSB) or WORD basis. With the Op
parameter set to LSB all bits except the LSB are set to 0. With the Op parameter
set to WORD the logic operation is performed on all 32 bits of the input word.
Inputs and output are INTEGER.
Y= 1
65635
Y= 0
65635
LSB
LSB
65635
65635
Y= 65535
65635
Y= 65536
65635
WORD
WORD
65635
65635
See Also:
Execution Time: 0.175 + no_inputs*0.05 s
eg. 2 input AND= 0.275 s
3.22
CC BLOCKS
NOT
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
NOT
RSCAD/Draft ICON:
rtds_sharc_ctl_NOT
OP= LSB
OP= WORD
Description:
output= input. The logic operation may be performed on a Least Significant Bit
(LSB) or WORD basis. With the Op parameter set to LSB all bits except the LSB
are set to 0. With the Op parameter set to WORD the logic operation is performed
on all 32 bits of the input word. Input and output are INTEGER.
Y= 0
65635
Y= 65536
65635
OP= LSB
OP= WORD
See Also:
3.23
CC BLOCKS
BITSHIFT
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
BIT SHIFT
RSCAD/Draft ICON:
rtds_sharc_ctl_BSHIFT
<< 1
>> 1
SD= Left
SD= Right
Description:
output= logical shift(input). Left or right shift operation may be performed. Input
and output are INTEGER.
>> 1
Y= 0
SD= Right
See Also:
3.24
CC BLOCKS
BIT2WORD
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
CONVERT BITS to WORD
RSCAD/Draft ICON:
rtds_sharc_ctl_BIT2WORD
dot represents LSB

connection wire
b
i
t
w
o
r
d
Description:
Converts multiple logical inputs to a single word. The least significant bit input wire
is identified by a small dot. All input signals must be logical (ie. 0 or 1 only). The
number of inputs may be specified up to a maximum of 8. The output is INTEGER.
See Also:
Execution Time: 0175 + no_inputs * 0.125 s
3.25
CC BLOCKS
WORD2BIT
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
CONVERT WORD TO BITS
RSCAD/Draft ICON:
rtds_sharc_ctl_WORD2BIT
w
o
r
d
b
i
t
dot represents LSB

connection wire
Description:
Converts multiple an integer word to multiple logical signals. The least significant
bit input wire is identified by a small dot. All output signals are logical (ie. 0 or 1
only). The input is INTEGER.
See Also:
Execution Time: 0175 + no_outputs * 0.125 s
3.26
CC BLOCKS
SR FLIPFLOP
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
SET RESET TYPE FLIPFLOP
RSCAD/Draft ICON:
rtds_sharc_ctl_SRFF
SR
FLIP
FLOP
SR
FLIP
FLOP
INV= LOW
INV= HIGH
Description:
Set Reset, non clocked flipflop. The flipflop operates according to the following
truth tables. The initial state of the flipflop (Q=0 or Q=1) is defined by the ISTA
parameter.
Inputs Active High:
Inputs Active Low
Qinit= 0
Qinit= 0
See Also:
3.27
CC BLOCKS
TTYPE FLIPFLOP
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
TTYPE (Toggle Type) FLIPFLOP
RSCAD/Draft ICON:
rtds_sharcu_ctl_Tflipflop
The TType flip flop toggles its outputs on a clock signal when input T=1. When
T=0, the current state of the output is equal to the previous state. The initial state of
the flipflop (Q=0 or Q=1) is defined by the Init parameter. The flip flop can trigger
on a rising edge, falling edge or a level clock signal. The trigger type is defined by
the Trig parameter. The flipflop operates according to the following truth table.
T
Q(t)
Q(t+1) Q(t+1)
Execution Time: 1.48 s (3PC)

66.7 nS (RPC)
40.0 nS (GPC)
3.28
CC BLOCKS
RING COUNTER
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
Ring Counter
RSCAD/Draft ICON:
rtds_sharc_ctl_RINGCOUNTER
Description:
The output value increments to next table entry each time a valid input transition
occurs. Valid input transitions are defined by the OP parameter and may be set to
Rising Edge (0>1), Falling Edge (1>0) or Both. A valid input transition when the
output is at the last table entry results in the first table entry being output.
See Also:
3.29
CC BLOCKS
EDGE DETECTOR
LOGIC
CLASS:
LOGIC FUNCTION
FUNCTION:
Edge Detector
RSCAD/Draft ICON:
rtds_sharc_ctl_EDGEDET
Edge
Detector
Description:
A single timestep pulse is output when a valid input transition occurs. Valid input
transitions are defined as 0>1, 1>0 or Both by the ED parameter. The magnitude
of the one timestep pulse is defined by the OV parameter.
Input and output are INTEGER.
See Also:
3.30
CC BLOCKS
LOGIC
BIT MAPPER
CLASS:
LOGIC FUNCTION
FUNCTION:
Bit Mapper
RSCAD/Draft ICON:
rtds_sharc_ctl_MAPBITS
Bit Mapper
6 5 4 321
65 4 32 1
Description:
One to six bits in an input integer can be rearranged in a user selectable way for the
output.
Input and output are INTEGER.
See Also:
3.31
CC BLOCKS
SELECT6
SELECTOR
CLASS:
SELECTOR FUNCTION
FUNCTION:
6 INPUT SELECTOR
RSCAD/Draft ICON:
rtds_sharc_ctl_SELECT6
1
2 S
E
L
3
E
C
4 T
5
6
S
Description:
Output is set equal to input 16 selected by value at input S. Function can operate
on REAL or INTEGER numbers. For example, if S= 1 then output= input 1. A select
value less than 1 selects input 1. A select value greater than 6 selects input 6.
See Also:
3.32
CC BLOCKS
MIN/MAX
SELECTOR
CLASS:
SELECTOR FUNCTION
FUNCTION:
2 or 6 input Minimum or Maximum selector
RSCAD/Draft ICON:
rtds_sharc_ctl_MINMAX,
rtds_sharc_ctl_MINMAX6
max
min
min
max
Description:
Output is set equal to the minimum or maximum input value. Input and Output can
be selected as INTEGER or REAL.
See Also:
Execution Time: minmax= 0.3 s
minmax6= 0.8 s
3.33
CC BLOCKS
IFTHENELSE
SELECTOR
CLASS:
SELECTOR FUNCTION
FUNCTION:
IfThen_else select block
RSCAD/Draft ICON:
rtds_sharc_ctl_COMPARE
IF A>= B
Y= 1
Else
Y= 2
EndIf
IF A!= B
Y= 1
Else
Y= 2
EndIf
LOG= A==B
LOG= A>=B
A
IF A== B
Y= 1
Else
Y= 2
EndIf
LOG= A!=B
IF A> B
Y= 1
Else
Y= 2
EndIf
LOG= A>B
Description:
Output is set equal to the specified value depending on inputs A and B and chosen
logic function.
A>=B:
A==B:
A!=B:
A>B:
A greater than or equal to B

A equal to B
A not equal to B
A greater than B
Inputs and output can be independently specified as INTEGER or REAL.

See Also:
3.34
CC BLOCKS
RANGE CHECK
SELECTOR
CLASS:
SELECTOR FUNCTION
FUNCTION:
IfThen_else select block
RSCAD/Draft ICON:
rtds_sharc_ctl_RANGE
UL
A
LL
LL <= A <= UL
Y= 1
Else
Y= 2
EndIf
OP= LL<=A<=UL
UL
Y
A
LL
LL < A < UL
Y= 1
Else
Y= 2
EndIf
OP= LL<A<UL
Description:
Output is set equal to the specified value depending on whether input A is within or
outside the range specified by inputs UL and LL.
LL<=A<=UL: A greater than or equal to LL and
A less than or equal to UL
LL<A<UL: A greater than LL and A less than UL
Inputs and output can be independently specified as INTEGER or REAL.
See Also:
3.35
CC BLOCKS
SIGNAL SELECT
SELECTOR
CLASS:
SELECTOR FUNCTION
FUNCTION:
Signal select based on input logic
RSCAD/Draft ICON:
rtds_sharc_ctl_SIGSW2
If (C1 > C2)

Out= A
Else
Out= B
C1
C2
Logic Options
C1 > C2
C1 >= C2
C1 == C2
C1 < C2
C1 <= C2
Description:
Output is set equal to the input signal A or B depending on the selected logic option
(LOG parameter) and inputs C1 and C2.
C1>C2:
C1>=C2:
C1==C2:
C1<C2:
C1<=C2:
C1 greater than C2
C1 greater than or equal to C2
C1 equal to C2
C1 less than C2
C1 less than or equal to C2
Inputs and output are REAL.

See Also:
3.36
CC BLOCKS
SIGNAL SWITCH
SELECTOR
CLASS:
SELECTOR FUNCTION
FUNCTION:
Signal select based on control signal
RSCAD/Draft ICON:
rtds_sharc_ctl_SIGSW
Ctrl= 0
B
Ctrl
Description:
Output is set equal to the input signal A or B depending on the Ctrl signal value. If
the Ctrl signal is equal to the specified value (A parameter) then the output is set equal
to the A signal, otherwise the output is set equal to the B signal.
The Ctrl signal must be INTEGER. Data flow signals A, B and output may be
specified as REAL or INTEGER.
See Also:
3.37
CC BLOCKS
FIXED LIMITS
LIMITER
CLASS:
LIMITER
FUNCTION:
Fixed Limit
RSCAD/Draft ICON:
rtds_sharc_ctl_LIMITS
+1.0
1.0
Description:
Output is limited to the specified range (upper and lower range values are specified
as fixed values). Input and output may be specified as REAL or INTEGER.
See Also:
3.38
CC BLOCKS
DYNAMIC LIMITS
LIMITER
CLASS:
LIMITER
FUNCTION:
Dynamic Limit
RSCAD/Draft ICON:
rtds_sharc_ctl_DYNLIMS
Max
Min
Description:
Output is limited to the specified range (upper and lower range values are input
signals which may change dynamically). Input, output and maximum and minimum
limits may be specified as REAL or INTEGER.
See Also:
3.39
CC BLOCKS
FIXED RATE LIMITS
LIMITER
CLASS:
LIMITER
FUNCTION:
Fixed Rate Limit
RSCAD/Draft ICON:
rtds_sharc_ctl_RATELIMIT
+1.0
1.0
Rate Limiter
Description:
Rate of change of output is limited to the specified range (upper and lower range
values are input signals which may change dynamically). The lower range limit must
be specified as a negative number. A positive or negative rate limit of 0.0 will result
in no change to the output if the input changes in the corresponding direction. Input
and output are REAL.
See Also:
3.40
CC BLOCKS
DYNAMIC RATE LIMITS
LIMITER
CLASS:
LIMITER
FUNCTION:
Dynamic Rate Limit
RSCAD/Draft ICON:
rtds_sharc_ctl_VRATELIMIT
max
min
Rate Limiter
Description:
Rate of change of output is limited to the specified range (upper and lower range
values are specified as fixed values). The lower range limit must be specified as a
negative number. A positive or negative rate limit of 0.0 will result in no change to
the output if the input changes in the corresponding direction. Input and output are
REAL.
See Also:
3.41
CC BLOCKS
DEADBAND
LIMITER
CLASS:
LIMITER
FUNCTION:
DeadBand
RSCAD/Draft ICON:
rtds_sharc_ctl_DEADBAND
Description:
Output= Input only if the input is outside the specified limits. If the input is within
the specified limits (THL parameter) the output is set equal to 0.0.
See Also:
3.42
CC BLOCKS
LIMITER
FIXED OUTPUT DEADBAND
CLASS:
LIMITER
FUNCTION:
Fixed Output DeadBand
RSCAD/Draft ICON:
rtds_sharc_ctl_DEADFIX
Description:
Output= specified value when the input is outside the specified limits. If the input
is within the specified limits (UTH and LTH parameters) the output is set equal to
0.0.
See Also:
3.43
CC BLOCKS
HYSTERSIS
LIMITER
CLASS:
LIMITER
FUNCTION:
Hystersis Function
RSCAD/Draft ICON:
rtds_sharc_ctl_HYSTER1
0
Low
0
1
High
1
Description:
The Hystersis function allows inputs and outputs to be INTEGER or FLOAT. The
initial state of the output can be set. The input values for trasnition to the output state
are selectable and the values of the output are selectable. Time at or above the input
value required to cause a transition to a high output as well as time at or below the
input level required to cause a transition to a low state are user selectable. Zero means
no time at these levels is required.
See Also:
3.44
CC BLOCKS
DATA CONVERSION
NEC>IEEE
CLASS:
DATA CONVERSION
FUNCTION:
Convert NEC Format number to IEEE Format
RSCAD/Draft ICON:
rtds_sharc_ctl_NEC2IEEE
IEEE
NEC
Description:
A NEC Format REAL input signal is converted to IEEE Format. NEC Format
signals occur only for simulation cases which include TPC processor cards. RTDS
simulators which contain only 3PC processor cards do not use NEC format data.
Control or power system signals IMPORTED from a TPC based processor must be
converted to IEEE format before being used as input to a SHARC control
component.
See Also:
3.45
CC BLOCKS
DATA CONVERSION
IEEE>NEC
CLASS:
DATA CONVERSION
FUNCTION:
Convert IEEE Format number to NEC Format
RSCAD/Draft ICON:
rtds_sharc_ctl_IEEE2NEC
NEC
IEEE
Description:
An IEEE Format REAL input signal is converted to NEC Format. NEC Format
signals occur only for simulation cases which include TPC processor cards. RTDS
simulators which contain only 3PC processor cards do not use NEC format data.
Control system signals EXPORTED from a 3PC based processor must be converted
to IEEE format before being used as input to TPC or 3PC based power system
components when the simulation includes both TPC and 3PC cards.
See Also:
3.46
CC BLOCKS
DATA CONVERSION
INT>REAL
CLASS:
DATA CONVERSION
FUNCTION:
Convert INTEGER to IEEE Format number
RSCAD/Draft ICON:
rtds_sharc_ctl_INT2IEEE
IEEE
INT
Description:
An INTEGER input is converted to IEEE REAL.
See Also:
3.47
CC BLOCKS
DATA CONVERSION
REAL>INT
CLASS:
DATA CONVERSION
FUNCTION:
Convert an IEEE Format number to INTEGER
RSCAD/Draft ICON:
rtds_sharc_ctl_IEEE2INT
INT
IEEE
Description:
An IEEE REAL format number is converted to INTEGER. The OP parameter may
be set to round or truncate mode to control the conversion.
See Also:
3.48
CC BLOCKS
DATA CONVERSION
RAD<>DEG
CLASS:
DATA CONVERSION
FUNCTION:
Radian and Degree conversion
RSCAD/Draft ICON:
rtds_sharc_ctl_DEGRAD
deg
rad
Fun= deg>rad
rad
deg
Fun= rad>deg
Description:
Converts degrees to radians (Fun= deg>rad)or radians to degrees (Fun= rad>deg).
See Also:
3.49
CC BLOCKS
DATA CONVERSION
DBL2SGL
CLASS:
DATA CONVERSION
FUNCTION:
Double to Single precision number conversion
RSCAD/Draft ICON:
rtds_sharc_ctl_DBL2SGL
Description:
The input double precision floating point number is converted into a single precision
floating point number using a user specified rounding mode. The resulting single
precision floating point number is then converted back to a double precision floating
point number.
This component is very specific to number precision and in general will rarely be
used.
The process in this model can be written in Pseudocode as shown below:
double
float
double
dblInput;
floatInput;
dblOutput;
dblInput = <input value>;

floatInput = (float) dblInput; // specified rounding mode is used
dblOutput = (double)floatInput;
Four different rounding modes are available;
Round tonearest
Round towardzero (Truncate)
Round up (Towards +Infinity)
Round down (Towards Infinity)
3.50
CC BLOCKS
Below is an example using the different rounding modes.
DRAFT case
RUNTIME results
It is noted above that the same floating point input produces different results
according to the rounding mode used.
Execution Time:
25 nS
15 nS
(RPC)
(GPC)
3.51
CC BLOCKS
DIGITAL INPUT
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Digital Input
RSCAD/Draft ICON:
rtds_sharc_ctl_DIGINP
.
.
.
.
.
.
.
.
.
.
.
DIGITAL
INPUT PORT
Processor #1
Description:
16 bit data is read from the processors digital input port. 3PC processors A and B
have access to a digital input port. The C Processor does not have access to a digital
port. The digital input port component reads 16 bits and returns an INTEGER.
Digital input port pins which are not connected to external equipment read a logic
1. A value of 65535 (=0xFFFF) is returned if no connections are made to the digital
input port. A mask parameter is available to mask off unwanted bits from the digital
input port. For example, a mask value of 000F will read only the four lowest order
bits.
The Del parameter is used to delay the read of the digital input port with respect to
the timestep. The delay time is specified in microseconds from the placement of
the digital input port component within the processor. If the digital input component
is the first component executed in the assigned processor, the delay corresponds to
the time from the start of the timestep.
See Also:
Execution Time: 0.2 + delay s
3.52
CC BLOCKS
DIGITAL OUTPUT
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Digital Output
RSCAD/Draft ICON:
rtds_sharc_ctl_DIGOUT
.
.
.
.
.
.
.
.
.
.
.
DIGITAL
OUTPUT PORT
Processor #1
Description:
16 bit data is written to the processors digital output port. 3PC processors A and B
have access to a digital output port. The C Processor does not have access to a digital
port. The digital output port component writes a 16 bit INTEGER to the digital
output port. A mask parameter is available to mask off unwanted bits from the digital
data. For example, a mask value of 000F will cause only the four lowest order bits
to be written. All other bits will be logic 0.
See Also:
3.53
CC BLOCKS
ANALOGUE OUTPUT
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Analogue Output
RSCAD/Draft ICON:
rtds_sharc_ctl_AOUT
da1
da #1
ICON= LARGE
ICON= SMALL
Description:
Data is written to the specified analogue output channel on the assigned processor.
Each 3PC processor has direct access to 8 analogue output channels. The analogue
channels output voltage range is +/ 10 volts peak. A digital signal with a value of
+1.0 will result in an analogue output of +10 volts. An input signal outside the range
+/1.0 will result in clipping of the analogue output voltage to +/10 volts. The SC
parameter is used to scale the input signal so that the specified value will result in an
analogue output voltage of 5 volts (half scale).
Dynamic offset and scale sliders may be included (SL parameter). If enabled the user
is able to create RSCAD/RunTime sliders to dynamically adjust the analogue output
offset and scale. A RSCAD/RunTime switch may also be created which controls the
LED associated with the analogue output channel. The LED can be turned on by the
switch to help locate the analogue output port on the front of the RTDS.
The front panel analogue output channels use 12 bit D/As and do not include optical
isolation. For high precision, optically isolated analogue output see information
regarding the DAC16 component.
See Also: DAC16
3.54
CC BLOCKS
ANALOGUE INPUT
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Analogue Input from OADC
RSCAD/Draft ICON:
rtds_sharc_ctl_OADC
1
2
3
1
4
5
OADC Analogue Input

NS= 1
6
OADC
Analogue Input
NS= 6
Description:
Read data from the Optical Analogue Input Card (OADC). The OADC reads data
from up to six analogue input channels and converts it to digital format for use by the
RTDS. A separate scale value is included for each input signal (SC1 ... SC6). Scale
values represent the analogue signal peak voltage (in volts) which will result in a
value of 1.0 to be present on the corresponding output signal wire (labelled 1 .. 6).
For example, a scale value of SC1=5.0 means that a voltage of 1 volt on the analogue
input channel #1 will result in a value of 1.0 on the output wire labelled 1. The
maximum input range of the OADC is +/ 10 volts peak.
See Also:
3.55
CC BLOCKS
FDAC DAC16
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
DAC16 Analogue Output
RSCAD/Draft ICON:
rtds_sharc_ctl_FDAC
1
2
3
FDAC
dac16
Description:
These components write output signals to a DAC16 or an FDAC. These are high
precision analogue output boards providing 3 channels on the DAC16 and 6 channels
on the FDAC. Both D/A converters are optional RTDS hardware components which
are mounted in the rear of the cubicle. The DAC16 interfaces to a digital I/O port
while the FDAC interfaces to an optical output port. As a result, the FDAC
communicates through a C processor while the DAC16 communicates through an
A or B processor.
Inputs to both components are REAL. Software converts and scales the input signals
to 16 bit and writes them out. Both components have an output range of +/10 volts.
The S1M, S2M, ... parameters are used to set the scale values such that the specified
input signal magnitude will result in an analogue output voltage of +5 volts (half
scale).
Both cards include optical isolation.
See Also: rtds_sharc_ctl_DDAC
3.56
CC BLOCKS
DITS
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Digital TimeStamp Card Input
RSCAD/Draft ICON:
rtds_sharc_ctl_DITS
FP
EN
DITS
ACT
Frac
Description:
The DITS component is an optional RTDS hardware component which is used in
conjunction with power system components such as HVDC Valve Groups to provide
high resolution firing. The DITS hardware component takes in six firing pulses from
an external controller and sends the information to a 3PC via the digital input port.
The Firing Pulse Word (FP output signal) represents the state of the six firing pulses.
The ACT output (INTEGER) signal indicates which firing pulse (1..6 or 0 for none)
which changed since the last read of the DITS input. The Frac output (REAL)
represents the fraction within the timestep at which the DITS card noted the last
firing pulse to change. The FRAC output is non zero only during the timestep after
a firing pulse was detected.
The ACT and Frac output signals may be specified as active on the rising or falling
edge of the firing pulse (EN parameter). A mask is available (FPM parameter) to
force specific bits of the FP word to zero. If six firing pulses are to be used the FPM
parameter should be set to 3F. The INV parameter may be used to invert the FP output
signal.
The DITS component includes optical isolation.
See Also:
Execution Time: 1.325 + US s
US parameter is the user specified delay.
3.57
CC BLOCKS
DOPTO
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Digital Optical Isolation Card Input and/or Output
RSCAD/Draft ICON:
rtds_sharc_ctl_DOPTO
Description:
The DOPTO component is to be used with a Digital Optical Isolation Card
(DOPTO). The DOPTO component must be assigned to a sharc processor C. The
DOPTO card is physically connected to processor C of a sharc card. Signals are
passed between the C processor and the DOPTO card through the link port.
A DOPTO keyword must be entered in the config_file at the slot number associated
with the C processor connected to the DOPTO card.
The DOPTO component can be used to read 24 bit digital inputs from the DOPTO
card, write 24 bit signals to the digital output, or both. A toggle box is available to
select the DOPTO component function. Select INPUT, the DOPTO component
will read inputs from the DOPTO card. Select OUTPUT, the DOPTO component
will write information to the digital output pins. Select BOTH, the DOPTO
component will read and write information to the DOPTO card.
DOPTO input and output digital pins which are not connected to external equipment
read a logic 1.
Mask parameters are available to mask off unwanted bits from the input and output
digital data. For example, a mask value of 00000F will cause only the four lowest
order bits to be read or written. All other bits will be logic 0.
See Also:
3.58
CC BLOCKS
I/O
DDAC
DDAC
CLASS:
INPUT/OUTPUT
FUNCTION:
Analogue Output
RSCAD/Draft ICON:
rtds_sharc_ctl_DDAC
Description:
The component writes input signals to a DDAC high precision analogue output
board. The DDAC board is an optional 12 channel RTDS hardware component
which is mounted in the rear of the cubicle. The DDAC board is connected to a 3PC
card via the optical port and therefore must be assigned to a C processor. A DDAC
keyword must be entered in the config_file at the slot number which corresponds to
the processor that the DDAC is connected too.
3.59
CC BLOCKS
Inputs to the DDAC component are REAL. The components software converts and
scales the input signals to 16 bit and writes them to the DDAC card via the optical
port. The DDACs output range is +/10 volts.
Oversampling is available and can be toggled on or off. Oversampling produces an
output signal with a sample rate of 2.5 s. When using oversampling, an initial
output advance parameter in timesteps is required. This parameter specifies the
starting point of the output signal for the next timestep. The nominal value is 1.0.
Please refer to the Interfacing Manual Chapter 1 section 1.2.3 for more information.
The 12 channels are divided into four groups. Each group contains three channels.
If three inputs are considered a group, then one scale value and an output advance
is required per group. Alternatively, the inputs do not have to be treated as groups,
each channel can be scaled independently and initial output advance is set to 1.0.
The outputs of all groups can be aligned. If the Align Groups parameter is set to Yes,
the output from each group is sent to the DDAC at the same time. If the groups are
not aligned, the output is sent as soon as the data is ready.
See Also:
rtds_sharc_ctl_FDAC
3.60
CC BLOCKS
FRONT PANEL LEDS
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
3PC Front Panel Orange LEDs
RSCAD/Draft ICON:
rtds_sharc_ctl_LED8
Description:
Turn on or off the eight front panel orange LEDs available on 3PC cards. Any input
signal other than 0 on an input will cause the corresponding LED to turn on.
See Also:
3.61
CC BLOCKS
GTAO
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Analog Output
RSCAD/Draft ICON:
rtds_risc_ctl_GTAOOUT
This model writes input signals to a GTAO high precision analogue output card. The
GTAO card is an optional 12 channel RTDS hardware component which is mounted
in the rear of the cubicle. The GTAO card is connected to a GPC card via the GTIO
port using a fiber cable. A GTAO# keyword must appear in the config_file for the
Draft case to compile successfully. The # character appearing in the keyword is
replaced with the GTIO port #. The keyword should be placed at the slot number of
the GPC processor that the GTAO card is physically connected too. Please refer to
the RTDS Hardware Manual Chapter 3B GIGA Processor Card(GPC) for location
3.62
CC BLOCKS
of GTIO ports. For example, if a GTAO card is connected to the GTIO port #2 of
the GPC card occupying slots 34 and 35, the config_file would appear as shown
below.
34 GPC VER 1.00 GTAO2
35 GPC VER 1.00
Note: Gigabit transceiver cards are always placed in the config_file on GPC card
processor A.
The config_file can be modified and/or automatically generated from
RSCAD/RunTime. If the GTAO card is physically connected to a GPC port during
automatic generation of the config_file, the correct keyword will be inserted. For
more information on generating the config_file using the RSCAD software, please
see the Config File Editor in RSCAD/RunTime online help.
Inputs to the GTAO model are IEEE754 double precision floating point numbers
This model converts and scales input signals to 16bit integers and writes them to
the GTAO card via the GTIO interface. All the outputs signals are sent to the DtoA
converters on the GTAO card at the same time (aligned). The GTAO cards output
range is +/ 10 volts. Inputs to the GTAO component must be scaled to produce a
desired voltage on the output channels of the GTAO card. The scale values can be
entered in the D/A Output Scaling menu item. For example, an input signal of
magnitude 187.79 kV LN peak is input to the GTAO component. Entering a scale
value of 187.79 will result in a 5V pk signal output of the GTAO card.
An initial output advance parameter in timesteps is required. This parameter
specifies the starting point of the output signal for the next timestep. The advance
factor can be used to advance the GTAO output signal in an attempt to elimate time
delays introduced when interfacing to external equipment. If no advance is required,
the advance factor should be set to 1.0. Setting the advance factor to 1.0 indicates
that the latest information is being used. Setting the advance factor to 0.0 will result
in a one timestep delay between the input and output of the GTAO.
advance factor = 2.0
tT
t
Figure 1. Advance Factors
t+T
time
3.63
CC BLOCKS
Oversampling can be activated using the OVERSAMPLING ACTIVATION

FACTOR menu item. Oversampling produces an output signal from the GTAO card
every 1.0 s. An oversampling factor between 0.0 and 1.0 is required. This factor
determines the slope of the oversampled output data. Typically a value of 1.0 is used.
Entering a value of 0.0 will turn oversampling off.
rise factor
slope = run
oversampling factor = 1.0
rise
run
tT
t+T
time
Figure 2. Oversampling Factors

The waveform capture in Figure 3 shows the effect of oversampling. With
oversampling turned off, the output from the GTAO is the waveform with the 50usec
steps. With oversampling turned on, the output from the GTAO is the smooth line.
Figure 3. GTAO Output

In some instances, oversampling can produce undesirable overshoot. Adjusting the
oversampling factor can decrease the amount of overshoot.
3.64
CC BLOCKS
tT
t+T
time
tT
t+T
time
original signal
oversampled output
Figure 4. Overshoot Adjustment Using The Oversampling Factor
Execution Time: 321 + (n * 100) nS (GPC)

n: Number of Analog Channel Output
3.65
CC BLOCKS
GTAI
I/O
CLASS:
FUNCTION:
RSCAD/Draft ICON:
INPUT/OUTPUT
Analog Input
rtds_risc_ctl_GTAI
Description:
This model reads data from the Analogue input Card (GTAI). The GTAI card is an
optional 12 channel RTDS hardware component which is mounted in the rear of the
cubicle. The GTAI card is connected to a GPC card via the GTIO port using a fiber
cable. The GPC GTIO port number connected to the GTAI card is required as an
input parameter to the model. In some cases, more than one GTAI card may be
connected to the same GPC GTIO port. Therefore, the GTAI card number to read
the input data must also be specified.
3.66
CC BLOCKS
The GTAI reads data from up to twelve analogue input channels and converts it to
digital format for use by the RTDS. Each channel may be enabled or disabled using
the toggle boxes provided in the ENABLE A/D INPUT CHANNELS menu. A
separate scale value is specified for each input signal (scl1 ... scl12). Scale values
represent the analogue signal peak voltage (in volts) which will result in a value of
1.0 to be present on the corresponding output signal wire (labelled 1 .. 12). For
example, a scale value of scl1=5.0 means that a voltage of 1 volt on the analogue
input channel #1 will result in a value of 1/5 (0.2) on the output wire labelled 1.
The maximum input range of the GTAI is +/ 10 volts peak.
The sampling method must be specified. Two options exist, Timestep Beginning
or Most Recent. The analogue input to the GTAI card is sampled a number of times
per timestep. The GTAI component reads the data only once per timestep. If the
sampling method is set too Timestep Beginning, the last data point sampled from
the previous timestep is used. If the sampling method is set too Most Recent, the
most recent sample is used. This feature is useful if the inputs read from two different
GTAI cards are to be aligned, the sampling method can be set too Timestep
Beginning.
See Also:
Execution Time: 646 + ( #channels * 25) ns
3.67
CC BLOCKS
GTDI
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Digital Input
RSCAD/Draft ICON:
rtds_risc_ctl_GTDIINP2
rtds_risc_ctl_GTDIINP2
rtds_risc_ctl_GTDIINP
Description:
The GTDI component is used to read digital input information from a GTDI card.
The GTDIINP2 model reads a 64 bit signal from the GTDI card and returns four
16bit INTEGER (INT) signals. The GTDIINP component reads a 64 bit signal
from the GTDI card and returns two 32 bit signals. Unlike the 3PC digital input port,
with no connection the GTDI output is logic 0.
Execution Time: rtds_sharc_ctl_GTDIINP = 105 nS (GPC)

rtds_sharc_ctl_GTDIINP2 = 126 nS (GPC)
3.68
CC BLOCKS
GTDIDITS
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Digital TimeStamp Input from GTDI
RSCAD/Draft ICON:
rtds_sharc_ctl_DITS
Description:
The GTDI_DITS model is used to provide high resolution firing information to
power system components such as HVDC Valve Groups. This model must be used
with a GTDI card. The GTDI card takes in six firing pulses from an external
controller and sends the information to a GPC via a fiber cable which connects the
GTDI card with one of the GPC GTIO ports on the rear of the GPC card. The Firing
Pulse Word (FP output signal) represents the state of the six firing pulses. The ACT
output (INTEGER) signal indicates which firing pulse (1..6 or 0 for none) changed
since the last read of the GTDI input. The Frac output (REAL) represents the fraction
within the timestep at which the GTDI card noted the last firing pulse to change.
The FRAC output is non zero only during the timestep after a firing pulse was
detected.
The ACT and Frac output signals may be specified as active on the rising or falling
edge of the firing pulse (EN parameter). A mask is available (FPM parameter) to
force specific bits of the FP word to zero. If six firing pulses are to be used the FPM
parameter should be set to 3F. The INV parameter maybe used to invert the FP output
signal.
Execution Time: 116 nS + US uS (GPC)

US parameter is the user specified delay.
3.69
CC BLOCKS
GTDO
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Digital Output
RSCAD/Draft ICON:
rtds_risc_ctl_GTDOOUT
The GTDO component writes binary data to the GTDO digital output card. The
GTDO component can write up to four 16 bit INTEGER signals to the 64 channel
GTDO card. Toggle parameters are available to disable output channels not in use.
Output channels in 16 bit blocks may be disabled. For example, output channels
116 may be used and channels 1764 disabled.
Execution Time: 112 nS (GPC)

3.70
CC BLOCKS
GTDODOTS
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Digital TimeStamp Output from GTDO
RSCAD/Draft ICON:
rtds_risc_ctl_GTDO_DOTS
Description:
The GTDO_DOTS model provides bit transition information to external controllers.
One of the models applications is offering the accurate valve turn off information to
an external HVDC controller. This model must be used with a GTDO card.
A six bit word is sent to the GTDO_DOTS component input marked as 063. The
model also requires a floating point fraction at input FRAC. The fractional
information indicates the exact moment within the time step a bit transition occurred
within the input word. This information is then sent to the GTDO card. When the
GTDO card receives the information, it replicates the input word at its output
channels at either FRAC or 1FRAC time later.
Below is the parameter dialog box which enables a user to set various parameters in
the model:
3.71
CC BLOCKS
An explanation of each parameter follows:
unit GTDO card starting channel number for the DOTS function. The 64 channels
of the GTDO card have been divided into 88channelgroups. If the starting channel
number selected is 1, the first six channels will be used, channel 7 and 8 remain
unused.
cfrac If this parameter is set to FRAC, the output of the GTDO card occurs at
FRAC moment within a time step. If this parameter is set 1FRAC the output
of the GTDO occurs at 1FRAC moment within a time step.
hold Minimum hold time of the GTDO output channels. This parameter is only
used if the cfrac parameter above is set to FRAC.
hold1 Minimum hold time of the GTDO output channels. This parameter is only
used if the cfrac parameter above is set to 1FRAC.
xoro bit MASK used to invert the output
Port GPC GTIO fiber port number
Card GTDO card number
Proc control processor number
Pri priority value
Execution Time: 175 nS

(GPC)
3.72
CC BLOCKS
GTFPI
I/O
CLASS:
INPUT/OUTPUT
FUNCTION:
Front Panel Interface
RSCAD/Draft ICON:
_rtds_GTFPI_V2.def
Description:
The GTFPI component writes/reads binary integer data to/from a GTFPI card. A
GTFPI card is physically connected to the RTDS front panel. A GTFPI card can be
used with a digital I/O front panel and/or a high voltage front panel. Options exist
in the GTFPI component to specify if the digital I/O panel and/or the high voltage
panel is to be used. The inputs and outputs of the GTFPI component will change
according to the selections made. There are four options available if using the digital
I/O panel. Sending a signal to the digital output panel (Outputonly), reading a
signal from the digital input panel (Inputonly), using both the digital input and
digital output panel (Both) and not utilizing the digital I/O panel (None). The high
voltage panel can be configured to include high voltage inputs. For more information
regarding the high voltage panel configuration, please refer to the GTFPI chapter of
the RTDS Hardware Manual. If high voltage inputs are available on the high voltage
panel, the number of high voltage inputs to be used can be specified in the GTFPI
component. Otherwise, the high voltage panel operates as 16 channel output. For
both the high voltage panel and the digital output panels, a starting bit number can
be specified. The starting bit number determines which channel to send the output.
Bit number 1 corresponds to first output channel. The number of consequtive
channels to use can also be specified.
Execution Time: 101 nS

(GPC)
3.73
CC BLOCKS
RMS
METERS
CLASS:
METERS
FUNCTION:
Single or Three Phase RMS Meter
RSCAD/Draft ICON:
rtds_sharc_ctl_RMS
rms
Mode= 3 Phase
rms
Mode= Single Phase
Description:
Three Phase RMS output is computed using the following
rms= sqrt( 1/3 * (Va2 + Vb2 + Vc2) )
The output may be scaled to a perunit quantity by setting the pu parameter to Yes
and entering the rated lineline rms value of the input as the SC parameter.
In 3 Phase operation mode, the user may specify whether the meter output is to be
a LineLine measurement or a LineNeutral measurement (LL parameter).
Single phase RMS output is computed using the circuit shown below. An integrator
computes the mean value of the square of the input. The integrator output is scaled
by the measured frequency and the square root is taken. The zero crossing detector
resets the integrator output each half cycle and triggers the sample and hold block.
The sample and hold block is used to hold the value computed by the integrator over
the input signals last half cycle.
The output of the single phase rms meter may be scaled to give a perunit value by
setting the pu parameter to Yes and entering the rated lineground rms value of the
input signal.
3.74
CC BLOCKS
SINGLE PHASE RMS METER CIRCUIT
See Also:
Execution Time: 3 Phase 1.1 s
1 Phase 4.625 s
3.75
CC BLOCKS
FREQUENCY
METERS
CLASS:
METERS
FUNCTION:
Frequency meter
RSCAD/Draft ICON:
rtds_sharc_ctl_FREQ
frequency
Output Options (mo parameter)

Frequency
Frequency
Omega
Omega
Description:
The frequency of the input signal is computed using zero crossing detection.
Interpolation of the zero crossings is included in the calculation of frequency. By
setting the mo parameter the frequency in Hz, Omega in rad/sec or change from rated
value can be produced as output. The output may also be scaled to a perunit value
(pu parameter)
See Also:
3.76
CC BLOCKS
ANGLE DIFFERENCE
METERS
CLASS:
METERS
FUNCTION:
Angle Difference Meter (3 Phase Sets)
RSCAD/Draft ICON:
rtds_sharc_ctl_ANGDIFF
A1
A2
B1
B2
rad
C1
C2
angle difference
bus1 bus2
Description:
The angle between two three phase signal sets is computed. The meter is most often
supplied with two three phase bus voltages which are used to measure the angle
between the two power system buses. The output may be specified in radians or
degrees (OSU parameter) and the reference direction as bus1bus2 or bus2bus1
(Ref parameter). For example, if the Ref parameter is set to bus1bus2 and bus 2
leads bus 1 by 10 deg., the meter will read 10.0 deg.
See Also:
3.77
CC BLOCKS
3 PHASE P & Q
METERS
CLASS:
METERS
FUNCTION:
3 Phase real and reactive power measurement
RSCAD/Draft ICON:
rtds_sharc_ctl_PQMET
Va
Vb
Vc
Ia
3 Phase Pm
P&Q
Meter
(pu)
Qm
Ib
Ic
Description:
The 3 Phase real and reactive power is computed from using the instantaneous
voltage and current signals as follows
Pm= Va*Ia + Vb*Ib + Vc*Ic
Qm= 1/sqrt(3) * ( Va*(IbIc) + Vb*(IcIa) + Vc*(IaIb) )
The output may be scaled to perunit by setting the pu parameter to Yes and
providing the rated MVA (MVA parameter).
In some cases the measured voltage and current signals will be out of sync by one
timestep. In this case the adv parameter may be set to delay either the voltage or
the current by one timestep.
See Also:
Execution Time: without averaging circuit 1.425 s
3.78
CC BLOCKS
FULL WAVE RECTIFIER
METERS
CLASS:
METERS
FUNCTION:
Full Wave Rectifier
RSCAD/Draft ICON:
rtds_sharc_ctl_FWR
Description:
Output= MAX(abs(input #1), abs(input #2), abs(input#3)).
The output can also be scaled to a perunit value by setting the pu parameter to Yes
and entering the rated lineline value of the input (Sc parameter). The scaled output
value is computed as;
Output =
3 * * scaleparameter
2
* Output
See Also:
3.79
CC BLOCKS
TRANSFER FUNCTION
INTEGRATOR
CLASS:
TRANSFER FUNCTION
FUNCTION:
Integrator Function
RSCAD/Draft ICON:
rtds_sharc_ctl_INTGL
Rval
1 X(t)dt
T
T= 1.0
RST= No
LIM= None
1 X(t)dt
T
T= 1.0
1 X(t)dt
T
T= 1.0
RST
RST= Yes
LIM= Internal
Description:
Integrator function using trapezoidal rule of integration. Input and Output are
REAL. The integrator may be dynamically reset to a specified value (Rval
) by setting the RST parameter to Yes. The integrator output is set to Rval when
the RST input signal is nonzero. Rval is REAL and RST is INTEGER.
Internal or External limits may be applied to the integrator output by setting the LIM
parameter. With external limits (LIM= External) the integrator will exhibit windup.
In this case the internal state of the integrator will continue to change for nonzero
input when the output has reached an upper or lower limit. Internal limits (LIM=
Internal) do not exhibit windup. In this case both the internal state and output are
limited to the designated values.
For cases where the value of T is very large relative to the simulation timestep and
where very small changes to the input are expected, extended precision mode (XP=
Yes) may be used. With extended precision very small increments to the internal
state will be accumulated until they have an impact on the integrator output.
See Also:
extended precision add 0.45 s
internal limits add 0.3 s
external limits add 0.25 s
reset add 0.4 s
3.80
CC BLOCKS
TRANSFER FUNCTION
CLASS:
TRANSFER FUNCTION
FUNCTION:
First Order Lag
RSCAD/Draft ICON:
rtds_sharc_ctl_REALPL
LAG
Rval
G
1 + sT
G
1 + sT
RST= No
LIM= None
G
1 + sT
RST
RST= Yes
LIM= Internal
Description:
First Order Lag (realpole) function using trapezoidal rule of integration. Input and
Output are REAL. The output may be dynamically reset to a specified value (Rval)
by setting the RST parameter to Yes. The output is set to Rval when the RST input
signal is nonzero. Rval is REAL and RST is INTEGER.
Internal or External limits may be applied to the output by setting the LIM parameter.
With external limits (LIM= External) the function will exhibit windup. In this case
the internal state of the function will continue to change for nonzero input when the
output has reached an upper or lower limit. Internal limits (LIM= Internal) do not
exhibit windup. In this case both the internal state and output are limited to the
designated values.
See Also:
reset add 0.4 s
3.81
CC BLOCKS
TRANSFER FUNCTION
LEADLAG
CLASS:
TRANSFER FUNCTION
FUNCTION:
LeadLag
RSCAD/Draft ICON:
rtds_sharc_ctl_LEADLAG
Rval
G (1 + sT1)
1 + sT2
RST= No
LIM= None
G (1 + sT1)
1 + sT2
G (1 + sT1)
1 + sT2
RST= Yes
LIM= Internal
RST
Description:
LeadLag function using trapezoidal rule of integration. T1 represents the lead time
constant and T2 the lag timeconstant. Input and Output are REAL. The output may
be dynamically reset to a specified value (Rval) by setting the RST parameter to
Yes. The output is set to Rval when the RST input signal is nonzero. Rval is REAL
and RST is INTEGER.
designated values.
See Also:
reset add 0.4 s
3.82
CC BLOCKS
TRANSFER FUNCTION
WASHOUT
CLASS:
TRANSFER FUNCTION
FUNCTION:
LeadLag
RSCAD/Draft ICON:
rtds_sharc_ctl_WASHOUT
Rval
G sT
1 + sT
RST= No
LIM= None
G sT
1 + sT
G sT
1 + sT
RST= Yes
LIM= Internal
RST
Description:
Washout function using trapezoidal rule of integration. Input and Output are
REAL. The output may be dynamically reset to a specified value (Rval) by setting
the RST parameter to Yes. The output is set to Rval when the RST input signal is
nonzero. Rval is REAL and RST is INTEGER.
designated values.
See Also:
reset add 0.4 s
3.83
CC BLOCKS
TRANSFER FUNCTION
2nd ORDER
CLASS:
TRANSFER FUNCTION
FUNCTION:
Second Order Polynomial
RSCAD/Draft ICON:
rtds_sharc_ctl_POLY3
aos2 + a1s + a2
s2 + b1s + b2
Description:
Second order polynomial with parameters determined directly or calculated as part
of a filter design.
Direct parameter entry is for the polynomial coeffecients ao, a1, a2, b1 and b2.
Filter design is for a Low Pass (LP), High Pass (HP), Band Pass (BP) or Band Stop
(BS). In the LP filter, a0 and a1 are zero, in the HP filter a1 and a2 are zero, in the
BP filter, a0 and a2 are zero and finally in the BS, a1 is zero.
If the largest time constant is Tlg and the smallest time constant in Tsm, then the time
step T used to calculate the coefficients should be about
Tsm > 5 to 10T and Tlg < 1000 to 5000T
In other words, for a normal T of say 50.0 microsec, Tsm should be no smaller than
250.0 microseconds and Tlg should be less than 250.0 milliseconds. As these
bounderies are encroached or exceeded, accuracy will be noticablely degraded.
See Also:
3.84
CC BLOCKS
STATESPACE
TRANSFER FUNCTION
CLASS:
FUNCTION:
RSCAD/Draft ICON:
TRANSFER FUNCTION
STATESPACE
_rtds_STATESPACE
X=[A]X+[B]U
Y=[C]X+[D]U
NumStates = 10
NumOut = 10
NumInp = 1
Description:
This component allows the user to specify a linear system of equations given in
StateSpace form. The component currently supports a maximum of 10 inputs, 10
outputs and up to 10 states. The user must specify the four matrices which make up
the state equation along with initial conditions in an external text file. The text file
must contain six lines. The first four lines correspond to matrices A, B, C and D
respectively while the last two are vectors containing the initial conditions for the
state variables and inputs respectively. An example showing an arbitrary state
equation and how it would be properly represented in the required text format is
given below.
NOTE: This component does check to ensure the stability of the StateSpace
equation entered by the user. If the user enters an Amatrix with positive
eigenvalues, the simulation will become unstable and will eventually terminate with
a floating point error.
General StateSpaceEquation:
.
[x] = [A][x] + [B][u]

y = [C][x] + [D][u]
Arbitrary Example State Equation with Initial Conditions:

.
69 107 uu
01 00 10uu
x1
5
1 2 x1
x2 = 3 4 x2 + 8
y1
11 12 x 1
y 2 = 13 14 x 2 +
1
2
1
2
3.86
CC BLOCKS
x 01 = 0.0,
u 01 = 1.23,
x 02 = 0.0
u 02 = 4.56,
u 03 = 0.00
Required Text File Formatting for the Arbitrary Example:

Line 1:
[ 1 2; 3 4]
Line 2:
[5 6 7; 8 9 10]
Line 3:
[11 12; 13 14]
Line 4:
[0 0 0; 1 0 0]
Line 5:
Line 6:
[1.23; 4.56, 0.00]
NOTES:
Columns are separated by spaces ( ) or by commas (,)
Rows are separated by semicolons (;)
The format of the text is compatible with the vector/matrix format used
by many commercially available mathematical analysis tools.
If a matrix or vector is zero then a 0 can be entered on the appropriate line
and the component will interpret it as an empty matrix/vector.
3.87
CC BLOCKS
TIME
TIMERS
CLASS:
TIMERS
FUNCTION:
TIME
RSCAD/Draft ICON:
rtds_sharc_ctl_TIME
RST
.
.
Description:
Output= time since last reset. A nonzero value on the RST input (INTEGER) will
reset the output to 0.0. The Mode parameter may be set to output a new value every
SECOND or every TIMESTEP.
See Also:
3.85
CC BLOCKS
ELAPSED TIME
TIMERS
CLASS:
TIMERS
FUNCTION:
ELAPSED TIME
RSCAD/Draft ICON:
rtds_sharc_ctl_TIMER
Start
Start
Stop
TIMER
Stop
TIMER
rst
RST= No
RST= Yes
Description:
Output= elapsed time between start and stop signals. Inputs may be specified active
on Rising Edge or Any Transient (Tran parameter). The output is updated after a
STARTSTOP sequence if the SRST parameter is set to No. If the SRST parameter
is set to Yes then any valid transition on the Start input will reset the timer.
A reset signal may be optionally included (RST parameter) which is used to reset the
output to 0.0. Any nonzero value on the RST input will cause the output to reset
to 0.0.
Only the first valid transition on the START input will be registered. For example,
a STARTSTARTSTOP sequence will cause the output to register the elapsed time
between the first START and STOP signal. The second START signal is ignored.
Inputs are INTEGER, output is REAL.
See Also:
Execution Time: RST= No 0.7 s
RST= Yes 0.97 s
SRST= Yes add 0.2 s
3.86
CC BLOCKS
COUNTER
TIMERS
CLASS:
TIMERS
FUNCTION:
COUNTER
RSCAD/Draft ICON:
rtds_sharc_ctl_UPDOWN
+10
Up
Up
Up
Down
Counter
Down
Counter
rst
RST= No
RST= Yes
Down
Counter
10
LIM= FIXED
Description:
The output is incremented each time a valid transition occurs on the Up input signal
and decremented each time a valid transition occurs on the Down input signal. The
Tran parameter is used to define a valid transition as Rising (0>1), Falling (1>0)
or Both rising and falling. With Tran set to Both a single pulse on the Up input
signal will cause the output to increment by 2. If set to either Rising or Falling the
output will increment by 1.
An optional reset (RST parameter) is available. Any nonzero value applied to the
RST input signal will cause the output to become 0.
Fixed or Dynamic Limits may be included (LIM Parameter) to limit the output and
to prevent windup.
All inputs and output are INTEGER.
See Also:
Execution Time:
RST= No, LIM= No 0.55 s

RST= Yes add 0.25 s
LIM= Fixed add 0.2 s
LIM= Dynamic add 0.3 s
3.87
CC BLOCKS
SCHEDULER
TIMERS
CLASS:
TIMERS
FUNCTION:
Scheduler
RSCAD/Draft ICON:
rtds_sharc_ctl_SCHED
.
.
.
.
scheduler
scheduler
EN=No
EN=Yes
Description:
The scheduler component sets its output based on a list of time and output pairs. If
the elapsed time exceeds a particular time entry the output changes accordingly. An
example usage of the component would be to modify the power order for loads and
generators in the system to simulate a daily load curve.
The SDS parameter is used to set the source of the time and output data. A LIST of
up to 30 pairs may be entered, up to 8000 data pairs may be read from a FILE, or up
to 8000 pairs may be generated using a RANDOM number generator.
The RST parameter is used to reset the schedulers internal clock so that the schedule
is repeated after the reset time. Output may be specified as equal to the specified
output (parameter Ym set to new value) or as a scale value of the initial output
(Y0*Yn).
The Tu parameter is used to identify whether the time units should be interpreted as
seconds, minutes or hours. For example, entering a timeoutput pair as (1.0,5.0) in
the LIST could be interpreted as setting the output to 5.0 after 1 second, 1 minute or
1 hour.
An optional Start/Stop control input can be enabled on the component by setting the
EN parameter to Yes. If this input is a logic 1, the component will output the
scheduled data. If this input is a logic 0, the component will output only the initial
output Y0.
When the SDS parameter is set to FILE, data is read from a file. The filename
containing the data is required as a parameter. The filename should have no filename
extension and appear in the same directory as the Draft case. The data file should
contain columns of tab or space separated columns. The first column is referred to
as column 0 and must contain the time data. The maximum column number that can
be read is 10. If more than 10 columns of data exist in the data file, the file can still
be used, but only data from the first 10 columns can be read . The first line of the data
file may contain an optional comment line starting with a #. If desired, the data may
3.89
CC BLOCKS
continously be output by setting the Loop parameter to Yes. This option overrides
the RST parameter. Therefore, rather than the data being restarted after the RST time
has elapsed, it will loop back to the beginning of the data file after the last data point
is output. The last data point is output for a time according to t[x] t[x1] before
looping back to the start of the data file. (where t[x] is the time of the last data point)
When the SDS parameter is set to RANDOM, both the time and output data are
computed using a Gaussian distribution of numbers. The user must enter the mean
and standard deviation for both the time and output data. The random time and output
values generated are stored in a file with filename Fn2 as entered by the user.
3.90
CC BLOCKS
1 T DELAY
TIMERS
CLASS:
TIMERS
FUNCTION:
One TimeStep Delay
RSCAD/Draft ICON:
rtds_sharc_ctl_DTDEL
rtds_sharc_ctl_DELBUF
z1
T
del
Trig
Description:
Delay the input by 1 timestep. Input and Output may be REAL or INTEGER. The
Delbuf function uses an external trigger to create large time steps that are some
multiple of the actual time step for the case.
See Also:
3.89
CC BLOCKS
SAMPLED DELAY
TIMERS
CLASS:
TIMERS
FUNCTION:
Sampled Delay
RSCAD/Draft ICON:
rtds_sharc_ctl_SDELAY
DELAY
0.01
Description:
Output= sampled delay of the input. The delay time in seconds is specified using the
DEL parameter and the number of samples to be taken during the delay time is
specified using the NS parameter. The maximum number of samples which may be
specified for a given delay is equal to DEL/t (t= simulation timestep).
The INIT parameter is used to specify the initial output.
Input and Output are REAL.
See Also:
3.90
CC BLOCKS
PULSE GENERATOR
TIMERS
CLASS:
TIMERS
FUNCTION:
Pulse Generator
RSCAD/Draft ICON:
rtds_sharc_ctl_MONO
0.001
TM= Fixed
time
TM= Variable
Description:
Fixed or variable width (TM parameter) pulse generator. A pulse is generated when
a valid input transition occurs. A valid input transition is defined by the PN
parameter and may be set to Rising (0>1), Falling (1>0) or Both. For variable
width pulse mode (TM parameter= Variable) the time input signal determines the
pulse width in seconds.
The output during the off state (ie. no pulse) is set by the OR parameter and the output
when triggered is set by the OT parameter. Both OR and OT are INTEGER.
Input and output are INTEGER, the time input is REAL.
See Also:
Execution Time: Fixed Width 0.48 s
Variable Width 0.78 s
3.91
CC BLOCKS
VARIABLE DELAY
TIMERS
CLASS:
TIMERS
FUNCTION:
Variable Delay
RSCAD/Draft ICON:
rtds_sharc_ctl_VDB
Input Signal
Variable
Delay Block
Delayed Output
Variable Delay Input

(seconds)
Description:
This component continuously buffers an input signal and outputs the signal with a
delay specified by the Variable Delay Input. Variable Delay Input accepts a REAL
value in seconds. The specified delay should be less than the maximum delay.
Maximum delay = buffer length * timestep.
0
Circular Buffer
Delayed Output
Variable Delay
Previous Entry
Latest Entry
Both inputs and the output are REAL.
3.95
CC BLOCKS
ZERO CROSSING
DETECTOR
SIGNAL
PROCESSING
CLASS:
SIGNAL PROCESSING
FUNCTION:
Zero Crossing Detector
RSCAD/Draft ICON:
rtds_sharc_ctl_ZCDET
/+ zero Zc
crossing
detector
FRAC= No
/+ zero Zc
crossing
detector Frac
FRAC= Yes
Description:
Zc output signal is set to the value specified by the OVal parameter when a valid zero
crossing is detected on the input signal. A valid zero crossing is defined by the Mode
parameter and may be set to +ve > ve, ve > +ve, or both.
An option fractional output may also be include by setting the Frac parameter to Yes.
The fractional output is in the range 0<frac<1. A frac value of 0.5 indicates that the
zero crossing occurred in the middle of the timestep. The frac value is nonzero
only during the timestep in which a zero crossing occurred.
Input and outputs are REAL.
See Also:
Execution Time: Frac=No 0.35 s
Frac= Yes 0.83 s
3.94
CC BLOCKS
SIGNAL
PROCESSING
PHASE LOCKED LOOP

(transvector type)
CLASS:
SIGNAL PROCESSING
FUNCTION:
Phase Locked Loop (transvector type)
RSCAD/Draft ICON:
rtds_sharc_ctl_PLL
Phi
A
B
PLL
60 Hz
Shift= In Phase
WMON= No
SMON= No
+
PLL
60 Hz
Phi
F
Shift= Lead 30
WMON= Hz
SMON= No
A
B
C
PLL
60 Hz
Phi
W
St
Shift= Lag 30
WMON= rad/sec
SMON= Yes
Description:
When locked, the Phi output represents the phase ( 2 < Phi <= 0) of the A input.
The Shift parameter is used to shift the phase signal relative to the A Phase input.
Lead by 30 deg., Lag by 30 deg. or no phase shift may be selected. The phase signal
is a sawtooth whose magnitude is less than or equal to 2. If the Phase is computed
internally as a value greater than or equal to 2 then the output is set equal to
phase2.
The computed frequency in Hz. or rad/sec may be provided as output by setting the
WMON parameter. A status output (St) is optionally available by setting the SMON
parameter to Yes. Status= 0 means that error signal causes either the Min or Max
limit to be active. Status= 1 means that the phase locked loop frequency is within
the specified min/max frequency.
3.95
CC BLOCKS
ab a
B
C
3
b
Phase
Kp
Err
1
Ts
max
+
+
Phi
cos
ramp
0.0
sin
min
transvector type phase locked loop circuit

It is important to note that the loop gain of this phase locked loop depends upon the
magnitude of the input signal. In the case where the input signal magnitude may
fluctuate significantly it is recommended that the arctan2 type phase locked loop
(rtds_sharc_ctl_PLLT2) component be used. An example where the arctan2 type
phase locked loop should be used is if the 3 phase input is based on measured line
currents as is often the case with Thyristor Controller Series Capacitor (TCSC)
controllers.
See Also: rtds_sharc_ctl_PLLT2
3.96
CC BLOCKS
SIGNAL
PROCESSING
PHASE LOCKED LOOP

(atan2 type)
CLASS:
SIGNAL PROCESSING
FUNCTION:
Phase Locked Loop (atan2 type)
RSCAD/Draft ICON:
rtds_sharc_ctl_PLLT2
Phi
A
B
PLLT2
60 Hz
WMON= No
EMON= No
Phi
PLLT2 F
60 Hz
B
C
WMON= Hz
EMON= No
A
B
C
Phi
PLLT2 W
60 Hz
Err
WMON= rad/sec
EMON= Yes
Description:
When locked, the Phi output represents the phase ( 2 < Phi <= 0) of the A input.
The phase signal is a sawtooth whose magnitude is less than or equal to 2. If the
Phase is computed internally as a value greater than or equal to 2 then the output
is set equal to phase2.
The computed frequency in Hz. or rad/sec may be provided as output by setting the
WMON parameter. The error signal is optionally available as output by setting the
EMON parameter to Yes.
The loop gain of this phase locked loop does not depend upon the magnitude of the
input signal. In the case where the input signal magnitude may fluctuate significantly
it is recommended that the this type of phase locked loop is used. An example where
the arctan2 type phase locked loop should be used is if the 3 phase input is based
on measured line currents as is often the case with Thyristor Controller Series
Capacitor (TCSC) controllers.
3.97
CC BLOCKS
3phase to
cos
ab a
B
C
Im
sin
3
b
Phase
Re
if b lags a
sin
cos
3phase to
cos
ab a
B
C
Im
sin
3
b
Phase
Re
if b leads a
sin
cos
W
Err
rated
PIPG
Im
ATAN2
Re
1
1 + sTft
Input from 3phase

to block above
Filter
1
Tpiits
ramp
0.0
Ramp
Generator
Phi
cos
cos
sin
sin
PIController
atan2 type phase locked loop circuit

See Also: rtds_sharc_ctl_PLL
3.98
CC BLOCKS
SIGNAL
PROCESSING
DFT
CLASS:
SIGNAL PROCESSING
FUNCTION:
Discrete Fourier Transform
RSCAD/Draft ICON:
rtds_sharc_ctl_DFT
PHASE
IN
DFT 4
Hn= 1
PHASE
An
Bn
OUTF= An&Bn
TRIG= No
IN
DFT 4
Hn= 1
PHASE
Cn
Phi
OUTF= CN&Phi
TRIG= No
IN
DFT 4
Hn= 1
OUTF= CN
TRIG= No
PHASE
Cn
IN
DFT 4
Cn
Hn= 1
TRIG
TRIG= Yes
Description:
The discrete fourier transform (DFT) is used to extract information regarding a single
harmonic from the input signal. For example, the DFT function can be used to find
the magnitude of the fundamental component (ie. 50 or 60 Hz) of a signal which
includes other harmonics or dc offset. The information to extract is specified by the
HARM parameter, where
0= DC Component
1= Fundamental frequency
2= 2nd harmonic
...
The PHASE input signal is a sawtooth waveform in the range 0 2*PI which must
be locked to the INput signals fundamental. Typically, the PHASE input signal is
obtained from a phaselockedloop (PLL) whose input signals are the bus voltage
or line current corresponding to the INput signal. The PHASE input signals period
defines the fundamental frequency used to compute the DFT. The PHASE input
signal is also used as the phase reference for the DFT function.
The INput signal is sampled N times per fundamental cycle. The first sample is taken
when the PHASE signal falls from its max (~2*PI) value to its min value (~0.0).
Subsequent samples are taken every 2*PI / N radians. Sample instants may be
monitored by specifying Yes for the MONS parameter. In this case a TRIG output
signal becomes available. The TRIG signal is an integer in the range of 1 ... N and
changes value whenever a new sample is taken. The TRIG signal value indicates the
sample number within in the cycle.
3.99
CC BLOCKS
The DFT function requires that more than two samples are taken per cycle for the
frequency which is to be extracted. For example, to extract the fundamental
frequency the number of points per cycle (N Parameter) must be set to 3 or more.
To extract the second harmonic, N must be set to 5 or more.
DFT outputs are updated whenever a new sample is taken. The TRIG signal value
changes whenever a new DFT output is available. DFT outputs may be specified as
An and Bn (real and imaginary components) or alternatively as Cn and Phi
(magnitude and angle). An, Bn and Cn, Phi are related by
Cn= sqrt(An2 + Bn2)
Phi= arctan(Bn/An)
The OUTF parameter is used to specify the DFT output format. If the phase angle
is not required then the OUTF parameter may be set to Cn. This eliminates the
requirement to compute the arctan function and thus reduces the execution time of
the DFT block.
The phase reference parameter PHRF may be set to COS or SIN. If the PHASE input
signal is in phase with the INput signal and the PHRF parameter is set to SIN, then
the An, Bn and Cn, Phi outputs will be as follows for the fundamental
An= MAG of fundamental
Bn= 0.0
Cn= MAG of fundamental
Phi= 0.0
If the INput signal contains a second harmonic component with a magnitude of 0.2
and phase equal to 0.5236 rad (= 30 deg) lagging the fundamental, then the DFT
outputs will be as follows when the 2nd harmonic is selected for the HARM
parameter and the PHRF parameter is set to SIN
An= 0.1732
Bn= 0.1
Cn= 0.2
Phi= 0.5236 rad
See Also:
Execution Time:
An,Bn output: 0.175*N + 0.5 s

Cn,Phi output: 0.175*N + 4.25 s
Cn only output: 0.175*N + 1.1 s
3.100
CC BLOCKS
SIGNAL
PROCESSING
3 Phase
CLASS:
SIGNAL PROCESSING
FUNCTION:
3 Phase to Transformation
RSCAD/Draft ICON:
rtds_sharc_ctl_3PH2AB
ab
B
C
3 + b
Phase
Shift= Lag30
LdLg= b leads a
ab
3 b
Phase
Shift= In Phase
LdLg= b lags a
A
B
+
ab
3
Phase
Shift= Lead30
Description:
Convert a 3 Phase signal to a two phase signal. The a output can be selected to be
in phase with the A input signal, lead the A input signal by 30 deg. or lag the A
input signal by 30 deg. The b output can be set to lead or lag the a output by 90
degrees using the LdLg parameter.
If the Shift parameter is set to In Phase then a will be in phase with A and the
b output in phase with BC.
Outputs are scaled to perunit using the Vrat parameter. To scale the a and b signals
to perunit, the Vrat parameter must be set to the rated line to line voltage of the
A/B/C input. For example, if the A/B/C inputs have a magnitude of 230 kV ll rms
and the Vrat parameter is set to 230.0, then the a and b outputs will have a peak value
of 1.0.
Zero sequence is removed from the a signal using the following relation
Vz= 1/3*(VA+VB+VC)
Va= VAVz
See Also: rtds_sharc_ctl_ABC2DQ0
3.101
CC BLOCKS
3.102
CC BLOCKS
SIGNAL
PROCESSING
3 Phase DQ0
CLASS:
SIGNAL PROCESSING
FUNCTION:
3 Phase to DQ0 Transformation
RSCAD/Draft ICON:
rtds_sharc_ctl_ABC2DQ0
DQ0
B
C
Vd
Vq
ABC
V0
PH
Description:
Convert a 3 Phase rotating vector set to a stationary vector set using Parks
transformation
Ld parameter: Vq lags Vd
Vd
sin(PH)
Vq = 2/3 cos(PH)
V0
1/2
sin(PH120)
cos(PH120)
1/2
sin(PH+120)
cos(PH+120)
1 /2
Va
Vb
Vc
With the Ld parameter set to Vq lags Vd, if PH is fixed at 0.0 and inputs
Va,Vb and Vc are a balanced set of positive sequence signals, the output Vd
will lead Vq by 90 degrees. Vq will be in phase with Va. If PH is changing at
a certain frequency, and Va Vb and Vc inputs are balanced sine waves with
phase of Va slightly greater than PH, then Vd will be slightly less than 1.0 and
Vq will be slightly greater than 0.0.
3.103
CC BLOCKS
Ld parameter: Vq leads Vd
Vd
cos(PH)
Vq = 2/3 sin(PH)
V0
1/2
cos(PH120)
sin(PH120)
1/2
cos(PH+120)
sin(PH+120)
1 /2
Va
Vb
Vc
With the Ld parameter set to Vq leads Vd, if PH is fixed at 0.0 and inputs
Va,Vb and Vc are a balanced set of positive sequence signals, the output Vq
will lead Vd by 90 degrees. Vd will be in phase with Va. If PH is changing at
a certain frequency, and Va Vb and Vc inputs are balanced sine waves with
phase of Va slightly greater than PH, then Vq will be slightly less than 1.0 and
Vd will be slightly greater than 0.0.
The DQ0 quantities may be scaled to Peak or RMS values by setting the Pk
parameter appropriately.
The PH input reference signal is required in radians.
See Also:
rtds_sharc_ctl_DQ02ABC
3.104
CC BLOCKS
SIGNAL
PROCESSING
DQ0 3 Phase
CLASS:
SIGNAL PROCESSING
FUNCTION:
DQ0 to 3 Phase Transformation
RSCAD/Draft ICON:
rtds_sharc_ctl_DQ02ABC
Vd
ABC
Vq
V0
DQ0
PH
Description:
Convert DQ0 components to a 3 Phase rotating vector set using the inverse Parks
transformation
Ld parameter: Vq lags Vd
Va
Vb =
Vc
sin(PH)
cos(PH)
sin(PH120) cos(PH120)
sin(PH+120) cos(PH+120)
1
1
1
Vd
Vq
V0
1
1
1
Vd
Vq
V0
Ld parameter: Vq leads Vd
Va
Vb =
Vc
cos(PH)
sin(PH)
cos(PH120) sin(PH120)
cos(PH+120) sin(PH+120)
The Pk parameter should be set appropriately so that the magnitude of the 3 Phase
vector set is converted with the correct scale.
The PH input signal is the Phase signal (in rad) of the output vector set. PH is in phase
with the A input signal and may be obtained from a PhaseLockedLoop.
3.105
CC BLOCKS
See Also:
rtds_sharc_ctl_3PHDQ
3.106
CC BLOCKS
SIGNAL
PROCESSING
DOWN SAMPLER
CLASS:
SIGNAL PROCESSING
FUNCTION:
Down Sampler
RSCAD/Draft ICON:
rtds_sharc_ctl_SAMPLER
Frac
sampler
sampler
0.8 kHz
Trig = Yes
Intp = No
Trig
0.8 kHz
Trig
Trig = Yes
Intp = Yes
IntpFrac = Yes
Description:
The component samples the input at the specified frequency (SF parameter). The
output value is held until the next sample is taken. The Trig output signal is equal
to 1 only when a sample is taken, otherwise, the Trig output is 0.
When the interpolation option is on (Intp parameter = Yes) the output signal is
computed using linear interpolation between the current value of the input and the
input value 1 simulation timestep previous. The interpolation fractional value can
be output from the sampler (IntpFrac = Yes) this option is enabled for only GPC/PB5.
The Trig output signal may be used as input to other sampled blocks (eg. fir filter,
moving average filter, synchronous counter etc.)
The sampling frequency may not be greater than 1/t (where t is the simulation
timestep).
See Also: synchronous counter, synchronous buffer, fir filter, moving average filter
Execution Time:
Interpolation off 0.45 s

Interpolation on 0.75 s
3.107
CC BLOCKS
SIGNAL
PROCESSING
VAR FREQ SAMPLER
CLASS:
SIGNAL PROCESSING
FUNCTION:
Down Sampler with Variable Sampling Frequency
RSCAD/Draft ICON:
rtds_sharc_ctl_VDSAMP
Frac
sampler
sampler
kHz
Trig
Trig = Yes
Intp = No
kHz
Trig
Trig = Yes
Intp = Yes
IntpFrac = Yes
Description:
The component samples the input at the frequency specified by the signal connected
to the input labeled kHz. The output value is held until the next sample is taken.
The Trig output signal is equal to 1 only when a sample is taken, otherwise, the Trig
output is 0.
When the interpolation option is on (Intp parameter = Yes) the output signal is
computed using linear interpolation between the current value of the input and the
input value 1 simulation timestep previous. The interpolation fractional value can
be output from the sampler (IntpFrac = Yes) this option is enabled for only GPC/PB5.
The Trig output signal may be used as input to other sampled blocks (eg. fir filter,
moving average filter, synchronous counter etc.)
The sampling frequency may not be greater than 1/t (where t is the simulation
timestep).If it is then the input is sampled every timestepand the output signal will
be the same as the input signal.
See Also: synchronous counter, synchronous buffer, fir filter, moving average filter
3.111
CC BLOCKS
MOVING AVERAGE
FILTER
SIGNAL
PROCESSING
CLASS:
SIGNAL PROCESSING
FUNCTION:
Moving Average Filter
RSCAD/Draft ICON:
rtds_sharc_ctl_MAVG
64
Trig
64
Description:
The output is computed as the average of the last N input samples where N is
specified by the user as the number of points to average (parameter Pnts). When
operated without a Trig signal, the input signal is sampled every timestep. With a
Trig signal the input is sampled only when the Trig signal is nonzero.
The circuit diagram representing the blocks operation is shown below.
delay
delay
...
delay
1/pnts
Moving Average Filter circuit
See Also: synchronous counter, synchronous buffer, fir filter, down sampler
Execution Time:
No Trigger Signal 0.65 s

With Trigger Signal 0.825 s
3.108
CC BLOCKS
SYNCHRONOUS
BUFFER
SIGNAL
PROCESSING
CLASS:
SIGNAL PROCESSING
FUNCTION:
Synchronous Buffer
RSCAD/Draft ICON:
rtds_sharc_ctl_SYNBUF
max
Trig
BUF 16
Trig
BUF 16
min
MM= Yes
Description:
The input is sampled and data moved one buffer location to the right only when the
TRIG signal is nonzero. The TRIG signal is typically a one timestep wide pulse.
The number of stages in the buffer is specified by setting the N parameter. The IorF
parameter specifies whether the data path is INT or FLOAT.
Setting the MM parameter to Yes causes two additional outputs to become available.
The maximum and minimum values currently in the buffer are available on the
labelled outputs.
See Also: synchronous counter, down sampler

Execution Time:
MM= No:
MM= Yes
0.8 s
1.1 + N*0.15 s (N= Number of stages)
3.109
CC BLOCKS
SIGNAL
PROCESSING
SAMPLE & HOLD
CLASS:
SIGNAL PROCESSING
FUNCTION:
Sample and Hold
RSCAD/Draft ICON:
rtds_sharc_ctl_SH
S/H
S/H
Description:
The input is sampled and passed through to the output or held depending on the state
of the S/H input. The main data input may be FLOAT of INTEGER but the trigger
S/H input must be INTEGER. The active level for Hold can be specified.
See Also:
3.110
CC BLOCKS
SYNCHRONOUS
COUNTER
SIGNAL
PROCESSING
CLASS:
SIGNAL PROCESSING
FUNCTION:
Synchronous Counter
RSCAD/Draft ICON:
rtds_sharc_ctl_SYNCNT
10
RST
Trig
Synch.
Counter
Synch.
Counter
Trig
Trig
Synch.
Counter
0
rst= Yes
Lim= Fixed
Lim= Variable
Description:
The user may specify the action (increment, decrement or none) separately for an
input signal of 0 and an input signal of 1. The output is only modified when the Trig
signal is nonzero.
The user may optionally specify a reset signal. A non zero value applied to the reset
signal resets the counter output to a specified value (rval parameter). The reset Fixed
or variable limits may also be specified.
Fixed or variable limits may be set (Lim parameter).
See Also: synchronous buffer, down sampler

Execution Time:
0.55 s
if rst=Yes add 0.25 s
if lim= Fixed add 0.4 s
if lim= Variable add 0.5 s
3.111
CC BLOCKS
Pickup & Dropoff

Timer
SIGNAL
PROCESSING
CLASS:
FUNCTION:
RSCAD/Draft ICON:
SIGNAL PROCESSING
Pickup & Dropoff Timer
rtds_sharc_ctl_PUDOT
RST
p/u & d/o
Timer
p/u & d/o

Timer
Trig
rst= No
trg= Yes
rst= No
trg= No
Trig
p/u & d/o

Timer
rst= Yes
trg= Yes
input
Description:
With no trigger signal input (trg parameter = No), the component output goes to 1
(ie. pickup) if the input has been 1 for the amount of time specified by the tpu
parameter. The pickup timer is reset to 0 if the input changes to 0 for one or more
timesteps. The dropoff condition (output changes to 0) is met when the input has
been 0 for the time specified by the tdo parameter.
tpu
output
pickup timer value
1) Pickup timer is reset when input changes to 0

2) Output goes to 1 (pickup) when input has
been 1 for a time specified by tpu.
Component Operation with no trigger input signal
3.112
CC BLOCKS
trig
input
If the trg parameter is set to Yes, the input must be 1 for the number of clock counts
specified by the spu parameter in order for the component output to pickup. Dropout
occurs when the input has been 0 for the number of clock counts specified by the sdo
parameter. Each rising edge on the Trig signal input is one clock count.
spu
output
pickup counter value
1) Pickup counter is reset when input changes to 0

2) Output goes to 1 (pickup) when input has been 1 for
a time specified by spu.
Component Operation with trigger input signal
See Also: synchronous counter

Execution Time:
0.75 s
if rst=Yes add 0.3 s
if trg=Yes add 0.3 s
3.113
CC BLOCKS
SIGNAL
PROCESSING
FIR FILTER
CLASS:
SIGNAL PROCESSING
FUNCTION:
Finite Impulse Response Filter
RSCAD/Draft ICON:
rtds_sharc_ctl_FIR
Trig
FIR 16
Description:
N Stage FIR Filter. The circuit diagram for the block is shown below. Constants A1
... An may be entered by the user or computed as cosine or sine terms (Con
parameter). If a Trig input signal is used, the input is only sampled when the Trig
signal is equal to 1.
delay
delay
A1
A2
...
delay
An1
An
FIR Filter circuit
See Also: down sampler

Execution Time:
0.2+N*0.2 s
N= number of stages in filter
3.114
CC BLOCKS
BUTTERWORTH
BUTTERWORTH
FILTER
FILTER
SIGNAL
PROCESSING
CLASS:
SIGNAL PROCESSING
FUNCTION:
Butterworth Filter
RSCAD/Draft ICON:
rtds_sharc_ctl_BWFILTER
LOWPASS
BUTTERWORTH
FILTER
HIGHPASS
BUTTERWORTH
FILTER
Description:
The Butterworth Filter can be realized as a Lowpass or a Highpass version. It can also
be implemented as a 2nd, 4th, 6th, 8th or 10th order function.
The Lowpass version is given as
A(k) * ( z**2 + 2*z + 1 )
H(z) =
z**2 + B(k)*z + C(k)
The Highpass expression is the same except that the sign on the 2*z term in the
numerator is and not +.
The coefficients for the lowpass filter are computed as follows;
wcp = sin( fc * PI * delt ) / cos( fc * PI * delt )
cosn = cos(( 2.0 * ( k + nsf + 1.0 ) 1.0 ) * PI / ( 4.0 * nsf ))
x = 1.0 / ( 1.0 + wcp * wcp 2.0 * wcp * cosn )
A( k ) = wcp * wcp * x
B(k ) = 2.0 * ( wcp * wcp 1.0 ) * x
C( k ) = ( 1.0 + wcp * wcp + 2.0 * wcp * cosn ) * x
3.115
CC BLOCKS
The coefficients for the highpass filter are computed as follows;
wcp = sin( fc * PI * delt ) / cos( fc * PI * delt )
cosn = cos(( 2.0 * ( k + nsf + 1.0 ) 1.0 ) * PI / ( 4.0 * nsf ))
A( k ) = 1.0 / ( 1.0 + wcp * wcp 2.0 * wcp * cosn )
B( k ) = 2.0 * ( wcp * wcp 1.0 ) * A( k )
C( k ) = ( 1.0 + wcp * wcp + 2.0 * wcp * cosn ) * A( k )
where fc is the cutoff frequency, k is the current section of the filter and nsf is the total
number of sections in the filter.
See Also: Poly3
3.116
CC BLOCKS
SIGNAL
GENERATOR
SOURCE
CLASS:
SIGNAL GENERATOR
FUNCTION:
Sine, Triangle, Sawtooth or Square wave generator
RSCAD/Draft ICON:
rtds_sharc_ctl_SRC
Mag
Mag
(pk)
(pk)
Freq
Freq
(Hz)
(Hz)
Phase
Phase
(rad)
(rad)
WType= Square
WType= Sine
Mag
Mag
(pk)
(pk)
Freq
Freq
(Hz)
(Hz)
Phase
Phase
(rad)
(rad)
WType= SawTooth
WType= Triangle
Description:
The output signal shape is defined by the WType parameter. Signal magnitude (peak
value), frequency (in Hz.) and phase (in radians) may be dynamically modified. A
change in the phase input represents an instantaneous change from the current phase
angle. Positive phase change corresponds to phase advance and negative phase
change to phase retard.
The square wave signal duty cycle is set using the Duty parameter.
See Also:
Execution Time:
WType= Sine 3.0 s

WType= Triangle 1.8 s
WType= SawTooth 1.05 s
WType= Square 0.7 s
3.117
CC BLOCKS
SIGNAL
GENERATOR
FIXED RAMP
CLASS:
SIGNAL GENERATOR
FUNCTION:
Fixed Frequency Ramp Generator
RSCAD/Draft ICON:
rtds_sharc_ctl_ARAMP
Frac
RAMP
2PI
0
Hz= 60.0
RAMP
Trig
RAMP
2PI
0
Hz= 60.0
Intp
Intp = Yes
Description:
The function output is a fixed rate ramp in the range of 0 2PI which can be used
as the phase input for sine wave generation. The output is stationary with respect to
power system source models, as well as, generators running in LOCKED mode. The
output can be phase adjusted by by one or two timesteps (Nadv parameter) in order
to account for timedelays if the phase signal passed to another processor.
When the interpolation option is on (Intp parameter = Yes) the output signal Intp is
computed when the Trig signal is high using the fraction value of the linear
interpolation between the current value of the input and the input value 1 simulation
timestep previous. See rtds_sharc_ctl_SAMPLER. This option is enabled for only
GPC/PB5.
See Also:
3.118
CC BLOCKS
SIGNAL
GENERATOR
VARIABLE RAMP
CLASS:
SIGNAL GENERATOR
FUNCTION:
Variable Frequency Ramp Generator
RSCAD/Draft ICON:
rtds_sharc_ctl_RAMPG
MAX RAMP =
6.283
1
sT
MIN RAMP =
0.0
Description:
The function output is a variable rate ramp with a user specified minimum and
maximum range. The input signal is integrated with a time constant specified by the
T parameter. For example, an input of constant value equal to 2f (f= frequency in
Hz) would produce a ramp which could be used as input to a sine wave generator to
produce a sine wave of f Hz.
See Also:
3.119
CC BLOCKS
SIGNAL
GENERATOR
FIRING PULSE
CLASS:
SIGNAL GENERATOR
FUNCTION:
Firing Pulse Generator
RSCAD/Draft ICON:
rtds_sharc_ctl_FPGEN
FR En
DeBlock
FIRING
PULSE
GENERATOR
FP
DeBlock
FIRING
PULSE
GENERATOR
FP
Phi
(rad)
Lag 30
Phi
(rad)
Lag 30
FLAST
Alpha
(rad)
PW= 120
Alpha
(rad)
PW= 120
FRAC
FRA= No
FRA= Yes
Description:
Function generates a firing pulse signal (FP output) which can be used as input to
power system components such as the HVDC valve group and GTO Bridge. The
INTEGER firing pulse word uses the six lowest order bits to represent firing pulses
for thyristors 1..6 respectively (ie. LSB corresponds to thyristor #1). Firing pulses
may be specified as 120_ or 180_ in length (FPW parameter). A new firing pulse is
generated when the Phase input (Phi) is equal to or exceeds the alpha order input
(Alpha) and the DeBlock signal not equal to logic 0.
Outputs for improved firing (FLAST(INTEGER) & FRAC(REAL) ) are optionally
available by setting the FRA parameter to Yes. Improved firing can also be
dynamically disabled by setting the FR En input (INTEGER) to a value other than
0. In this case the FLAST and FRAC outputs are set to 0.
See Also:
Execution Time: FRA= No 1.675 s
FRA= Yes 3.00 s
3.120
CC BLOCKS
HIGH PRECISION
ANGLE GENERATOR
SIGNAL
GENERATOR
CLASS:
SIGNAL GENERATOR
RSCAD/Draft ICON:
rtds_sharc_ctl_ANGIN
Hz = 60.0
2PI
dW
dW
+
+
1 2PI
s 0
Description:
This component generates an accurate ramp of phase corresponding to the integral
of a selectable frequency base. The output may be advanced by 0, 1 or 2 time steps.
See Also:
3.121
CC BLOCKS
DYLOAD
LOAD
CLASS:
LOAD
COMPONENT:
Load Model
RSCAD/Draft ICON:
rtds_udc_DYLOAD
cc = Slider
Vmeas = Internal
cc = CC
Vmeas = Internal
cc = CC
Vmeas = External
Description:
The load model can be used to dynamically adjust the load to maintain the P & Q set
points. This is achieved using a variable conductance.
Parameters:
3.122
CC BLOCKS
type RL,RC or RX type loads can be modelled. If RX is selected, the load type
will change based on the value of Q. If Q is negative, the load is modelled as an RC
type, if Q is positive, the load is modelled as an RL type load.
btype the load can be modelled as parallel (R//X) or series (RX).
cc with the cc parameter set to Slider, RSCAD/RunTime sliders are available to
set/change the P & Q set points. The RunTime sliders are initialized using the Pinit,
Qinit, Pmin, Pmax, Qmin and Qmax parameters. For example, in RunTime the
power set point slider will have a minimum value of Pmin, a maximum value of Pmax
and an initial value of Pinit. By setting the cc parameter to CC, the P and Q set
points are provided to the Pset and Qset control input wires. In this case the real and
reactive setpoints may be provided from control components such as ZIP or
Exponential load computation blocks (rtds_sharc_ctl_ZIP and rtds_sharc_ctl_ECL
respectively). With the cc parameter set to ConstZ, the load is no longer dynamic
and treated as a constant impedance.
gnd selecting Yes to this parameter enables a neutral point connection as shown
below.
Neutral Connection
If the neutral connection is disabled, the load branch is grounded.

Vmeas with the Vmeas parameter set to Internal, the RMS bus voltage is used
to calculate the load parameters. With the Vmeas parameter set to External, a
control input is required to represent the bus voltage. RMS calculations are intended
for balanced conditions, therefore, if the bus voltage is not balanced, the voltage can
be calculated using controls components. An example is shown below.
In this example, the positive sequence voltage is calculated and applied as input to
the load model. The component named _rtds_PN_SEQ.def is used to calculate the
positive sequence voltage. The output from the sequence component is in real and
3.123
CC BLOCKS
imaginary terms, this is then converted to polar coordinates, converted to a LL
voltage and input to the load component.
Vmin If the bus voltage during the simulation is below this level, the load is not
changed. The impedance of the load is proportional to voltage, so if the voltage is
low the impedance is small. If the load impedance is adjusted to a very small value
the simulation results will not be reasonable. Therefore a minimum voltage must be
specified.
Pinit/Qinit if the real and reactive set points are input using the controls compiler,
the inital control input is not known and the inital set points are set to Pinit and Qinit.
This value is also used by the RSCAD/Draft loadflow program.
See Also: ZIP, ECL
Execution Time:
3PC
GPC
RC (R//X)
6.6
0.26
RC (RX)
6.2
0.25
RL (R//X)
8.4
0.34
RL (RX)
6.4
0.26
RX (R//X)
6.3
0.25
RX (RX)
11.5
0.46
3.124
CC BLOCKS
ZIP
LOAD
CLASS:
LOAD
COMPONENT:
ZIP Calculation
RSCAD/Draft ICON:
rtds_sharc_ctl_ZIP
Pset
Qset
ZIP
Load
Pord
Qord
Description:
The ZIP Calculation Block reads, as input, real and reactive power orders (Pord and
Qord respectively) and computes the corresponding real and reactive power order
setpoints. The setpoint outputs are used as input to the load model
(rtds_udc_DYLOAD). Computations are based on user data representing the
fraction of the load which is constant power (PP, QP parameters), constant
impedance (ZP, ZQ parameters) and constant current (IP, IQ parameters). The sum
PP+ZP+IP and the sum PQ+ZQ+IQ must both equal 1.0.
The ZIP model includes a bus voltage measurement timeconstant (Tf parameter),
as well as, a startup time out. Pset is set equal to Pord and Qset equal to Qord from
simulation start until the simulation time exceeds the time set for the time out (TS
parameter in seconds).
A block diagram showing the component comprising the ZIP load calculation block
is shown below.
See Also: DYLOAD, ECL
Execution Time:
Mon= No 5.975 s
3.125
CC BLOCKS
3.126
CC BLOCKS
ECL
LOAD
CLASS:
LOAD
COMPONENT:
Exponential Coefficient Load Calculation
RSCAD/Draft ICON:
rtds_sharc_ctl_ECL
Pset
Qset
Exponential
Coefficient
Pord
Qord
Description:
The Exponential Coefficient Calculation Block reads, as input, real and reactive
power orders (Pord and Qord respectively) and computes the corresponding real and
reactive power order setpoints. The setpoint outputs are used as input to the load
model (rtds_udc_DYLOAD). Computations are based on the following equations;
Pset= Pord*V/Vo**Kpv * [1.0 + Kpf*(ffo)]

Qset= Qord*V/Vo**Kqv * [1.0 + Kqf*(ffo)]
The ZIP model includes a bus voltage measurement timeconstant (Tf parameter),
as well as, a startup time out. Pset is set equal to Pord and Qset equal to Qord from
simulation start until the simulation time exceeds the time set for the time out (TS
parameter in seconds).
A block diagram showing the component comprising the exponential coefficient
load calculation block is shown below.
See Also: DYLOAD, ZIP
Execution Time:
Mon= No 13.1 s
3.127
CC BLOCKS
3.128
CC BLOCKS
STOP
MISC
CLASS:
MISCELLANEOUS
FUNCTION:
Simulator Stop Function
RSCAD/Draft ICON:
rtds_sharc_ctl_HALT
STOP
Description:
An INTEGER input other than 0 will cause the simulation case to stop running.
RSCAD/RunTime will display the message USER SPECIFIED HALT
CONDITION if the function detects a non zero input. The function works by
entering an infinite loop when the input is nonzero which forces a timestep
overflow. Upon detecting a timestep overflow, the WIF card in each RTDS rack
participating in the simulation will set the front panel analogue output channels to
0.
See Also:
3.129
CC BLOCKS
PLOT UPDATE
MISC
CLASS:
MISCELLANEOUS
FUNCTION:
RSCAD/RunTime Plot Update
RSCAD/Draft ICON:
rtds_sharc_ctl_PLOT_UPDATE
Description:
An INTEGER transition from 0 to 1 will cause the RSCAD/RunTime plots to update
if this icon is included in an RSCAD/DRAFT case. For this function to operate, the
external plot update feature must be enabled in RSCAD/RunTime by selecting the
Arm External Update button. The button may be selected a second time to Disarm
the External Update.
Only 1 PLOT_UPDATE component may be allocated in each subsystem.
RSCAD/RunTime
Arm External Plot Update

Digital Input Port
or DOPTO
See Also:
3.130
CC BLOCKS
SET FLAG 0
MISC
CLASS:
MISCELLANEOUS
FUNCTION:
SET T0 Flag (PRIORITY Assignment Mode)
PSCAD/Draft ICON:
rtds_sharc_ctl_SETFLAG
SET
FLAG 0
Description:
The Set Flag 0 block is used to force a processor to participate in the T0
communications interval. This block should only be used if the controls assignment
mode is set to PRIORITY. In AUTOMATIC mode the rtds_sharc_ctl_SENDT0
component should be used.
Any control components assigned to the same processor as the Set Flag 0 component
an which have been assigned a priority value higher than the Set Flag 0 component
will be executed after the T0 communication interval. Control function blocks
executed after T0 will have access to any power system variables passed during the
T0 communication interval. This feature is used to avoid a timestep delay for time
critical signals.
A separate Set Flag 0 component may be used for each controls processor that is
required to participate in the T0 communications interval.
The Figure below illustrates an example where a controls processor needs time
critical signal T0VAR as input to a 1/X block. The T0VAR variable is produced by
a power system model running on its own processor. The power system processor
passes the T0VAR during the T0 communications interval. By using the Set Flag 0
block with a priority value less than the 1/X block the controls processor will wait
until after the T0 communications interval has occurred before executing the 1/X
block. When the 1/X block is executed the value of T0VAR computed by the power
system component during the StartT0portion of the code is available to the controls
processor. If the Set Flag 0 block were not used in this instance, input to the 1/X block
would be the value of T0VAR computed during the previous timestep.
The user does not need to include any Set Flag 2 blocks since all processors
participate in the T2 communication interval by default.
The MAP file entry for each controls processor lists all control system function
blocks which will be executed by that processor in the order in which they are
executed. The Set Flag 0 block is included in the list. All blocks listed after the Set
Flag 0 block will be executed after the T0 communication interval.
3.131
CC BLOCKS
Order Mode = PRIORITY
|X|
5.0
Proc= 1
Pri=10
Proc= 1
Pri=20
SET
FLAG 0
Proc= 1
Pri=40
T0VAR
1
X
TOVAR from
power sysetem
model
Proc= 1
Pri=50
Proc #1
Controls
|X| Block
Start T0
Gain *5 Block
Set Flag 0
WAIT
Proc #N
(produces T0VAR)
Execute
Power System
Code
T0VAR
Set Flag 0
...
timestep
S3
T0 communication interval
T0VAR
available
T0 T2
1/X Block
Set Flag 2
WAIT
See Also: rtds_sharc_ctl_SENDT0

3.132
CC BLOCKS
SENDT0
MISC
CLASS:
MISCELLANEOUS
FUNCTION:
SET T0 Flag (AUTO Assignment Mode)
PSCAD/Draft ICON:
rtds_sharc_ctl_SENDT0
TOVAR
Description:
The SENDT0 component is used to force controls processors to participate in the T0
communication interval when the controls assignment mode is set to AUTO. The
PSCAD/Draft software will automatically place the Set Flag 0 code block where
necessary during the COMPILE procedure.
The SENDT0 component should be attached to a wire which represents a variable
which is transferred during the T0 communication interval. Any control components
which need to be executed prior to the communication of the T0 variable will be
assigned to do so automatically. Control function blocks which need the T0 variable
as input will be assigned after the T0 communication interval.
3.133
CC BLOCKS
Order Mode = PRIORITY

TOVAR
|X|
5.0
Proc= 1
Pri=1
Proc= 1
Pri=1
1
X
S3
Proc= 2
Pri=1
Proc #1
Controls
|X| Block
Start T0
Gain *5 Block
Set Flag 0
WAIT
Proc #N
(produces T0VAR)
Execute
Power System
Code
T0VAR
Set Flag 0
...
timestep
T0VAR
available
T0 T2
1/X Block
Set Flag 2
WAIT
See Also: rtds_sharc_ctl_SENDT0

3.134
CC BLOCKS
PST
MISC
CLASS:
MISCELLANEOUS
FUNCTION:
STATISTICAL EVALUATION
PSCAD/Draft ICON:
rtds_sharc_ctl_PST
Blk5IP
PST
PST
ClkRst
Clk
Description;
The PST block is a flicker evaluation function, as defined in Flicker Measurement
and Evaluation, a publication of the UIE International Union for Electroheat. The
UIE document describes the calculation of the probability of flicker perceptibility,
based on instantaneous flicker levels, gathered over a period of 10 minutes. The PST
model sums the time spent at each of 64 equally spaced levels of instantaneous flicker
and computes a Cumulative Probability Function (CPF) in each time step. CPF
curves are then reduced to a single value, Pst, by use of the following formula;
Pst = k1p1 + k2p2 + . + k5p5

where the k# are weighting coefficients and the p# are CPF levels with an assigned
probability of being exceeded. For example, p1 could be the instantaneous flicker
level exceed by only 1% of the observation period. The actual p levels and k# are
specified by the UIE document.
The model should be run in its own controls processor, as it is long. The clock reset
input should be toggelled at the start of the test to reset the CPF curve and the input
then entered over a 10 minute interval. The maximum expected instantaneous input
should also be entered into the parameter menu to provide a good distribution for the
CPF curve to accurately compute all the P values.
3.135
CC BLOCKS
MISC
CAPTURE
CLASS:
MISCELLANEOUS
FUNCTION:
CAPTURE SIMULATION OUTPUT
RSCAD/Draft ICON:
rtds_risc_ctl_CAPTURE2
Description:
This component captures and stores a specified amount of simulation output. The
number of points to be captured and the time step number to begin the capture are
assigned as component parameters. After capturing and storing the simulation output
for the specified number of time steps, the stored data and time step index are
repeated. The following figure shows an example for the operation of this model.
The plot named Output shows the repetition of the captured data and the plot named
Index shows the time step when the corresponding data was captured.
Execution Time:
130nS
78nS
(RPC)
(GPC)
3.136
CC BLOCKS
MISC
MPPT
CLASS:
MISCELLANEOUS
FUNCTION:
Maximum Power Point Tracking (MPPT) Model
RSCAD/Draft ICON:
_rtds_MPPT.def
1. INTRODUCTION
The energy production of the solar generation system can be increased in two ways;
one is to build a larger Photo Voltaic (PV) array generation system and the other is
to achieve higher efficiency in converting incident solar energy into electrical energy.
Once the construction of the generation system has been completed, the only viable
solution is to maximize the conversion efficiency. The output of PV array generation
system depends upon factors such as sun light intensity (insolation), ambient
temperature, solar cell parameters and/or the arrays configuration; each of these
factors is either a fixed or natural condition and thus generally cannot be controlled.
Consequently, extracting the largest amount of power under a certain given set of
operating conditions becomes very important for the total economics of the PV
generation system.
For an arbitrary PV array configuration and set of operating conditions, it is possible
to plot an IV curve showing the arrays output current as a function of its output
voltage. The arrays PV curve, which shows the output power as a function of the
output voltage, can be superimposed on the same diagram. Figure 1A shows two
such curves for an arbitrary operating condition; the solid line shows the IV curve
of a PV array while the dotted line shows the power output of that same array. The
small square dot marked on the PV curve is known as the Maximum Power Point
(MPP) and it represents the maximum power that can be delivered by the PV array
under a specific set of operating conditions.
3.137
CC BLOCKS
Figure 1: (A) IV and PV characteristics of a PV array for an arbitrary operating point. (B)
Illustration of how the PV characteristic changes with operating point.
The purpose of the Maximum Power Point Tracking (MPPT) model is to follow the
MPP as it changes with the ambient operating conditions of the PV generation system
(temperature and the insolation level). In order to do such tracking the terminal
voltage of the PV array is manipulated. Consider Figure 1B, the MPP tracker would
be responsible for changing the terminal voltage of the array so that it operates at
MPP1, MPP2, MPP3 or MPP4 depending on if the ambient temperature is 75C,
50C, 25C or 0C respectively.
Many algorithms have been proposed for the MPPT application. Some widely
adopted algorithms include: the Constant Voltage Method, the NonLinearFunction
Solution Method, the Perturbation & Observation or Hill Climbing Method and the
Incremental Conductance Method. The RTDS MPPT model implementation is
based on the Incremental Conductance Method algorithm because it is widely
accepted as being efficient without incurring excessive computational burdens.
2. BACKGROUND
Incremental Conductance Method Algorithm
The Incremental Conductance Method is based upon the Hill Climbing Method
(Perturbation & Observation Method). A slight augmentation to this algorithm,
which makes it slightly more robust, results in what is know as the Incremental
Conductance Method.
3.138
CC BLOCKS
Figure 2: PV characteristic and various operating points near the MPP.
Details of the Perturbation & Observation algorithm are best explained using an
example. Figure 2 shows an arbitrary PV curve where the horizontal axis is the PV
array terminal voltage, V, and the vertical axis is the arrays output power, P. When
the array is operating at the MPP, dP = 0 therefore the objective of the MPPT
dv
algorithm is to seek the point where the dP value becomes zero. The PV Arrays
dV
terminal voltage should be increased if dP is positive; conversely the terminal
dV
dP
is negative.
voltage should be decreased if
dV
Assume first that the algorithm, through modification of a reference value, has just
triggered an increase in the arrays terminal from V1 to V2. The resulting difference
in the output power (dP = P2 P1) is positive so the algorithm should continue to
increase the terminal voltage beyond V2 to V3. Again, the resulting difference in
output power (dP = P3 P2) is positive and thus the algorithm will again trigger an
increase the terminal voltage beyond V3 to V4. Now the difference in output power
(dP = P4 P3) is negative and so the direction of movement in the terminal voltage
reference is reversed and the terminal voltage is next moved from V4 back to V3.
The resulting difference in P (dP = P3 P4) is negative so the terminal voltage will
be further decreased to from V3 to V2. Now the difference in P (dP = P2 P3) is again
negative so this signals that the direction in which the terminal voltage is moved
should be reversed. The algorithm continues in a like fashion reversing directions
every time the machine output power decreases; this implies that the algorithm, after
having approached the MPP, will constantly fluctuate around it by a small amount.
3.139
CC BLOCKS
The Hill Climbing Algorithm can be summarized as follows:
Recall that our objective is to track the MPP given the current operating conditions
of the PV array. The expression dP = 0 is very useful in this regard. As a first step
dV
dP
in terms of voltages and currents, the two quantities that are
it is useful to write
dV
typically metered at terminals of a PV array.

dP = d(V I) = V dI + I
dV
dV
dV
Eq. 1
A mathematically equivalent method of expressing dP/dV = 0 can then be derived

as shown below.
V dI + I = 0
dV
Eq. 2
Approximating dI and dV by i(t) i(t t) and v(t) vi(t t) respectively we can

approximate Equation 2 as follows:
i(t)
i(t) i(t t)
=
v(t)
v(t) v(t t)
Eq. 3
Equation 3 will be satisfied if we are operating at the MPP where dP = 0 . Similarly,

we can find equivalent expressions for dP < 0 and dP > 0 .
dV
dV
dV
i(t)
i(t) i(t t)
<
v(t)
v(t) v(t t)
Eq. 4
i(t) i(t t)
i(t)
>
v(t) v(t t)
v(t)
Eq. 5
and
The Incremental Conductance Method adds to the Hill Climbing method described
above by making provisions for when the sampled voltage doesnt change from one
sample to another. Such a situation can arise, for example, under rapidly changing
environmental conditions which trigger a change in the operating PV characteristic
of the array. Under such a situation the above method would fail since equations 46
would result in a division by zero.
If we begin again with Equation 1 and proceed by multiplying both sides of the
equation by dV, we get:
3.140
CC BLOCKS
dP = V dI + I dV
Eq. 6
when the voltage is unchanged from sample to the next ( dV = 0 ) Equation 6

simplifies to Equation 7.
dP = V dI
Eq. 7
From this equation we can deduce that an increase in output power P, when V is both
positive and constant will be accompanied by an increase in the output current of the
array. Similarly, a decrease in P will be accompanied by a decrease in I. This
realization enables us to continue moving towards the MPP even when the terminal
voltage is constant from one sampling period to the next.
The flowchart of Figure 3 summarizes the discussion above and shows how the
incremental conductance algorithm works.
Figure 3: Flow chart of the incremental conductance algorithm
Algorithm Startup:
One of the difficulties of the Incremental Conductance MPPT algorithm lies is
determining an initial value for the reference voltage, Vref, so that it corresponds with
3.141
CC BLOCKS
the actual terminal voltage of the PV array. Ensuring that the reference and actual
values are similar helps to avoid any large transients in the PV array terminal voltage
when the algorithm starts.
The RTDS MPPT model addresses this issue by having an initial waiting period
during which its output should not be used and during which the model runs a moving
average algorithm on its input voltage. Once this waiting period is over, the result
of the average is used as the initial reference voltage for the algorithm.
Inputs and Outputs of the model:
The inputs of the MPPT component are the PV Arrays terminal voltage and its
terminal current. The outputs of the component are a voltage reference signal and a
status signal indicating the state of the algorithm.
The voltage reference output is often used as an input to a regulator which in turn
controls the duty ratio of a DC/DC converter. DC/DC converters are one of the most
common methods to match the output voltage of PV array with the required network
voltage. This is especially true when the size of the generation is large and a two stage
approach (DC/DC converter and DC/AC converter) is employed. Since the voltage
reference signals is only valid after the waiting period, it is important to have an
output that indicates when this waiting period has passed. The components state
output will have a value of 0 if the initial waiting period has not yet passed and it will
change to 1 when the waiting period is over. The state output is useful for creating
a logic circuit which determines when it is safe to pass the voltage reference signal
to the DC/DC converters regulator.
3. CONFIGURATION
strtup The duration of the initial waiting period during which a moving average
of the input voltage is calculated in order to determine a starting point for voltage
3.142
CC BLOCKS
reference value. The reference signal should not be used before this waiting period
has passed.
samp The sampling period determines the frequency with which the MPPT
algorithm is executed.
vstep This parameter controls the step size of the voltage reference signal
increments. A large step means that the algorithm will quickly track changes in the
MPP but that the sustained oscillations about the MPP will be larger. Conversely,
a small step entails slower tracking of changes but smaller sustained oscillations
about the MPP.
rst This parameter is used to enable an optional external control input which can
be used to trigger a reset of the MPPT algorithm. When the signal connected to the
aforementioned input undergoes a transition from 0 > 1, the algorithm is reset and
the startup process whereby the input voltage has a moving average applied to it is
reexecuted.
4. REFERENCES
[1] Development of a Dynamic Test Module for Testing Grid Interface of
Renewable Energy Resource Generation, 2006, KERI (Korea)
3.143
Rev. 05: April. 12
GENERATOR CONTROLS
(PSS, AVR, GOV)
A library of predefined generator control blocks is available. The Generator

Controls library contains IEEE Standard power system stabilizer (PSS) models,
automatic voltage regulator models (AVR) and speed governor (GOV) models.
Speed governor models also include representation of the associated turbine.
References, listed at the end of this Section, provide additional information
regarding the representation of the various generator control models.
Upon starting RSCAD/Draft, the Generator Controls library tab will appear in the
library.
Select
4.1 CONNECTION OF GENERATOR CONTROLS TO RTDS GENERATOR MODEL

Connection of the various generator control models available in the library to the
RTDS generator model is done in a similar matter for each type of controller. The
two Figures below illustrate the connection of generator controls to the RTDS
generator model. The generator model produces as output the generator speed (w
in rad/sec), and the field current (If in perunit). Generator required inputs are
mechanical torque (Tm in perunit) obtained from the GOV model and field voltage
(Ef in perunit) obtained from the AVR model. Note that the AVR model accepts
perunit value (Vpu) and includes the option to include load compensation. When
load compensation is included in the AVR model, a load compensator model is used
to provide a compensated voltage as input to the AVR model. The PSS models
stabilizer signal output is used as input by the AVR model. The PSS requires the
generator speed (w in rad/sec) and electrical power (Pe in MW) as inputs.
Each of the generator control models connected to a particular generator must be
assigned the same name (Gen parameter in the PSS, AVR and GOV models) as that
assigned to the generator model.
RTDS
Technologies
4.1
WM1
0.0
Pe
PSS Model
IEE2ST
PSS
Vs
M1
M1
IEEE Type AC1
Excitation
System
Vc
Vs
Ef
If
Vpu
EF
IF
M1
AVR Model
(Include load compensation = Yes)
Load Compensation Model
IEEEVC
|Vt + (Rc+jXc)*It|
Vpu
TMVA = 100.0
13.8
230.0
A
B
SHARC
W
TM
Tm
Steam Turbine
Governor
LAGS
GOV Model
M1
Connection of Generator Control Components

to the lf_rtds_sharc_sld_MACV31 Model
(Generator vtcc parameter = Yes)
RTDS
Technologies
4.2
WM1
0.0
Pe
PSS Model
IEE2ST
PSS
M1
Vs
M1
IEEE Type AC1
Excitation
System
AVR Model
(Include load compensation = No)
Vs
Ef
If
EF
IF
M1
Vpu
VMPU
TMVA = 100.0
13.8
230.0
A
B
SHARC
W
TM
Tm
Steam Turbine
Governor
LAGS
GOV Model
M1
Connection of Generator Control Components

to the lf_rtds_sharc_sld_MACV31 Model
(Generator vtcc parameter = Yes)
RTDS
Technologies
4.3
4.2 AUTOMATIC INITIALIZATION

Generator control models contained in the Generator Controls library include the
capability to initialize their internal variables and to configure setpoint sliders
available in RSCAD/RunTime. Such initialization ensures that when the simulation
case is started long time constants associated with any of the generator controls will
not cause a significant startup transient. The generator initial load flow data, real and
reactive power and terminal voltage magnitude and angle, are used to compute the
initial field voltage and mechanical torque. These computed values are available to
the generator control models at compile time. Given the initial field voltage Ef, the
initial terminal voltage (Vi parameter) and the various gains of the AVR components
it is possible to compute the initial inputs and outputs associated with each block.
As an example consider the circuit below. Note that all of the blocks initial input
and output values can be computed given the initial field voltage (Ef) and terminal
voltage (Vpu), when load compensation is included the initialization is carried out
using the compensated voltage (Vc). The initial value of the setpoint slider (Vset)
can also be computed.
max
+
Err
V1
G
1 + sT
V2
1 + sTa
1 + sTb
Ef
Vset
Vpu/Vc
1.0
1 + sT
Ef:
Vpu/Vc
Vfb
V2
V1
Err
Vf
Vset
Vfb
Vf
min
G sT
1 + sT
Initial field voltage from generator model (known)

Initial terminal voltage/compensated voltage (known)
0.0 in steadystate
equal to Ef in steadystate
equal to V2/G in steadystate
equal to V1 + Vfb in steadystate
equal to Vpu in steadystate
equal to Err+Vf to satisfy initial conditions
A warning message is issued at compile time if any blocks computed initial output
value exceeds limits associated with that block. If such a warning message occurs
it means that the computed initial condition for the power system cannot be met given
the controllers parameters.
RTDS
Technologies
4.4
4.3 INTERNAL VARIABLE MONITORING

Each generator controller includes an option to monitor an internal variable (Mon
parameter). If the Mon parameter is set to Yes the user can assign a signal name
to the internal variable. This signal name is available for selection under the
associated generator name when creating a plot or meter in RSCAD/RunTime. For
example, to monitor internal variable named test for an AVR associated with a
generator named M1 in subsystem #1 make the following selection in
RSCAD/RunTime
A dial component is available in RSCAD/RunTime for each monitored variable.

Shown in the block diagrams for each controller are the internal variables. Internal
variables available for monitoring are identified with a MON# wire label where the
# corresponds to the DIAL position. The Dial component is selected in the same way
as the meter component illustrated above. Changing the DIAL setting in
RSCAD/RunTime changes the internal variable which is monitored.
Generator control block diagrams are shown in section 4.5 and also available by
selecting Help from the component menu in RSCAD/Draft.
RTDS
Technologies
4.5
4.4 RSCAD/RUNTIME COMPONENTS

For each generator controller the user is able to create various input components (eg.
Switch, Slider etc.) in RSCAD/RunTime. Input components available for the
various controller types include
PSS:
AVR:
On/Off Switch
SetPoint Slider
Mode Switch (some models)
GOV:
Power Order or W order SetPoint
Generator controller input components can be chosen by selecting the

Subsystem #>CTLs>Inputs
section in RSCAD/RunTime.
RTDS
Technologies
4.6
4.5 BLOCK DIAGRAMS

Block diagrams for each controller are shown in this section. Internal variables
available for monitoring are identified with a MON# wire label where the #
corresponds to the DIAL position required to monitor that variable. The
RSCAD/Draft DIAL component allows for 20 unique positions. For generator
controllers which have less than or equal to 20 internal points, the DIAL component
is initialized with each output assigned a corresponding DIAL position (ie. DIAL
position #1 produces as output mon1, position #2 produces as output mon2 etc.) For
generator controllers which have more than 20 monitored points the DIAL
component will not have unique positions but will be displayed as a circular bar as
shown below. In this case, the dial position is changed by clicking on the right side
of the dial. For example, to have the MON variable display the signal labelled mon21
in the PIDGOV governor model. Click on right side of the DIAL component until
21 is displayed. With the dial in this position, mon21 signal is monitored.
DIAL
output value
Position Values are

defined here
RTDS
Technologies
4.7
The following references should be consulted to obtain detailed information

regarding the structure and valid data ranges for the parameters of the generator
control blocks listed here.
[1] Kundur, Prabha Power System Stability and Control 1994 McGrawHill.
Chapter 8: Excitation Systems and Chapter 9: Prime Movers and Energy Supply
Systems.
[2] IEEE Committee Report Dynamic Models for Steam and Hydro Turbines in
Power System Studies, IEEE Transactions on Power Apparatus and Systems, Vol.
PAS92, No. 6, Nov/Dec 1973. pp 19041915.
[3] IEEE Working Group on Prime Movers, Hydraulic Turbine and Turbine Control
Models for System Dynamic Studies. IEEE Transactions on Power Systems, Vol.
7, No. 1, February 1992. pp. 167179.
[4] IEEE Working Group on Prime Mover and Energy Supply. Dynamic Models for
Fossil Fueled Steam Units in Power System Studies. IEEE Transactions on Power
Systems, Vol. 6, No. 2, May 1991. pp. 753761.
[5] IEEE Committee Report: Excitation System Models for Power System Stability
Studies. IEEE Transactions on Power Apparatus and Systems, Vol. PAS100, No.
2, February 1981. pp. 494509.
[6] Computer Models for Representation of DigitalBased Excitation Systems,
Digital Excitation Task Force, IEEE Transactions on Energy Conversion, Vol. 11,
No. 3, September 1996. pp 607613.
[7] A New Thermal Governor Modeling Approach in the WECC, IEEE Transactions
on Power Systems, Vol. 18, No. 2, May 2003, p. 819829
RTDS
Technologies
4.8
IEE2ST
PSS
CLASS:
PSS
COMPONENT:
IEEE Type 2 Stabilizer
RSCAD/Draft ICON:
_rtds_IEE2ST
Pe
IEE2ST
PSS
Vs
M1
Vpu
Description:
Dual Input stabilizer with bus voltage based output limiter. The bus voltage output
limiter is enabled if either Vcu or Vcl are entered as nonzero. The Vpu bus voltage
signal is connected to the IEE2ST component. When the bus voltage signal is outside
the range specified by Vcu, Vcl the stabilizer output is set to 0.0.
See Also: IEEEST, PSS2A
RTDS
Technologies
4.9
RTDS
Technologies
IEE2ST
PSS
1.0
mon1
K1
w in rad/sec
1 + sT1
1/wo
+
+
P
P in MW
K2
1/MVA
1 + sT2
mon2
on
off
Lsmax
sT3
mon3
1 + sT4
1 + sT5
mon4
1 + sT6
1 + sT9
1 + sT7
mon5
1 + sT8
mon6
1 + sT10
VCU
VPU
VCL
mon7
Lsmin
mon8
LL < A < UL
Y= 1.0
Else
Y= 0.0
EndIf
PSS
mon10
VS
mon9
IEE2ST
Stabilizer
4.10
IEEEST
PSS
CLASS:
PSS
COMPONENT:
IEEE Type ST Stabilizer
RSCAD/Draft ICON:
_rtds_IEEEST
W
IEEEST
PSS
Vs
M1
Vpu
IC = w
Description:
Single input stabilize with second order input filter and terminal voltage based output
limiter. Input to the stabilize is one of the following signals
w
generator speed in rad/sec
df
bus frequency deviation in pu
Pe
Generator electrical power in MW
Pa
Accelerating power in pu
Vb
Bus Voltage in pu
dVb
Bus Voltage deviation in pu
See Also: IEE2ST, PSS2A
RTDS
Technologies
4.11
RTDS
Technologies
IEEEST
PSS
on
off
Lsmax
mon1
1 + A5s + A6s2
1 + sT1
1 + sT3
1 + A1s + A2s2
1 + A3s + A4s2
1 + sT2
1 + sT4
mon2
Polynomial 1
mon3
mon4
Ks * sT5
mon5
1 + sT6
VCU
VPU
1.0
w in rad/sec
W
1/wo
1/MVA
Sig
1.0
mon7
mon8
VS
Lsmin
Polynomial 2
IC= w
mon6
PSS
VCL
LL < A < UL
Y= 1.0
Else
Y= 0.0
EndIf
mon9
mon1
IC= Pe
P in MW
IC= df, Pa, Vb or dVb

sig in pu
mon1
mon1
IEEEST
Stabilizer
4.12
PSS2A
PSS
CLASS:
PSS
COMPONENT:
2 Input Stabilizer with ramp tracking filter
RSCAD/Draft ICON:
_rtds_PSS2A
Pe
PSS2A
PSS
Vs
M1
Description:
2 Input stabilizer with ramp tracking filter. The theory of operation of the PSS2A
stabilizer model is given in the papers
Lee D.C., Beaulieu R.E., Service J.R.R, A Power System Stabilizer using Speed and
Electrical Power Inputs Design and Field Experience, IEEE Transactions on
Power Apparatus and Systems, Vol. PAS100, No. 9, September 1981. pp.
41514157.
Berube, G.R., Hajagos L.M., Beaulieu R.E., Practical Utility Experience with
Application of Power System Stabilizers. Presented at the IEEE Working Group
Panel Presentation on Power System Stabilizers, July 1999.
See Also: IEEEST, IEE2ST
RTDS
Technologies
4.13
RTDS
Technologies
PSS2A
PSS
1.0
w in rad/sec
W
+
1/wo
mon2
mon3
sTw1
mon4
sTw2
mon11
1 + sT6
1 + sTw2
1 + sTw1
mon5
mon10
mon1
+
+
1+sT8
(1 + sT9)M
KS3
ramp tracking
filter
mon12
P
P in MW
1/MVA
mon6
mon7
sTw3
mon8
sTw4
1 + sT7
1 + sTw4
1 + sTw3
KS2
mon9
VSTmax
mon13
1 + sT1
KS1
mon14
1 + sT2
1 + sT3
mon15
1 + sT4
mon16
VSTmin
mon17
on
off
PSS
VS
PSS2A
Stabilizer
4.14
PSS2Ax
PSS
CLASS:
PSS
COMPONENT:
2 Input Stabilizer with ramp tracking filter
RSCAD/Draft ICON:
_rtds_PSS2Ax
Pe
PSS2A
PSS
Vs
M1
Description:
2 Input stabilizer with ramp tracking filter with additional gain ks4 and lead lag block
with parameters a, Ta, Tb. The theory of operation of the PSS2A stabilizer model
is given in the papers.
Lee D.C., Beaulieu R.E., Service J.R.R, A Power System Stabilizer using Speed and
Electrical Power Inputs Design and Field Experience, IEEE Transactions on
Power Apparatus and Systems, Vol. PAS100, No. 9, September 1981. pp.
41514157.
Berube, G.R., Hajagos L.M., Beaulieu R.E., Practical Utility Experience with
Application of Power System Stabilizers. Presented at the IEEE Working Group
Panel Presentation on Power System Stabilizers, July 1999.
See Also: IEEEST, IEE2ST
RTDS
Technologies
4.15
RTDS
Technologies
PSS2Ax
PSS2Ax
PSS
1.0
w in rad/sec
W
+
1/wo
mon2
mon3
sTw1
mon4
sTw2
mon11
1 + sT6
1 + sTw2
1 + sTw1
mon5
+
+
mon10
mon1
1+sT8
mon12
(1 + sT9)M
KS4
KS3
ramp tracking
filter
P
P in MW
1/MVA
mon6
mon7
sTw3
mon8
sTw4
1 + sT7
1 + sTw4
1 + sTw3
KS2
mon9
VSTmax
mon13
1 + sT1
KS1
mon14
1 + sT2
1 + sT3
mon15
1 + sT4
a(1 + sTa/a)
mon161 + sTb
mon17
VSTmin
mon18
on
off
PSS
VS
PSS2Ax
Stabilizer
4.16
PSS
PSS
STAB2A
STAB2A
CLASS:
PSS
COMPONENT:
STAB2A Stabilizer System
RSCAD/Draft ICON:
_rtds_STAB2A.def
Description:
Pe
STAB2A
PSS
Vs
M1
STAB2A Single Input Stabilizer
Power Sensitive Stabilizing Unit.
RTDS
Technologies
4.17
RTDS
Technologies
PSS
STAB2A
STAB2A
K3
P
P in MW
1/MVA
mon1
K2sT2
(1 + sT2)
mon3
mon5
1 + sT3
1
+
+
mon7
mon4
K4
K5
(1 + sT5)
on
off
HLim
mon9
PSS
VS
mon10
HLim
mon6
STAB2A
Stabilizer
4.18
PSS1A
PSS
CLASS:
PSS
COMPONENT:
IEEE Type PSS1A
RSCAD/Draft ICON:
_rtds_PSS1A
Pe
IEEE PSS1A
PSS
Vs
M1
IC = Pe
Description:
Single input stabilizer. Input to the stabilizer is one of the following signals
w
Generator speed in rad/sec
Pe
F
Pa
|V|
|I|
Generator electrical power in MW

Bus frequency in Hz.
Accelerating power in pu
Amplitude of bus voltage
Amplitude of branch current
Common stabilizer input signals are speed, frequency and power. The remote bus
number, k, is fixed at zero where the signal is taken from the terminal of the generator
on which the stabilizer is located. The stabilizer output is removed if the generator
terminal voltage deviates outside the Vcu and Vcl limits as specified in the output
limiter.
RTDS
Technologies
4.19
RTDS
Technologies
PSS1A
PSS
on
off
Vrmax
1
mon2
1 + sT6
mon3
Ks
sT5
1 + sT5
mon4
1 + sT1
1+sT3
1 + A1s + A2s2
1 + sT2
1 + sT4
mon5
mon6
mon7
mon8
PSS
mon10
VS
Vrmin
VCU
IC= w
VPU
IC= F
1.0
1.0
w in rad/sec
W
1/wo
mon2
F in Hz
1/Fo
mon1
VCL
mon2
LL < A < UL
Y= 1.0
Else
Y= 0.0
EndIf
mon9
Output Limiter
mon1
IC= Pe
P
1/MVA
P in MW
IC= Pa
Pa
Pa in pu
1.0
mon2
mon2
PSS1A
Stabilizer
4.20
EXAC1
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type AC1 Excitation System
RSCAD/Draft ICON:
_rtds_EXAC1
M1
M1
IEEE Type AC1

Excitation
System
IEEE Type AC1

Excitation
System
Vc
Vs
Ef
If Vpu
Ef
If
Vpu
LDComp = No
PSS= No
LDComp = Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
Exciter AC1 models an AC alternator based exciter with an uncontrolled rectifier
bridge. The Westinghouse Brushless Excitation system has such characteristics.
Since the rectifier is uncontrolled field voltage is adjusted using the alternator output.
Saturation of the AC alternator is modelled using the SE block and the rectifiers
commutation drop is modelled using the FEX block. The uncontrolled rectifier
output is lower limited to zero volts.
See Also: EXAC1A, EXAC2, EXAC3, EXAC4
RTDS
Technologies
4.21
RTDS
Technologies
EXAC1
AVR
Vref
VSIG
VRmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
1 + sTc
1 + sTb
999.0
Ka
mon5
1 + sTa
mon6
+
mon7
VRmin
Te
X(t) dt
mon8
Efield
0.0
mon10
sKf
mon12
1 + sTf
mon15
+
+ mon13
SE
Kc
mon14
X
/
mon11
Kd
If SpdMult equals
Yes then output
multiplied by pu
generator speed Efield
VSIG = VS + VUEL + VOEL
X/Y
mon9
FEX
Ifield
wpu
Efield*wpu
EXAC1
Excitation System
4.22
EXAC1A
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type AC1A Excitation System
RSCAD/Draft ICON:
_rtds_EXAC1A
M1
M1
IEEE Type AC1A

Excitation
System
IEEE Type AC1A

Excitation
System
Vc
Vs
Ef
If Vpu
Ef
If
Vpu
LDComp = No
PSS= No
LDComp = Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
Exciter EXAC1A is virtually the same as EXAC1 except for the location of the input
to the transient gain reduction in the feedback path.
See Also: EXAC1
RTDS
Technologies
4.23
RTDS
Technologies
EXAC1A
AVR
Vref
VSIG
VRmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
1 + sTc
Ka
1 + sTb
1 + sTa
mon5
999.0
mon6
1
Te
mon7
VRmin
X(t) dt
mon8
Efield
0.0
mon10
sKf
mon12
1 + sTf
mon15
+
+
SE
mon13
Kc
X
mon11
Kd
mon14
If SpdMult equals
Yes then output
multiplied by pu
X/Y
mon9
FEX
Ifield
wpu
Efield*wpu
EXAC1A
Excitation System
4.24
EXAC2
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_EXAC2
M1
M1
IEEE Type AC2

Excitation
System
IEEE Type AC2

Excitation
System
Vc
Vs
Ef
If Vpu
Ef
If
Vpu
LDComp = No
PSS= No
LDComp = Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
High Initial Response Field Controlled AlternatorRectifier.
See Also: EXAC1, EXAC1A, EXAC3, EXAC4
RTDS
Technologies
4.25
RTDS
Technologies
EXAC2
AVR
1.0
1 + sTr
mon1
Vpu/Vc
Vref
If SpdMult equals
Yes then output
multiplied by pu
mon2
VSIG
VAmax
1.01
mon2
mon3
+
+
mon4
1 + sTc
Ka
1 + sTb
1 + sTa
mon5
mon6
min
mon7
mon8
KB
mon9
mon10
KL
mon17
mon16
Te
mon11
VRmin
VAmin
Efield*wpu
999.0
VRmax
+
wpu
X(t) dt
Efield
0.0
+
VLR
KH
sKf
mon19
mon18
1 + sTf
mon15
mon12
+
+
SE
mon13
Kc
X
mon20
Kd
mon14
X/Y
mon21
FEX
mon22
Ifield
EXAC2
Excitation System
4.26
EXAC3
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_EXAC3
M1
M1
IEEE Type AC3

Excitation
System
IEEE Type AC3

Excitation
System
Vc
Vs
Ef
If Vpu
Ef
If
Vpu
LDComp = No
PSS= No
LDComp = Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
Field Controlled Alternator Rectifier.
RTDS
Technologies
4.27
RTDS
Technologies
EXAC3
AVR
1.0
1 + sTr
mon1
Vpu/Vc
mon2
KLV
mon20
mon21
+
VLV
Vref
VSIG
max
1.01
mon2
mon3
VAmax
Ka
1 + sTc
+
+
mon4
1 + sTb
999.0
mon5
mon6
1 + sTa
mon7
mon8
VAmin
1
Te
mon9
mon10
X(t) dt
Efield
0.0
mon17
Kr
+
+
s
mon19
1 + sTf
mon13
Y=F(X)
SE
mon11
Kc
mon18
X
mon14
Kd
mon12
X/Y
mon15
mon16
Ifield
If SpdMult equals
Yes then output
multiplied by pu
4.28
FEX
wpu
Efield*wpu
EXAC3
Excitation System
EXAC4
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_EXAC4
M1
M1
IEEE Type AC4

Excitation
System
IEEE Type AC4

Excitation
System
Vc
Vs
Ef
If Vpu
Ef
If
Vpu
LDComp = No
PSS= No
LDComp = Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
Alternator Supplied Controlled Rectifier.
RTDS
Technologies
4.29
RTDS
Technologies
EXAC4
AVR
Vref
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon8
Vimax
1.01
+
+
mon3
mon4
1 + sTc
Ka
1 + sTb
1 + sTa
mon5
Efield
mon6
mon9
Vimin
VSIG
VRmax
If SpdMult equals
Yes then output
multiplied by pu
Ifield
wpu
Efield*wpu
Kc
VRmin
mon8
mon7
mon9
EXAC4
Excitation System
4.30
EXDC2
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type DC2 Excitation System
RSCAD/Draft ICON:
_rtds_EXDC2
M1
M1
IEEE Type DC2

Excitation
System
IEEE Type DC2

Excitation
System
Vs
Vc
Vpu
Ef
Ef
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
Field Controlled DC Commutator Exciter with continuous acting voltage regulator.
See Also: IEEET1
RTDS
Technologies
4.31
RTDS
Technologies
EXDC2
AVR
VSIG
mon7
Vref
Vmx
VPU
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
1 + sTc
Ka
1 + sTb
1 + sTa
mon5
1
mon9
X(t) dt
Te
Efield
mon8
Vmn
VPU
mon6
SE+KE
mon10
sKf
mon11
1 + sTf1
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
EXDC2
Excitation System
4.32
EXST1
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type ST1 Excitation System
RSCAD/Draft ICON:
_rtds_EXST1
M1
M1
IEEE Type ST1

Excitation
System
IEEE Type ST1

Excitation
System
Vc
Vs
Ef
If Vpu
Ef
If Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
EXST1 represents a static excitation system whose source voltage is derived from
the generator terminals through a transformer (PPT). The exciter maximum output
voltage is thus limited by the source voltage. The fixed gain Ka assumes that the
rectifier controller of the static excitation system being represented includes an
inverse cosine function to linearize the exciters gain.
Transient gain reduction may be implemented using either the forward paths leadlag
block (Tb, Tc) or the washout function (Tf, Kf) in the feedback path.
Excitation limiter inputs may be provided to the Vs input if required.
See Also: EXST1A, EXST2, EXST3
RTDS
Technologies
4.33
RTDS
Technologies
EXST1
AVR
Vref
VSIG
mon1
Vpu/Vc
1 + sTr
mon2
mon11
Vimax
1.01
1.0
mon3
++
1 + sTc
mon4
1 + sTb
mon5
Ka
mon6
1 + sTa
Efield
mon7
mon13
Vimin
sKf
1 + sTf
mon8
mon2
Ifield
If SpdMult equals
Yes then output
multiplied by pu
VRmin
Kc
mon12
mon13
mon10
wpu
Efield*wpu
mon2
VRmax
mon9
mon11
EXST1
Excitation System
4.34
EXST1A
AVR
AVR
CLASS:
AVR
COMPONENT:
Type ST1A Excitation System
RSCAD/Draft ICON:
_rtds_EXST1A
M1
M1
IEEE Type ST1A

Excitation
IEEE Type ST1A

Excitation
System
System
Vc
Vs
Ef
If
Vpu
Ef
If
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
The ST1A exciter represents a static exciter with inputs for load compensation and
for PSS signals. The block diagram for the exciter is shown below. From the block
diagram alternate PSS and VUEL inputs can be selected by using the posPSS and
posVuel toggle option. Selecting incVUEL and/or incVOEL = CC signal enables the
user to enter the signal name of the VUEL and VOEL inputs. Selecting incVUEL
and/or incVOEL = constant enables the user to specify a constant value in the exciter
parameters (Kvuel or Kvoel) for the over and underexcitation limits.
Setting the LDComp parameter to Yes enables the load current compensation input
as shown in page 3. See model IEEEVC to include load compensation. The voltage
drop across an impedance defined by the Rc + jXc parameters in the IEEEVC model
is computed using the generators stator current. Note that the values of Rc and Xc
are entered in ohms. Often Rc and Xc represent the generators unit transformer
impedance.
RTDS
Technologies
4.35
EXST1A
AVR
AVR
In this case the per unit parameters entered for trpos and txpos under the generator
TRANSFORMER PARAMETERS must be converted to ohms and entered as Rc
and Xc for the IEEEVC component.
If the include over and under excitation limiter inputs signal is enabled the user has
the option to select the signal as a constant signal or a controls compiler signal name.
If CC is selected under the option incVuel or incVoel then a separate tab called
SIGNAL NAMES is enabled where the name of the control word of the
underexcitation or overexcitation limit is entered into the model.
See Also: EXST1, EXST2, EXST3
RTDS
Technologies
4.36
RTDS
Technologies
EXST1A
AVR
Vref
posPSS=1
VS
posPSS=2
VS
mon2
Vamax
Vimax
1.01
+
++
+ mon4
mon3
VUEL
posVuel=1
mon5
max
1 + sTc1
1 + sTc
1 + sTb
mon6
mon7
1 + sTb1
Vimin
ULIM
Ka
mon8
+
max
min
+
mon9 mon10
mon11
1 + sTa
mon12
Efield
LLIM
Vamin
VUEL
posVuel=3
VUEL
posVuel=2
VoEL
sKf
mon13
1 + sTf
999.0
Ifield
Ilr
mon14
Klr
mon15
0.0
If SpdMult equals
Yes then output
multiplied by pu
4.37
See Next Page for additional Cicuit Details
mon16
wpu
Efield*wpu
ST1A
Excitation System
RTDS
Technologies
EXST1A
AVR
1.0
mon1
Vpu/Vc
Vmx
mon2
1 + sTr
Ifield
Kc
Vmn
ULIM
LLIM
Dynamic Limit
Calculations
4.38
EXST2
EXST2
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_EXST2
W
M1
M1
IEEE Type ST2

Excitation
System
IEEE Type ST2

Excitation
System
Vc
Vs
Ef
If Vpu
Ef
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
If Vpu
Description:
Exciter type EXST2 models a static exciter where both generator terminal voltage
and current are used to provide power to the exciter. Such exciters are referred to
as compound source exciters. An example is the GE SCT/PPT excitation system
used for gas and steam turbines. By using both voltage and current as the exciter
driving source it is possible to maintain field voltage even during fault conditions
where the generator terminal voltage is low.
Often the bridge is mounted on the rotor and is not controlled. Field voltage is
regulated by changing the magnitude of the source voltage applied to the bridge.
Regulation of the source voltage is done by adjusting the level of saturation on
reactors coupled to the transformer used to obtain power for the bridge.
The only difference between types EXST2 and EXST2A is whether the current
driven portion of the power sourse is added (type 2) or multiplied (type 2A) with the
voltage driven portion of the power source.
See Also: EXST1, EXST1A, EXST3
RTDS
Technologies
4.39
RTDS
Technologies
EXST2
AVR
Vref
VSIG
Vrmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
++
mon3
Ka
1 + sTa
mon4
EFDmax
type 2
mon5
+
+
mon10
1
mon11
Vrmin
Te
X(t) dt
Efield
0.0
Ke
mon12
sKf
1 + sTf
mon13
| KpVt + jKi*It |
PGEN
mon6
*
Y
QGEN
Ifield
Kc
X/Y
mon7
FEX
mon8
mon9
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
EXST2
Excitation System
4.40
EXST3
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_EXST3
M1
M1
IEEE Type ST3

Excitation
System
IEEE Type ST3

Excitation
System
Vc
Vs
Ef
If Vpu
Ef
If
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
Exciter type EXST3 represents a compound type exciter with a controlled rectifier.
See the description for EXST2(A) above for details regarding the model. The major
difference between EXST2 and EXST3 is that EXST2 models a non controlled
rectifier and EXST3 models a controlled rectifier.
RTDS
Technologies
4.41
RTDS
Technologies
EXST3
AVR
VGmax
mon10
Kg
Vref
mon9
1.0
mon1
Vpu/Vc
1 + sTr
mon2
+
+
Kj(1 + sTc)
mon3
999
VRmax
Vimax
1.01
mon4
1 + sTb
mon5
EFDmax
Ka
1 + sTa
mon6
Vimin
mon7
VRmin
Efield
mon8
999.0
VSIG
PGEN
| KpVt + j(Ki+KpXl)*It |
mon11
QGEN
Ifield
mon15
*
Y
X
Kc
mon12
X/Y
mon13
FEX
mon14
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
EXST3
Excitation System
4.42
EXPIC1
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE PI Type Excitation System
RSCAD/Draft ICON:
_rtds_EXPIC1
M1
Type EXPIC1
Excitation
System
M1
Vc
Vs
Ef
If Vpu
Type EXPIC1
Excitation
System
Ef
If Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
ProportionalIntegral Excitation System.
RTDS
Technologies
4.43
RTDS
Technologies
EXPIC1
AVR
Vref
1.01
1.0
1 + sTr
mon1
Vpu/Vc
mon2
mon3
mon18
SE+KE
VSIG
Ta1*Ka
mon3
++
mon5
VR1
mon4
1
1/Ka
VRmax
VR1
+
+
X(t) dt
mon7
VR2
mon8
1+sTa3
1 + sTa2
1 + sTa4
mon9
mon10
VRmin
mon6
VR2
1 + sTf1
mon16
1 + sTf2
mon13 mon14
EFDmin Eo
mon15
Te
X(t) dt
Efield
If Te= 0.0, Efield is

set equal to Eo (see
next page).
mon11
If Kp and Ki are both equal to

0.0, VB is set equal to 1.0 (see
next page).
mon2
PGEN
| KpVt + j(KiKpXl)*It |
mon20
*
Y
QGEN
Ifield
4.44
sKf
mon17
EFDmax
Kc
X/Y
FEX
mon12
(VB)
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
mon19
EXPIC1
Excitation System
RTDS
Technologies
EXPIC1
AVR
Vref
1.01
1.0
1 + sTr
mon1
Vpu/Vc
VSIG
Ta1*Ka
mon3
++
mon5
VR1
mon4
1
1/Ka
mon2
mon3
VRmax
VR1
+
+
X(t) dt
mon7
VR2
mon8
1+Ta3
1 + sTa2
1 + sTa4
mon9
mon10
VRmin
EFDmax
*
mon13
EFDmin
Efield
If Te= 0.0, Efield is
set equal to Eo
mon6
VR2
mon17
sKf
1 + sTf1
1 + sTf2
mon16
mon11
If Kp and Ki are equal to 0.0,

Vb is set equal to 1.0
1.0
mon12
4.45
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
EXPIC1
Excitation System
IEEET1
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type 1 Excitation System
RSCAD/Draft ICON:
_rtds_IEEET1
M1
M1
IEEE Type 1
Excitation
System
IEEE Type 1
Excitation
System
Vs
Ef
Vpu
Ef
Vc
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
The IEEE Type 1 Excitation System is used to represent DC exciters. DC exciters
use a dc generator, often connected to the main generator shaft, to supply the field
voltage and current. Older generating plants may still use DC exciters, however,
many have been replaced with modern static excitation systems.
See Also: IEEET2, IEEET3, IEEET4, IEEET5, EXDC2
RTDS
Technologies
4.46
RTDS
Technologies
IEEET1
AVR
SE*EFD
mon7
Vref
VRmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon8
VSIG
mon3
++
Ka
mon4
1 + sTa
mon5
KE
++
1
mon6
Te
X(t) dt
Efield
VRmin
sKf
mon9
If SpdMult equals
Yes then output
multiplied by pu
1 + sTf
wpu
Efield*wpu
IEEET1
Excitation System
4.47
IEEET2
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_IEEET2
M1
M1
IEEE Type 2
Excitation
System
IEEE Type 2
Excitation
System
Vs
Ef
Vpu
Ef
Vc
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
IEEE Standard Type 2 Excitation System.
See Also: IEEET2, IEEET3, IEEET4, IEEET5
RTDS
Technologies
4.48
RTDS
Technologies
IEEET2
AVR
SE+KE
Vref
VSIG
VRmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
Ka
1 + sTa
mon4
mon5
1
mon6
Te
Efield
X(t) dt
VRmin
mon9
mon7
sKf
1 + sTf2
1 + sTf1
mon8
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
IEEET2
Excitation System
4.49
IEEET3
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_IEEET3
M1
M1
IEEE Type 3
Excitation
System
IEEE Type 3
Excitation
System
Vs
Ef
If
Vpu
Ef
Vc
If Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
RTDS
Technologies
4.50
RTDS
Technologies
IEEET3
AVR
Vref
VSIG
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
0.0
VRmax
+
mon3
++
Ka
1 + sTa
mon4
mon5
+
+
A
VRmin
1.0
A
Ctrl=0
VBmax
1
mon12
mon10
If A>=B
Y=0
Else
Y=1
EndIf
mon13
Ke + sTe
Efield
0.0
mon11
sKf
mon14
PGEN
1 + sTf
mon6
| KpVt + j(Ki*It) |
QGEN
Y
Ifield
0.78
X/Y
*
1.0
If SpdMult equals
Yes then output
multiplied by pu
SQRT
mon7
mon9
mon8
wpu
Efield*wpu
IEEE T3
Excitation System
4.51
IEEET4
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_IEEET4
M1
M1
IEEE Type 4
Excitation
System
IEEE Type 4
Excitation
System
Ef
Ef
Vpu
Vc
Vpu
LDComp=No
LDComp=Yes
spdMult = No
spdMult = Yes
Description:
RTDS
Technologies
4.52
RTDS
Technologies
IEEET4
AVR
SE
Vref
mon1
Vpu/Vc
VRmax
*
1.0
+ mon2
mon3
1
KR
1
KR
Trh
X(t) dt
mon4
Ctrl=0
mon10
VRmin
KR
mon8
+
mon9
Ke + sTe
Efield
VRmax
KV
VRmin
KV
mon5
KV
|X|
mon6
KV
If A>=B
Y=0
Else
Y=1
EndIf
mon7
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
IEEET4
Excitation System
4.53
IEEET5
AVR
AVR
CLASS:
AVR
COMPONENT:
RSCAD/Draft ICON:
_rtds_IEEET5
M1
M1
IEEE Type 5
Excitation
System
IEEE Type 5
Excitation
System
Ef
Ef
Vpu
Vc
Vpu
LDComp=No
LDComp=Yes
spdMult = No
spdMult = Yes
Description:
RTDS
Technologies
4.54
RTDS
Technologies
IEEET5
AVR
SE
Vref
VRmax
mon1
Vpu/Vc
mon2
1
Trh
X(t) dt
mon3
Ctrl=0
mon9
1.0
VRmin
mon7
+
mon8
Efield
Ke + sTe
VRmax
KV
KV
mon4
VRmin
KV
|X|
mon5
KV
If A>=B
Y=0
Else
Y=1
EndIf
mon6
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
IEEE T5
Excitation System
4.55
IEEEX1
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type X1 Excitation System
RSCAD/Draft ICON:
_rtds_IEEEX1
M1
M1
IEEE Type X1
Excitation
System
IEEE Type X1
Excitation
System
Vc
Vs
Ef
Vpu
Ef
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
IEEE Type X1 Excitation System.
See Also: IEEEX2, IEEEX2A
RTDS
Technologies
4.56
RTDS
Technologies
IEEEX1
AVR
Vref
VSIG
VRmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
1 + sTc
Ka
1 + sTb
1 + sTa
mon5
mon6
1
mon7
Te
X(t) dt
Efield
VRmin
SE+KE
sKf
mon9
mon8
1 + sTf1
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
IEEEX1
Excitation System
4.57
IEEEX2
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type X2 Excitation System
RSCAD/Draft ICON:
_rtds_IEEEX2
M1
M1
IEEE Type X2
Excitation
System
IEEE Type X2
Excitation
System
Vc
Vs
Ef
Vpu
Ef
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
IEEE Type X2 Excitation System.
See Also: IEEEX1, IEEEX2A
RTDS
Technologies
4.58
RTDS
Technologies
IEEEX2
AVR
Vref
VSIG
VRmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
1 + sTc
Ka
1 + sTb
1 + sTa
mon5
mon6
1
mon7
Te
X(t) dt
VRmin
mon10
sKf
1 + sTf1
1 + sTf2
mon9
SE+KE
mon8
If SpdMult equals
Yes then output
multiplied by pu
Efield
wpu
Efield*wpu
IEEEX2
Excitation System
4.59
IEEEX2A
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type X2A Excitation System
RSCAD/Draft ICON:
_rtds_IEEX2A
M1
M1
IEEE Type X2A

Excitation
System
IEEE Type X2A

Excitation
System
Vc
Vs
Ef
Vpu
Ef
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
IEEE Type X2A Excitation System.
See Also: IEEEX1, IEEEX2
RTDS
Technologies
4.60
RTDS
Technologies
IEEEX2A
AVR
Vref
VSIG
VRmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
1 + sTc
Ka
1 + sTb
1 + sTa
mon5
999.0
mon6
VRmin
mon9
mon7
X(t) dt
Efield
0.0
sKf
1 + sTf1
1
Te
SE+KE
mon8
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
IEEEX2A
Excitation System
4.61
DC1
AVR
AVR
CLASS:
AVR
COMPONENT:
DC1 Excitation System
RSCAD/Draft ICON:
_rtds_EXDC1xv2.def
M1
DC1 Type
Excitation
System
Ef
M1
Vpu
DC1 Type
Excitation
System
Vs
Ef
Vc
Vpu
PSS = No
PSS = Yes
LDComp = No
LDComp = Yes
Description:
Field controlled DC exciter with added speed multiplier. If load compenstation input
is included, Vc is used as input rather than Vpu.
See Also: EXDC2, DC2
RTDS
Technologies
4.62
RTDS
Technologies
DC1
AVR
Vref
VSIG
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
wpu
VRmax
+
mon3
++
mon4
Ka
1 + sTc
1 + sTb
1 + sTa
mon5
mon6
1
mon7
Te
X(t) dt
Efield
VRmin
mon8
SE+KE
mon9
wpu
w > wpu
sKf
0.0026526
mon10
1 + sTf1
DC1 Type
Excitation System
4.63
DC2
AVR
AVR
CLASS:
AVR
COMPONENT:
DC2 Excitation System
RSCAD/Draft ICON:
_rtds_EXDC2xv2.def
M1
DC2 Type
Excitation
System
Ef
M1
Vpu
DC2 Type
Excitation
System
Vs
Ef
Vc
Vpu
PSS = No
PSS = Yes
LDComp = No
LDComp = Yes
Description:
Field controller DC exciter with alternate feedback path and speed multiplier.
Referring to the block diagram below, if alternate feedback path is set to Yes, the
feeback point is mon6 otherwise mon10 is used.
See Also: EXDC2, DC1
RTDS
Technologies
4.64
RTDS
Technologies
DC2
AVR
Vref
VSIG
Vrmax
Vpu
wpu
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
Ka
1 + sTb
1 + sTa
mon5
Vpu
1.0
mon9
1 + sTe
Efield
mon10
mon8
SE+KE
mon11
wpu
A
W
0.0026526
Vrmin
w > wpu
mon6
1 + sTc
Kf
s
1 + sTf1
mon7
1 + sTf2
feedBack
DC2 Type
Excitation System
4.65
AVR
AVR
REXS
REXS
CLASS:
AVR
COMPONENT:
REXS Excitation System
RSCAD/Draft ICON:
rtds_REXSv3.def
M1
M1
REXS
REXS
Excitation
Excitation
System
System
Vs
Ef
If
Vpu
LDComp=No
PSS= No
Ef
If
Vc
Vpu
LDComp = Yes
PSS= Yes
Description:
General purpose rotating excitation system model.
RTDS
Technologies
4.66
RTDS
Technologies
AVR
REXS
Vref
1.01
1.0
VSIG
1 + sTr
mon1
Vpu/Vc
Vimax
mon2
mon3
++
+
mon4 mon5
Kvp
mon8
+
+
mon6
Vimax
1 + sTf1
sKf
1 + sTf2 mon37
mon36
1
S
E
L
E
C
T
2
3
Kvi
1 + sTf
mon38
1
T
mon7
1 + sTc1
1 + sTc2
mon10 1 + sTb1 mon11 1 + sTb2 mon12
X(t) dt
T=1.0 mon9
VRmax
1
mon13
1 + sTa
mon17
mon14
Kefd
mon16
VRmin
mon16
+
Vfmax
Kip
mon15
Kh
fbf=2 selects
feedback
path mon14
Kii
999.0
mon21
mon18
fbf
wpu
mon26
+
+
mon22
1
X(t) dt
mon19 T T=1.0 mon20
1
1 + sTp
+
+
mon23
mon28
+
mon27
Te
mon29
x
X(t) dt
Efield
0.0
Vfmin
mon30
Kd
SE+KE
++
Ifield
mon32
mon29
mon33
Kc
Y
X/Y
mon34
mon35
FEX

0.0
mon24
Istator
Xc
mon25 1e6
The Istator is calculated from the 3

phase stator currents of the machine.
mon26 Istator = rms value of the 3 phase stator currents.
W
w in rad/sec
1/wo
wpu
4.67
REXS
Excitation System
AVR
AVR
IEEE AC7B
CLASS:
AVR
COMPONENT:
IEEE AC7B Excitation System
RSCAD/Draft ICON:
rtds_AC7Bv2.def
M1
M1
IEEE AC7B
Excitation
System
IEEE AC7B
Excitation
System
Ef
If
Vpu
Vs
Ef
If
Vc
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
IEEE AC7B Exciter.
Alternatorrectifier excitation system
RTDS
Technologies
4.68
RTDS
Technologies
AVR
IEEE AC7B
Vref
1.01
1.0
VSIG
Kpr
mon7
1 + sTr
mon1
Vpu/Vc
mon2
++
++
mon3
Kir
mon5
mon4
X(t) dt
T=1.0
Vrmax
mon6
+
+
+
mon9
Vrmin
mon31
sKdr
Vuel
1 + sTdr
mon24
+
mon11
mon10
mon8
VFEmaxKd*IFLD
Se(VE) + KE
999.0
mon21
SE+KE
1 + sTdr
sTe
VEmin
sKdr
mon20
mon19
Vamax
mon15
+
+
*
Vamin
mon23
Limit1
mon17
mon23 mon22
+
+
mon25
mon16
mon18
A
Ctrl= 0
mon13
1.0
Kp
Ctrl
Kd
Kpa
mon14
X(t) dt
T=1.0
mon12
Kia
Vpu
monKp
Ifield
mon21
Efield
mon31
+
+
Kc
mon30
Kf2
mon26
Y
X
X/Y
mon27
FEX
mon28
mon23
mon29
Kl * 1
Kf1
4.69
If SpdMult equals
Yes then output
multiplied by pu
mon23
Control Logic monKp.
wpu
If monKp = 0.0
*
then mon17 = 1.0

Efield*wpu
else mon17 = KpVt
Kp
IEEE
INT
Limit1

monKp
AC7B
Excitation System
REXSYS
AVR
AVR
CLASS:
AVR
COMPONENT:
REXS Excitation System
RSCAD/Draft ICON:
_rtds_REXSYS.def
M1
M1
REXSYS
REXSYS
Excitation System
Excitation System
Vpu
If
Ef
Vc
Vpu
Vs
If
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Ef
Description:
General purpose rotating excitation system model.
RTDS
Technologies
4.70
RTDS
Technologies
AVR
REXSYS
1.0
mon1
Vpu/Vc
Vref
1.01
VSIG
1 + sTr
Vimax
+
mon2
sKf
0
1
2
1 + sTf1
mon8
+
+
mon6
Kvi
mon31
1
T
mon7
1 + sTc1
1 + sTc2
mon10 1 + sTb1 mon11 1 + sTb2 mon12
X(t) dt
T=1.0 mon9
F*VRmax
1
mon13
1 + sTa
mon14
F*VRmin
Efield
+
fbf
fbf=1 selects
feedback
path mon14
+
mon4 mon5
Kvp
Vimax
1 + sTf mon30 1 + sTf2
mon29
S
E
L
E
C
T
mon3
++
F*Vfmax
Kip
mon17
mon16
+
+
mon15
Kh
Kii
mon18
mon20
X(t) dt
T T=1.0 mon19
mon22
1
1 + sTp
mon21
1
Te
mon23
X(t) dt
Efield
F*Vfmin
mon24
Kd
mon23
Kc
VSIG = VOTHSG + VUEL + VOEL

F = [1.0 + F1IMF(Et1.0)*(KE+KD+SE)
SE+KE
++
Ifield
mon25
If SpdMult equals
Yes then output
multiplied by pu
mon26
X
Y
X/Y
mon27
mon28
FEX
wpu
Efield*wpu
4.71
REXSYS
Excitation System
ESST3A
AVR
CLASS:
AVR
COMPONENT:
ESST3A Excitation System
RSCAD/Draft ICON:
_rtds_ESST3A.def
Ef
M1
M1
ESST3A
Excitation
System
ESST3A
Excitation
System
If
Vpu
Vs
Ef
If
Vc
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
IEEE Type ST3A Potential or compoundsource controlled rectifier exciter with
field control voltage control loop.
RTDS
Technologies
4.72
RTDS
Technologies
ESST3A
AVR
VGmax
Kg
Vuel
Vref
1.0
mon1
Vpu/Vc
1 + sTr
mon2
+
+
mon3 mon4
Vimin
mon11
VRmax
Vimax
1.01
max
mon5
1 + sTc
Ka
1 + sTb
1 + sTa
mon6
mon7
VRmin
VMmax
mon10
999
Km
mon8
mon9
1 + sTm
Efield
VMmin
VSIG
VBmax
PGEN
If SpdMult equals
Yes then output
multiplied by pu
VSIG = VS + VOEL
*
Y
QGEN
wpu
mon12
Efield*wpu
Ifield
Kc
mon13
mon17
mon16
999
X/Y
mon14
FEX
mon15
ESST3A
Excitation System
4.73
ESAC8B
AVR
AVR
CLASS:
AVR
COMPONENT:
ESAC8B Excitation System
RSCAD/Draft ICON:
_rtds_ESAC8B.def
M1
M1
ESAC8B
Excitation
System
ESAC8B
Excitation
System
Ef
Vpu
Vs
Ef
Vc
Vpu
PSS = No
PSS = Yes
LDComp = No
LDComp = Yes
SpdMult = No
SpdMult = Yes
Description:
Model ESAC8B represents the Basler digital excitation control system voltage
regulator as applied to a brushless exciter.
RTDS
Technologies
4.74
RTDS
Technologies
ESAC8B
AVR
Vref
VSIG
Kp
1.0
1.0
mon1
Vpu/Vc
1 + sTr
+
mon2
++
mon3
mon4
mon5
Ki
mon6
X(t) dt
sKd
1+sTd
VRmax
+
+
+
mon8
Ka
1 + sTa
mon9
VRmin
X(t) dt
Te
mon10
Efield
0.0
mon7
SE+KE
mon11
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
ESAC8B
Excitation System
4.75
ESAC1A
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type ESAC1A Excitation System
RSCAD/Draft ICON:
_rtds_ESAC1A
M1
M1
IEEE Type ESAC1A

Excitation
System
IEEE Type ESAC1A

Excitation
System
Vc
Vs
Vpu
Ef
If
Ef
If
Vpu
LDComp=No
PSS= No
LDComp=Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
Exciter ESAC1A is virtually the same as EXAC1 except for the inclusion of the HV
and LV Gates.
See Also: EXAC1
RTDS
Technologies
4.76
RTDS
Technologies
ESAC1A
AVR
Vref
VS
VAmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
1 + sTc
1 + sTb
VRmax
Ka
mon5
max
1 + sTa
mon6
VAmin
mon7
min
VRmin
VOEL
VUEL
mon9
mon8
999.0
Efield
Te
mon11
X(t) dt
mon10
0.0
mon18
Y
sKf
mon14
1 + sTf
FEX
X/Y
mon17
SE+KE
X
mon16
Ifield
If SpdMult equals
Yes then output
multiplied by pu
Kc
mon12
+
+
mon13
mon15
Kd
wpu
Efield*wpu
ESAC1A
Excitation System
4.77
ESAC4A
ESAC4A
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type AC4A Excitation System
RSCAD/Draft ICON:
_rtds_ESAC4A
M1
M1
IEEE Type AC4A

Excitation
System
IEEE Type AC4A

Excitation
System
Vc
Vs
Ef If Vpu
Ef
If
Vpu
LDComp = No
PSS= No
spdMult = No
LDComp = Yes
PSS= Yes
spdMult = Yes
Description:
Alternator Supplied Controlled Rectifier.
RTDS
Technologies
4.78
RTDS
Technologies
ESAC4A
AVR
Vref
mon8
Vimax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
+
+
1 + sTc
mon3
Vimin
VSIG
mon4
1 + sTb
mon5
max
Ka
mon6
1 + sTa
VRmin
VRmax
Ifield
VSIG = VS + VOEL
Efield
VUEL
Kc
mon8
mon7
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
ESAC4A
Excitation System
4.79
AVR
AVR
BBSEX1
CLASS:
AVR
COMPONENT:
BBSEX1 Excitation System
RSCAD/Draft ICON:
_rtds_BBSEX1.def
M1
M1
BBSEX1
BBSEX1
Excitation System
Excitation System
Vc
Vpu
If
Vs
Ef
Vpu
If
Ef
LDComp = Yes
PSS= Yes
LDComp = No
PSS= No
spdMult = Yes
spdMult = No
Description:
Brown Boveri Static Exciter
RTDS
Technologies
4.80
RTDS
Technologies
BBSEX1
AVR
Vref
1.0
1
mon1
Vpu/Vc
1 + sTf
+
+
mon3
mon2
1 + sT4
VPU*EFmax
VRmax
1 + sT3
mon4
KT2
T1 mon6 mon7
+
+
+ mon8
VRmin
mon5
mon10
Efield
VPU * EFmin
GAIN
mon9
GAIN = 1 / K * ( T1 / T2 1)
1 + sT2
SW=0
If SpdMult equals
Yes then output
multiplied by pu
VSIG
wpu
*
Efield*wpu
zero
nonzero
SW
BBSEX1
Excitation System
4.81
ESDC1A
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type DC1A Excitation System
RSCAD/Draft ICON:
_rtds_ESDC1A
M1
M1
IEEE Type DC1A

Excitation
System
IEEE Type DC1A

Excitation
System
Vs
Vc
Vpu
Ef
Ef
Vpu
LDComp = No
PSS= No
LDComp = Yes
PSS= Yes
spdMult = No
spdMult = Yes
Description:
The IEEE Type DC1A excitation model is used to represent fieldcontrolled dc
commutator exciters with continously acting voltage regulators. These voltage
regulators use power sources which are not affected by brief transients on the
synchronous machine. The VX output is the product of EFD and the value of the
nonlinearfunction SE(EFD) at the exciter voltage. If load compensation is included
then VPU will be replaced with VC as the input to the voltage transducer block.
When the spdMult is set to yes, the exciter output is multiplied by the machine speed
in per unit.
RTDS
Technologies
4.82
RTDS
Technologies
ESDC1A
ESDC1A
AVR
Vref
VS
Vrmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
mon3
++
mon4
1 + sTc
1 + sTb
Ka
max
mon5
1 + sTa
mon6
mon7
Vrmin
VUEL
999.0
Efield
Te
X(t) dt
mon8
0.0
SE(EFD)
sKf
mon10
If SpdMult equals
Yes then output
multiplied by pu
VS = VOTHSG + VOEL
switch = 0
Efield multplied by 1.0
SE
VX
+
+
mon9
VX = EFD* SE(EFD)
Ke
wpu
1 + sTf1
1.0
Efield*wpu
ESDC1A
Excitation System
4.83
AVR
AVR
ESST4B
CLASS:
AVR
COMPONENT:
ESST4B Excitation System
RSCAD/Draft ICON:
_rtds_ESST4B.def
M1
M1
ESST4B
ESST4B
Excitation System
Excitation System
Vc
Vpu
If
Vs
Ef
Vpu
If
LDComp = Yes
PSS= Yes
LDComp = No
PSS= No
spdMult = Yes
spdMult = No
Ef
Description:
IEEE Type ST4B Potential or Compounded SourceControlled Rectifier Exciter.
RTDS
Technologies
4.84
AVR
ESST4B
RTDS
Technologies
Vref
1.01
1.0
mon1
Vpu/Vc
Vs
mon18
Kpr
1 + sTr
++
++
mon4
mon3
mon2
Kir
mon6
VUEL
Kpm
mon12
mon11
Kim
mon5
VRmax
1 + sTa
VMmax
+
+
LV GATE
mon15 mon16
X(t) dt
VMmin
T T=1.0 mon14
mon17
mon13
1.0
+
+ mon8 mon9
1
VRmin
X(t) dt
T T=1.0 mon7
Efield
Kg
+
mon10
Efield
VOEL
VBmax
mon19
PGEN
QGEN
mon23
mon24
999.9
Ifield
Kc
Y mon21
mon22
FEX
/
X
mon20
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
4.85
ESST4B
Excitation System
AVR
AVR
SCRX
CLASS:
AVR
COMPONENT:
SCRX Excitation System
RSCAD/Draft ICON:
_rtds_SCRX.def
M1
M1
SCRX
SCRX
Excitation System
Excitation System
Vc
Vpu
If
Vs
Ef
Vpu
If
Ef
PSS= Yes
PSS= No
LDComp = Yes
LDComp = No
spdMult = Yes
spdMult = No
Description:
Bus Fed or Solid Fed Static Exciter.
RTDS
Technologies
4.86
RTDS
Technologies
SCRX
SCRX
AVR
Vref
Emax
1.0
mon1
Vpu/Vc
+
+
mon2
VSIG
1 + sTa
1 + sTb
1 + sTe
mon3
mon6
*
Emin
A
Vpu
1.0
Bus
Solid
mon4
If SpdMult equals
Yes then output
multiplied by pu
SW=Bus
wpu
Efield*wpu
mon5
NEGATIVE
SW
CURRENT
LOGIC
Efield
Ifield
SCRX
Excitation System
4.87
IVOEX
AVR
AVR
CLASS:
AVR
COMPONENT:
IVO Excitation System
RSCAD/Draft ICON:
_rtds_IVOEXx.def
M1
M1
IVO
Excitation
System
IVO
Excitation
System
Ef
Vpu
PSS = No
LDComp = No
Vs
Vc
Vpu
Ef
PSS = Yes
SpdMult = Yes
LDComp = Yes
Description:
IVO Excitation model.
RTDS
Technologies
4.88
RTDS
Technologies
IVOEX
AVR
Vref
mon1
Vpu/Vc
MAX3
MAX1
1.01
+
VSIG
mon2
K1*A1
K3*A3
A2 + sT2
A4 + sT4
mon3
W0
+
+
A2 + sT2
MIN1
MAX5
mon11
+
+
Efield
mon8
MIN5
MAX3
K1*sT1
MAX1
wpu
mon9
A6 + sT6
MIN3
MIN1
+
+ mon5
w > wpu
K5*A5
mon6
K3*sT3
mon4
A4 + sT4
K5*sT5
mon7
A6 + sT6
mon10
MIN3
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
IVOEX
Excitation System
4.89
EXST2A
AVR
AVR
CLASS:
AVR
COMPONENT:
IEEE Type ST2A Excitation System
RSCAD/Draft ICON:
_rtds_EXST2A
M1
M1
IEEE Type ST2A
Excitation
System
Ef
If
Vpu
LDComp = No
PSS= No
spdMult = No
IEEE Type ST2A

Excitation
System
Vc
Vs
Ef
If Vpu
LDComp = Yes
PSS= Yes
spdMult = Yes
Description:
Exciter type EXST2A model a static exciter where both generator terminal voltage
and current are used to provide power to the exciter. Such exciters are referred to
as compound source exciters. An example is the GE SCT/PPT excitation system
used for gas and steam turbines. By using both voltage and current as the exciter
driving source it is possible to maintain field voltage even during fault conditions
where the generator terminal voltage is low.
Often the bridge is mounted on the rotor and is not controlled. Field voltage is
regulated by changing the magnitude of the source voltage applied to the bridge.
Regulation of the source voltage is done by adjusting the level of saturation on
reactors coupled to the transformer used to obtain power for the bridge.
The only difference between types EXST2 and EXST2A is whether the current
driven portion of the power sourse is added (type 2) or multiplied (type 2A) with the
voltage driven portion of the power source.
RTDS
Technologies
4.90
RTDS
Technologies
EXST2A
AVR
Vref
VSIG
Vrmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
++
mon3
EFDmax
type 2a
Ka
1 + sTa
mon4
mon5
mon10
1
mon11
Vrmin
Te
X(t) dt
Efield
0.0
Ke
mon12
sKf
1 + sTf
mon13
| KpVt + jKi*It |
PGEN
mon6
*
Y
QGEN
Ifield
Kc
X/Y
mon7
FEX
mon8
mon9
If SpdMult equals
Yes then output
multiplied by pu
wpu
Efield*wpu
EXST2A
Excitation System
4.91
AVR
AVR
URST5T
URST5T
CLASS:
AVR
COMPONENT:
IEEE Type URST5T Excitation System
RSCAD/Draft ICON:
_rtds_URST5T
M1
M1
IEEE Type URST5T
Excitation
System
Ef
LDComp = No
PSS= No
spdMult = No
If
Vpu
IEEE Type URST5T

Excitation
System
Vc
Vs
Ef
If Vpu
LDComp = Yes
PSS= Yes
spdMult = Yes
Description:
Exciter type URST5T
RTDS
Technologies
4.92
RTDS
Technologies
AVR
URST5T
Vref
Vrmax/KR
Vrmax
1.01
1.0
mon1
Vpu/Vc
1 + sTr
mon2
Vrmax*Vpu
Vrmax/KR
max
mon3
Vuel
VUEL
1+sTc1
++
1 + sTb1
mon4
mon7
mon6
mon5
Vsig
Voel
VOEL VSIG Vrmin/KR
Vrmin/KR
min
1+sTc2
1 + sTb2
mon8
mon10
KR
mon9
1 + sT1
Vrmin
Vrmin*Vpu
+
Ifield
If SpdMult equals
Yes then output
multiplied by pu
Kc
Efield
mon11
wpu
Efield*wpu
URST5T
Excitation System
4.93
GAST
GOV
GOV
CLASS:
GOV
COMPONENT:
Gas Governor/Turbine
RSCAD/Draft ICON:
_rtds_GAST
Tm
Gas
Governor/Turbine
M1
Lrf= RunTime
Tm
Gas
Governor/Turbine
Pset
M1
Lrf= CC
Description:
The GAST model represents a Gas Turbine and its associated Speed Governor. A
permanent droop loop is included as part of the speed governor so that system load
will be shared amoung multiple generators. The load reference slider may be
adjusted by a system frequency controller to maintain rated frequency with changing
load.
Maximum turbine output may be limited due to the temperature sensitive feedback
loop.
RTDS
Technologies
4.94
Werr pu
1.0
Wpu
mon1
W
Generator W r/s > Wpu
Speed
(Rad/sec)
mon2
mon3
Dturb
1/R
Speed Gov.
time constant
Droop
Vmax
0.5
Load Reference
mon5
min
mon6
mon7
mon8
1
1 + sT2
1 + sT1
mon13
*
mon4
Pset
Combustion
chamber
time constant
TrateMVA
TrateMVA =
Vmin
Trate
MVA
mon12
X
+
+
mon11
Kt
mon10
mon9
Load Limit
Gain adjustment
1
1 + sT3
Exhaust gas temp.
measurement time
constant
mon1 Y
RTDS
Technologies
GAST
GOV
TM1
X/Y
Mechanical
Torque (pu)
At
Ambient temp.
Load Limit
4.95
GAST
Gas Turbine &
Speed Governor
HYGOV
GOV
GOV
CLASS:
GOV
COMPONENT:
Hydro Governor/Turbine
RSCAD/Draft ICON:
_rtds_HYGOV
Tm
Hydro
Governor/Turbine
M1
Lrf= RunTime
Tm
Hydro
Governor/Turbine
Pset
M1
Lrf= CC
Description:
Speed governor and turbine model used for hydraulic generators. The speed
governor uses a PI regulator to control the speed. Gate limit positions and gate rate
of change limiters are included to model the gate hydraulics. A permanent droop
loop is included as part of the speed governor so that system load will be shared
amoung multiple generators. The load reference slider may be adjusted by a system
frequency controller to maintain rated frequency with changing load. A no load gate
position (Qnl) is specified to indicate the gate position required to keep the generator
operating at rated speed with no load.
The turbine portion of the HYGOV model is suitable for the full range of gate
position. Reference [2] above describes the derivation of the turbine model as
implemented in HYGOV.
RTDS
Technologies
4.96
RTDS
Technologies
HYGOV
GOV
Pset
Werr pu
W r/s > Wpu

W
Generator
Speed
(Rad/sec)
Wpu
1.0
mon1
mon2
1/TD
0.50
+
+
mon3
1
mon4
1 + sTf
mon6
Gmax
mon5
1
TDTr
Velm
+
+
X(t) dt
mon10
mon9
mon8
Velm
Gmin
Gate
Position
Gmax
1
1 + sTg
mon12
mon7
Gmin
PD
mon11
Permanent
Droop
HYGOV
Speed Governor
4.97
Werr pu
mon2
Mon2, Mon12
from HYGOV
Speed Governor
(see above)
mon12
Dt
mon13
Turbine
Damping
*
Wpu
mon1
Y
/
mon15
X/Y
mon14
mon16
1.0
+
mon17
1
Tw
X(t) dt
mon18
*
+
mon19
mon20
At
mon21
Turbine Gain
mon22
TrateMVA
TrateMVA =
Trate
Gate
Position
RTDS
Technologies
HYGOV
GOV
TM
X/Y
Mechanical
Torque (pu)
MVA
Qnl
HYGOV
Turbine
4.98
IEESGO
GOV
GOV
CLASS:
GOV
COMPONENT:
IEEE Standard Governor/Turbine
RSCAD/Draft ICON:
_rtds_IEESGO
Tm
IEEE Standard
Governor/Turbine
M1
Lrf= RunTime
Tm
IEEE Standard
Governor/Turbine
Pset
M1
Lrf= CC
Description:
IEEE Standard Governor model. The IEEE Standard Governor / Turbine model may
be used to represent a hydraulic or steam system. The turbine model is a linear model
and is only adequate for small changes around a steadystate operating point. The
HYGOV model described above is suited for the full operating range of the
generator.
See Also: IEEET2, IEEET3, HYGOV
RTDS
Technologies
4.99
RTDS
Technologies
IEESGO
GOV
Pset
Werr pu
1.0
W
Generator
Speed
(Rad/sec)
Wpu
mon1
mon2
Pmax
0.5
K1
mon3
1 + sT2
mon4
1 + sT3
1 + sT1
w r/s > wpu
mon5
mon6
Pmin
wpu
1
mon7
1K2
1 + sT4
MVA
TrateMVA
++
+
mon12
mon1
Y
X
/ X/Y
Mechanical
Torque (pu)
TM
K3
K2
1 + sT5
mon10
TrateMVA =
1K3
mon9
Trate
mon8
1 + sT6
mon11
IEEE Standard
IEESGO
Governor / Turbine
4.100
IEEEG1
GOV
GOV
CLASS:
GOV
COMPONENT:
IEEE Type 1 Governor/Turbine
RSCAD/Draft ICON:
_rtds_IEEEG1
Tm1
IEEE Type 1
Governor/Turbine
M1
Lrf= RunTime
TurbTyp = Tandem Compound
Tm1
IEEE Type 1
Governor/Turbine
Pset
M1
Lrf= CC
Tm1
M1
IEEE Type 1
Governor/Turbine
Pset
M2
Tm2
Lrf= CC
TurbTyp = Cross Compound
Description:
IEEE Type 1 Speed Governor and Steam turbine model. The turbine portion of the
IEEEG1 model may be used to model nonreheat, tandem compound and cross
compound arrangements. For cross compound connected generators two torque
signals are available as output corresponding to the two shaft torques to which
generator 1 and generator 2 are connected.
See Also: IEEET2, IEEET3
RTDS
Technologies
4.101
RTDS
Technologies
IEEEG1
GOV
Valve operating
time constant
Pset
Werr pu
1.0
Wpu
mon1
W
Speed
(Rad/sec)
mon2
K(1 + sT2)
1 + sT1
0.5
mon3
mon4
1/T3
rate limits
Position limits
Uo
Pmx
mon5
Uc
mon6
T=1
1
T
X(t) dt
Valve Position
mon7
Pmn
See diagram below

for turbine circuit
IEEE G1
Speed Governor
4.102
RTDS
Technologies
IEEEG1
GOV
mon15
++
mon19
++
TrateMVAhp = Trate
MVAhp
Mechanical
Torque (pu)
mon1
mon1= wpu
from diagram above
K7
mon22
K5
mon17
K3
K1
mon12
/
Y
TrateMVAhp
mon9
X/Y TM1
mon24
*
++
mon7 = Valve
Position (from
diagram above)
mon11
K2
mon10
mon14
mon13
mon21
1 + sT7
1 + sT6
1 + sT5
1 + sT4
K8
mon8
K6
K4
mon7
mon18
mon23
TrateMVAlp =
Trate
MVAlp
TrateMVAlp
++
mon16
K2, K4, K6, K8 nonzero for

cross compound configured
generators only
++
mon20
++
X/Y
mon25
/
Y
mon1
mon1= wpu
from diagram above
TM2
Mechanical
Torque (pu)
Tm2 used for 2nd generator
in cross compund system
4.103
IEEEG1
Steam Turbine
IEEEG2
GOV
GOV
CLASS:
GOV
COMPONENT:
RSCAD/Draft ICON:
_rtds_IEEEG2
Tm
IEEE Type 2
Governor/Turbine
M1
Lrf= RunTime
Tm
IEEE Type 2
Governor/Turbine
Pset
M1
Lrf= CC
Description:
The IEEE Type 2 Governor / Turbine model may be used to represent a hydraulic
system. The turbine model in IEEE Type 2 is a linear model and is only adequate
for small changes around a steadystate operating point. The HYGOV model
described above is suited for the full operating range of the generator.
See Also: IEEEG3, IEESGO, HYGOV
RTDS
Technologies
4.104
RTDS
Technologies
IEEEG2
GOV
Pset
Werr pu
1.0
Wpu
W
Generator w r/s > wpu
Speed
(Rad/sec)
mon1
mon2
K
1 + sT1
mon3
1 + sT2
1 + sT3
mon4
Gate Position
Pmax
0.5
+
mon5
mon6
Pmin
wpu
mon1
TrateMVA =
Trate
MVA
TrateMVA
1 sT4
1 + 0.5sT4
mon7
X
*
TM
/ X/Y
Mechanical
Torque (pu)
IEEE G2
Governor / Turbine
4.105
IEEEG3
GOV
GOV
CLASS:
GOV
COMPONENT:
RSCAD/Draft ICON:
_rtds_IEEEG3
Tm
IEEE Type 3
Governor/Turbine
M1
Tm
IEEE Type 3
Governor/Turbine
Pset
Lrf= RunTime
M1
Lrf= CC
Description:
IEEE Type 3 Governor model. The IEEE Type 3 Governor / Turbine model may be
used to represent a hydraulic system. The turbine model in IEEE Type 3 is a linear
model and is only adequate for small changes around a steadystate operating point.
The HYGOV model described above is suited for the full operating range of the
generator.
See Also: IEEEG1, IEEEG2, IEESGO, HYGOV
RTDS
Technologies
4.106
RTDS
Technologies
IEEEG3
GOV
Pset
TrateMVA =
0.5
1.0
W
Generator w r/s > wpu
Speed
(Rad/sec)
mon1
mon2
Werr pu
+
mon3
Pmx
1
1/Tg
mon4
1 + sTp
T=1
Pmn
Uc
X(t) dt
Gate Position
mon5
a23*(1+sTw*K2)
1 + sTw*a11
K2= a11 a13*a21/a23
wpu
mon1
MVA
TrateMVA
Y
*
Wpu
Uo
Trate
mon9
TM
/ X/Y
Mechanical
Torque (pu)
mon8
+
+
mon6
sig
del sTr
mon7
1 + sTr
4.107
IEEE G3
Governor\Turbine
TGOV1
GOV
GOV
CLASS:
GOV
COMPONENT:
Steam Governor/Turbine
RSCAD/Draft ICON:
_rtds_TGOV1
Tm
TGOV1
Governor/Turbine
M1
Lrf= RunTime
Tm
TGOV1
Governor/Turbine
Pset
M1
Lrf= CC
Description:
Simple steam governor/turbine model.
See Also: IEEEG1
RTDS
Technologies
4.108
RTDS
Technologies
TGOV1
GOV
Pset
Vmax
0.5
mon4
1/R
mon5
1 + sT1
mon6
1 + sT2
1 + sT3
mon1
W
Speed
(Rad/sec)
mon2
mon7
TrateMVA =
Dt
mon8
TrateMVA
Vmin
1.0
Wpu
X/Y TM
Y
Trate
MVA
mon3
Mechanical
Torque (pu)
TGOV1
Speed Governor
4.109
GOV
GOV
WEHGOV
WEHGOV
CLASS:
GOV
COMPONENT:
Woodward Electric Hydro Governor
RSCAD/Draft ICON:
_rtds_WEHGOV.def
Tm
IEEE Type WEHGOV

Governor/Turbine
M1
Feedback = Power
Lrf = Runtime
Tm
IEEE Type WEHGOV

Governor/Turbine
Pset
M1
Pe
Feedback = Gate
Lrf = CC
Description:
Woodward electronic hydrogovernor with proportional, integral and derivative
control. The feedback signal can be selected as Power or Gate. Referring to the block
diagram below, if Power feedback is selected, then mon7 is the feedback point. If
Gate is selected, then mon12 is the feedback point. If Gate feedback is selected, the
generator power is required as input to the component. The generator power is scaled
to p.u. with base Trate. If Trate is 1, the generator MVA is used.
RTDS
Technologies
4.110
RTDS
Technologies
WEHGOV
WEHGOV
GOV
KDs
1 + sTD
Pset
Wpu
1.0
mon1
mon2
mon5
Kp
mon3
0.0
PELEC
+
+
+
1
X(t) dt
+
mon8 mon9 TDV
1.0
mon7
1 + sTp
GTMXCL*Tg
GMINDDPV
Gmax+DICN
1/Trate
GTMXOP*Tg
GMAX+DPV
0.01
W r/s > Wpu

W
Generator
Speed
(Rad/sec)
mon4
RPERMPE
A
Ki
B
1
T
GminDICN
1 + sTpe
mon13
PowerOrGate
RPERMGATE
mon6
mon10
X(t) dt
Gmax
1
T
PowerOrGate
X(t) dt
mon11
1/Tg
Gmin
mon12
g, gate position
continued on next page
4.111
WEHGOV
Governor
RTDS
Technologies
WEHGOV
WEHGOV
GOV
mon2
Dturb
mon21
mon12
mon15
Flow
mon16
mon22
mon1
X/Y
+
Ho
1
mon17
Tw
Pmss
X(t) dt
mon18
Flow
mon19
mon20
mon14
mon23
mon24
Y
/
Gate
mon12
TMECH
X/Y
Trate/MVA
4.112
WEHGOV
Governor
GOV
GOV
HYGOV4
HYGOV4
CLASS:
GOV
COMPONENT:
RSCAD/Draft ICON:
_rtds_HYGOV4.def
Tm
HYGOV4 Type
Governor/Turbine
M1
Lrf = Runtime
Tm
HYGOV4 Type
Governor/Turbine
Pset
M1
Lrf = CC
Description:
Hydro governor turbine model. The characteristics of the turbine can be represented
by entering different gateheadflowpowercharacteristics. This characteristic is
entered in the component as a set of six points GV0/Pgv0 GV5/Pgv5. To represent
a simple hydro turbine model, a linear curve is required. To represent the
Francis/Pelton turbine model, a non linear curve is required. The Kaplan turbine
model is not currently supported. Referring to the block diagram below, the two
deadbands are included in the model, but the hysteresis is not modeled.
RTDS
Technologies
4.113
RTDS
Technologies
HYGOV4
HYGOV4
GOV
Pset
W
Generator
Speed
(Rad/sec)
Wpu
1.0
mon1
Uo
0.01
W r/s > Wpu

+
mon2
mon3
1.0
mon4
1 + sTp
mon5
1/Tg
mon6 mon7
Uc
Pmax
1
T
X(t) dt
mon8
Pmin
++
mon12
mon10
Rperm
mon9
sTr rtemp
mon11
1 + sTr
continued on next page
4.114
HYGOV4
Governor/Turbine
RTDS
Technologies
HYGOV4
HYGOV4
GOV
mon2
mon9
*
mon21
Dturb
mon14
pgv
mon15
mon1
mon22
X/Y
1
mon16
Tw
X(t) dt
mon18
mon19
At
mon20
mon24
mon23
+
*
X
mon13
Y
/
gv
mon9
TM
X/Y
hdam
qnl
mon17
TrateMVA
TrateMVA =
Trate
MVA
4.115
HYGOV4
Governor/Turbine
GGOV1
GOV
GOV
CLASS:
COMPONENT:
RSCAD/Draft ICON:
W
Tm
GOV
_rtds_GGOV1
W
GGOV1
GGOV1
M1
Lrf= Runtime
Tm
Pset
M1
Lrf= CC
The GGOV1 model was proposed by the WECC to address the often
significant discrepancies that tended to occur between simulated governor
responses and the actual responses of physical governor systems. It was
concluded that the main cause of these discrepanceies was the incorrect
modeling of base load and load limited generators. In practice, these most
often happen to be thermal and gas turbine units. The GGOV1 model is thus
intended to provide a more accurate representation of the governor systems
for thermal and gas turbine units.
The GGOV1 model consists of components which represents the turbine,
governor as well as a basic supervisory system of a generator. The core
governor is a PID controller and the supervisory controller has both load
limiting and acceleration limiting functions. The GGOV1 model requires
two inputs; (1) the electrical power output (MW) and (2) the speed (rad/sec)
of the machine being governed. Both quantities are perunitized inside the
model based on the user specified parameters. The governor model is
initialized when RSCADs integrated loadflow funtion is run. Initialization
is important in order to avoid transients during the startup of the simulation.
The Pref slider in the governors block diagram is initialized once and its
value cannot be modified throughout the simulation. The Pset parmeter is
the perunitized power setpoint. This parameter is analoguous to what is
commonly refered to as a load reference setpoint. Its value is adjustable
during RUNTIME either through a RUNTIME slider or through the CC. The
ability to modify Pset through the CC is useful if an AGC system needs to
be implemented. The rselect parameter is used to control whether valve
position, electrical power or neither is used as a feedback signal for the
RTDS
Technologies
4.116
governor. This gives the model the flexibility to represent either modern
equipment or older mechanicalhydraulic governors. Additional details
pertaining to the GGOV1 model can be found in [7]. Details about the
tracking logic which make for smooth transitions between active controllers
were not provided so the logic had to be implemented in an ad hoc fashion.
In the chosen implementation, the output of the inactive controller is limited
to 1.1 times the output of the active controller. A multiple of 1.1 was chosen
so that output tracking doesnt itself inadventently trigger a change in the
active controller.
NOTE: Because of the feedback in this controller, some of the nonlinear
elements in the circuit (ie: tracking logic, low value select) have to be initially
disabled so that the controller can arrive at a normal operating state. At the
beginning of the simlulation the supervisory controller is disabled and the
main governor loop is closed. The main governors integrator output is held
at its initial values for one second before being released. After two seconds
the tracking logic is enabled. Half a second later, the supervisory controller
is enabled and GGOV1 enters a normal operating state.
RTDS
Technologies
4.117
RTDS
Technologies
GOV
GGOV1
wfnl
mon17
++
1/Kturb
mon18
+
mon16
1
1 + sTfload
Ldref
1 + sTsa
1 + sTsb
mon15
Speed
Dm
if Dm < 0
x
mon14
Kiload
1.0
++
Kiload X(t)dt
mon20
mon19
oo
aset
mon21
1.0
Wpu
W
mon1
:
MVA
1
1 + sTa
mon4
mon6
mon7
++
Kimw X(t)dt
mon8
mon22
mon21
0.0
4.118
rselect
1 S
E
2 L
E
3 C
T
4
vmax
Gmax
mon9
mon11
mon12
min
Kigov X(t)dt
++
+
mon21
sKdgov
1 + sTdgov
mon13
mon10
mon1
Mechanical
Torque (pu)
Tm
+
mon27
mon26
1 + sTc
1 + sTb
Ctrl= 0
B
0
1
mon1
Dm
mon22
X
A
1.0
mon1
1
1 + sTg
vmin
Gmin
1.1r
mon6
mon23
mon5
Kpgov
1.1r
+
++
Ka At
mon3
0.01
0.01
1
1 + sTpelec
+
Pref
Pset
Pelect
mon2
Ctrl
Flag
if Dm > 0
wfnl
Kturb
e sTeng
mon25
+
mon24
wfnl
GOV
GOV
TGOV5
TGOV5
CLASS:
COMPONENT:
RSCAD/Draft ICON:
GOV
IEEE Type 1 SpeedGovering Model Modified to
Include Boiler Controls
_rtds_TGOV5.def
lp (Include Low Pressure Out?) = Yes
Description:
Model TGOV5 is a classical turbine model which considers fuel flow regulation to
the boiler, boilers response to frequency change and steam loss.
Note: Since the possible delay time of fuel supply (Td) could be set in the range from
0.5 to 100 seconds, the size of the memory that reserved for storing the data (going
into the delay component) is fixed to 5000.
RTDS
Technologies
4.119
TGOV5
GOV
RTDS
Technologies
W r/s > Wpu
mon6
Ctrl= 0
K
mon3
1 + sT2
1 + sT1 mon4
B
Uo
1/T3
mon5 + mon7
mon8 mon9
Ctrl
Uc
mon59
0
1
SW1
Generator
Speed
(Rad/sec)
1.0
mon1
Wpu
+
mon2
++
mon49
mon46
1
1 + sT6
mon12
1
1 + sT7
mon48
mon52
mon56
++
mon50
++
Vmin
*
mon10
1
1 + sT4
mon57
mon58
Tm1
PMCHhp
(pu)
mon13
K8
mon11
mon55
K5
K3
mon51
++
K6
K2
mon57
1
1 + sT5
mon53
K4
K1
mon47
++
X(t) dt
K7
mon45
Vmax
mon54
++
Tm2
PMCHlp
(pu)
4.120
TGOV5
IEEE Type 1 Speed Governing Model Modified to Include Boiler Controls
TGOV5
GOV
PELEC
mon2
mon64
Kmw
1 + sTmw
RTDS
Technologies
in pu
mon16
Lmax
Rmax
MWdemand
mon63
C2
mon22
++
*
mon19
mon15
+
K14
mon17
mon20
Rmin
mon24
X(t) dt
mon59
Lmin
K13
mon18
mon21
mon25
K12
mon43
mon57
KL
mon23
C3
+
+
*
mon42
mon41
mon59
mon60
Cmax
mon62
mon30
mon26
mon28
X(t) dt
+
+
KI
1 + sTI
1 + sTR1
mon25
+
mon40
Cmin
mon33
mon63
1
1 + sTF
mon34
1
1 + sTW
mon35
Ctrl= 0
mon38
mon37
sTD
Ctrl
4.121
0
1
SW2
mon36 B
+
++
K9
C1
1/(sCB)
TR
mon39
mon61
mon27
mon29
K11
mon58
mon44
TGOV5
mon32
K10
IEEE Type 1 Speed Governing Model

Modified to Include Boiler Controls
WSIEG1
GOV
GOV
COMPONENT:
IEEE Type WSIEG1
RSCAD/Draft ICON:
_rtds_WSIEG1v2
Tm1
IEEE Type WSIEG1

Governor/Turbine
M1
Lrf = RunTime
TurbTyp = Tandem
Tm1
IEEE Type WSIEG1

Governor/Turbine
Pset
M1
Lrf = CC
TurbTyp = Tandem
Tm1
M1
IEEE Type WSIEG1

Governor/Turbine
Pset
M2
Tm2
Lrf = CC
Description:
IEEE Type WSIEG1 SpeedGoverning Model. For cross compound connected
generators two torque signals are available as output corresponding to the two shaft
torques to which generator 1 and generator 2 are connected.
See Also: IEEEG1.
RTDS
Technologies
4.122
RTDS
Technologies
WSIEG1
GOV
Pset
Valve operating
time constant
GVO
Werr pu
1.0
Wpu
W
Speed
(Rad/sec)
wpu
mon1
err
db1
mon2
mon3
(1 + sT2)
1 + sT1
0.5
mon4
mon5
1/T3
rate limits
Position limits
Uo
Pmax
mon6
mon7
1
T
Uc
Pmin
X(t) dt
Valve Position
mon8
mon9
db2
See diagram below

for turbine circuit
WSIEG1v2
Speed Governor
4.123
RTDS
Technologies
WSIEG1
GOV
TrateMVAhp = Trate
MVAhp
wpu
TrateMVAhp
Tm1
X/Y
Mechanical
Torque (pu)
K7
mon20
K5
K3
K1
mon18
mon16
++
Y
/
mon15
++
mon19
++
mon17
mon9 = Valve
Position (from
diagram above)
1
mon11
mon12
mon13
mon14
1 + sT7
1 + sT6
1 + sT5
K8
1 + sT4
K6
mon10
K4
NGV
K2
mon9
mon21
mon22
mon24
mon26
TrateMVAlp =
Trate
wpu
MVAlp
TrateMVAlp
Y
X
K2, K4, K6, K8 nonzero for

cross compound configured
generators only
mon25
++
mon23
++
++
Tm2 used for 2nd generator

in cross compund system
Tm2
X/Y
Mechanical
Torque (pu)
4.124
WSIEG1v2
Steam Turbine
GOV
GOV
WSHYGP
CLASS:
GOV
COMPONENT:
WECC GP Hydro Governor Plus Turbine
RSCAD/Draft ICON:
_rtds_WSHYGP.def
Tm
WECC WSHYGP
Governor/Turbine
M1
Lrf = CC
Pe
Tm
WECC WSHYGP
Governor/Turbine
Pset
M1
Pe
Lrf = Runtime
Description:
Proportionalintegralderivative (PID) governor and turbine.
Notes
If the pu data is given on turbine MW base, this base value is entered as the Trate
parameter. If this value is unknown, then the base turbine MW rating (Trate) should
be set to 1 and the generator MVA base is used. If the feedback path is such that
the electric power (PELEC) is used as input, R is required in pu on generator MVA
base.
Hysterisis is not currently supported in the deadband models. If the nonlinear curve
points GV*,PGV* are entered as all zeroes, a linear curve is used. If Kd and Tf are
both entered as 0, the washout is ignored. If Tf is 0.0 and Kd is nonzero, Tf is set
to 4.0*dt.
RTDS
Technologies
4.125
RTDS
Technologies
WSHYGP
WSHYGP
GOV
Kp
mon6
Pset
0.01
W r/s > Wpu

W
Generator
Speed
(Rad/sec)
Wpu
1.0
mon1
mon2
err
db1
mon3
1
mon4
1 + sTd
Ki
mon5
1
T
X(t) dt
mon7
+
+
+
sKd
1 + sTf
mon11
mon8
mon9
A
B
mon10
Tt > 0.0 select B
1
1 + sTt
1/Trate
PELEC
4.126
WSHYGP
Governor
RTDS
Technologies
WSHYGP
WSHYGP
GOV
mon1
Rate Limits
VELopen
1 + sTp
VELclose
mon13
1
T
X(t) dt
PGV
mon14
db2
GV
Pmin
mon16 1 + sAturbTturb mon17

1 + sBturbTturb
mon18
*
Kg
Y
/
mon9
mon12
Pmax
TMECH
X/Y
TrateMVA
mon15
TrateMVA =
Trate
MVA
4.127
WSHYGP
Governor
URGS3T
GOV
GOV
CLASS:
COMPONENT:
RSCAD/Draft ICON:
Tm
WECC URGS3T
Gas Turbine
M1
Lrf = Runtime
GOV
WECC Gas Turbine Model
_rtds_URGS3T
Tm
WECC URGS3T
Gas Turbine
Pset
M1
Lrf = CC
The URGS3T governor is a WECC gas turbine model. The model requires only a
single input, the speed (rad/sec) of the machine being governed. The machine speed
is perunitized inside the model based on user specified parameter(s). The governor
model is initialized when RSCADs integrated loadflow funtion is run. Initialization
is important in order to avoid transients during the startup of the simulation. The
Pref slider is analoguous to what is commonly refered to as a load reference setpoint.
Its value is initialized when the loadflow is run but can be adjusted during
RUNTIME either through a RUNTIME slider or through the CC. The ability to
modify Pref through the CC is useful if an AGC system needs to be implemented.
Notes The data required is on turbine MW rating base. If the turbine MW base is
unknown, then the base turbine MW rating should be set to the generator MVA.
Hysterisis is not currently supported in the deadband models. If the nonlinear curve
points GV and PGV are all entered as zeroes, a linear curve is used. The GV points
on the nonlinear charactersistic should increase monotonically.
RTDS
Technologies
4.128
RTDS
Technologies
GOV
URGS3T
Ltrat
Rmax
If (C1 > C2)
Out= A
Else
Out= B
C1
mon12
mon11
1
1 + sTltr
mon13
mon12
C2
Tm
Trate
X/ Y
mon23
GEN MVA
Linc
Y
mon1
Pref
mon13
mon3
Ka (1+sT4)
err
+
mon4
db
mon5
min
1 + sT5
mon6
mon7
mon8
mon9
Vmax
1 X(t) dt
T
mon10
1 + asT2
+
Vmin
mon14
1 + bsT2
mon15
mon21
PGv
Gv
mon20
db
+
Filde
1
mon19
++
Fidle
mon17
mon18
Kt
mon16
1 + sT3
Lmax
1.0
wpu
mon1
Dturb
mon2
mon22
URGS3T
Gas Turbine
4.129
GOV
GOV
WSHYDD
CLASS:
GOV
COMPONENT:
WECC DD Hydro Governor
RSCAD/Draft ICON:
_rtds_WSHYDD.def
Tm
WECC WSHYDD
Governor
Pset
M1
Pe
Tm
WECC WSHYDD
Governor
Pset
M1
Pe
Description:
Doublederivative (DD) governor.
Notes Hysterisis is not currently supported in the deadband models. If the
nonlinear curve points GV*,PGV* are entered as all zeroes, a linear curve is used.
If any data point other than the first data point is entered as (0.0,0.0), remaining data
points are set as (1.0,1.0). If the first and last data points are not (0.0,0.0) and
(1.0,1.0) respectively, the (0.0,0.0) and (1.0,1.0) points are added to the nonlinear
curve. If Kd and Tf are both entered as 0, the washout is ignored. If Tf is 0.0 and
Kd is nonzero, Tf is set to 4.0*dt.
RTDS
Technologies
4.130
RTDS
Technologies
WSHYDD
GOV
Pset
0.01
W r/s > Wpu

Wpu
W
Generator
Speed
(Rad/sec)
1.0
mon1
err
mon2
db1
mon3
1 + sTd
sK1
mon5
1 + sTf
mon4
sK2
1 + sTf
+
+
+
s
mon6
1 + sTf
mon7
A
mon10
mon12
mon9
mon8
Ki
X(t) dt
B
mon11
Tt > 0.0 select B
1
1 + sTt
1/Trate
PELEC
4.131
WSHYDD
Governor
RTDS
Technologies
WSHYDD
GOV
mon1
Rate Limits
Pmax
mon13
Kg
1 + sTp
VELclose
mon14
1
T
Pmin
X(t) dt
mon15
mon16
db2
PGV
GV
mon17 1 + sAturbTturb mon18

1 + sBturbTturb
mon19
*
mon10
Y
/
VELopen
TMECH
X/Y
TrateMVA
TrateMVA =
Trate
MVA
4.132
WSHYDD
Governor
PIDGOV
GOV
GOV
CLASS:
GOV
COMPONENT:
Hydro Turbine and Governor
RSCAD/Draft ICON:
_rtds_PIDGOV.def
Tm
PIDGOV
Governor/Turbine
M1
Pe
Lrf = Runtime
Tm
PIDGOV
Governor/Turbine
Pset
M1
Pe
Lrf = CC
Description:
RTDS
Technologies
4.133
RTDS
Technologies
PIDGOV
GOV
Pset
M=0
0.50
Rperm
mon22
1 + sTreg
mon21
1/Trate
mon19
+
PELEC
M=1
mon20
mon14
Flag
M=0
M=1
Kp
mon4
+
+
W r/s > Wpu

Wpu
W
Generator
Speed
(Rad/sec)
mon1
mon2
Ki
mon3
1
T
X(t) dt
1
mon7
1 + sTa
mon8
+
+
mon9
1
1 + sTa
mon10
mon5
1.0
sKd
1 + sTa
mon6
4.134
PIDGOV
Governor/Turbine
mon10
1.0
+
mon11 Tb mon12
VELmin
1
mon13
Power
Gmax
T
Gmin
X(t) dt
3
2
mon14
1
0
Gate
1 Tz
mon15
1 + sTz/2
TrateMVA =
mon16
Trate
MVA
TrateMVA
Tz = (Atw) * Tw
+
mon18
mon1 Y
Dturb
mon2
VELmax
RTDS
Technologies
PIDGOV
GOV
X/Y TM
mon17
4.135
PIDGOV
Governor/Turbine
BBGOV1
GOV
GOV
CLASS:
GOV
COMPONENT:
European Governor Model
RSCAD/Draft ICON:
_rtds_BBGOV1.def
Tm
BBGOV1
European Governor
M1
Lrf = Runtime
SW = 0
Tm
BBGOV1
European Governor
Pset
M1
Pe
Lrf = CC
SW = 1
Description:
RTDS
Technologies
4.136
RTDS
Technologies
BBGOV1
GOV
PELEC
1/Trate
SW=0
Pset
Wpu
+
mon1 mon2
fcut
fcut
mon3
Ks
KLS
mon4 mon5
mon6
KLS
+
+
SW=1
mon13
SW
mon14
0.50
W r/s > Wpu

W
Generator
Speed
(Rad/sec)
1
1 + sT1
Po
mon9
Kp
1 + sTn
SW=0
SW=1
mon10
1.0
1
mon8 T=1
X(t) dt
mon7
Kg
Kls
4.137
BBGOV1
European Governor
RTDS
Technologies
GOV
BBGOV1
Pmax
1
Kd
mon10
1 + sTd
mon11
mon12
1 + sT4
1 K2
mon13
mon18
TrateMVA =
Pmin
Trate
MVA
mon1
TrateMVA
Y
1 K3
mon16
mon19
mon15
1 + sT5
+
++
K2
X/Y
TM
K3
1 + sT6
mon17
4.138
BBGOV1
European Governor
DEGOV
GOV
GOV
CLASS:
GOV
COMPONENT:
Woodward Diesel Governor
RSCAD/Draft ICON:
_rtds_DEGOV.def
Tm
DEGOV
Governor
M1
Description:
DEGOV is a model of a governor for a diesel engine. This model is based on a
Woodward diesel engine where droop control is used with either throttle or electric
power feedback.
See DEGOV1
RTDS
Technologies
4.139
RTDS
Technologies
GOV
DEGOV
Tmax
W r/s > Wpu
1.0
+
mon1 mon2
T3s + 1
1+ T1s+ T1T2s2 mon3
T4s + 1
mon4
mon5
1+(T5+T6)s+T5T6s2
1
mon6 T
X(t) dt
esTd
mon7
TM
TrateMVA
T = 1.0
Tmin
mon8
W
Generator
Speed
(Rad/sec)
Wpu
TrateMVA =
Trate
MVA
DEGOV
4.140
DEGOV
DEGOV1
GOV
GOV
CLASS:
GOV
COMPONENT:
RSCAD/Draft ICON:
_rtds_DEGOV1.def
Tm
DEGOV1
Governor
Tm
DEGOV1
Governor
M1
M1
Pset
Lrf = Runtime
Lrf = CC
Description:
RTDS
Technologies
4.141
HYGOV2
GOV
GOV
CLASS:
GOV
COMPONENT:
Hydro Turbine Governor
RSCAD/Draft ICON:
_rtds_HYGOV2.def
Tm
HYGOV2
Governor/Turbine
M1
Lrf = Runtime
Tm
HYGOV2
Governor/Turbine
Pset
M1
Pe
Lrf = CC
Description:
RTDS
Technologies
4.142
RTDS
Technologies
HYGOV2
GOV
Kp
mon3
W
Generator
Speed
(Rad/sec)
mon9
0.50
W r/s > Wpu

Wpu
T1
T3
Pset
mon1
+
+
mon2
mon6
+
+
mon7
1.0
1
Ki
mon4
T=1
1
mon8
T3
mon11
X(t) dt
mon10
X(t) dt
mon5
mon16
srTr
1 + sTr
mon15
mon17
4.143
HYGOV2
Governor/Turbine
RTDS
Technologies
GOV
HYGOV2
Gmax
VGmax
mon11
Ka
1 + sT2
mon12
1 + sT4
1
mon13
mon14
T=1
X(t) dt
1
mon15
1 + sT6
mon19
Trate
TrateMVA =
VGmax
Gmin
MVA
TrateMVA
mon20
Pmax
mon21
X
/
mon1 Y
X/Y TM
sT5
1 + sT6
mon18
HYGOV2
4.144
Governor/Turbine
GOV
GOV
TGOV5
CLASS:
COMPONENT:
RSCAD/Draft ICON:
W Tm1
IEEE Type TGOV5
Governor/Turbine
M1
Lrf
= Runtime
GOV
IEEE Type 1 SpeedGovering Model Modified to
Include Boiler Controls
_rtds_TGOV5v3.def
W Tm1
M1
IEEE Type TGOV5
Governor/Turbine
Pset
M2
Tm2
Lrf = CC
Description:
Model TGOV5v2 (which is the modified version of TGOV5) is a classical turbine
model which considers fuel flow regulation to the boiler, boilers response to
frequency change and steam loss.
Note:
For generator models that have a single speed input with two torque outputs such as
IEEEG1, WSIEG1 and TGOV5 (see figure below), their governor/turbine shaft
arrangements can either be tandemcompound or cross compound. The TurbTyp
parameter is used to select the type of turbine compounding. For Tandem
compounding, only the torque output Tm1 is used and the second torque output Tm2
is set to zero as the gain parameters K2,K4,K6,K8 must be zero and the sum of the
gain parameters K1,K3,K5,K7 must be 1. For cross compounding, the summation
of K1,K2,K3,K4,K5,K6,K7,K8 must add up to 1.0.
Since the possible delay time of fuel supply (Td) could be set in the range from 0.5
to 100 seconds, the size of the memory that reserved for storing the data (going into
the delay component) is fixed to 5000.
RTDS
Technologies
4.148
GOV
1.0
mon1
Wpu
+
mon2
Ctrl= 0
K
mon3
1 + sT2
1 + sT1 mon4
B
Vmax
Uo
X(t) dt
1/T3
mon5 + mon7
mon8 mon9
Ctrl
Uc
mon59
Vmin
*
mon10
TrateMVAhp = Trate
MVAhp
mon13
K8
1
1 + sT7
K6
mon12
K7
mon55
K5
K3
1
1 + sT6
K4
K1
K2
mon11
TrateMVAlp =
mon48
mon52
mon50
++
mon56
mon54
++
TrateMVAlp
Trate
mon1
MVAlp
Y
mon46
++
Tm1
X/Y
1
1 + sT5
PMCHhp
(pu)
mon57
mon51
++
Y
/
mon47
++
mon53
++
mon49
mon57
mon1
TrateMVAhp
mon45
1
1 + sT4
mon58
0
1
SW1
W r/s > Wpu
mon6
PMCHlp
(pu)
RTDS
Technologies
W1
Generator
Speed
(Rad/sec)
TGOV5
Tm2
X/Y
4.149
TGOV5v3
IEEE Type 1 Speed Governing Model Modified to Include Boiler Controls
TGOV5
GOV
mon64
1/Trate
PELEC
RTDS
Technologies
Kmw
1 + sTmw
mon2
mon16
Pset
Lmax
Rmax
MWdemand
mon63
C2
mon22
++
*
mon19
mon15
+
K14
mon17
mon20
Rmin
mon24
X(t) dt
mon59
Lmin
K13
mon18
mon21
KL
mon25
K12
mon43
mon57
mon23
C3
+
+
*
mon42
mon41
mon59
mon60
Cmax
mon62
mon30
mon26
mon28
X(t) dt
+
+
KI
1 + sTI
1 + sTR1
mon25
+
mon40
Cmin
mon33
mon63
1
1 + sTF
mon34
1
1 + sTW
mon35
Ctrl= 0
mon38
mon37
sTD
Ctrl
4.150
0
1
SW2
mon36 B
+
++
K9
C1
1/(sCB)
TR
mon39
mon61
mon27
mon29
K11
mon58
mon44
TGOV5v3
mon32
K10
IEEE Type 1 Speed Governing Model

Modified to Include Boiler Controls
Rev. 00: Jan 02
COMPLEX MATH FUNCTIONS
A set of complex math function blocks are available as part of the sharc controls components. These blocks work with complex numbers either in the form of Real, Imaginary (Re,Im) or Magnitude, Angle (|X|,/_X) pairs. The angle component (/_X) is in
radians. Each complex math functions operation mode can be set to either Re,Im
or |X|,/_X. A single control wire carries the pair of numbers. Connection of complex
number outputs to real number inputs generates an error. Connection of complex
Re,Im format numbers to inputs specified as |X|,/_X also generates an error.
Function blocks are available to convert real numbers to and from complex format.
Input and output connection points which require complex numbers as input are
identified by wide line segments.
Re
1.0
Im
1.0
|X|
1.0
/_X
1.0
convert Re,Im
to
complex
CPX1
convert |X|,/_X
to
complex
CPX2
wide lines segments indicate

complex number data
For the example above, the signals CPX1 and CPX2 are complex and each wire carries a pair of numbers. The CPX1 wire carries (1, 1) and CPX2 carries (1.4142,
0.7854). These values may be monitored in PSCAD/RunTime. CPX1 will be listed
as CPX1[Re] and CPX1[Im] and CPX2 as :CPX2: and /_CPX2.
Since wire labels may only be 10 characters long, complex signal names are limited
to 6 characters so that the [Re] and [Im] extensions may be applied.
Converting from complex values back to real values is done using the function blocks
shown below. In this case the numbers RE1, IM1, MAG2, ANG2 have been converted back to real numbers.
5.1
COMPLEX NUMBER BLOCKS
CPX1
CPX2
Re,Im
|X|,/_X
Re
convert
from
Im
complex
|X|
convert
from
complex /_X
RE1
IM1
MAG2
ANG2
wide lines segments indicate

complex number data
5.2
COMPLEX
CONVERT TO COMPLEX
CLASS:
COMPLEX NUMBER FUNCTION
FUNCTION:
Convert 2 real numbers to a complex number pair
RSCAD/Draft ICON:
rtds_sharc_ctl_RI2CPX
Re
Im
convert Re,Im
to
complex
input mode= Re,Im
output mode= Re,Im
|X|
/_X
convert Re,Im
to
complex
input mode= |X|,/_X
output mode= Re,Im
Re
Im
convert |X|,/_X
to
complex
input mode= Re,Im

output mode= |X|,/_X
|X|
/_X
convert |X|,/_X
to
complex
input mode= |X|,/_X

Description:
2 real inputs are converted to a complex pair. The user may specify the complex format as real,imaginary or magnitude,angle. Angle (/_X is in radians). The output signal can be used as input to complex number math functions.
See Also:
Convert from Complex
Execution Time:
Re,Im > Re,Im mode
Re,Im > |X|,/_X mode
|X|,/_X > Re,Im mode
|X|,/_X > |X|,/_X mode
0.3 s
4.65 s
3.1 s
0.3 s
5.3
COMPLEX CONVERT FROM COMPLEX

CLASS:
FUNCTION:
Convert a complex number pair to real numbers
RSCAD/Draft ICON:
rtds_sharc_ctl_CPX2RI2
Re,Im
convert Re
from
Im
complex
input mode= Re,Im
output mode= Re,Im
Re,Im
convert |X|
from
/_X
complex
input mode= |X|,/_X
output mode= Re,Im
|X|,/_X
Re
convert
from
Im
complex
input mode= Re,Im

|X|,/_X
|X|
convert
from
/_X
complex
input mode= |X|,/_X

Description:
A complex pair is converted to 2 real outputs. The user may specify the complex format as real,imaginary or magnitude,angle. Angle (/_X is in radians). The user may
specify which outputs are available (SELO parameter).
See Also:
Convert to Complex
Execution Time:
Re,Im > Re,Im mode
|X|,/_X > Re,Im mode
|X|,/_X > |X|,/_X mode
SELO= BOTH: 0.5 s

SELO not BOTH: 0.25 s
SELO= BOTH: 4.65 s
SELO= Mag/Re: 1.0s
SELO= Phase/Im: 3.25s
SELO= BOTH: 3.5 s
SELO= BOTH: 0.5 s
5.4
COMPLEX
CONVERT COMPLEX
CLASS:
FUNCTION:
Convert complex number format
RSCAD/Draft ICON:
rtds_sharc_ctl_CPXCONV
Re,Im
convert
complex
|X|,/_X
input mode= Re,Im

|X|,/_X
convert
complex
Re,Im
input mode= |X|,/_X

output mode= Re,Im
Description:
Convert complex number format from Re,Im to |X|,/_X or from |X|,/_X to Re,Im.
/_X is in radians.
See Also:
Convert to Complex, Convert from Complex
Execution Time:
|X|,/_X > |X|,/_X mode
4.65 s
3.1 s
5.5
COMPLEX
COMPLEX CONJUGATE
CLASS:
FUNCTION:
Complex Conjugate
RSCAD/Draft ICON:
rtds_sharc_ctl_CPXCONV
Re,Im
complex
conjugate
Re,Im
mode= Re,Im
|X|,/_X
complex |X|,/_X
conjugate
mode= |X|,/_X
Description:
Computes the complex conjugate of the input. Re,Im > Re,Im or |X|,/_X >
|X|,/_X.
See Also:
5.6
SUMMING JUNCTION
COMPLEX
CLASS:
MATH FUNCTION
FUNCTION:
2 or 3 Input Summing Junction
RSCAD/Draft ICON:
rtds_sharc_ctl_CPXSUM
Num= 3
Num= 2
Description:
2 or 3 input summing junction. Inputs may be individually set to add to or subtract
from the output. Both Re,Im and |X|,/_X formats are supported.
See Also:
Execution Time:
Re,Im mode (2 or 3 inputs)
|X|,/_X (2 input)
|X|,/_X (3 input)
0.75 s
8.45
14.65
5.7
COMPLEX MULTIPLICATION JUNCTION

CLASS:
MATH FUNCTION
FUNCTION:
2 or 3 Input Multiplication Junction
RSCAD/Draft ICON:
rtds_sharc_ctl_CPXMUL
Num= 3
Num= 2
Description:
2 or 3 input multiplication junction Both Re,Im and |X|,/_X formats are supported.
See Also:
Execution Time:
|X|,/_X mode (2 or 3 inputs) 0.75 s
Re,Im (2 input)
0.5
Re,Im (3 input)
0.75
5.8
COMPLEX
INVERSE
CLASS:
FUNCTION:
Invert complex input
RSCAD/Draft ICON:
rtds_sharc_ctl_CPXINP
Re,Im
1/_0
X
Re,Im
mode= Re,Im
|X|,/_X
1/_0
X
|X|,/_X
mode= |X|,/_X
Description:
Compute the inverse of the input complex number. For divide by 0, the user may
specify that the simulation case be halted, or that the output be set to a specified value.
See Also:
Execution Time:
Re,Im mode 0.70 s
|X|,/_X mode 1.075 s
5.9
CHAPTER:6
FIGURE:8.
SEQUENCER
( rtds_sharcu_SEQUENCER )
6.1 INTRODUCTION
The sequencer component is a controls model. It is used to create a series of events
which will occur at certain points in time during a simulation. These events include
opening and closing of breakers, applying and clearing of faults as well as initializing
variables. Many different sequencer operations can be selected in the sequencer
component. The appearance of the sequencer component changes based on the
sequencer operation selected.
The sequencer component can be used on 3PC or RISC processors.
6.2 PARAMETER MENU
The default sequencer component is a host trigger component and its parameter
menu and its icon are shown below.
CONFIGURATION:
The configuration menu specifies the type of the sequencer component, the control
processor number and the priority.
6.1
SEQUENCER
sequencer type:
type
Trigger:
host trigger;
Cross:
signal crossing;
Delay:
time delay;
Brk:
breaker operation;
Fault:
fault operation;
Init:
breaker word initialization;
Var:
set variable.
Proc
control processor number. Please note that all the sequencer components
must be on the same control processor for the sequencer to function properly.
Pri
priority level in manual mode.
All sequencer components produce a rising edge as their output signal. Most
sequencer components require a rising edge signal as input to activate the
component. Host trigger and some initialization sequencer components do not need
an input signal.
HOST TRIGGER (type=Trigger)
The menu specifies the name of the RunTime host trigger button. The host trigger
sequencer component creates a RunTime push button. When the button is pressed,
a rising edge is produced as its output signal.
WAIT FOR SIGNAL CROSSING (type=Cross)

The menu specifies the following parameters:
6.2
SEQUENCER
sig
name of the signal;
level
level of crossing;
slope slope of crossing.

The component is activated by a rising edge input signal. After it finds the specified
signal crossing the given level with the specified slope, it produces a rising edge as
its output.
DELAY TIME (type=Delay)
The menu specifies the parameters for a time delay sequencer block:
dtype delay type:

Fixed:
fixed delay time;
Slider:
variable delay time controlled by a RunTime slider;
CC:
variable delay time controlled by a Controls Compiler signal.
Fixed
Slider
CC
dtype2 unit of delay time: mS or degree.

freq
base frequency for converting delay time in electrical degree to mS.
dslider the RunTime slider name when dtype=Slider.

delay delay time of the sequencer block. It is used as the fixed delay time when
dtype=Fixed. It is also used as RunTime sliders initial delay time setting
when dtype=slider.
maxDelay the maximum delay time setting of the RunTime slider.
The component is activated by a rising edge input signal. After the elapse of the
specified delay time, it produces a rising edge as its output.
6.3
SEQUENCER
BREAKER OPERATION (type=Brk)

The menu specifies the parameters for a breaker operation:
swdnm1
name of the switch word for the breaker being operated.
bitw1 bit number for the breaker being operated (an integer between 1 and 21).
op
type of breaker operation: Open or Close.
ph3
whether or not to operate the next two bits at the same time. If bitw1=1 and
ph3=Yes, the breakers associated with bit 1, bit 2 and bit3 will be operated at
the same time.
FAULT OPERATION (type=Fault)

There are three variations of the fault operation block depending on the value of the
parameter ftype (fault operation type). The parameter nflt is only used in the Fault
Group Definition sequencer block to indicate the number of fault switches in the
fault group.
6.4
SEQUENCER
SINGLE FAULT OPERATION (ftype=Single Bit)

ftype=Single Bit
The sequencer block will operate a single fault switch defined by the switch word and
the bit number.
swdnm name of the switch word for the fault being operated.
bitw
bit number for the fault being operated (an integer between 1 and 21).
fltOP type of fault operation: Clear or Apply.
GROUP FAULT OPERATION (ftype=Group)

ftype=Group
The sequencer block will operate a group of fault switches defined by a Fault Group
Definition sequencer block.
6.5
SEQUENCER
grpnmI name of the fault group.
swdnmG name of the switch word for the fault group.
fltOPG type of fault operation: Clear or Apply.
FAULT GROUP DEFINITION (ftype=Group Def)

ftype=Group Def
The block is a definition block. It defines the name and bit numbers of a fault group.
It also defines the RunTime fault control switch names.
grpnmO name of the fault group.

gb1
bit number for fault #1 (an integer between 1 an 21).
.....
gb6
bit number for fault #6 (an integer between 1 an 21).
Please note that the number of fault switches in the fault group is defined in the
FAULT OPERATION TYPE parameter menu. There can be up to 6 fault switches
in a fault group. The switch word name is defined in the GROUP FAULT
OPERATION menu of the group fault operation sequencer block.
swtFG1 RunTime switch name for fault #1.
6.6
SEQUENCER
....
swtFG2 RunTime switch name for fault #6.
RunTime fault control switches themselves do not turn on/off the faults directly.
They are used to control whether or not a particular fault will be operated by the
group fault operation sequencer block. Please also note that the initial status of
all fault control switches are OFF. To include a particular fault in the group
fault operation, its control switch should be created in RunTime and set to ON.
SWITCH WORD INITIALIZATION (type=Init)
The sequencer block is used to initialize a switch
word. There can only be one such sequencer block for
each switch word. No components other than the
sequencer should be allowed to modify or initialize
a switch word used by the sequencer blocks.
SET VARIABLE (type=Var)
The sequencer block is used to initialize and set control variables.

vtype variable type (INT or FLOAT).
vname variable name.
vval
variable value to be set.
vinit whether or not to initialize the variable. Only one such block should be used
to initialize a variable.
viniv
the initial value of the variable (if it is initialized by the same block).
6.7
SEQUENCER
Please note that other RTDS nonsequencer components can only use (not modify)
the value of a variable set by a sequencer block.
6.3 SAMPLE CASE
A sample case for the usage of the model is shown in the DRAFT case
Tutorial/SAMPLES/SequencerExample/seqExample.dft.
6.8
Rev. December 2009
7A
GTNETGSE
( rtds_ctl_GTNET_GSE_v2.def )
The GTNETGSE component provides IEC 61850 GSSE or GOOSE communications using the GTNET hardware. The GTNETGSE component can be configured
to send GSSE or GOOSE messages containing the status from up to 64 binary output
points from the simulator. The GTNETGSE can be configured to receive GSSE or
GOOSE messages from 8 unique external Intelligent Electronic Devices (IEDs) for
a total number of 64 binary inputs. The GTNETGSEcan also be configured to send
and receive up to 8 analog GOOSE messages. The GOOSE communication also provides access to the data Quality bitmap and the header Test, and Needs Commissioning (NdsComm) flags for both transmit and receive messages. The receive Time Allowed To Live (TATL) check can also be done per GOOSE message, when enabled
this option determines if each configured GOOSE input is receiving data from the
external IED, providing an on/off status.
The GTNET is connected to the RTDS simulator through one GTIO port on a GPC.
It is connected to external IEDs through the GTNET Ethernet port. The typical setup
is shown in the figure below, refer to the GTNET chapter of the RTDS Hardware
Manual for more information. Some terminology in this section is specific to the IEC
61850 standards, it is recommended that the user be familiar with the 61850 standards before proceeding.
For more information on the GTNET IEC 61850 implementation read the conformance statments found in Appendix B of the SCD Editor manual.
7A.1
GTNET GSE
EXTERNAL DEVICES
(IEDs)
GPC
ETHERNET SWITCH
GTNET
NOTE: GOOSE and GSSE peertopeerhigh speed nonconnection oriented communication is supported. The GTNET does not support IEC 61850 client/server connection oriented communication.
7A.1 GOOSE MODE
GOOSE communication is configured using an IEC 61850 Substation Configuration
Language (SCL) Substation Configuration Description (SCD) file. RSCAD contains
an embedded IEC 61850 System Configuration Tool that is used to generate the SCD
file. For more information on the SCD Editor select the help menu option from the
SCD Editor main menu.
Rightclicking on the component will provide a menu with a choice to start the SCD
Editor, within the SCD Editor an IED Capabilities Description (ICD) file for the
GTNETGSE can be exported and is used to specify the GTNETGSE to other system configuration tools. The logical functionality of the GOOSE mode of the
GTNETGSE is shown in the following figure (only binary points are shown).
GOOSE Message to Network

OUT_GGIO1 to OUT_GGIO64
From
Network
To
Network
Network
GOOSE Message from

external IED
GOOSE <> B_IN_GGIO

Mapping
16bit RTDS word

16bit RTDS word
Output words
16bit RTDS word

16bit RTDS word
32bit RTDS word
32bit RTDS word
Input words
There can be 4 GOOSE messages, the dataset name is fixed and the dataset members
can be 16 binary or 16 binary and 2 analogs per each GOOSE message from the
GTNET . The ICD file can be generated in draft by placing the cursor on the component using the right click menu or exporting the ICD in the SCD Editor. The dataset
contains a boolean status value (stVal) and a bitstring quality (q) for each of the 16
binary and 2 analog for a total of 36 data entries including detailed quality.
7A.2
GTNET GSE
The 64 binary inputs on the GTNET are represented in the SCL file by logical nodes
(LN) B_IN_GGIO1 to B_IN_GGIO64. The ExtRefs for the LN can have a data attribute (DA) of type BOOLEAN or INT. If multiple DAs are specified in the input
element, exactly one DA must have a daName of stVal. If only a single DA ExtRef
is specified, it will used as the input, regardless of the the daName. All other DA,
including the q DA are ignored by the GTNET when qualities are disabled by parameter eTNQ.
When GOOSE messages are received from external IEDs, the GTNET performs filtering based only upon the destination multicast address and APPID. All other fields
in the GOOSE message except the data entries are ignored. For this reason, each
unique GOOSE message sent by an external IED must be sent to a unique multicast
address.
The SCD editor shows the external references of the first 15 inputs using the
StVal and quality part of the GOOSE message from two different IEDs.
7A.3
GTNET GSE
The 8 analog inputs on the GTNET are represented in the SCL file by logical nodes
(LN) A_IN_GGIO1 to A_IN_GGIO8. The ExtRefs for the LN can have a DA of type
mag.f indicating it is the floating point deadbanded value.
The 8 analog outputs (2 per GOOSE message) have a fixed sample rate (smpRate)
of 10 Hz and can only be floating point values. In the following GTNETGSEanalog
input list example the IED_Y.CTRL.A_OUT_GGIO1.AnIn.mag.f will be mapped
to A_IN_GGIO1.
The SCD file must contain a GSE entry for the GTNET in the Communication section. In particular, it must contain address entries for MACAddress, APPID,
VLANPRIORITYand VLANID. It must also include a MaxTime entry. The APPID for GOOSE is a hexadecimal value ranging from 0 to 3FFF. The VLAN
PRIORITY ranges from 0 to 7. VLANID is a hexadecimal value ranging from 0
to FFF. The range for the MaxTime entry is 1000 to 30000 msec, rounded to the nearest second.
Within the GSEControl element in LN0, only the confRev and appID (also known
as goID) fields are configurable. The value for confRev is an integer ranging from
2,147,483,648 to +2,147,483,647. The value for appID is a string up to 11 characters in length.
The GTNET can be configured to provide access to the transmit and receive data
Quality bitmap , header Test, and header Needs Commissioning flags. The 13 bits
of the data Quality bitmap can be selectively enabled or disabled. The following table
shows the quality bit mapping.
GOOSE Quality Bitmap Name
Value / Value Range
Validity Bit 0
good | invalid | reserved | questionable
Validity Bit 1
detailQual overflow
boolean
detailQual outOfRange
boolean
detailQual badReference
boolean
detailQual oscillitory
boolean
detailQual failure
boolean
detailQual oldData
boolean
detailQual inconsistent
boolean
detailQual inaccurate
boolean
Source
process | substituted
Test
boolean (default False)
OperatorBlocked
Two flags in the GOOSE message header can be dynamically changed, they are
the global Test and Needs Commissioning flags for each of the output multicast
messages.
7A.4
GTNET GSE
GOOSE Header Name
Value / Value Range
Test
Needs Commissioning
A 32bit word will contain binary outputs 132 and a second 32bit word will
contain information for binary outputs 3364. A third 32bit word will contain
information for the analog outputs 18.
The following tables shows a summary of input and output signal names for the
binary, analog, quality, test, and needs commissioning points.
Input and Output Signals:
Wired Input signals for the GOOSE component
Signal
Description
Test
4 bits to control the header Test Flag of Integer

GOOSE messages
bit 0 TX1
bit 1 TX2
bit 2 TX3
bit 3 TX4
NdsComm
4 bits to control the header Needs

Commssioning Flag of GOOSE messages
Integer
bit 0 TX1
bit 1 TX2
bit 2 TX3
bit 3 TX4
GOOSE 1
GOOSE TX Message 1 16 bits
16bit
Analog11
GOOSE TX Message 1 analog 1
Float
Analog12
Float
GOOSE 2
16bit
Analog21
Float
Analog22
Float
GOOSE 3
16bit
Analog31
Float
Analog32
Float
GOOSE 4
16bit
Analog41
Float
Analog42
Float
Format
Wired Output signals for the GOOSE component

7A.5
GTNET GSE
Signal
Description
Format
132
GOOSE External References 132
32bit
3364
GOOSE External References 3364
32bit
A1
GOOSE External analog point
Float
A2
Float
A3
Float
A4
Float
A5
Float
A6
Float
A7
Float
A8
Float
External Variable Input/Output signals for the GOOSE component

Signal Type
Number of Signals
Data Quality
39 words for inputs, 39 words for outputs
Test (subscriber)
3 words for inputs, not used for outputs
Needs Commissioning (subscriber) 3 words for inputs, not used for outputs
TATL expired (subscriber)
3 words for inputs, not used for outputs
NOTE: Enabling test, needs commisioning, quality, and TATL will require 87
variables; increasing the time step for larger execution time and backplane
transfers.
7A.1.1 GOOSE SCL XML PREVIEW
NOTE: SCL is an XML based readable text file format defined by part 6 of the
IEC 61850 standard.
The following is an example of a GSE element for the GTNETGSE:
<Communication>
<SubNetwork name=net1>
<ConnectedAP iedName=GSE1 apName=P1>
<GSE ldInst=CTRL cbName=GOOSE_outputs_control>
<Address>
000
4
010CCD010101
0003
</Address>
<MinTime unit=s multiplier=m>10</MinTime>
<MaxTime unit=s multiplier=m>2000</MaxTime>
</GSE>
<GSE ldInst=CTRL cbName=GOOSE_outputs_control2>
<Address>
7A.6
GTNET GSE
</Address>
<MinTime unit=s multiplier=m>10</MinTime>
</GSE>
</ConnectedAP>
</SubNetwork>
...
The following is an example of a GSEControl element.

<GSEControl name=GOOSE_outputs_control datSet=GOOSE_outputs confRev=1
appID=1 />
The following is an example of a binary input list for the GTNETGSE.In this example SEL_421_1.ANN.CCOUTGGIO21.Ind01.stVal will be mapped to
B_IN_GGIO1 and also SEL_421_1.ANN.CCOUTGGIO21.Ind01.q which is the
quality part of the GOOSE message.
<LN desc= lnType=IED_A/CTRL/LPHD1 lnClass=LPHD inst=1/>
<LN inst=1 desc=Binary Input 01 (bit 00) to GTNET prefix=B_IN_ lnClass=GGIO lnType=IED_A/CTRL/GGIO_BIN>
<Inputs>
<ExtRef iedName=SEL_421_1 ldInst=ANN prefix=CCOUT lnClass=GGIO lnInst=21 doName=Ind01 daName=stVal/>
<ExtRef iedName=SEL_421_1 ldInst=ANN prefix=CCOUT lnClass=GGIO lnInst=21 doName=Ind01 daName=q/>
</Inputs>
</LN>
In the following GTNETGSE analog input list example the

IED_Y.CTRL.A_OUT_GGIO1.AnIn.mag.f will be mapped to A_IN_GGIO1.
<LN desc=Analog Input 01 to GTNET lnType=IED_X/CTRL/GGIO_AIN lnClass=GGIO inst=1 prefix=A_IN_>
<Inputs>
<ExtRef iedName=IED_Y ldInst=CTRL prefix=A_OUT_ lnClass=GGIO lnInst=1 doName=AnIn daName=mag.f/>
</Inputs>
</LN>
7A.2 GSSE MODE

GSSE communication is configured through the component properties. Inputs are
configured by identifying the external IEDs that send GSSE messages for the
GTNET and mapping the bits in the GSSE message to two 32bit input word bitmaps. Two 32bit output word bitmaps are mapped to specific GSSE bitpairs in the
output message. The logical functionality of the GSSE mode of the GTNETGSE
is shown in the following figure.
7A.7
GTNET GSE
GSSE Message to Network

32 DNA bitpairs + 96 UserSt Bitpairs
From
Network
To
Network
RTDS bit <>GSSE bitpair

Mapping
32bit RTDS word
32bit RTDS word
Network
GSSE Message from external IED

32 DNA bitpairs + 96 UserSt Bitpairs
GSSE bitpair/Multicast Addr <> RTDS bit

Mapping
32bit RTDS word
32bit RTDS word
Output words
Input words
7A.3 RSCAD DRAFT COMPONENT AND PARAMETER ENTRIES

The RSCAD Draft component used for GTNETGSE is named
_rtds_GTNET_GSE_v2.def and can be found in the MLIB/RPC/CTLS directory.
The figures below illustrate the menus used for the GTNETGSE component.
The configuration tab is common to both GSSE and GOOSE modes. It is used to
identify the GTNET hardware in the system and select the protocol.
Within the configuration menu the following items must be specified:

Port The port number of the GTIO fiber port of the GPC card that the GTNET is
connected to.
Card The number of the GTNET card on the GPC GT peripheral chain. 1 refers
to the first GTNETGSE on the GT peripheral chain, 2 refers to the second
GTNETGSE on the GT peripheral chain.
Trans The mode of the GTNETGSE. This setting controls additional tabs specific
to each communication protocol.
IECver The version of the IEC Standard. This setting controls the behavior of the
communication protocol, edition 1 is only supported.
7A.8
GTNET GSE
prtyp The type of processor card to assign this model to.
Proc The controls processor to assign this model to.
Pri The priority level for this component.
GOOSE CONFIGURATION
The GOOSE configuration tab is used to specify the IEC 61850 configuration for the
GTNET IED.
Fname The name of the SCL file that describes the GTNET GOOSE inputs and
configuration. This SCD file is generated by the embedded RSCAD IEC 61850
System Configuration Tool. Rightclicking on the component will provide a menu
with a choice to start the SCD editor.
Vlevel Set to generate a log file for each GTNET when parsing the SCL file. The
log file is called iedNamegoose.log and is located in the current working directory.
sfx Specifies the suffix to be added to the input and output signal names. If specified
the suffix is concatenated onto the default signal names.
eTNQ Enables the the transmit and receive Quality bitmap , Test, and Needs
Commissioning points.
eTATL Enables the the receive Time Allowed to Live check for each GOOSE input.
IEDName Specifies the IED Name of the GTNET in the SCL file. Default name
is TEMPLATE and the user is required to change the name.
NOTE: The remaining parameters are normally controlled with the SCD Editor, but
7A.9
GTNET GSE
are enabled when a new TEMPLATE of the GTNET is added from the component
library.
TX1EN Enables the 16 bit multicast message 1.
iAout Enables the analog outputs, 2 per each multicast message for a total of 8.
iBin Specifies the number of Binary Inputs, 32 or 64.
iAin Specifies the number of Analog Inputs, 0 8.
GOOSE Binary Output 132 Signal Names
The GOOSE Binary Output configuration tab specifies the signal names used to
access the quality bitmap of the GTNET binary outputs message 1 and 2. There are
16 binary dataset members per 4 available GOOSE messages for a total of 64 binary
points.
Parameters nTX1b0q through nTX1b12q are 32bit word variables used to send the
GOOSE (quality) information to the external IEDs. The first 16 bits are for outputs
1 16, and the second 16 bits are for outputs 17 32. The input Test is used to set
the TEST flag of the GOOSE message, a 4bit word controls the TEST flag in
GOOSE messages 1 through 4. The input NdsComm is used to set the Needs
7A.10
GTNET GSE
Commissioning flag of the GOOSE message, a 4bit word controls the Needs
Commissioning flag in GOOSE messages 1 through 4.
The tab GOOSE Binary Output 3364 Signal Names is similiar as above and is
shown if TX3EN or TX4EN is enabled.
The MMS Ethereal capture of a GOOSE message from the GTNET shown next is
used to analyze the GOOSE information on the Ethernet. The header Test flag is set
to FALSE, the header Needs Commissioning flag is set to FALSE, the number of
dataset members is 36 meaning there are 16 binary points, each with a stVal and q
attribute, plus 2 analog points each with mag.f and q attribute. The 36 members are
16 binary with StVal and Quality (16x2=>32 members) and 2 analog with mag.f and
Quality (2x2=>4 members). The Quality information shows all 0s (default). The first
Boolean item shows FALSE and the second Boolean item shows TRUE.
GOOSE Analog Output 18 Parameter/Signal Names

The GOOSE Analog Output configuration tab specifies the parameters to set the
deadband for each input and specify the signal names used to access the quality
bitmap of the GTNET analog outputs. There are 2 analog GOOSE dataset members
per GOOSE message for a total of 8 analog points. The analog points are sampled
at a fixed rate of 10Hz. An optional trigger signal can be used to signal when the
analog points are being sampled by the GTNET.
7A.11
GTNET GSE
External floating point variables are used to send the deadbanded GOOSE (mag.f)
information to external IEDs. Parameter dTX1a1, minTX1a1, and maxTX1a1 are
used to calculate a deadband used to specify the absolute difference between samples
necessary to indicate a change in the GOOSE dataset item. Parameters nAO1b0q
through nAO1b12q are 8bit word variables used to send the GOOSE (quality)
information to the external IEDs. The 8 bits are for outputs 1 8, the Test and Needs
Commissioning flags are a global portion of the 4 GOOSE messages and set by the
appropriate bit.
deadband =
dTX1a1
* (maxTX1a1 - minTX1a1)
100.0
The deadband for each analog point is calculated as shown above, with the
appropriate parameters for each point (point 1 is shown).
GOOSE Output Quality, Test, NdsComm Bitmap Enables
7A.12
GTNET GSE
This tab is available when parameter eTNQ is enabled and provides control for each
of the data quality bits, test, and needs commissioning flags. Enabling a point in the
quality bitmap requires a signal name (word variable) containing the information for
that particular point.
For example if TX1EN, TX2EN, TX3EN,TX4EN, and iAout are enabled and
eTXQ0 is enabled then 3 external variables would be required to provide the values
for quality bit 0 in the 4 GOOSE messages sent by the GTNET. These variables
would be referenced to the GTNET with parameters nTX1b0q, nTX2b0q, and
nAO1b1q.
GOOSE Binary Input 132 Signal Names
The GOOSE Binary Input configuration tab specifies the signal names used to access
the binary information of GOOSE messages received by the GTNET. There are 2
x 32 bits input signal names for a total of 64 binary points on outputs 132 and
3364. The GTNET can listen for GOOSE messages from up to 8 unqiue IEDs,
the SCD editor is used to map the messages from the external IEDs. The ExtRefs
for the B_IN_GGIO LN can have a DA of type BOOLEAN or INT.
Output 132 receives the first 32 external binary points and output
3364receives the second 32 eternal binary points. Outputs A1 though A8 receive
the 8 external analog points. Parameters nBI1q0 through nBI1q12 are 32bit word
variables used to receive the GOOSE (quality) information from the external IEDs.
Parameter nBI1gt is a 32bit word variable used to receive the Test flag of the
GOOSE messages. Parameter nBI1nc is a 32bit word variable used to receive the
Needs Commissioning flag of the GOOSE messages.
The tab GOOSE Binary Input 3364 Signal Names is similiar and is shown if iBin
is set to 64.
7A.13
GTNET GSE
Parameter nBI1TATL specifies the 32bit word variable that is used to indicate the
presence of the external GOOSE message mapped to each of the GTNET inputs. The
Time Allowed to Live portion of a GOOSE message contains a value of time that the
message is valid. The publisher must send the GOOSE message within the TATL
value, if the message is not received by the GTNET the appropriate bit is turned OFF.
GOOSE Analog Input 18 Signal Names

The GOOSE Analog Input configuration tab specifies the signal names used to
receive the analog information from external IEDs. The GTNET can listen to a
maximum of 8 GOOSE analog points.
Outputs A1 through A8 are used to receive the GOOSE analog information.
Parameters nAI1q0 through nAI1q12 are 8bit word variables used to receive the
GOOSE (quality) information from the external IEDs. Parameter nAI1gt is an 8bit
word variable used to receive the Test flag of the GOOSE messages. Parameter
nAI1nc is an 8bit word variable used to receive the Needs Commissioning flag of
the GOOSE messages.
Parameter nAI1TATL specifies the 8bit word variable that is used to indicate the
presence of the external GOOSE message mapped to each of the GTNET inputs. The
Time Allowed to Live portion of a GOOSE message contains a value of time that the
message is valid. The publisher must send the GOOSE message within the TATL
value, if the message is not received by the GTNET the appropriate bit is turned OFF.
7A.14
GTNET GSE
GOOSE Input Quality, Test, NdsComm Bitmap Enables

This tab is available when parameter eTNQ is enabled and provides control for each
of the data quality bits, test, and needs commissioning points. Enabling a point
requires a signal name (word variable) containing the information for that particular
point.
7A.15
GTNET GSE
GSSE CONFIGURATION
The GSSE configuration menu is used to define the overall parameters for GSSE
operation such as the number of external IED and number of input/output bits.
Dev The number of external IEDs that the GTNET will receive messages from.
Ibits The number of bits received from GSSE messages
Obits The number of bits sent in the GSSE output message
Uptim Defines the maximum time to wait before retransmitting GSSE messages.
udmc Enables a user specified TX multicast address. Default is to use the physical
MAC address ofthe GTNET and replace the first 2 bits to 01 which defines a
multicast message.
MACH Enter the 3 most significant bytes in hex of the multicast address that the
GTNET will send GSSE messages to.
MACL Enter the 3 least significant bytes in hex of the multicast address that the
GTNET will send GSSE messages to.
GsID Enter the name of the GSSE messages that the GTNET will use.
7A.16
GTNET GSE
EXTERNAL IED #n
An external IED #n identification tab is provided to identify each external device
from which the GTNETGSE will receive messages.
EDMAnH Enter the 3 most significant bytes in hex of the multicast address that the
external IED is sending GSSE messages to.
EDMAnL Enter the 3 least significant bytes in hex of the multicast address that the
external IED is sending GSSE messages to.
INPUT BIT DEFINITION

The input bit definition tab(s) are used to map the bitpairs received in GSSE
messages from external IEDs into the 64 input bits that the GTNETGSE presents
to RTDS control components as inputs. The number of input bits is specified in the
GSSE configuration tab. The 64 inputs are put into two 32 bit word outputs from the
component.
Idevn Specify the external IED that transmits the message to be mapped to RTDS
input bit #n.
Ibitn Specify the GSSE bitpair to map to RTDS input #n. GSSE messages contain
32 DNA bitpairs and 64 UserSt bitpairs. To monitor DNA bitpairs, enter a value from
7A.17
GTNET GSE
132. To monitor UserSt bitpairs, enter a value from 3396 for bitpairs 164
respectively.
OUTPUT BIT DEFINITION
The output bit definition tab(s) are used to map the 64 output bits from RTDS control
components into a single GSSE message. The 64 outputs are taken from two 32 bit
word inputs from the component.
Obitn Specify the GSSE bitpair that RTDS output bit #n is mapped to. GSSE
messages contain 32 DNA bitpairs and 64 UserSt bitpairs. To set DNA bitpairs, enter
a value from 132. To set UserSt bitpairs, enter a value from 3396 for bitpairs 164
respectively.
7A.4 GSSE/GOOSE SPECIFICATIONS
For more complete specifications see the hardware manual and conformance
statements.
Latency:
GSSE input < 1 ms.

GOOSE input < 500 us + 50us for each data entry
GOOSE output < 1 ms
Execution Time
GPC
0.053
us
GSSE Protocol
0.684
us
GOOSE without Test, NdsComm,

Quality, TATL
13.375
us
GOOSE with either Test, NdsComm,

Quality, TATL
7A.18
Rev. 0.2 March 2014
7AX
GTNETGSE
( _rtds_GTNET_GSE_v5.def )
The GTNETGSE component provides IEC 61850 GOOSE communications using

the GTNET hardware. The GTNET_GSE component supports up to 4 RX/TX modules. The modules can be arranged to model 14 IEDs (Intelligent Electronic Devices). For example, the GTNETGSEcould be set up as a single IED with 4 RX/TX
modules or as a 4 IEDs, each with a single RX/TX module. Each module can send
up to 64 points or 32 points plus quality bitmaps for each point. Each module can
receive up to 32 points each with an associated quality bitmap or up to 64 points if
quality bitmap support is not required. The GOOSE messages can be received from
a total of 16 unique external IEDs. The GOOSE communication provides access to
the data Quality bitmap and the header Test, and Needs Commissioning (NdsComm)
flags for both transmit and receive messages. A Time Allowed To Live (TATL)
check can also be performed per received GOOSE message. When enabled, this option determines if each configured GOOSE input is receiving data from the external
IED, within the timeout specified by the TATL in the last received GOOSE message.
The GTNET is connected to the RTDS simulator through one GTIO port on a GPC/
PB5. It is connected to external IEDs through the GTNET Ethernet port. The typical
setup is shown in the figure below, refer to the GTNET chapter of the RTDS Hardware Manual for more information. Some terminology in this section is specific to
the IEC 61850 standards, it is recommended that the user be familiar with the IEC
61850 standards before proceeding.
EXTERNAL DEVICES
(IEDs)
GPC
ETHERNET SWITCH
GTNET
7Ax.1
GTNET GSE
NOTE: GOOSE peertopeer, high speed, nonconnectionoriented communication
is supported. The GTNET does not support IEC 61850 client/server connection oriented communication. GSSE mode is not supported by this version of GTNETGSE
component. For GSSE mode, use GTNETGSE v2.
7Ax.0 REQUIRED FIRMWARE
The following minimum version of RTDS firmware are required for use with
GTNETGSEv5:
5.15 GTNETGSE
4.103 build D GTWIF OS (WIF OS not supported)
v337 or v395 GPC FPGA
v19 PB5 FPGA
7Ax.1 GOOSE OVERVIEW
GOOSE communication is configured using an IEC 61850 Substation Configuration
Language (SCL) Substation Configuration Description (SCD) file. RSCAD contains an embedded IEC 61850 System Configuration Tool that is used to generate the
SCD file. For more information on the SCD Editor select the help menu option from
the SCD Editor main menu.
Rightclicking on the GSE component within Draft will provide a menu with a
choice to start the SCD Editor. Within the SCD Editor an IED Capabilities Description (ICD) file for the GTNETGSE can be exported and is used to specify the
GTNETGSE to other system configuration tools. The logical functionality of one
RX/TX module in the GTNETGSE is shown in the following figure.
GOOSE Message to Network

(OUT_GGIO1 to OUT_GGIO64)
From
Network
To
Network
Network
GOOSE Message from

external IED(s)
Mapping to RTDS input points

(IN_GGIO1 to IN_GGIO32)
Outputs
Inputs
The Draft component parameters for IED Name, LDName are used to associate each
RX/TX module with an IED, Logical Device and Logical Nodes within the SCD file.
The GSEControl field specifies the GSEControl block to be used for the TX GOOSE
message.
When transmitting GOOSE messages from the GTNET, the content in the GOOSE
messages by the GTNET is configured through the GTNET Draft component param-
7Ax.2
GTNET GSE
eters and/or the RSCAD SCD Editor. Each dataset can contain up to 64 points which
can be configured as Boolean, 32bit floating point (FLOAT32), 32bit integer
(INT32) or 13bit quality bitmaps (Quality).
The SCD file must contain a GSE entry in the Communication section for each logical GTNET IED. In particular, it must contain address entries for MACAddress,
APPID, VLANPRIORITY and VLANID. It must also include a MaxTime entry.
The APPID for GOOSE is a hexadecimal value ranging from 0 to 3FFF. The VLAN
PRIORITY ranges from 0 to 7. VLANID is a hexadecimal value ranging from 0
to FFF. The range for the MaxTime entry is 1000 to 30000 msec, rounded to the nearest second. The GTNETGSE v5 component has a feature where the retransmit timer, the time allowed to live/maxTime and the VLAN priority can be specified for each
point on a 10 point retransmit curve. See the settings for the Output Retransmit Curve
for more information. The following is an example of a GSE element for the
GTNET_GSE:
<Communication>
<SubNetwork name=TEST_NETWORK>
<ConnectedAP iedName=IED_A apName=P1>
<Address />
<GSE ldInst=CTRL cbName=GOOSE_outputs_control>
<Address>
</Address>
</GSE>
</ConnectedAP>
...
Within the GSEControl element in LN0, the confRev, appID and datSet fields are
configurable. The value for confRev is an integer ranging from 2,147,483,648 to
+2,147,483,647. The value for the appID and datSet fields are strings up to 32 characters in length. The RTDS SCD Editor should be used to modify these fields to ensure all references within the SCD file remain consistent. The following is an example of a GSEControl element.
<GSEControl name=GOOSE_outputs_control datSet=GOOSE_outputs confRev=1 appID=1 />
OUTPUTS
Each RX/TX module can transmit up to 64 points of any type. When quality bits are
required in the TX messages, the maximum is 32 points of any type plus a quality
bitmap associated with each point. Output points which are configured as 32bit
floating point are checked against a deadband to determine if the point value has
changed significantly enough to generate a new GOOSE message. For each
GTNETGSE component, there are 16 sets of output deadband settings. Floating
point outputs are associated with 1 of the 16 analog deadband settings (FLOAT1 to
FLOAT16).
The 64 output points in each logical GTNET RX/TX module are represented in the
SCL file by logical nodes (LN) OUT_GGIO1 to OUT_GGIO64, for the first RX/TX
7Ax.3
GTNET GSE
module, 65128 for the second RX/TX module, 129192 for the third RX/TX module and 193256 for the fourth RX/TX module. When quality bitmap support is enabled (eTNQ=1), only 32 GGIO logical nodes are present, but a q bitmap can be sent
for each point. The output dataset can be constructed of FCDA references to these
logical nodes. The RTDS SCD Editor must be used to construct the dataset. When
the IED name has been changed from the default TEMPLATE, the component parameters are no longer editable through the component and the SCD Editor must be
used to change the output type and/or disable the output using the DataSet editor.
INPUTS
When receiving points from up to 16 unique external IED GOOSE messages, up to
32 points plus associated quality bitmaps can be received by each GTNET RX/TX
module. A quality bitmap (q) may be received for each point. In addition, the test
and NdsComm bits from the received GOOSE message and a rx message timeout can
be enabled for each received point. When quality bitmap support is not required, an
additional 32 Boolean points can be received.
Note: The GTNET is limited to process up to 128 dataset items in a GOOSE message. Items greater than 128 are not processed and error checking has been added
since RSCAD 4.001
The 32 or 64 input points in each logical GTNET RX/TX module are represented in
the SCL file by logical nodes (LN) IN_GGIO1 to IN_GGIO64, for the first RX/TX
module, 65128 for the second RX/TX module, 129192 for the third RX/TX module and 193256 for the fourth RX/TX module. The inputs are configured using the
<Inputs> and <ExtRef> elements of the GGIO LN the SCL file. The RTDS SCD
Editor must be used to configure the GTNET inputs. The first 32 IN_GGIO for each
RX/TX module can be configured as either a 32bit integer or 32bit floating point
within the RTDS. This type is automatically set by the SCD Editor when points are
mapped. The second 32 IN_GGIO for each module, when enabled, are represented
in the RTDS only as Boolean bits. The ExtRefs for the first 32 IN_GGIO points may
have a 61850 Data Attribute (DA) of type Boolean, Dbpos, ENUMERATED, INT8,
INT16, INT32, or FLOAT32. The ExtRefs for the second IN_GGIO may have a DA
of type Boolean, INT8, INT16 or INT32. When receiving integer or Dbpos data for
Booleanonlypoints, the least significant bit is used as the Boolean value. The RTDS
SCD Editor inserts a <Private> subelement in the <Inputs> element which is used
to umbrageously specify the source of the GOOSE message, in cases where an ExtRef may exist in multiple GOOSE messages from the same IED.
When receiving GOOSE messages from external IEDs, the GTNET performs filtering based upon the destination multicast address and the message APPID. All other
fields in the received GOOSE message, except the data entries, are ignored. For this
reason, each unique GOOSE message sent by an external IED must be sent to a
unique multicast address and/or APPID. Multicast address filtering is performed in
hardware. APPID filtering is performed by software.
7Ax.4
GTNET GSE
7Ax.5
GTNET GSE
7Ax.2 Quality Bitmaps
The GTNET can be configured to provide access to Quality bitmaps sent and received in GOOSE messages. For reference, the following table shows the quality bit
mapping.
Bit number GOOSE Quality Bitmap Name
Value Range
Validity Bit 0
good | invalid | reserved | questionable
Validity Bit 1
detailQual overflow
boolean
boolean
boolean
detailQual oscillitory
boolean
detailQual failure
boolean
detailQual oldData
boolean
boolean
boolean
10
Source
process | substituted
11
Test
12
OperatorBlocked
7Ax.3 COMPONENT INPUT AND OUTPUT VARIABLES

The following tables shows a summary of input and output signal names for RX/TX
modules within the GTNETGSE Component.
COMPONENT OUTPUT VARIABLES
Signal
Description
Control/Format
nIEDxBI
Input 132 status when input is

boolean
Integer bitmap
bit 1 input 1
bit 2 input 2
bit 32 input 31
nIEDxI1
nIEDxI32
Input 1 input 32 value when input Integer, float or disabled

is nonboolean
Type selected by IEDxI1T IEDxI32T
nIEDxITATL
Input 132 TATL status

(1=OK, 0=timeout)
Integer bitmap
bit 1 input 1
bit 2 input 2
bit 32 input 32
Enabled/disabled by eTATL
nIEDxIq0
nIEDxIq12
Input 132 Quality bit status
Integer bitmap
bit 1 input 1
bit 2 input 2
bit 32 input 32
Enabled/disabled by eTNQ and
eRXQ0eRXQ12
7Ax.6
GTNET GSE
nIEDxIgt
Input 132 global Test flag status
Integer bitmap
bit 1 input 1
bit 2 input 2
bit 32 input 32
Enabled/disabled by eTNQ and eRXGT
nIEDxInc
Input 132 NdsComm flag status
Integer bitmap
bit 1 input 1
bit 2 input 2
bit 32 input 32
Enabled/disabled by eTNQ and eRXNC
nIEDxBI2
Input 3364
Integer bitmap
bit 1 input 33
bit 2 input 34
bit 32 input 64
Only available when eTNQ=0
nIEDxITATL2
Input 3364 TATL status

(1=OK, 0=timeout)
Integer bitmap
bit 1 input 33
bit 2 input 34
bit 32 input 64
Enabled/disabled by eTATL
COMPONENT INPUT VARIABLES

Signal
Description
nIEDxO1
nIEDxO64
Output 1 output 32 variable name Integer, boolean, float116

float1 16 or disabled
Type selected by IEDxO1T IEDxO32T
nIEDxOgt
Output global Test flag control
Integer
Enabled/disabled by eTNQ and eTXGT
nIEDxOnc
Output NdsComm flag control
Integer
Enabled/disabled by eTNQ and eTXNC
nIEDxOq0
nIEDxOq12
Output132 Quality bit status
Integer bitmap
bit 1 output 1
bit 2 output 2
bit 32 output 32
Enabled/disabled by eTNQ and
eTXQ0eTXQ12
Output 33
Output 33 output 64 variable
output 64
name
variable name
Control/Format
Integer, boolean, float116 or disabled

Type selected by IEDxO33T IEDxO64T
Only available when eTNQ=0
NOTE: Enabling quality, Test, NdsComm, or TATL handling will increase the number of required variables in the simulation; increasing the time step due to longer execution time and increased number of backplane transfers. Care should be taken to
enable only variables that are utilized within the simulation.
7Ax.4 CUSTOM RETRANSMIT CURVE and DYNAMIC VLAN PRIORITY
The GTNETGSE component allows customization of the retransmission curve and
allows the VLAN priority to be set dynamically at each point on the curve. In most
7Ax.7
GTNET GSE
applications, customization is not required and the defaults should be used. The resolution of retransmission timers is approximately 2 msec.
The default retransmission follows the sequence:
4 msec, 8 msec, 16 msec, 32 msec, 64 msec, 128 msec, 256 msec, 500 msec, 1000
msec, 2000 msec ... up to the MaxTime parameter read from the SCD file. The holdTime parameter in the GOOSE message is set to 3x the retransmit time for all points
on the curve up to the default retransmit point (MaxTime), and 2x the retransmit for
default retransmissions.
7Ax.5 RSCAD DRAFT COMPONENT AND PARAMETER ENTRIES

The RSCAD Draft component used for GTNETGSEv5 is named
_rtds_GTNET_GSE_v5.def and can be found in the MLIB/CTLS_V2/IO directory.
The figures below illustrate the menus used for the GTNETGSE component.
CONFIGURATION
The configuration tab is used to identify the GTNET hardware in the system and enable the synchronization to the GTSYNC, if desired.
Within the Configuration menu the following items must be specified:

sCompName Specifies the name of this GTNETGSE component for use in errors
and RTDS compiler messages. This parameter has no relationship with the IED
names used in the SCL file.
Port The port number of the GTIO fiber port of the GPC/PB5 card that the GTNET
is connected to.
Card The number of the GTNET card on the GPC GT/PB5 peripheral chain. 1
refers to the first GTNETGSE on the GT peripheral chain, 2 refers to the second
7Ax.8
GTNET GSE
GTNETGSEon the GT peripheral chain. The GTNETGSEv5 component can not
be daisychained, so this parameter is fixed at 1.
prtyp The type of processor card to assign this model to.
IECver The version of the IEC 6185081 standard. This setting controls the
behavior of the communication protocol. Only IEC 6185081 Edition 1 is
supported.
TSYNCEN Set this field to yes if a GTSYNC is available and synchronized to an
external time sync signal. The time sync is used to accurately timestamp the
GOOSE messages. If no GTSYNC is available, the time in the GTNETGSE can
be synchronized via SNTP. If no SNTP server is available, the time in the GOOSE
messages will be incorrect.
GT_SOC and GT_STAT When TSYNCEN is set to yes, these fields must be set to
the signal names of the nam1 and nam2 signals specified in the GTSYNC Draft
component. nam1 and nam2 are typically set to ADVSECD and ADVSTAT.
GOOSE CONFIGURATION
The GOOSE Configuration tab is used to specify the IEC 61850 configuration for
the GTNET IED.
Fname The name of the SCL file that describes the GTNET GOOSE inputs and
configuration. This SCD file is generated by the embedded RSCAD IEC 61850
System Configuration Tool. Rightclicking on the component will provide a menu
with a choice to start the SCD editor.
7Ax.9
GTNET GSE
Vlevel Set to generate a log file when parsing the SCL file. The log file is called
sCompNamegoose.log and is located in the current working directory for the Draft
case.
sfx Specifies the suffix to be added to the input and output signal names. If specified
the suffix is concatenated onto the default signal names.
eTNQ Enables the the transmit and receive Quality bitmap , Test, and Needs
Commissioning points. When disabled (eTNQ=0), allows additional 32 Boolean
GOOSE inputs and 32 additional GOOSE outputs
eTATL Enables the the receive Time Allowed to Live check for each GOOSE input.
OUTPUT DEADBAND PARAMETERS

The Output Deadband Parameters tab is used to specify the deadbands for floating
point signals with types FLOAT1 to FLOAT16 in transmitted GOOSE messages.
The deadband sets the amount of change in the floating point signal which will cause
a the data in the GOOSE message to be updated and a new sequence of GOOSE
messages to be sent. Setting the deadband too low will cause excessive GOOSE
messages to be sent. Setting the deadband too high will suppress the updating of
floating point values in the GOOSE message. Parameter dA1, minA1, and maxA1
are used to calculate a deadband used to specify the absolute difference between
samples necessary to indicate a change in the GOOSE dataset item.
FLOAT1 _ deadband
dA1
* ( maxA1 - minA1)
100.0
The deadband for each analog point is calculated as shown above, with the
appropriate parameters for each point (FLOAT1 is shown).
7Ax.10
GTNET GSE
dAn Deadband in percent for output points with type FLOATn

minAn/maxAn Minimum and maximum values of output points with type FLOATn
IED x GENERAL CONFIGURATION
sIEDxName14 Specifies the IED Name of this RX/TX module in the SCL file.
Longer IED names need to be broken into parts. A * in a sIEDxName field indicates
that the string is empty and terminates the IED Name regardless of the content of
subsequent fields. For example if sIEDxName1 = IED1234567,
sIEDxName2=ABCD, sIEDxName3 = *, and sIEDxName4 = efg, the IED
Name string will be IED1234567ABCD.
7Ax.11
GTNET GSE
sIEDxLDINST14 Specifies the Logical Device instance (LDInst) of this RX/TX
module in the SCL file. Similar string construction rules as the sIEDxName
parameters applies.
sIEDxGSEName4 Specifies the GSEControl name of this RX/TX module in the
SCL file. Similar string construction rules as the sIEDxName parameters applies.
IED x OUTPUT RETRANSMIT CURVE
The GTNETGSE component allows customization of the retransmission curve and

allows the VLAN priority to be set dynamically at each point on the curve. In most
applications, customization is not required and the defaults should be used. The
resolution of retransmission timers is approximately 2 msec.
IEDxCRTC Enable custom retransmit curve and dynamic VLAN priority. If set to
7Ax.12
GTNET GSE
no, the default retransmit curve is used and the VLAN priority is read from the SCD
file. See section Custom Retransmit Curve and Dynamic VLAN priority for more
details.
IEDxRTTO19 Specify the retransmission timeout for each point on the retransmit
curve
IEDxRTTO10 Specify the default retransmission timeout used for retransmitting
sequence number 10 and above
IEDxHT08 Specify the HoldTime value used for GOOSE messages with sqNum
08
IEDxHT9 Specify the HoldTime value used for GOOSE messages with sqNum 9
and higher
IEDxVP08 Specify the VLAN priority used for GOOSE messages with sqNum
08
IEDxVP9 Specify the VLAN priority used for GOOSE messages with sqNum 9 and
higher
RX/TX x OUTPUT SIGNAL NAMES/TYPES
The RX/TXx Output Signal Names/Types configuration tab specifies the signal
names and types used for the output signals for a GTNETGSE RX/TX module.
Normally, the signal type fields in this tab (IEDxO1T, IEDxO2T...) are managed by
the RSCAD SCD Editor and reflect the signals types specified in the output dataset
for this IED.
IEDxO1T IEDxO64T Specify the type of each of the generictypeoutputs for this
IED. The type can be integer, boolean or deadbanded floating point
(FLOAT1FLOAT16). This setting is controlled by the SCD Editor based on the
7Ax.13
GTNET GSE
type selected in the output dataset editor and is user configurable after the IED name
has changed from TEMPLATE.
IEDxO1B IEDxO64B Specify the bit number for each outputs when the type of
the output is boolean. Bit 1 is on the right of the bitmap.
nIEDxOgt Specify the signal name for the global Test flag in the GOOSE message
transmitted by this RX/TX module. The Test flag is located in the header of the
GOOSE message and there is only one of these Test flags in each message. This Test
flag is unique from from the quality bit 11 which is also called Test.
nIEDxOnc Specify the signal name for the NeedsCommissioning flag in the
GOOSE message transmitted by this RX/TX module. The NeedsCommisioning flag
is located in the header of the GOOSE message and there is only one of these
NeedsCommissioning flags in each message.
RX/TX x INPUT SIGNAL NAMES/TYPES
The RX/TX x Input Signal Names/Types configuration tab specifies the signal
names and types used for the input signals for a GTNETGSE RX/TX module.
Normally, the signal type fields in this tab (IEDxI17T, IEDxI18T...) are managed by
the RSCAD SCD Editor and reflect the signals which have inputs mapped to them.
nIEDxBI Specify the signal name for the binary input bitmap used when mapped
points have a type of Boolean. Used for inputs 132 of this RX/TX module. This
signal is an integer with binary input 1 as bit 1, binary input 2 as bit 2, binary input
32 as bit 32. Bit 1 is on the right.
nIEDxBI2 Specify the signal name for the binary input bitmap used for binary
inputs 3364 of this RX/TX module. This signal is an integer with binary input 33
as bit 1, binary input 34 as bit 2, binary input 64 as bit 32. Bit 1 is on the right. Only
enabled when eTNQ=0
7Ax.14
GTNET GSE
IEDxI1T IEDxI32T Specify the type of each of the generictype inputs for this
RX/TX module. The type can be integer, boolean or floating point.
nIEDxIq0nIEDxIq12 Specify the signal name for the input bitmap for the quality
bits of inputs 132 of this RX/TX module when eTNQ=1. Each bitmap contains the
status of the individual quality bit for all 32 inputs. This signal is an integer with
quality bit for binary input 1 as bit 1, binary input 2 as bit 2, and binary input 32 as
bit 32. Bit 1 is on the right.
nIEDxIgt Specify the signal name for the input bitmap used for the Test flag of the
GOOSE message for inputs 132 of this RX/TX module. This signal is an integer
with the Test flag status for binary input 1 as bit 1, binary input 2 as bit 2, and input
32 as bit 32. Bit 1 is on the right.
nIEDxIgt Specify the signal name for the input bitmap used for the
NeedsCommissioning flag of the GOOSE message for inputs 132 of this RX/TX
module. This signal is an integer with the NeedsCommissioning flag status for
binary input 1 as bit 1, binary input 2 as bit 2, and input 32 as bit 32. Bit 1 is on the
right.
7Ax.6 GOOSE SPECIFICATIONS

For further specifications see the GTNET section of the RTDS Hardware Manual.
Nominal Latency: GOOSE input < 500 us + 35us for each decoded data entry
GOOSE output < 750 us
Execution Time
PB5
4.58
GPC
4.75
us
GOOSE without Test, NdsComm,

Quality, TATL
5.64
6.69
us
GOOSE with either Test, NdsComm,

Quality, TATL
Note: One published GOOSE with 1 Boolean, 1 Int32, 1 Dbpos and 1 Float32, together with one subscribed GOOSE with 1 Boolean, 1 Int32, 1 Dbpos and 1 Float32
are configured in the GTNETGSEv5 for the above execution time test.
7Ax.15
GTNET COMTRADE
file is not an optional file and must be included if proper playback is to be achieved.
The configuration file is denoted as <filename>.cfg
The Data File contains the data values for each channel for each sample point. The
numbers stored in the data file represent scaled values of the actual quantities recorded or produced during data capture. Conversion factors specified in the configuration file define how the stored points are converted to produce actual engineering
units. The data file is not an optional file and must be included if proper playback is
to be achieved. The data file is denoted as <filename>.dat
The Information File is an optional file which contains additional information that
producers and users of the COMTRADE data records may wish to communicate or
exchange in addition to that contained in the minimal data set. The information file
is denoted as <filename>.inf
The RTDS simulator GTNET COMTRADE playback facility is concerned only with
the two mandatory files, that is, the configuration file and the data file. These two
files must exist in the users RSCAD working directory whenever the playback facility is utilized. The GTNET COMTRADE component supports COMTRADE .dat
files in ASCII or BINARY format.
7B.2 RTDS FILES
Data points are read from the .dat file and scaled according to the information in the
.cfg file. The scaled data points are then stored in files with the same base name
as the COMTRADE data files with .pbk and .cnv filename extensions. The
.pbk and .cnv files are automatically generated during the RSCAD/Draft compile
process. The .pbk file is a compact binary data file used for playback. The .cnv
file is created for reference only. It contains the same data as the .pbk file, but can
be plotted using RSCAD MultiPlot. .cnv file creation can be disabled to allow fast
case compiling by changing the Gcnv setting.
A .par file is also created during the compile process. This file is used for error
checking to inform the user when the .pbk file needs to be regenerated. The format
of the .par file is as shown.
t pfcop lpfc #pnts
where:
t simulation time step in secs.
pfcop prefault cycle operation, 0=auto, 1=none, 2=manual
lpfc last data point in the prefault cycle
#pnts total number of data points read from .dat file
7B.2
GTNET COMTRADE
7B.3 LINEAR INTERPOLATION

Stored data associated with a particular channel in the COMTRADE data file corresponds to a sample taken at a specified instant in time. The elapsed time between
successive samples is referred to as the sample period. Because the RTDS simulator
will not necessarily be run at the same sampling rate ( ie: it may be shorter or longer
than the stored sampling rate ), some data processing must be performed. As part of
the preprocessing, linear interpolation is applied between successive points stored
in the original <filename>.dat file. The chosen RTDS simulation time step t is used
as a basis for the linear interpolation function.
The linear interpolation is done during the RSCAD/Draft compile process. The interpolated points are stored in the .pbk file, a binary file. A text file containing the
interpolated data can optionally be generated and stored in a .cnv file. Please refer
to Section 7b.7 for details on how to generate the above mentioned files.
The figure below illustrates how the interpolated output would look with respect to
the original data from the .dat file for a particular case.
time
sample period
Data points read from .dat file

Data points computed by interpolation
7B.4 DATA SCALING

COMTRADE analogue channel information from a .cfg file typically appears in
a format as shown.
7B.3
GTNET COMTRADE
An,ch_id,ph,ccbm,uu,a,b,skew,min,max,chratio
where:
An channel index number
ch_id channel identifier
ph phase identifier
ccbm circuit component being monitored
uu channel units
a channel multiplier
b channel offset
skew time skew
min minimum data value allowed
max maximum data value allowed
chratio primary to secondary conversion ratio
Data read from the .dat file is scaled by the channel multiplier (a) and channel offset
(b) from the .cfg file.
scaled data = .dat value * a + b
The scaled data is further processed based on the gain implied by the units (uu) and
the primary to secondary ratio (chratio).
scaled data = scaled data * gain / chratio
The scaled data is stored in the .pbk file as a 32bit floating point number.
Scaling of digital channels is not required.
There is no imposed limit to the .pbk file size although compiling very large files
(>100 MB) will take a number of minutes.
7B.5 OPERATING IN PRETRANSIENT ( PREFAULT ) AND POSTTRANSIENT
(POSTFAULT) DATA MODE
Normally the event stored in the COMTRADE file represents a transient condition
on the power system. In some cases a short interval of steady state ( or pre transient )
operation precedes the event being considered. The RTDS playback facility includes
a feature which allows playback of the pretransient state for a predetermined period of time as specified in the component LCNT variable. This variable controls the
number of times to playback the prefault data. The number of times to loop at the
end of prefault data is equal to LCNT1. Prefault data loops do not increase the
size of the .pbk and .cnv file.
The PRE variable controls the prefault data mode. When creating the .pbk file,
the RTDS compiler can be directed to automatically detect the last point of prefault
7B.4
GTNET COMTRADE
data by setting the PRE parameter to Auto. Setting the PRE parameter to Auto
enables a PREFAULT DATA menu. Operation in prefault mode can be useful
when interconnected external equipment is being initialized.
The algorithm used to define the prefaultdata detects the positivegoingzerocross
that occurs after the APFC setting value and then adjusts it by the offset to the first
positivegoing zerocross in the file. The SDAT setting specifies the beginning of
the pretransient data. If no prefault cycle can be detected, an Error message is issued and the user is advised to set the PRE variable to None, as described below.
The automatic PRETRANSIENT DATA option may be turned off by setting the
PRE variable to None or Manual in the RSCAD/Draft playback components
CONFIGURATION menu. The end of prefault data can be specified manually by
the user. Selecting Manual for the PRE variable creates a menu for the user to enter
the last data point of the interpolated prefault data.
The posttransient data is defined as all data in the file after the pretransient data.
It can be played back multiple times if desired by setting the PFDC field. Jumps in
the waveform can occur if the last sample in the file does not align properly with the
first sample of posttransient data. Looping in posttransient mode increases the
.pbk and .cnv file sizes because postfault data is replicated for each loop.
Once the stored event has been played back, all signal levels are immediately forced
to 0.0. Output will remain in this state until the case is restarted.
7B.6 PLAYBACK
The GTNET COMTRADE playback facility uses one GPC/PB5 processor for all
channels. Up to 8 independent channels can be supported through a single playback
component.
In addition to the GPC/PB5 processor card, the playback requires a Windows PC and
GTNET peripheral with GTNET_PLAYBACK firmware as shown below.
7B.5
GTNET COMTRADE
GTNET
Card
Windows PC
GPC/PB5
Card
14
or 18
GT Ports
GT Optical
Cable
Ethernet Switch
At startup, the PC server program reads the entire .pbk file and opens a TCP port
to receive requests over the Ethernet from the GTNET. The GTNET continuously
requests data from the server program until its buffers are full. While the GTNET
is filling its buffers, the GPC/PB5 is also filling its buffers by requesting data via
the GT optical interface to the GTNET. The startup delay of the system allows the
buffers to be full prior to playing back the waveforms. During operation, when there
is enough free buffer space in the GPC/PB5, the GPC/PB5 requests more data from
the GTNET. Similarly, when there is enough free buffer space in the GTNET, the
GTNET requests data from the server program. The optional buf_cnt output of the
GTNET COMTRADE allows the GPC/PB5 buffer level to be monitored.
The start of the output of the playback system can be synchronized to other signals
by using the optional trigger input. The trigger is level sensitive and has no effect
until after the startup delay.
The GTNET COMTRADE component has Ready and Done status outputs. The
Ready signal goes high after the startup delay has been met. It goes low when playback begins. The Done signal is initially low and goes high when the file playback
has completed.
A configurable Pause input allows the user to temporarily pause the output of the
GTNET COMTRADE component and force all signal levels to 0.0.
The GTNET PLAYBACK system requires a server program running on a Windows
PC to transfer the .pbk file to the GTNET. The server program can be started automatically by RSCAD Runtime or it can be manually run on a separate PC. Contact
RTDS for information regarding manually starting the server program.
7B.7 RSCAD DRAFT COMPONENT AND PARAMETER ENTRIES
The RSCAD Draft component used for GTNET COMTRADE is named
rtds_risc_ctl_GTNETCOMTRADE and can be found in the MLIB/RPC/CTLS di-
7B.6
GTNET COMTRADE
rectory.
The figures below illustrate the menus used for RTDS GTNET COMTRADE playback.
CONFIGURATION
The configuration tab is used to specify global settings for the GTNET COMTRADE
component.
NAME Each COMTRADE component requires a unique name. This is used for
crossreferencing variables between RSCAD/Draft and RSCAD/RunTime.
DF The name of the COMTRADE file set ( without an extension ).
NCH The number of channels that are to be played back. A maximum of 8 channels
can be specified for each COMTRADE component used.
PRE Set to Auto to have the RTDS software attempt to find the prefault data.
Set to No to have no looping through prefault. If Auto or Manual is selected
as the prefault data mode, a new menu tab PREFAULT CYCLE will appear with
parameter entry as shown.
Sdly Minimum startup delay to allow playback buffers to be filled at the start of
a case. All outputs are set to 0.0 during startup and until playback begins.
Trig Set to include a trigger signal input on the component to control startup.
When included, playblack will begin only after the startup delay has been met and
the trigger signal is asserted.
7B.7
GTNET COMTRADE
Bufc Include buffer count signal for debugging. The buffer count signal allows
monitoring the number of samples in the GPC playback buffer.
Ovwt The regenerate .pbk file setting allows the user to disable regeneration of
the .pbk file during a recompile. A warning is generated if conversion is required
and the Ovwt setting is set to no.
Gcnv Control the generation of the text .cnv data file for viewing the interpolated
data file.
Statsv Control automatic server invocation by RSCAD Runtime. Parameters in the
GTNET_PLAYBACK_CONFIGURATION menu must be set to allow the GTNET
to connect to the server. If Statsv is set to NO, a server must be manually started prior
to starting the case in Runtime.
Paus Include an input to allow playback to be temporarily paused.
Port The port number of the GTIO fiber port of the GPC/PB5 card that the GTNET
is connected to.
Card The number of the GTNET card on the GPC/PB5 GT peripheral chain. Since
the GTNET COMTRADE model requires exclusive use of a GPC/PB5 GT port, this
must be set to 1.
GTNET_PLAYBACK CONFIGURATION
7B.8
GTNET COMTRADE
Sip1Sip4 Sets the IP address of the PC running the GTNET server program. The
IP address is entered in 4 parts. For example, to enter the address 192.168.1.173.
Sip1 is set to 192, Sip2 is set to 168, Sip3 is set to 1, Sip4 is set to 173.
Sport Sets the TCP port number of the GTNET server program. By default, the
server program uses TCP port 3671.
PRE FAULT DATA
APFC The user can direct the automatic prefault data detection algorithm by entering the approximate finish time of the last cycle of prefault data. The compiler
will attempt to calculate the last sample of prefault data with a time that is equal to
or less than the value specified. See Section 7B.5 for more information.
SDAT Sample Number of first data point of prefaultdata .dat file. This can be used
to jump over any invalid samples at the beginning of a file to allow smooth prefault
looping.
MPFC the user can define the prefault data by entering the last data point of the
interpolated data to be used in the prefault cycle. For example, if a .pbk file contains data for a 60 Hz waveform with a timestep of 51.28secs. There are 325 data
points/cycle. If we want the first cycle of data to be continuously played back in pre
fault mode, the MPFC parameter would be set to 325.
For convenience, weve include some equations which can be used to calculate the
number of interpolated data points from the number of sampled data points, N. Depending on whether the user wants the last interpolated point to fall before or after
the last prefault sample data point, either Eq. 7b.1 or Eq. 7b.2 may be used. ***
If the last interpolated point should be before the last prefault data point:
# of interpolated data points = FLOOR
Period
(N 1) Sample
+1
t
Eq. 7b.1
7B.9
GTNET COMTRADE
If the last interpolated point should be after the last prefault data point:
Period
(N 1) Sample
+1
t
# of interpolated data points = CEIL
Eq. 7b.2
***Please note that both these equations yield the same result if either
Sample Periodt or tSample Period is a whole number. In such a situation, the last
prefault sampled data point coincides exactly with the last interpolated data point.
LCNT Number of times to playback prefault data. For example, a value of 1 plays
back the prefault data once and then continues on with the rest of the file. A value
of 2 plays back the prefault data twice and then continues on with the rest of the file.
POSTFAULT DATA
PFDC Number of times to playback postfault data. For example, a value of 1

plays back the postfaultdata once. A value of 2 plays back the postfaultdata twice.
SIGNAL #n
For each signal channel, a menu tab will be created. Each channel menu will contain
the menu options discussed below.
7B.10
GTNET COMTRADE
CTC1 The COMTRADE file channel number to be played back must be specified.
UG1 Indicates whether the units in the .cfg file are to be used to scale the data. Valid
units from the .cfg file are kV, kA, KILO, uV, UA, mV, mA, Milli, MA, MV, mega,
amp, volt, A, V.
MUG1 If the UG1 parameter above is set to No then the value entered for the
MUG1 parameter is used for scaling.
PS1 The chratio is the primary to secondary ratio. Setting this parameter to Yes
will scale the data according to the chratio in the .cfg file. Sometimes the ratio is not
included in the .cfg file and the ratio can be entered manually.
Note: In IEEE COMTRADE versions prior to 1997, the primary to secondary ratio
was referred to as the chratio. The chratio was displayed as primary:secondary separated by a colon. Versions after 1997, the ratio is referred to as the primary to secondary ratio and is separated by commas.
SC1 This parameter defines the primary to secondary ratio to be applied for internal
signal scaling if the chratio is not being read from the .cfg file.
TS1 This parameter can be used to introduce a time shift of the signal being considered. If no shift is required then TS1 should be left at 0.0. If a skew value exists for
the channel, the skew value will be added to the time shift entered.
7B.8 SENDING COMTRADE SIGNALS TO A PERIPHERAL DEVICE
Typically play back is used to send some prerecorded transient event or waveform
to an external device. In RSCAD/Draft, the GTNET COMTRADE component signals are available as wires from the component. All signals are floating point.
7B.11
Rev. 01 August 2008
7C
GTNET DNP
( rtds_ctl_GTNET_DNP_V2.def )
Data may be exchanged between the RTDS and external equipment over a LAN/
WAN using DNP (Distributed Network Protocol). DNP is often used by electric utilities as a communication mechanism between a control center and substations. In
particular, SCADA systems commonly use DNP as their communications protocol.
In order to use the DNP communication function with the RTDS, the user must have
a GTNET card equipped with the DNP firmware installed in one of the RTDS racks
and have access to a DNP master station. DNP firmware installed on the GTNET
card acts only as a slave interface for the RTDS simulator.
Details regarding DNP standards and terminology may be found at www.dnp.org.
A typical connection arrangement for the DNP function on the RTDS is shown below
in Figure 7C.1. The GTNET card is connected to a GPC card using a fiber optic cable
connected between GT Ports located on the rear of the GPC and GTNET cards. Fiber
ports 1 or 2 on the GPC card may be used to connect to the GTNET card. Data computed on or required by the simulation case running on the RTDS is sent between the
GPC and GTNET over the GT Port fiber optic connection. Refer to the GTNET
chapter of the RTDS Hardware Manual for more information regarding setup of the
GTNET card.
The GTNET is connected to the DNP LAN/WAN Master Station through the
GTNETs Ethernet port. A DNP Master Station may be dedicated hardware or a
computer workstation running DNP Master software (eg. Triangle Microworks
Communication Protocol Test Harness software, a windows application that simulates a DNP Master Station).
7C.1
GTNET DNP
DNP Master Station

GT Port Fiber Cable
GPC
ETHERNET SWITCH
Ethernet Cable
GTNET
Figure 7C.1: Typical GTNET DNP Connection
7C.1 DESCRIPTION
The DNP Master station initiates all DNP communication by sending requests to
slave stations for updated data values. The term polling is used to refer to the master
station action requesting updated data from the slave stations. The master station can
also send messages to the slave stations to change the value of a parameter. In order
to avoid ambiguity, the terms input and output are avoided here. Rather, the terms
status and control are used. Status signals refer to signals that are sent from the slave
station to the master station. Control signals refer to signals that are sent from the
master station to the slave station. In terms of the RTDS simulation case, control signals are those that are used as input to a component in RSCAD/Draft and status signals are those that are output from a component.
7C.2
GTNET DNP
Control Signal:
Status Signal:
Master > Slave

Slave > Master
SIGNAL TYPES AND UPDATE FREQUENCY

The GTNET DNP component can handle binary and analogue control and status
data. The maximum number of binary and analogue signals that can be handled by
a single GTNET card are
DNP
Object No.
BINARY STATUS:
1
BINARY CONTROL:
10
ANALOGUE STATUS:
30
ANALOGUE CONTROL: 40
Qty.
Format
1024
512
500
100
(32 x 32 bit words)

(16 x 32 bit words)
(32 bit single precision)
Status points are mapped to DNP Binary Input objects 1 and 2, and DNP Analogue
Input to objects 30 and 32. Control points are mapped to DNP Binary Output objects
10 and 12 and DNP Analogue Output Block objects 40 and 41.
In order to use the DNP function on the RTDS, the DNP controls component must
be assigned to a GPC processor on the GPC card to which the GTNET card is connected. The DNP controls component is responsible to oversee the exchange of data
between the GTNET card and the GPC processor.
Every millisecond the DNP controls component latches all 32 binary status words
and generates a change map. The change map is generated by applying an XOR function to the newest 32 binary status words and those from the previous sample. The
binary status words and change event words are then sent from the GPC to the
GTNET card using the GT I/O port connection between the two cards. The change
event words are used within the GTNET to generate buffered DNP object 2 change
events. All changes within the same sample are stamped with the same time. The
DNP master can obtain the most recent information by polling the GTNET DNP
slave.
Operation of the DNP controls component for analogue status points is somewhat
similar to that of the binary status points. However, a change status for the analogue
signals is based on the most recent sample changing by more than a user specified
deadband value. Since 500 analogue status words are permitted, the update frequency for the analogue status signals is 4 Hz. Every 0.25 seconds all analogue status
points are sampled, change events generated and the data transferred from the GPC
to the GTNET. The analogue change events are assigned DNP object number 32.
Control signals are sent to the GTNET from the DNP Master. Binary control signals
are transferred from the GTNET to the GPC card whenever a new control signal is
7C.3
GTNET DNP
received from the DNP master. If the DNP master sends a packet to the GTNET
which includes multiple point changes, the GTNET card processes these multiple
points serially. Analogue controls signals are handled similarly, but are updated on
the GPC only every 0.25 seconds.
A complete GTNET DNP device profile and implementation table may be obtained
from the RTDS website (www.rtds.com) under the customer login > downloads
area.
7C.2 DNP <> RTDS POINT MAPPING FILE

A points mapping text file is used to map DNP data point addresses to signal names
assigned in RSCAD/Draft. The points mapping text file contains a single line for
each mapping between the DNP address and the corresponding RTDS variable name.
The points mapping text file is accessed during the RSCAD/Draft compile and must
be located in the same directory as the RSCAD/Draft file for the simulation case. The
text file name must have .txt as its suffix. The user specifies the points mapping
file name under the Fname parameter in the RSCAD/Draft DNP controls component.
Lines of text in the mapping file which begin with the # character are considered
comments. Binary status, Binary control, Analogue Status and Analogue Control
signals are mapped using the following format in the points mapping file. Note that
each mapping must use a single line of text.
BINARY BINARY STATUS POINTS

Binary status points are mapped to DNP Binary objects using a data line in the points
file of the format
BI:
DNP_address
user_label
bitmap_name
bitmap_bit_num
where:
DNP_address: The address of the DNP Binary Status point. The range
is 0 to 1023.
user_label: A user defined label for the point. This field is ignored by
the RTDS compiler.
bitmap_name: The name of the RTDS bitmap variable containing this point.
Typically, the bitmap_name is the wire label name assigned in RSCAD/Draft
to the integer output signal from the component producing the signal.
7C.4
GTNET DNP
bitmap_bit_num: The position of the point within the signal bitmap_name.
Bit 0 is the rightmost (LSB) bit.
For example, the points file entries
BI: 0 STATUS00 STATUS 0
map bits 0, 1 and 2 from the RSCAD/Draft signal named STATUS into DNP
Binary status addresses 0, 1 and 2 respectively. The user labels STATUS00 . . .
STATUS02 are only used to identify these points within the DNP point map.
DNP BINARY CONTROL POINTS
Binary control points are mapped to DNP Binary objects using a data line in the
points file of the format
BO: DNP_address user_label bitmap_name bitmap_bit_num default_state
where:
DNP_address: The address of the DNP Binary Output point. The range
is 0 to 511.
the RTDS compiler.
bitmap_name: The name of the RTDS bitmap variable containing this
point Typically, the bitmap_name is the wire label name assigned in
RSCAD/Draft to the integer input signal to a component.
bitmap_bit_num: The position of the point within the signal
bitmap_name. Bit 0 is the rightmost (LSB) bit.
default_state: The default value (0 or 1) for the point at the start of
simulation.
For example, the points file entry
BO: 0 TRIPA BRK 4 1
maps DNP Binary Control address 0 to bit 4 of the RSCAD/Draft variable named
BRK. The user label TRIPA has been given to easily identify this point within
the DNP point map. Bit 4 of the signal BRK has a default value of 1 at simulation
startup.
7C.5
GTNET DNP
DNP ANALOGUE STATUS POINTS

The AI section is used to map Analogue status points. The format of each entry is:
AI:
DNP_address variable_name deadband% [serializer_name]
where:
DNP_address: The address of the DNP Analogue Status point.
The range is 0 to 499.
variable_name: The name of the RSCAD/Draft variable for
the DNP data point assigned address DNP_address. The signal
named variable_name must be obtained from an output of a
RSCAD/Draft component.
deadband: The deadband used to determine the required level of
change in the data point in order to generate a DNP change event. The
deadband value is in %.
serializer_name: Optional. Only required for points transferred from
subsytems using the GTNET Analogue Status Serializer
component. See below for more information regarding the use
of the serializer component.
For example, the entry
AI: 0 VBUSA 5% S1
maps RSCAD/Draft variable named VBUSA using the Analogue Status Serializer
component with name S1 to Analogue Status address 0. A change of 5% or greater
from the previous change event is required to generate a status change.
DNP ANALOGUE CONTROL POINTS

The AO section is used to map Analogue control points to DNP addresses. The format of each analogue control entry is:
AO: DNP_address variable_name default_value
[serializer_name]
where:
DNP_address: The address of the DNP Analogue Control point.
The range is 0 to 99.
7C.6
GTNET DNP
the DNP data point assigned address DNP_address. The signal
named variable_name must be used as an input to an RSCAD/Draft
component.
default value: The default value for the signal.
subsytems using the GTNET Analogue Control Serializer
component. See below for more information regarding the use
of the serializer component.
AI: 0 VSETA 500 C1
maps the Analogue Control signal at DNP address 0 to an RSCAD/Draft variable
named VSETA using the Analogue Control Serializer component with name C1.
The signal VSETA is assigned the value 500.0 at the start of the simulation case.
VSETA remains at 500.0 until the DNP Master sends a message which changes the
value.
7C.7
GTNET DNP
7C.3 RSCAD DRAFT COMPONENT AND PARAMETER ENTRIES
The
RSCAD
Draft
component
for
GTNET_DNP
is
named
rtds_ctl_GTNET_DNP_V2.def and can be found in the MLIB/RPC/CTLS directory
under the RSCAD installation directory. Figure 7C.3 below illustrates the menus
used for the GTNET_DNP component.
Figure 7C.2: GTNET DNP Component and CONFIGURATION Menu
CONFIGURATION MENU ITEMS

Name The components name.
Port Indicates whether the GTNET is connected to GT I/O port 1 or 2 on the GPC.
Card The number of the GTNET card on the GPCs GT port peripheral chain. 1
7C.8
GTNET DNP
refers to the first GTNET_DNP on the GT peripheral chain, 2 refers to the second
GTNET_DNP on the GT peripheral chain. The GTNETs card number is indicated
on the seven segment display on the cards face plate.
Proc The controls processor to which the GTNET DNP function is assigned.
Pri The priority of execution for the GTNET DNP function in the assigned controls
processor.
DNP SETUP MENU ITEMS
Figure 7C.3: GTNET DNP Component DNP SETUP Menu
Nmode Sets the type of DNP protocol. TCP/UDP, UDP only or TCP only options
are available. TCP/UDP mode uses TCP for all communications except broadcast
messages which will be expected over UDP.
NRACS If set to Yes the strobe signal required for the multirack serializer
component is made available and the strobe signal output connection appears. See
the section entitled Multirack Communication below for more information
regarding the multirack serializer component.
7C.9
GTNET DNP
Sip1Sip4 Specifies the IP address of the station acting as the DNP Master. The
IP address is entered in 4 parts. For example, to enter the address 192.168.1.173, Sip1
is set to 192, Sip2 is set to 168, Sip3 is set to 1 and Sip4 is set to 173. If the Master
Station IP address is set to 0.0.0.0 then the GTNET DNP function responds to all
DNP master commands.
Sport Sets the TCP/UDP port number for DNP LAN/WAN communications. The
default DNP LAN/WAN port is 20000.
Fname The name of the point mapping text file. The extension is expected to be
.txt and should not be entered in this field. The file must be located in the same
directory as the RSCAD draft file for this case.
Trans DNP slave address. Range is 1 to 65519.
7C.4 MULTIRACK COMMUNICATION

DNP control and status signals are transferred between the GTNET card and the GPC
card to which the GTNET is connected. In multirack simulation cases the control
and status signals may be required on or originate from GPC processors installed in
racks other than where the GTNET is connected. In this case DNP control and status
signals must be passed from the GPC card to which the GTNET is connected to the
GPC cards in the remote RTDS racks over the IRC channels. Figure 7C.4 illustrates
the data flow for a multirack case.
2. from GPC to IRC
4. from IRC to GPC
Rack #1
1. from GTNET to GPC
Rack #2
3. from IRC (rack 1) to IRC (rack 2)
Figure 7C.4: DNP Data Flow for MultiRack simulation case
7C.10
GTNET DNP
It is possible then that a large number of signals will have to be transferred between
the rack in which the GTNET is connected and the other racks participating in the
simulation. Transferring hundreds of signals between racks would result in an unacceptably long communication time and correspondingly large simulation timestep.
For analogue signals in particular it is not necessary to transfer all of the signals used
with the DNP function in a single simulation timestep since the update frequency
for DNP analogue signals is 4 Hz. Instead a single data and single address location
are transferred each timestep. Data assigned to the allocated location changes each
timestep so that all required analogue points are transferred with the 0.25 seconds
available. All 500 analogue points can be transferred from another rack in 0.025 seconds given a simulation timestep of 50 microseconds (ie. 500 * 50.0e6 = 0.025
sec.).
To use the multirack DNP analogue signal communication functionality, the rack to
which the GTNET DNP is connected must export and import synchronization and
data transfer variables. Synchronization is done via the GTNET DNP components
strobe signal which is enabled by setting the MRACS parameter under the DNP SETUP menu in the GTNET DNP component to Yes. A GTNET DNP Serializer component (rtds_ctl_GTNET_DNPserializer.def) must be assigned in those racks
which are to receive or send signals to the GTNET DNP component. Figure 7C.5
shows the RSCAD/Draft placement and signal assignment required for the GTNET
DNP serialization function.
The strobe signal is exported from the subsystem containing the GTNET DNP component and imported into each subsystem which receives or produces data associated
with the GTNET DNP function. In Figure 7C.5 the strobe signal is given the name
STROBE1 and is exported from Subsystem #1 and imported into Subsystem #2.
Analogue Control signals address and data are exported from the subsystem containing the GTNET DNP component and imported to the GTNET DNP serializer
component. In Figure 7C.5 the Analogue Control signal address is given the signal
name C1CA and the corresponding data signal is named C1CD. Analogue Status signals address and data are exported from the subsystem where the data is produced and imported into the subsystem containing the GTNET DNP component.
Address and data signals are named S1SA and S1SD respectively in Figure
7C.5. The serializer component assigned in a given subsystem is responsible to read
or write the required signals (as defined in the point mapping file) to the assigned data
signal so that the information is transerred to or from the GTNET DNP component
in the given subsystem.
7C.11
GTNET DNP
Place the GTNET DNP component on the RSCAD/Draft page assigned to the subsystem which contains the GPC card connected to
the GTNET.
Enable the Strobe signal (MRACS = Yes)
Use IMPORT and EXPORT components to associate the Analogue

Control and Status signal address
and data with the GTNET DNP
Serializer component in the other
subsystem.
SUBSYSTEM #1
Attach an EXPORT component to the Strobe output

connection point and assign the EXPORT component a
name (eg. STROBE1)
Use an IMPORT component to connect the

strobe signal to the GTNET DNP Serializer
Use IMPORT Components to

associate the Analogue Control signal Address and Data
with the GTNET DNP component.
Use EXPORT Components to
associate the Analogue Status
signal Address and Data with
the GTNET DNP component.
SUBSYSTEM #2
Figure 7C.5: DNP Data Flow for MultiRack simulation case
7C.12
GTNET DNP
GTNET DNP SERIALIZER COMPONENT
The RSCAD Draft component for the GTNET_DNP Serializer is named
rtds_ctl_GTNET_DNPSerializer_V2.def and can be found in the MLIB/RPC/
CTLS directory under the users RSCAD installation directory. Figure 7C.6 below
illustrates the menu used for the serializer component.
Figure 7C.3: GTNET DNP Component DNP SETUP Menu
Figure 7C.6: DNP Serializer Component

DName The name of the GTNET DNP component to which the serializer is associated.
ACEn Enable or disable the Analogue Control signal deserializer function
ASEn Enable or disable the Analogue Status signal serializer function.
7C.13
GTNET DNP
ACName Name of the Analogue Control signal Deserializer. This name is used
in the points file AO: command line as described above. Each Analogue Control signal defined in the points file which is required in the subsystem in which the GTNET
DNP serializer component is placed must include the name assigned to the ACName
variable. Only used if ACEn is set to Yes.
ASName Name of the Analogue Status signal Serializer. This name is used in the
points file AI: command line as described above. Each Analogue Status signal defined in the points file which is produced in the subsystem in which the GTNET DNP
serializer component is placed must include the name assigned to the ASName variable. Only used if ASEn is set to Yes.
Proc The controls processor to which the GTNET serializer function is assigned.
Pri The priority of execution for the GTNET serializer function in the assigned controls processor.
7C.14
Rev. 0.2 October2013
7D
GTNET PLAYBACK
( rtds_ctl_GTNET_PLAYBACK_V2 )
The RTDS simulator can be used to playback captured waveform data stored in
ASCII data files at an arbitrary sample rate in the same manner as a real time play
back system. File sizes of 100s of MB are supported allowing waveforms with high
sample rates to be played back for an extended time period. The GTNET
PLAYBACK component provides this functionality by employing a GTNET
peripheral and a Windows PC based file server. The component has optional inputs
to allow synchronization between the playback data and parts of the power system.
7D.1 MODEL DESCRIPTION

Although the primary application of the RTDS simulator is to simulate the operation
of power systems and study events initiated by the user during a test series, a need
for replaying data which was previously captured and stored may arise. For example,
if stored waveforms representing electric arc furnace currents are available, a
playback facility enables the replay of such waveforms into real and simulated
system voltage controllers to evaluate the system performance.
Typically, the GTNET PLAYBACK model is used when the amount of playback data
exceeds the memory storage capability of the GPC/PB5 processor. A real time
simulation running in the RTDS can read in the external data using the GTNET
PLAYBACK model and GTNET hardware. Up to 8 channels of floating point data
can be imported from an external data file. The GTNET card brings in the data using
TCP/IP ethernet communication and sends the data to the GPC/PB5 card over the
GTIO fiber channel as shown in figure 1.
7D.1
GTNET PLAYBACK
GTNET Card
GPC/PB5 Card
Figure 1: Data Flow From Data Source to GPC/PB5Card
7D.2 PLAYBACK DATA FILE FORMAT

The GTNET PLAYBACK component requires the filename of the data to be played
back.
The playback data must be stored in an ASCII file with a .txt filename extension. The
playback data file must contain column(s) of signal data with data for each sample
time. The numbers stored in the data file should not be scaled and are unitless. The
data must be arranged in the following format:
sample_time chan1 chan2 chan3 chan4 ...
The sample_time field has units of seconds and must represent a constant sample
rate. Any number of tabs or spaces may be used to separate fields. Each set of
samples must be on the same line. The file may contain any number of nondata
header lines at the start of the file containing information such as creation date or
column labels. Any line in the input file starting with a# will be treated as a
comment.
During the Draft compile process, the playback data stored in the .txt file is translated
to a binary file with extension .pbk for input to the GTNET card.
7D.3 PLAYBACK OPERATION
At the beginning of a GTNET playback simulation, RSCAD/Runtime invokes an
7D.2
GTNET PLAYBACK
external server application named gtnet_playback_1.exe. The server is in charge

of reading the translated binary data file (with the file extension of .pbk) and
transmitting the data to GTNET card through TCP/IP ethernet communication. The
GTNET card receives the data from the server and sends it to a GPC/PB5 card. The
GTNET card sends data to the GPC/PB5 processor running the playback model via
the GTIO fiber channel. Once received, data is stored in the internal buffer memory
of the model and is produced as output. The GTNET card and the model cooperate
to maintain the uninterrupted flow of the data throughout the simulation until the end
of playback data has been reached. All outputs are set to 0.0 when all the data has been
played back.
7D.4 RSCAD DRAFT COMPONENT AND PARAMETER ENTRIES
The RSCAD Draft component used for GTNET playback is named
rtds_ctl_GTNETPLAYBACK_V2 and can be found in the MLIB/RPC/CTLS
directory.
Two default outputs are provided to monitor the internal status of the model. The first
default output is named Ready. A logic 1 at the Ready output indicates that the
the initial startup delay time has elapsed and output from the model is available. A
logic 0 at the Ready output indicates that data is not yet available. The second
default output is named Done. A logic 1 at the Done output indicates that all
data has been sent. A logic 0 at the Done output indicates that data is still being
played back.
The figures below illustrate the menus used for RTDS GTNET PLAYBACK.
CONFIGURATION TAB
Figure 2. CONFIGURATION tab
NAME The NAME parameter in above dialog box is for assigning a name to the
model. The maximum length of the name is 10 characters.
7D.3
GTNET PLAYBACK
NCH The NCH parameter is for assigning the number of data channel(s) to the
model. The minimum number of channels is 1 and the maximum is 8. The number
of channels given to this field must match with the number of channels in the data
file. The graphical appearance of the component will change according to the
number of channels used.
Figure 3: NCH=1
Figure 4: NCH=8
Sdly The Sdly parameter is for assigning the initial delay time to the model.
The initial start up delay has to be more than 250msecs to allow the GTNET to initiate
the communication sequence. The delay time is calculated as:
Initial start up delay (in time steps) * Simulation time step
For example, when the initial start up delay is 5000 and the simulation time step is
50usecs, the initial start up delay time is 250msecs (= 5000 * 50usecs).
Trig The Trig parameter determines the existence of a trigger input to the model.
If Yes is selected from the toggle box, the model will have a trigger input. During
simulation, the model starts to produce its output once the trigger is given to the
model. The trigger is asserted when a logic 1 is applied.
Figure 5: Trig=No
Figure 6: Trig=Yes
Bufc The Bufc parameter determines the existence of a buffer count output. If
Yes is selected from the toggle box, the model will have a buffer count output. The
BufCnt output appears at the bottom right side of the model as shown in Figure 7.
7D.4
GTNET PLAYBACK
The buffer count output provides information on how much data is remaining in the
models internal buffer.
Figure 7: Bufc=Yes
Paus The Paus parameter determines the existence of a pause input to the model.
If Yes is selected from the toggle box, the model will have a pause input. When a
value of 1 is given to this input during simulation, the model pauses the operation
and the output is set to 0.0.
Sync The Sync parameter determines the synchronization option of the model.
If No is selected, the output of the model is updated every time step.
If PLL is selected, the model synchronizes the output with external phase sources
like PLL (Phase Locked Loop). Once this option is selected, the Phase input will
appear at the left side of the model in draft. A tab named SYNCHRONIZATION
will appear requesting the necessary parameters for PLL synchronization. This
synchronization method is found to be useful when the source of data is from
protective relays which usually samples power system data based on the number of
samples per cycle.
For example, when PLL is selected as source for synchronization, the frequency
of the data output from the model can be controlled by the phase input. The phase
input can be generated from an external phase source such as a PLL. If the phase
input becomes slower than nominal frequency, the output of the model slows down
accordingly. If the phase input increases, the output frequency of the model increases
accordingly. However, the model cannot track the phase input change if the size of
the change is too large. When the PLL is selected as source for the synchronization
and 16 is given to the Pnt parameter in the synchronization option, the model will
produce new output every 22.5 degree (22.5 = 360 / 16) or 0.393 radian per cycle.
In a 60 Hz system this angle value is equivalent to the 1.042msec. When the phase
input suddenly jumps an amount which is larger than 22.5 degree, the synchronism
between the input data and the phase input will be lost. Figure 8 illustrates the effect
of the phase change. If the phase input step change is within the 1.042msecs, the
model is able to maintain synchronism. This situation is depicted as Phase Jump 1
line and points 2 and 3. If the phase input step change is greater than the
7D.5
GTNET PLAYBACK
1.042msecs, the model is unable to maintain synchronism. This situation is depicted
by the Phase Jump 2 line.
Figure 8. Phase input change in PLL synchronization
Ifn The Ifn parameter assigns the name of the playback data input file. No
filename extension should be entered. The filename extension is determined by the
the Ovwt parameter.
lpc The stored data can be played back a specified number of times by setting the
lpc parameter. The entered lpc value is required in the .pbk file. If regeneration
of the .pbk file is set to NO and the number of times to playback data has been
modified, the .pbk file will automatically be regenerated. A warning message will
be given in this case just to indicate that the .pbk file was regenerated.
Ovwt The Ovwt parameter selects whether to translate the input text file to binary.
If Yes is selected, the filename given in the Ifn field with a .txt filename
extension will be translated into a binary playback file with extension .pbk. In other
words, the input file name which was given in the previous parameter field (Ifn)
must have the .txt extension when this parameter is set to Yes, otherwise the
translated .pbk file is used.
Tstp The Tstp asks if interpolation is needed during the translation process.
Interpolation must be used when the sample time of the input text file is different
from the simulation time step. This option is enabled only when the Ovwt
parameter is set to Yes. Figure 9 illustrates how the interpolated output would look
with respect to sampled data points for a particular case.
7D.6
GTNET PLAYBACK
time
t
sample period
Original data points

Data points computed by interpolation
Figure 8. Interpolation
Port The Port parameter assigns the fiber port number of a GPC/PB5 card
connected to the GTNET . The location of fiber port is presented in the Figure 9.
Figure 9. Ports in GPC card
Card The Card parameter assigns the GTNET card number . The GTNET card
number can be read from the 7segment display on the front panel. Figure 10 shows
the location of the 7segment display on the front panel.
7D.7
GTNET PLAYBACK
Figure 10. 7Segment Display On GTNET card
Proc The Proc parameter is for assigning a control processor number to the
model.
Pri The Pri parameter is for assigning a priority level to the model.
GTNET_PLAYBACK NETWORK CONFIGURATION TAB
Figure 11. GTNET_PLAYBACK NETWORK CONFIGURATION Tab
Sip1,Sip2,Sip3,Sip4 The parameters Sip1, Sip2, Sip3 and Sip4 are used to
assign the IP address of the computer running the GTNET server program. The
GTNET server program is included with the RSCAD software. Therefore the IP
address given will be for the computer running RSCAD. For example, if RSCAD
is running on a computer with IP address of 192.168.1.179, then
Sip1 is 192
7D.8
GTNET PLAYBACK
Sip2 is 168
Sip3 is 1
Sip4 is 179
Sport The parameter Sport is for assigning the port number which the server
program TCP/IP socket communicates through. By default, the server program uses
TCP port 3671.
SYNCHRONIZATION TAB
Figure 12. SYNCHRONIZATION tab
This tab appears only when the Sync parameter in the CONFIGURATION tab is
set to PLL.
Pnt The Pnt parameter determines how many times the output of the model is
updated during one cycle (2 radian).
Figure 13 is an example with the Pnt parameter set to 16 for a period of 2. Each
of the 16 samples are marked with the corresponding number. The model will try to
produce 16 output points per one cycle. The model will try to update the output every
1.024msecs (1.024msecs = (1 / 60 (Hz)) (360 (Degree) / 16 (Points)) (1 / 360
(Degree))) when the system frequency is 60 Hz.
7D.9
GTNET PLAYBACK
Figure 13. Pnt parameter set to 16 Samples per cycle
Freq The Freq parameter assigns the base frequency of the external phase source.
Interp The Interp parameter determines whether the intermediate point(s)
between the data updates should be interpolated.
INPUT DATA TRANSLATION TAB
Figure 14. INPUT DATA TRANSLATION tab
This tab appears only when the Ovwt (Translate and regenerate .pbk file?)
parameter in the CONFIGURATION tab is selected to Yes.
7D.10
GTNET PLAYBACK
chn1...chn8 The chn1... chn8 parameters determine which data column in the
input data file will be assigned to which channel. For example, if the 8th data column
in the input data file is to be assigned to the channel number 1, the chn1 parameter
would be 8.
7D.5 GTNET PLAYBACK EXAMPLE CASES

The operation of the model is further explained with three example cases.
Step 1 introduces simplest operation of the model.
1) A data file is prepared. For this example, a very short data file is prepared. The data
file contains 1 channel of data with 20 samples. However, any data file with arbitrary
size can be used with this model. A single data file over 500MB in size was
successfully tested with the model.
Here is the text file with 20 data points.
# STEP1 TEST DATA
0.000 0.0
0.001 0.1
0.002 0.2
0.003 0.3
0.004 0.4
0.005 0.5
0.006 0.6
0.007 0.7
0.008 0.8
0.009 0.9
0.010 0.0
0.011 0.1
0.012 0.2
0.013 0.3
0.014 0.4
0.015 0.5
0.016 0.6
0.017 0.7
0.018 0.8
0.019 0.9
The first column is the sample time and the second column is the data. Any line
beginning with # is considered a comment.
2) A RTDS simulation case is prepared as shown in the following figure.
7D.11
GTNET PLAYBACK
Figure 15. RTDS simulation case
The GTNET hardware needs to be connected to the GPC/PB5 processor where the
model is running and the config_file needs to reflect the correct hardware
configuration. The following excerpt from config_file shows the hardware setting
made for the above simulation case.
32 GPC
33 GPC
34 GPC
35 GPC
36 GPC
37 GPC
VER 1.00 GTNET_PB1

VER 1.00
VER 1.00 GTAI2
VER 1.00
VER 1.00
VER 1.00
Figure 16 shows the playback model settings.
7D.12
GTNET PLAYBACK
CONFIGURATION tab
Figure 16. CONFIGURATION Settings
The simulation time step of the case is 1000usecs (1msec). The Sdly parameter above
tells the model that the model waits 3 sec. (3000 * 1msec = 3000msec) before
producing the output. The Ovwt option is selected Yes, telling the model to
translate the input text file. The Tstp option is set to No, disabling the interpolation
during the translation.
7D.13
GTNET PLAYBACK
GTNET_PLAYBACK NETWORK CONFIGURATION Tab
Figure 17. GTNET_PLAYBACK NETWORK CONFIGURATION settings
The parameters are set to tell the model the IP address of the server program. The
server program reads the playback binary data file (with .pbk extension) and sends
the data to the GTNET card through TCP/IP ethernet communication.
3) Compile and run the case. After running the case, the output waveforms of the
model look like this.
Figure 18. Simulation Output
7D.14
GTNET PLAYBACK
Figure 19. Simulation Output (Zoomed)
1: The Ready output signal of the model was raised to 1 when the initial startup
delay time expires. The delay time is set to 3000 ms in this simulation case.
2: One time step after the Ready signal was raised; the model starts to produce the
output. The playback data (20 sample size) was coming out from the model.
3: The Done output signal of the model was raised to indicate that the output of
playback data is finished.
Step 2 introduces trigger operation of the model.
1) The same data file which was prepared during step 1 is used again for this step.
2) A RTDS simulation case is prepared. Figure 20 shows the RSCAD/Draft case.
7D.15
GTNET PLAYBACK
Figure 20. RTDS Simulation Case
Figure 21 shows the settings of the playback model.
Figure 21. CONFIGURATION settings
7D.16
GTNET PLAYBACK
Two parameters are different from the settings made during step 1. The first
difference is the Trig parameter. By setting this parameter to Yes, the model will
start to produce the output once the trigger signal is issued. The second difference is
the Ovwt parameter. Because the binary playback data file which was generated
during step 1 is used again, this parameter is set to No. It is noticed that the Tstp
parameter
is
disabled
accordingly.
The
parameters
in
the
GTNET_PLAYBACK_NETWORK CONFIGURATION tab are the same as
those in step 1.
3) Compile and run the case. After running the case, the output waveforms of the
model look like this.
The trigger needs to be given to the model after the initial startup delay time expires.
When the delay expires the Ready output signal of the model turns on, indicating
that the model is ready to produce output.
7D.17
GTNET PLAYBACK
Figure 23. Simulation Output (Zoomed)
1: The trig input signal is issued. The trigger initiates playback of data. It is noted
that the Ready output is already turned on before the trigger is given.
2: The model starts to produce the output.
3: The Done output signal of the model was raised to indicate that all data has been
played back.
Step 3 introduces PLL synchronization of the model.
1) A new data file was prepared for this step. The data file contains values which
were sampled from a 60 Hz sine wave with a sampling frequency of 16 samples per
cycle. Here is the beginning of the data text file.
# 16 points per cycle
0.00075
5.84197
0.0018
4.49838
0.00285
2.45909
0.0039
0.0394992
0.00495
2.3862
0.00595
4.35834
0.007
5.76641
0.00805
6.28269
0.0091
5.82732
0.01015
4.47073
0.0112
2.42272
0.0122
0.11845
0.01325
2.31298
0.0143
4.38669
7D.18
GTNET PLAYBACK
0.01535
0.0164
0.01745
0.01845
0.0195
<...>
5.78198
6.28306
5.81244
4.52585
2.49537
The sampling period of this data file is calculated like this:

Sampling Period = 1.0 / (Base Frequency * Number of samples per cycle)
1.042 (msec) = 1.0 / ( 60.0 * 16 )
2) The RTDS simulation case prepared in step 2 was modified to have a phase input
to allow synchronization . The phase input is generated from the PLL (Phase Locked
Loop) in the simulation case. The Draft case is shown below in figure 23.
Figure 24. RTDS Simulation Case
Figure 25 shows the settings of the playback model in the above simulation case.
7D.19
GTNET PLAYBACK
Figure 25. CONFIGURATION settings
The Synchronization Source is selected as PLL, indicating the phase input signal
will be used as a synchronization source for playback operation. With the selection
of Synchronization Source as PLL, a new tab appears beside the
GTNET_PLAYBACK NETWORK CONFIGURATION. The following figure
shows the settings in the new SYNCHRONIZATION tab.
Figure 26. SYNCHRONIZATION settings
The Number of points in 2*pi indicates that 16 samples would be produced by the
model during the period of 1 cycle (2*pi radian). The Initial Frequency indicates
that the base frequency of the input data is 60 Hz. By selecting No for Enable
Interpolation, the internal interpolation function of the playback model is disabled.
3) Compile and run the case. In order to see the operation of the PLL synchronization,
7D.20
GTNET PLAYBACK
two different runs are tested. First, the frequency of the sine wave generator and PLL
in the case is set to 60 Hz. Then the case is compiled and run. Second, the frequency
is set to 80 Hz and the case is compiled and run again. Figure 26 shows the
comparison between those two simulation runs.
The upper plot marked as 60 Hz is the simulation result when the frequency is set
to 60 Hz and the lower plot marked as 80 Hz is the simulation result when the
frequency is set to 80 Hz. As expected, the period of the sine wave output from the
playback model is shorter when the frequency is 80 Hz than the period of the output
when the frequency is 60 Hz. For the clearer comparison, those two plots are enlarged
and the period of one cycle in each of those two outputs were measured. Figure 27
is the zoomed plot for the case of 60 Hz simulation.
7D.21
GTNET PLAYBACK
Figure 28. 60 Hz simulation output
The period calculation on the left side shows that the period of the output waveform
is 16.7 msec which is the period of 60 Hz sine wave.
Figure 29 is the zoomed plot for the case of 80 Hz simulation.
Figure 29. 80 Hz Simulation Output
The period calculation on the left side shows that the period of the output waveform
is 12.5 msec which is the period of 80 Hz sine wave.
Using a different phase source other than PLL
The PLL(Phase Locked Loop) is not the only model which can provide phase
information to the playback model as synchronization source. The simulation case
7D.22
GTNET PLAYBACK
presented in Figure 29 shows a different way to generate the phase information. In

this case, a ramp generator is generating a phase ramp signal which is gradually
increasing from 0.0 to 2. The playback model is producing its output in
synchronism with the phase input signal from the ramp generator.
Figure 30. A Different Phase Source
Figure 31 shows the parameters given to the ramp generator model.
7D.23
GTNET PLAYBACK
Figure 31. Ramp Generator Parameters
Ramphi and Ramphlo values indicate the maximum and minimum value of the
ramp. T value dictates the period of the ramp signal. If the system freqieucy is 60
Hz, the period of one cycle is 16.6666 msec ( 16.6666(msec) = 1 / 60 (Hz) ). So, the
time constant T in Figure 30 is calculated in this way:
0.0026525823848649224 = 1.0 / (2 * * 60)
By controlling the Speed PU input to the ramp generator model the pace of the
output can be moderated. The following figure illustrates the different frequency of
output according to the different Speed PU input value.
7D.24
GTNET PLAYBACK
Figure 32. Controlling Output Pace
See Also:
RTDS Hardware Manual Chapter 19
GIGABIT TRANSCEIVER NETWORK INTERFACE SYSTEM (GTNET)
7D.25
GTNET PLAYBACK
Execution Time (Approximation):
Number of channel is 1
No synchronization: 5258 nsec
PLL synchronization without interpolation: 5248 nsec
PLL synchronization with interpolation: 5296 nsec
7D.26
Rev. 0.3 March 2014
7E
GTNET SV
( rtds_ctl_GTNET_SV92_v5.def )
The GTNET_SV92_v5 component provides IEC 6185092 Sampled Values

communications using the GTNET hardware. The GTNET_SV92_v5 component
has 2 configurations with 1 configuration being, the commonly used implementation
called 9.2LE. The other implementation is based on IEC 618699 and the Chinese
national Standard for SV merging units.
When 9.2LE configuration is used the GTNET is able to transmit up to two data
streams for up to 4 current and 4 voltage channels at a rate of 80 samples/cycle, or
one stream at 256 samples/cycle, or the GTNET_SV92_v5 can be configured to receive sampled data from one Merging Unit ( 4 currents and 4 voltages) at either 80
or 256 samples/cycle.
When Non9.2LE configuration is used the GTNET is able to transmit one datastream for up to 24 channels of voltage or current or a non voltage or current channel
called timedelay. The timedelay channel is the first channel in a Chinese merging
unit SV datastream. The data rate is currently limited to 80 samples/cycle.
The GTSYNC (synchronization card) is needed for use of the GTNET_SV92_v5
component in order to synchronize the SV timestamps to an external 1PPS (one
pulsepersecond) signal from a synchronized time source. Refer to the GTSYNC
chapter of the RTDS Hardware Manual for more information.
The GTNET is connected to the RTDS simulator through one GTIO port on a GPC/
PB5. It is connected to external IEDs through the GTNET Ethernet port. The typical
setup is shown in the figure below, refer to the GTNET chapter of the RTDS HardRTDS TECHNOLOGIES INC.
7E.1
GTNET SV
ware Manual for more information. Some terminology in this section is specific to
the IEC 61850 standards, it is recommended that the user be familiar with the 61850
standards before proceeding. The GTNETSV implementation closely follows the
R21 of the document titled Implementation Guideline for Digital Interface to Instrument Transformers using IEC 6185092published by the UCA International
Users Group. This document is commonly referred to as 92LE.
EXTERNAL DEVICES
(IEDs or Merging Unit)
GPC/PB5
ETHERNET SWITCH
GTNET
7E.0 MINIMUM VERSION REQUIREMENTS (9.2LE)

GTSYNC OS : 1.22
GTSYNC FPGA : 19
GTWIF OS : 4.103 build 7
GTWIF FPGA : 8070
GTNETSV : 4.11
GTNET FPGA : 24
RSCAD : 3.00x
GTNET firmware version prior to v4.11 require that the GTNET be synchronized
to an external or internally generated 1PPS signal. For GTNET firmware version
v4.11 and higher the 1PPS used to provide synchronized timestamping between the
sender and receiving devices is generated by the simulation. When the GTNET is
synchronized by the simulation a GTWIF must be used with a GTSYNC card, a WIF
can not support internal simulation synchronization. The GTSYNC card provides
a 1PPS signal to the GTWIF card via a fiber connection. The GTWIF synchronizes
to each 1PPS pulse and will adjust the internal timestep of the simulator.
7E.0a MINIMUM VERSION REQUIREMENTS (NON9.2LE)
GTSYNC OS : 1.22
GTSYNC FPGA : 19
GTWIF OS : 4.104 build 1
GTWIF FPGA : 8074
GTNETSV : 4.16
GTNET FPGA : 29
RSCAD : 4.002x
7E.2
GTNET SV
7E.1 SAMPLED VALUES COMMUNICATION (9.2LE)
OUTPUT MODE
IEC 6185092Sampled Value (SV) output is configured through the fields within
the GTNETSV92_v5 draft component. The parameters found in the IEC 61850
configuration tab are used to create the attributes LDName and MsvID. Within the
92 message the MsvID is created from the user configurable attribute LDName.
The LDName is configured by adding a user configurable prefix and suffix to the
string ppppMUss01 or ppppMUss02 where pppp is the parameter LDpre
and ss is the parameter LDsuf. The string MU and 01/02 are fixed and can not
be changed by the user. The value 01 is used for 80 samples/cycle and 02 is used for
256 samples/cycle. In addition, the confRev value and the sample sync also user configurable. The GTNETSV can output one stream at 256 samples/cycle or 2 streams
at 80 samples/cycle.
The voltage and current inputs to the GTNETSV92_v5component can not be individually enabled or disabled. When a channel is not required, the input should be set
to a value of 0.0 by using a constant.
When a case is compiled, an IEC 61850 SCL file is created in the case directory for
each SV output. The file name will use the parameter Name or Name2 and the extension *.iid for the filename of the SCL file. When there is two or more GTNETSV
components are in a draft case the user must ensure that each Name parameter is
unique so that an SCL file will be created for each output stream.
INPUT MODE
When the GTNET is operated in Input mode the samples contained in the IEC
6185092 messages are interpolated from the timestep. Therefore the timestep
must be smaller than the sampled value sample rate. When operating at 80 samples/
cycle, the maximum timestep period is 85 usec.
IEC 6185092 Sampled Value input is configured through the fields within the
GTNETSV92_v5 draft component. The GTNET uses the destination multicast
address of the SV packets to identify the intended SV stream. All other packets are
filtered and not processed by the GTNET. For this reason, the destination multicast
address of the SV must be unique within the connected Ethernet network. The
GTNET supports input of one stream at either 80 or 256 samples/cycle.
7E.1a SAMPLED VALUES COMMUNICATION (NON9.2LE)
OUTPUT MODE
The Non9.2LEconfiguration is basically a 9.2LE stream with up to 24 configurable
channels. IEC 6185092 Sampled Value (SV) output is configured through the
fields within the GTNETSV92_v5draft component. The GTNETSV can output
7E.3
GTNET SV
one stream of up to 24 channels at 80 samples/cycle. IEDs designed for SV use in
China do not require the IED to be synchronized to an external time source and the
GTNET must be capable of providing samples with less than 10 usec of jitter between samples. The GTNET requires a minimum version of FPGA to meet this low
jitter tolerance, see section 7E.0a for the minimum version requirements.
The parameters found in the IEC 61850 configuration tab are used to create the attributes LDName and MsvID. Within the 92 message the MsvID is created from the
user configurable attribute LDName. The LDName is configured by adding a user
configurable prefix and suffix to the string ppppMUss01 or ppppMUss02
where pppp is the parameter LDpre and ss is the parameter LDsuf. The
string MU and 01/02 are fixed and can not be changed by the user. The value 01 is
used for 80 samples/cycle and the confRev value and the sample sync also user configurable.
The parameter nChan in the GTNETSV92_v5component specifies the number
of channels between 124. When a channel is enabled but not required, the input
should be set to a value of 0.0 by using a constant.
Merging units in China typically are connected to the IED in a pointtopoint connection and use channel 1 of the datastream to transmit the time delay of this connection between the merging unit and IED. The channel 1 data input format must be set
to INT and channel 1 data type must be set to TimeDelay.
When a case is compiled, an IEC 61850 SCL file is created in the draft case directory.
The file name will use the parameter Name and the extension *.iid for the filename
of the SCL file. When there is two or more GTNETSV components are in a draft
case the user must ensure that each Name parameter is unique so that an SCL file will
be created for each output stream.
INPUT MODE
Input mode is not supported at this time.
7E.2 RSCAD DRAFT COMPONENT AND PARAMETER ENTRIES
The RSCAD Draft component used for GTNETSV92_v5 is named
rtds_ctl_GTNET_SV92_V5.def and can be found in the MLIB\CTLS_V2\IO directory. The figures below illustrate the menus used for the GTNET_SV92_v5
component.
7E.4
GTNET SV
Because Non9.2LE increases the amount of inputs by 3 times the number of inputs
used for 9.2LE, the input connections are done using external references. There are
three TABS used to config the external references, the signal name/format tab, the
channel offset tab, and the channel delays tab. The channel scaling TAB changes to
handle the additional channels.
CONFIGURATION TAB
The configuration tab is used to identify the GTNET hardware in the system.

Mode The component can be either set to Output mode or Input mode.
nSV When the Mode set to Output, up to two SV output can be set. Non 9.2LE does
not support SV output.
Note: Dual SV output is only available when operating at 80 samples/cycle.
SYSFREQ Either 50 or 60 Hz can be set for nominal system frequency.
SMPRT Either 80 or 256 samples/cycle can be set for sample rate. Dual SV output
or Non9.2LE does not support the sample rate of 256.
IECver The version of the IEC Standard. This setting controls the behavior of the
communication protocol, 9.2LE is supported or a Non9.2LE version is supported.
nChan The number of channels that the GTNET will provide in the datastream.
Port The GTIO fiber port number of the GPC/PB5 card that the GTNET is connected to.
Card The number of the GTNET card on the GPC/PB5 GT peripheral chain. 1 refers to the first GTNET_SV on the GT peripheral chain, 2 refers to the second
GTNET_SV on the GT peripheral chain.
7E.5
GTNET SV
Prtyp Only GPC/PB5 are supported with this component.
Name The name give to identify this component within Draft and Runtime. The
name used to create the SCL file and the iedName of the connectedAP in the SCL
file.
SV1 OUTPUT IEC 61850 CONFIG TAB
The SV1 OUTPUT IEC 61850 CONFIG tab is used to specify the IEC 61850
configuration for SV1 when Mode is set to Output.
APPID Ethertype PDU APPID value including the APPID type bits. The
recommended range for IEC 6185092 is 4000 (hex) to 7FFF (hex).
VLANPRI IEEE 802.1Q User Priority value used in the message link layer tag.
VLANID IEEE 802.1Q VID value used in the message link layer tag.
LDpre Prefix used for construction the LDName which is used to create the MsvID
string in the output messages. The LDName will be constructed as ppppMUss01
or ppppMUss02 where pppp is the 4 to 7 character LDpre string and ss is the LDsuf
value. For example, if LDpre is RTDS and LDsuf is 00, then the LDName is
RTDSMU0001 for 80 samples/cycle.
LDsuf Suffix used for construction of the LDName which is used to create the
MsvID string in the output messages. The suffix is a 2 digit value from 00 to 99.
MACH Enter the 3 most significant bytes in hex of the multicast address that the
GTNET sends the IEC 6185092 messages to.
7E.6
GTNET SV
MACL Enter the 3 least significant bytes in hex of the multicast address that the
GTNET sends the IEC 6185092 messages to.
INCRT Set to TRUE to include the refreshtime field in the IEC 6185092output
message. Currently fixed to FALSE.
INCSSF Set to TRUE to include the samplesynchronized field in the IEC
6185092 output message. Set to CC to allow user control with a controls
component. This field is normally set to TRUE.
INCSR Set to TRUE to include the samplerate field in the IEC 6185092output
message. Currently fixed to FALSE.
CONFREV Sets the ConfRev field value in the IEC 6185092 SV1 output
message.
sName This field is used in the creation of the SCL file
sLevel This field is used in the creation of the SCL file
sBay This field is used in the creation of the SCL file
VDLY Set to YES to delay voltage input signals by 1 timestep to align them with
the current inputs. In network simulations, the current signals are delayed by 1
timestep relative to the voltage signals. In such cases, the voltage inputs can be
delayed to align the voltage signals with the current signals.
SV2 OUTPUT IEC 61850 CONFIG TAB
The SV2 OUTPUT IEC 61850 CONFIG tab is used to specify the IEC 61850
configuration for SV2 when Mode is set to Output, and nSV is set to 2. Refer to
SV1 OUTPUT IEC 61850 CONFIG section for parameters setting.
SV1 OUTPUT CHANNEL QUALITY ENABLES TAB
The SV1Output Channel Quality Enables configuration menu is used to enable and
specify variables to control the quality bitmaps of the 8 output channels of the SV1.
7E.7
GTNET SV
ENxxQ and INxxQ Set to YES to enable control the quality bits for the channel.
Quality bits are fixed at 0 when this setting is set to NO. When set to YES, the
variable specified by INxxQ controls the value of the quality bitmap in the outgoing
message. Bit 0 is the least significant bit in the bitmap. The bits in the quality bitmap
are defined in IEC 6185073 as:
Bits
Attribute Name
Value/Value Range
1:0
validity
good=00, invalid=01, reserved=10, questionable=11, default=good
detailQual overflow
false=0, true=1, default=false
detailQual oscillatory
detailQual failure
detailQual oldData
10
source
process=0, substituted=1, default=process
11
test
12
operatorBlocked
13
derived
SV2 OUTPUT CHANNEL QUALITY ENABLES TAB

This tab is enabled when Mode is set to Output and nSV is set to 2. Refer SV1
OUTPUT CHANNEL QUALITY ENABLES TAB section for parameters setting.
CHANNEL SCALING TAB
The Channel Scaling tab is provided to display the IEC 61850 scale and offset values
used for the voltage and current channels and to allow selection of the units for the
7E.8
GTNET SV
voltage and current inputs to the GTNETSV92_V5 component.
SCALEV Displays the IEC 6185092sVC.scaleFactor used for voltage channels.

Default value as per 92LE is 0.01.
SCALEI Displays the IEC 6185092sVC.scaleFactor used for current channels.
Default value as per 92LE is 0.001.
OFFSETV Displays the IEC 6185092 sVC.offset used for voltage channels.
Default value as per 92LE is 0.
OFFSETI Displays the IEC 6185092 sVC.offset used for current channels.
UNITS Sets the units for the channels input to the GTNETSV92_V5component.
If the inputs to the GTNETSV92_V5are in units of kV and kA (primary values),
this setting should be set to kV/kA.
IEC 61850 CONFIG TAB (when SV Mode set to Input)
The IEC 61850 CONFIG tab is enabled to specify the IEC 61850 configuration when
SV mode is set to Input.
In Input Mode, the GTNETSV92_V5 component can subscribe to SV messages
from one Merging Unit, which provides four currents and four voltages, at either 80
or 256 samples/cycle.
7E.9
GTNET SV
MACINH Enter the 3 most significant bytes in hex of the multicast address that the
GTNET receives the IEC 6185092 messages from.
MACINL Enter the 3 least significant bytes in hex of the multicast address that the
GTNET receives the IEC 6185092 messages from.
INTERP Select YES to enable the Interpolated mode, NO to enable the Immediate
processing mode. The differences between this two modes are described below:
Interpolated mode The SV input data received from the merging unit is sampled
and after some userconfigurable time it appears on the components outputs.
This delay allows the processor card to buffer the samples being sent over the
network and being received by the GTNET . Because the SV merging unit is
operating asynchronously the SV sample instants do not line up with the timestep,
therefore interpolation is applied to generate signals synchronized to the timestep.
Users testing a merging unit would use this mode to compare the SV stream from
the MU with the signals applied to the MU using a GTAO.
Immediate processing mode The SV data appears on the component outputs as
soon as it is received by the processor card/GTNET. The data will exhibit jitter
7E.10
GTNET SV
due to network and processing variations but will have no extra delay added for
timealignment. Users designing their own SV reception and processing
algorithms would use this mode.
SMPDLY If interpolated mode is selected, enter a delay time in number of sample
periods to delay output samples. The delay is required to allow packets to be received
and buffered before interpolation. A delay time of 4 packets is normally sufficient.
When operating at 256 samples/cycle, this corresponds to a setting of 24 samples,
since SV messages at this sample rate are sent as a group of 8 samples. This setting
is a tradeoff between latency and reliability. A lower setting will provide lower
latency, but may have sporadic errors due to packet reception timing jitter. A higher
setting will provide more robust output, but at the expense of larger latency. Errors
can be monitored through bit 7 of the STATUS named output variable.
The following named variable outputs contain information about the packet being
output. These variables can be monitored in RunTime or utilized within the
simulation:
NEWPKT Set to 1 during the timestep that new packet data is output from the
component.
STATUS Bitmap containing information regarding the status of the GTNETSV
reception. The rightmost bit is bit 0. The definition of each bit in the STATUS is
shown below:
INITIALIZING
WAITING_FOR_CORRECT_SEQ
RX_PKT
GTNET_MSG_INCOMPAT_1
INVALID_SAMPLE_DATA_LEN
GTNET_MSG_INCOMPAT_1
BUFFER_OVERFLOW
INTERPOLATION_ERROR
BUFFER_EMPTY
SAMPLE_RDY
0
1
2
3
4
5
6
7
8
9
SMPSYNCH Set to 0, 1 or 2 if SV input packet contains the attribute SmpSynch

or 0 when attribute SmpSynch is not available in the SV buffer. As per the 92LE
version 3 documentation, 0 indicates no synchronization or synchronization lost, 1
indicates Local 1PPS synchronization and 2 indicates Global 1PPS
synchronization.
SMPCNT The SmpCnt field value in the IEC 6185092 SV input packet.
ASDU Application Service Data Unit index from the SV input packet.
CONFREV The ConfRev field value in the IEC 6185092 SV input packet.
7E.11
GTNET SV
SIGNAL NAME/FORMAT TAB (Non9.2LE)
The Signal/Name Format tab is provided to display the IEC 61850 input format, data
type, data signal name, and quality signal name for each channel.
CHxTYPE The format of the data used as input for the channel. Typically this is
a FLOAT but must be an INT if the channel is used as a time delay.
CHnVI The type of data used as input for the channel. Typically this will be set to
VA, VB, VC, VN, IA, IB, IC, or IN and only set to TimeDelay when used for Chinese
SV applications.
CHnD The name of the data signal used as input for the channel.
CHnQ The name of the quality signal used as the quality input for the channel.
Qualities by default are always transmitted with the data and can not be disabled.
CHANNEL OFFSET TAB (Non9.2LE)
CHnOFFSET Displays the IEC 6185092sVC.offset used for voltage or current
channels. If the channel is configured as a TimeDelay the parameter is disabled.
7E.12
GTNET SV
CHANNEL DELAYS TAB (Non9.2LE)
CHnDLY Set to YES to delay voltage input signals by 1 timestep to align them with
the current inputs. In network simulations, the current signals are delayed by 1
timestep relative to the voltage signals. In such cases, the voltage inputs can be
delayed to align the voltage signals with the current signals.
CHANNEL SCALING TAB (Non9.2LE)

UNITS Sets the units for the channels input to the GTNETSV92_V5component.
If the inputs to the GTNETSV92_V5are in units of kV and kA (primary values),
this setting should be set to kV/kA.
CHnSCALE Displays the IEC 6185092 sVC.scaleFactor used for voltage or
current channels. If the channel is configured as a TimeDelay the parameter is
disabled. Default value as per 92LE is 0.01 for voltage channels and 0.001 for
current channels.
7E.13
August 2012
7Ex
GTNET SV Special Edition

( rtds_ctl_GTNET_SVSE2.def )
The GTNET_SV_SE2 component is a special edition of the GTNET_SV92_v5

component. For the information that not mentioned in this documentation, please refer to the GTNET_SV92_v5 documentation.
Compared with GTNET_SV92_v5 component, GTNET_SV_SE2 component has
the following limitation and extra features:
It only supports 1 SV data output stream at 80 samples per cycle;
It can be configured to suppress a packet or packets;
It can be configured to change the order of two consecutive packets;
It can be configured to delay the packets;
CONTROL INPUT/OUTPUT SIGNAL NAMES TAB
The Control Input/Output Signal Names menu is used to specify variables for suppressing packets, changing the order of two consecutive packets, and delaying the
packets.
NsprsMsg The input variable name to suppress the sending of the packets. The
expected inputs are either integer 0 or 1. GTNET will stop sending packets whenever
an input of 1 is detected.
7Ex.1
GTNET SVSE
NchgOrdr The input variable name to trigger the swapping event. A single swap
between the two consecutive packets will occur when a change from 0 to 1 is detected in the input.
NdlyDt The input variable name to delay the packets. The unit of this input is in
Number of TimeSteps. The delay is limited between 0 and 3 sampleperiod (truncated into an integer). An input of 0 means no delay required. For a 50Hz system with
50us timestep, maximum delay value is 15. For a 60Hz system with 50us timestep,
maximum delay value is 12. Intentional jitter could be achieved by a varying delay
input.
NsmpCnter The output variable name to monitor the smpCnt information of the
latest sampled data. This variable could be used in logic where the input variables,
NsprsMsg, NchgOrdr, and NdlyDt are created.
Execution Time
PB5
1.057 us
One output stream at 80 samples/cycle

including quality bit control
7Ex.2
Rev. 0.7: October 13
7F
GTNET PMU
( _rtds_GTNET_PMU_v4.def )
The phasor measurement (PMU) component is suitable for providing the

symmetrical component information related to 3 phase sets of instantaneous values
of voltage and current. Eight PMUs are included in 1 component and operate
independently. If the C37118 data output is disabled the GTNETPMU8 component
a GTNET and GTSYNC card is not required and the phasor data is only available
as named output variables. If the C37118 data output is enabled the GTNETPMU24
component requires a GTNET and GTSYNC card to operate. The GTNET card is
connected to the RTDS through a GTIO port on a GPC/PB5 card. The GTNETPMU
component output is synchronized to an external 1PPS, IRIGB,or IEEE 1588 signal
via the GTSYNC . The GTSYNC card is connected to port 7 of a GTWIF card, see
the hardware manual for more information on the GTSYNC.
Description:
The measuring loops provide the phasor information for the voltage, current,
positive, negative, and zero sequence (voltage and current). These plot signals are
available in real and imaginary or magnitude and angle values. If all signals are
selected each PMU will provide a total of 12 phasors, the measured frequency, and
rate of change of frequency. Note: If the runtime plot signal outputs are not being
used they can be disabled to minimize backplane transfers and help optimize the
simulation timestep.
Operation:
The voltage and current signals are connected to each PMU via 6 signal name inputs
in the component menus. Two PMU algorithms can be used with this component,
the parameter pmutype changes the algorithm from Annex C of the IEEE
C37.11.8.12011 standard to P class or M class.
The angle difference between 2 PMUs can be measured and monitored, the output
is reported in degrees. A dial is used to select the reference PMU (default is PMU1)
and another dial is used to select the second PMU (default is PMU2).
7F.1
GTNET PMU
The P class and M class reference signal processing model found in Annex C of the
IEEE C37.118.1.2011 standard is described next, see the standard for complete
details.. Figure 7.1 shows the typical steps used within the PMU to process the input
signals. The antialiasing LP filter described above was not implemented in the
component, a GTNET card provides the absolute timereference and the simulation
data is sampled using a fixed sample rate. The quadrature oscillator operates at
nominal frequency and is used to perform complex multiplication of the input signal.
The LP filters are used to remove the double frequency component thus leaving the
Re and Im part of the original input signal. For P and M class the LP filters are
implemented using symmetrical FIR filters with a odd number of stages. The P class
filter coefficients are calculated using a triangular window and the M class filter
coefficients are calculated using windowed sinc function multiplied with a
Hamming window. Each sample is timestamped and compensated for the group
delay of the LP filter. The phasor estimate at the center of the estimation window is
unbiased by the actual system frequency and does not require further phase
correction when the timestamp at the center of the window is used. The P and M
class samples at 16 samples per cycle. The P class sample rate was changed from the
15 sample per cycle listed in the Annex to allow proper decimation at reporting rates
greater than 50 fps and 60 fps. The P class has 2 cycle window FIR window while
the M class window varies in length with the reporting rate.
Figure 7.1: Single phase section of PMU phasor signal processing model
7F.2
C37.118
Phasor Data
Visualization
Software
GPS Clock
1 PPS Signal, IRIGB, or IEEE 1588
GT Port Connection
GTSYNC
Phasor Data
Concentrator
(PDC)
Ethernet Switch
PB5
Ethernet LAN
GTWIF Port 7
GTNET
Figure 7.2: Using GTNET_PMU with PDC and Visualization Software
7F.3
GTNET PMU
Calibration of PMU:
A common angle offset can be applied to all signals using the calib_const
parameter found in the CONFIGURATION tab. A common timestep adjustmnet
can be applied to all signals using the dt_adj parameter. Each PMU has
independent angle offsets that can be applied to each voltage and current input.
The following reporting rates are supported for each P Class PMU
50 Hz
System frequency
Reporting rates
(Fs frames per second)
N = 30
1
2
5
10
25
50
100
200
Filter Order N = number of taps
60Hz
N = 30
1
2
4
5
10
12
15
20
30
60
120
240
When a sample interrupt occurs for a PMU the input data is processed and the
timestamp is saved. The PMU then processes the phasor information in a 4
timestep thread which means there is a 200 usec latency before all the phasor
information is processed with a simulation timestep of 50 usec. A decimator is used
to reduce to the appropriate reporting rate. Only 1 PMU can be serviced during a
timestep and counter is used to provide 5 timesteps delay before the GTNET can
output another PMUs data.
The following reporting rates are supported for each M Class PMU
System frequency
Reporting rates
50 Hz
N = 806
= 338
= 142
= 66
= 66
10
25
50
100
200
60Hz
N = 968
= 816
= 662
= 502
= 306
= 164
= 70
= 70
10
12
15
20
30
60
120
240
timestamp is saved. The PMU then processes the phasor information in a 7
7F.4
C37.118
timestep thread which means there is a 350 usec latency before all the phasor
information is processed with a simulation timestep of 50 usec. A decimator is used
to reduce to the appropriate reporting rate. Only 1 PMU can be serviced during a
timestep and counter is used to provide 5 timesteps delay before the GTNET can
output another PMUs data.
AC Input signals for each PMU (n = 18)
Signal
Description
Format
nVTA(n)
A phase voltage signal name
Float
nVTB(n)
B phase voltage signal name
Float
nVTC(n)
C phase voltage signal name
Float
nCTA(n)
A phase current signal name
Float
nCTB(n)
B phase current signal name
Float
nCTC(n)
C phase current signal name
Float
Analog/Digital Input signals for each PMU (n = 18)

Signal
Description
Format
p(n)AI1
Analog input 1 signal name
Float
p(n)AI2
Float
p(n)AI3
Float
p(n)AI4
Float
p(n)DI1
Digital input 1 signal name (16bit)
Integer
Output signals for each PMU

Signal
Description
Format
PM1
Reporting rate FPS trigger PMU1
Integer
PM2
Integer
PM3
Integer
PM4
Integer
PM5
Integer
PM6
Integer
PM7
Integer
PM8
Integer
1PPS
Internal Pulse per second trigger
Integer
Setting parameters for the PMU COMPONENT will be described in the following
paragraphs.
7F.5
GTNET PMU
CONFIGURATION:
Parameter
Range
Default
Unit
Description
eC37data
NO, YES
YES
Enable output of C37.118 data using a

GTNET card
Name
10 character
PMU1
Component Name
pmutype
RTDS,
AnnexC[P],
AnnexC[M]
RTDS
Type of PMU algorithm used to process the input signals.
cfgtype
Config_2,
Config_3
Config_2
Configuration frame format
freq
60, 50
60
Hz
Nominal system frequency
nPMU
0 8
Number of PMUs (maximum 8)
adv
None,
V by 1dt
V by 1dt
Delay Input Signal to align V & I
eAngM
NO, YES
NO
Enable Angle Difference Meter
nAngDiff
10 characters angdiff
Angle Difference Meter Name

(PMUxPMUy)
sfx
1 character
User defined suffix can be added to

plot signal names
calib_const
+/360
0.0
degrees
Common offset applied to all PMU inputs in degrees.
dt_adj
+/500
dt
Common offset applied to all PMU inputs in timesteps.
ePri
NO, YES
YES
Enable use of Primary Voltage and

Current signal names. Scaling is done
automatically based upon the ratios
GT_SOC
10 characters ADVSECD
The output signal of the GTSYNC

draft component that provides the second of century value for timestamping
GT_STAT
10 characters ADVSTAT

draft component that provides the
Time quality value for timestamping
phs_rot
ABC,
ACB
Phase rotation of system
ABC

ADV Set to yes to delay voltage input signals by 1 timestep to align them with the
current inputs.
7F.6
C37.118
Port The GTIO fiber port number of the GPC/PB5 card that the GTNET is
connected too.
Card The number of the GTNET card on the GPC/PB5 GT peripheral chain. 1
refers to the first GTNET_PMU on the GT peripheral chain, only 1 GTNETPMU
is allowed per chain.
PMU(18) CONFIGURATION:
Parameter
Range
p(n)FPSa
Unit
Description
1,2,4,5,10,12 30
,15,20,30,60,
120,240
Reporting Rate (frames/sec) 60.0 Hz
p(n)FPSb
1,2,4,5,10,25 25
,50,100,200
p(n)decimate
NO,
YES
YES
Decimate PMU runtime output to the

frames per second value
p(n)STN
10 character
PMU1
PMU Station Name
p(n)IDC
165534
PMU Hardware ID Code
p(n)TCP
165535
4712
PMU Output TCP/IP or UDP local

port
p(n)CFG
032767
PMU Configuration change count
p(n)PHSout
012
Number of Phasors per PMU
p(n)IofFp
INTEGER,
REAL
REAL
Phasor Number Format
p(n)OUTF
An & Bn,
Cn & Phi
An & Bn
Phasor Output Format (real and imaginary) or (magnitude and phase)
p(n)IofFf
INTEGER,
REAL
REAL
Frequency Number Format
p(n)iAout
0,1,2,3,4
Number of Analog values
p(n)IorFa
INTEGER,
REAL
REAL
Analog Number Format
p(n)iDout
0,1
Number of 16 bit Digital Status
p(n)LAT
90.0 to 90.0 49.88619
Latitude in degrees, WGS84 datum
p(n)LON
180.0 to
180.0
Default
97.1531
91
Longitude in degrees, WGS84 datum
7F.7
GTNET PMU
p(n)ELEV
0 to
4294967296
230.8
p(n)ePHS(n)
NO,VA,VB, NO
VC,IA,IB,IC
,V1,V2,V0,I
1,I2,I0
Elevation in meters, WGS84 datum
Phasors 112 Measured Quantity
p(n)erPHS(n) NO,YES
YES
Monitor Phasors 112 Runtime Output
p(n)eFREQ
NO,YES
YES
Monitor Frequency Runtime Output
p(n)eROCOF NO,YES
YES
Monitor ROCOF Runtime Output
p(n)eFRAC
NO,YES
YES
Monitor FRACSEC Runtime Output
p(n)PHS(n)sc
ale
Up sampled with
Up sampled
Phasors 112 data modification flag
interpolation;
with interpola-
Up sampled with
tion
extrapolation;
Down sampled,
Nth sample;
Down sampled
with FIR filter;
Filtered without
changing sampling;
Phasor Mag adjusted for calibration;
Phasor phase adjusted for calibration;
Phasor phase adjusted for rotation;
Pseudophasor value;
Modification applied, type not defined
p(n)PHS(n)us 0255
er
Phasors 112 user defined flag
p(n)ANUNT( 0255
n)a
Analogs 14 conversion factor

Most Significant Byte:
0 single pointonwave
1 rms of analog input
2 peak of analog input
564 reserved for future definition
65255 user definable
7F.8
C37.118
p(n)ANUNT( 8388608 to
8388607
n)b
100

Least Significant Byte:
A signed 24 bit word (CFG frame 2) /
32 bit word (CFG frame 3), user defined scaling
Analogs 14 offset
2147483648
to
2147483647
p(n)ANUNT( 2147483648 0
to
n)c
2147483647
p(n)eDIG(n)
NO:YES
YES
Digital status word bits 015 enable
p(n)sDIG(n)
NO:YES
YES
Digital status word bits 015 normal

state
p(n)eSTAT
NO:YES
NO
STAT (16 bits) field override enable
p(n)nSTAT
10 characters p(n)STAT
Signal name of STAT field
For user information, the word definitions for STAT field in IEEE C37.118.22011
and in IEEE C37.1182005 are listed below:
7F.9
GTNET PMU
Field
Size(bytes)
STAT
IEEE C37.118.22011
Bit mapped flags.
Bit 1514: Data error: 00 = good measurement data, no errors
01 = PMU error. No information about data
10 = PMU in test mode (do not use values) or
absent data tags have been inserted (do not use values)
11 = PMU error (do not use values)
Bit 13: PMU sync, 0 when in sync with a UTC traceable time source
Bit 12: Data sorting, 0 by time stamp, 1 by arrival
Bit 11: PMU trigger detected, 0 when no trigger
Bit 10: Configuration change, set to 1 for 1 min to advise
configuration will change, and clear to 0 when change effected.
Bit 09: Data modified, 1 if data modified by post processing, 0
otherwise
Bits 0806: PMU Time Quality. Refer to codes in Table 7.
Bits 0504: Unlocked time: 00 = sync locked or unlocked < 10 s (best
quality)
\01 = 10 s . unlocked time < 100 s
10 = 100 s < unlock time . 1000 s
11 = unlocked time > 1000 s
Bits 0300: Trigger reason:
11111000: Available for user definition
0111: Digital
0110: Reserved
0101: df/dt High
0100: Frequency high or low
0011: Phase angle diff
0010: Magnitude high
0001: Magnitude low
0000: Manual
7F.10
C37.118
Field
Size(bytes)
STAT
IEEE C37.1182005
Bitmapped flags.
Bit 15: Data valid, 0 when PMU data is valid, 1 when invalid or PMU
is in test mode.
Bit 14: PMU error including configuration error, 0 when no error.
Bit 13: PMU sync, 0 when in sync.
Bit 12: Data sorting, 0 by time stamp, 1 by arrival.
Bit 11: PMU trigger detected, 0 when no trigger.
Bit 10: Configuration changed, set to 1 for 1 min when configuration
changed.
Bits 0906: Reserved for security, presently set to 0.
Bits 0504: Unlocked time: 00 = sync locked, best quality
01 = Unlocked for 10 s
11 = Unlocked over 1000 s
0111: Digital
0110: Reserved
0101: df/dt high
0100: Frequency high/low
0011: Phaseangle diff
0001: Magnitude low
0000: Manual
7F.11
GTNET PMU
Monitoring signal names:
The default signal names of the Monitored signals for the PMU are shown next, the
names are fixed. An optional suffix can be added. Twelve phasors can be selected
per PMU. The phasor output can be configured with one of the following signals:
NO;VA;VB;VC;IA;IB;IC;V1;V2;V0;I1;I2;I0
(n = 18)
Signal
Description
Format
(P)p1(n)(a)
(P)p2n(a)
(P)p3n(a)
(P)p4n(a)
(P)p5n(a)
(P)p6n(a)
(P)p7n(a)
(P)p8n(a)
(P)p9n(a)
(P)p10n(a)
(P)p11n(a)
(P)p12n(a)
Phasors 1 12 real and imaginary or

magnitude and phase information of:
Where (P) = VA or VB or VC or IA or
IB or IC or V1 or V2 or V0 or I1 or I2
or I0
Where (n) = 1 8
Where (a) = re and im or c and phi
Float
PMU(n)freq
PMU measured frequency

Where (n) = 1 8
float (Hz)
PMU(n)rocof
PMU frequency rate of change

Where (n) = 1 8
float (Hz/s)
PMU(n)frac
PMU fracsec
Where (n) = 1 8
fraction of seconds
7F.12
Rev. 0.1: October 2013
7Fa
GTNET PMU24
( _rtds_GTNET_PMU_v5.def )

symmetrical component information related to 3 phase sets of instantaneous values
of voltage and current. Twentyfour (24) PMUs are included in 1 component and
operate independently. If the C37118 data output is disabled a GTNET and GTSYNC
card is not required and the phasor data is only available as named output variables.
If the C37118 data output is enabled the GTNETPMU24 component requires a
GTNET and GTSYNC card to operate. The GTNET card is connected to the RTDS
through a GTIO port on a GPC/PB5 card. The GTNETPMU component output is
synchronized to an external 1PPS, IRIGB, or IEEE 1588 signal via the GTSYNC
card. The GTSYNC card is connected to port 7 of a GTWIF card, see the hardware
manual for more information on the GTSYNC.
Description:
The measuring loops provide the positive sequence phasor information for the
voltage voltage and current. These plot signals are available in real and imaginary
or magnitude and angle values. An enabled PMU will provide a total of 2 phasors,
the measured frequency, and rate of change of frequency. Note: If the runtime plot
signal outputs are not being used they can be disabled to minimize backplane
transfers and help optimize the simulation timestep.
Operation:
The voltage and current signals are connected to each PMU via 6 signal name inputs
in the component menus. The PMU algorithm used in this component is the P class
reference algorithm from Annex C of the IEEE C37.11.8.12011 standard.
7Fa.1
GTNET PMU
The P class reference signal processing model found in Annex C of the IEEE
C37.118.1.2011 standard is described next, see the standard for complete details.
Figure 7Fa.1 shows the typical steps used within the PMU to process the input
signals. The antialiasingLP filter shown in figure 7Fa.1 was not implemented in the
component, a GTNET card provides the absolute timereference and the simulation
data is sampled using a fixed sample rate. The quadrature oscillator operates at
nominal frequency and is used to perform complex multiplication of the input signal.
The LP filters are used to remove the double frequency component thus leaving the
Re and Im part of the original input signal. The LP filters are implemented using
symmetrical FIR filters with a odd number of stages. The P class filter coefficients
are calculated using a triangular window. Each sample is timestamped and
compensated for the group delay of the LP filter. The phasor estimate at the center
of the estimation window is unbiased by the actual system frequency and does not
require further phase correction when the timestamp at the center of the window is
used. The P class samples at 16 samples per cycle and was changed from the 15
samples per cycle listed in Annex C. The P class has 2 cycle window FIR window.
Figure 7Fa.1: Single phase section of PMU phasor signal processing model
7Fa.2
C37.118
Phasor Data
Visualization
Software
GPS Clock
1 PPS Signal, IRIGB, or IEEE 1588
Phasor Data
Concentrator
(PDC)
GT Port Connection
GTSYNC
Ethernet Switch
PB5
Ethernet LAN
GTWIF Port 7
GTNET
Figure 7Fa.2: Using GTNET_PMU with PDC and Visualization Software
7Fa.3
GTNET PMU
Calibration of PMU:
A common angle offset can be applied to all signals using the calib_const
parameter found in the CONFIGURATION tab. A common timestep adjustment
can be applied to all signals using the dt_adj parameter. Each PMU has
independent angle offsets that can be applied to each voltage and current input.
The following reporting rates are supported for each P Class PMU
50 Hz
System frequency
Reporting rates
N = 30
1
2
5
10
25
50
60Hz
N = 30
1
2
4
5
10
12
15
20
30
60
timestampis saved. The PMU then processes the input data and produces the phasor
information in an 8 timestep thread which means there is a 400 usec latency before
all the phasor information is processed with a simulation timestep of 50 usec. Only
1 PMU can be serviced during a timestep, if all 24 PMUs are enabled it will take
24 timesteps before all the PMU data is sent to the GTNET.
Note: Reporting rates higher than nominal system frequency are not supported by
this component.
CONFIGURATION:
Parameter
Range
Default
Unit
Description
eC37data
NO, YES
YES
Enable output of C37.118 data using a

GTNET card
Name
10 character
PMU1
Component Name
pmutype
AnnexC[P]
AnnexC[P]
Type of PMU algorithm used to process the input signals.
cfgtype
Config_2,
Config_3
Config_2
Configuration frame format
7Fa.4
C37.118
freq
60, 50
60
Hz
nPMU
0 24
adv
None,
V by 1dt
V by 1dt
eAngM
NO, YES
NO
nAngDiff

(PMUxPMUy)
sfx
1 character

plot signal names
calib_const
+/360
0.0
degrees
Common offset applied to all PMU inputs in degrees.
dt_adj
+/500
dt
Common offset applied to all PMU inputs in timesteps.
ePri
NO, YES
YES

GT_SOC
10 characters ADVSECD

draft component that provides the second of century value for timestamping
GT_STAT
10 characters ADVSTAT

draft component that provides the
Time quality value for timestamping
phs_rot
ABC,
ACB
Phase rotation of system
ABC

ADV Set to yes to delay voltage input signals by 1 timestep to align them with the
current inputs.
Port The GTIO fiber port number of the GPC/PB5 card that the GTNET is
connected too.
Card The number of the GTNET card on the GPC/PB5 GT peripheral chain. 1
refers to the first GTNET_PMU on the GT peripheral chain, only 1 GTNETPMU
is allowed per chain.
7Fa.5
GTNET PMU
Parameter
Range
p(n)FPSa
Unit
Description
1,2,4,5,10,12 30
,15,20,30,60
p(n)FPSb
1,2,4,5,10,25 25
,50
p(n)decimate
NO,
YES
YES
Decimate PMU runtime output to the

frames per second value
p(n)STN
10 character
PMU1
PMU Station Name
p(n)IDC
165534
p(n)TCP
165535
4712
PMU Output TCP/IP or UDP local

port
p(n)CFG
032767
PMU Configuration change count
p(n)PHSout
012
Number of Phasors per PMU
p(n)IofFp
INTEGER,
REAL
REAL
Phasor Number Format
p(n)OUTF
An & Bn,
Cn & Phi
An & Bn
p(n)IofFf
INTEGER,
REAL
REAL
Frequency Number Format
p(n)iAout
0,1,2,3,4
Number of Analog values
p(n)IorFa
INTEGER,
REAL
REAL
Analog Number Format
p(n)iDout
0,1
Number of 16 bit Digital Status
p(n)LAT
90.0 to 90.0 49.88619
Latitude in degrees, WGS84 datum
p(n)LON
180.0 to
180.0
97.1531
91
Longitude in degrees, WGS84 datum
p(n)ELEV
0 to
4294967296
230.8
Elevation in meters, WGS84 datum
p(n)erPHS(n) NO,YES
YES
Monitor Phasors 12 Runtime Output
p(n)eFREQ
NO,YES
YES
Monitor Frequency Runtime Output
p(n)eROCOF NO,YES
YES
Monitor ROCOF Runtime Output
p(n)eFRAC
NO,YES
YES
Monitor FRACSEC Runtime Output
p(n)eTrig
NO,YES
YES
Monitor Sample Trigger Runtime Output
rVT(n)
1 to 10000
2000.0
PT turns ratio : 1
rCT(n)
1 to 5000
600.0
CT turns ratio : 1
nVTA(n)
10 characters N1
Default
7Fa.6
C37.118
nVTB(n)
10 characters N2
nVTC(n)
10 characters N3
nCTA(n)
10 characters IBRKA
nCTB(n)
10 characters IBRKB
nCTC(n)
10 characters IBRKC
p(n)AI1
10 characters p1A1
p(n)AI2
10 characters p1A2
p(n)AI3
10 characters p1A3
p(n)AI4
10 characters p1A4
p(n)DI1
10 characters p1D1
Digital input 1 signal name (16 bit)
p(n)Va_c
+/180
0.0
degrees
Calibration offset for VA input.
p(n)Vb_c
+/180
0.0
degrees
Calibration offset for VB input.
p(n)Vc_c
+/180
0.0
degrees
Calibration offset for VC input.
p(n)Ia_c
+/180
0.0
degrees
Calibration offset for IA input.
p(n)Ib_c
+/180
0.0
degrees
Calibration offset for IB input.
p(n)Ic_c
+/180
0.0
degrees
Calibration offset for IC input.
p(n)PHS(n)sc
ale
Up sampled with
Up sampled
Phasors 12 data modification flag
interpolation;
with interpola-
Up sampled with
tion
Phasors 12 user defined flag
extrapolation;
Down sampled,
Nth sample;
Down sampled
with FIR filter;
Filtered without
changing sampling;
Phasor Mag adjusted for calibration;
Phasor phase adjusted for calibration;
Phasor phase adjusted for rotation;
Pseudophasor value;
Modification applied, type not defined
p(n)PHS(n)us 0255
er
7Fa.7
GTNET PMU
p(n)ANUNT( 0255
n)a

Most Significant Byte:
0 single pointonwave
1 rms of analog input
2 peak of analog input
564 reserved for future definition
65255 user definable
p(n)ANUNT( 8388608 to
8388607
n)b
100

Least Significant Byte:
A signed 24 bit word (CFG frame 2) /
32 bit word (CFG frame 3), user defined scaling
Analogs 14 offset
2147483648
to
2147483647
p(n)ANUNT( 2147483648 0
to
n)c
2147483647
p(n)eDIG(n)
NO:YES
YES
Digital status word bits 015 enable
p(n)sDIG(n)
NO:YES
YES
Digital status word bits 015 normal

state
p(n)eSTAT
NO:YES
NO
STAT (16 bits) field override enable
p(n)nSTAT
10 characters p(n)STAT
Signal name of STAT field
For user information, the word definitions for STAT field in IEEE C37.118.22011
and in IEEE C37.1182005 are listed below:
7Fa.8
C37.118
Field
Size(bytes)
STAT
IEEE C37.118.22011
Bit mapped flags.
Bit 1514: Data error: 00 = good measurement data, no errors
01 = PMU error. No information about data
10 = PMU in test mode (do not use values) or
absent data tags have been inserted (do not use values)
11 = PMU error (do not use values)
Bit 13: PMU sync, 0 when in sync with a UTC traceable time source
Bit 12: Data sorting, 0 by time stamp, 1 by arrival
Bit 11: PMU trigger detected, 0 when no trigger
Bit 10: Configuration change, set to 1 for 1 min to advise
configuration will change, and clear to 0 when change effected.
Bit 09: Data modified, 1 if data modified by post processing, 0
otherwise
Bits 0806: PMU Time Quality. Refer to codes in Table 7.
Bits 0504: Unlocked time: 00 = sync locked or unlocked < 10 s (best
quality)
\01 = 10 s . unlocked time < 100 s
10 = 100 s < unlock time . 1000 s
11 = unlocked time > 1000 s
0111: Digital
0110: Reserved
0101: df/dt High
0100: Frequency high or low
0011: Phase angle diff
0001: Magnitude low
0000: Manual
7Fa.9
GTNET PMU
Field
Size(bytes)
STAT
IEEE C37.1182005
Bitmapped flags.
Bit 15: Data valid, 0 when PMU data is valid, 1 when invalid or PMU
is in test mode.
Bit 14: PMU error including configuration error, 0 when no error.
Bit 13: PMU sync, 0 when in sync.
Bit 12: Data sorting, 0 by time stamp, 1 by arrival.
Bit 11: PMU trigger detected, 0 when no trigger.
Bit 10: Configuration changed, set to 1 for 1 min when configuration
changed.
Bits 0906: Reserved for security, presently set to 0.
Bits 0504: Unlocked time: 00 = sync locked, best quality
11 = Unlocked over 1000 s
0111: Digital
0110: Reserved
0101: df/dt high
0100: Frequency high/low
0011: Phaseangle diff
0001: Magnitude low
0000: Manual
7Fa.10
C37.118
Monitoring signal names:
names are fixed. An optional suffix can be added. Two positive sequence phasors
are automatically generated per PMU. The phasor output uses V1 for phasor 1 and
I1 for phasor 2.
(n = 124)
Signal
Description
Format
V1p1(n)(a)
I1p2n(a)

Where (n) = 1 24
Where (a) = re and im or c and phi
Float
PMU(n)freq

Where (n) = 1 24
float (Hz)
PMU(n)rocof

Where (n) = 1 24
float (Hz/s)
PMU(n)frac
PMU fracsec
Where (n) = 1 24
fraction of seconds
REQUIRED FIRMWARE:
The following minimum version of RTDS firmware are required for use with
GTNETPMU24:
1.17 GTNETPMU
0029 GTNET FPGA
4.103 build E GTWIF OS (WIF OS not supported)
v337 or v395 GPC FPGA
v19 PB5 FPGA
7Fa.11
Rev. 01 May 2013
7G
GTNET 104
( _rtds_GTNET_IEC104.def )
Data may be exchanged between the RTDS and external equipment over a
LAN/WAN using IEC 608705104 (often referred to as 8705 or 104). IEC
608705104 is often used by electric utilities as a communication mechanism
between a control center and substations. In particular, SCADA systems commonly
use IEC 608705104as their communications protocol. In order to use the IEC 104
communication function with the RTDS, the user must have a GTNET card equipped
with the GTNET104 firmware installed in one of the RTDS racks and have access
to an IEC 608705104master station. IEC 104 firmware installed on the GTNET
card acts only as a slave interface for the RTDS simulator.
A typical connection arrangement for the IEC 104 function on the RTDS is shown
below in Figure 7G.1. The GTNET card is connected to a PB5/GPC card using a
fiber optic cable connected between GT Ports located on the rear of the PB5/GPC and
GTNET cards. Fiber ports 18 on the PB5/GPC card may be used to connect to the
GTNET card. The GTNET104 must be the only card on the fiber optic PB5/GPC
GT I/O port it can not be daisychained. Data computed on or required by the
simulation case running on the RTDS is sent between the PB5/GPC and GTNET over
the GT Port fiber optic connection. Refer to the GTNET chapter of the RTDS
Hardware Manual for more information regarding setup of the GTNET card.
The GTNET is connected to the IEC 608705104 Master Station through the
GTNETs Ethernet port. A Master Station may be dedicated hardware or a computer
workstation running IEC 608705104Master software (eg. Triangle Microworks
Communication Protocol Test Harness software, a windows application that
simulates an IEC 608705104 Master Station).
7G.1
GTNET 104
7G.0 MINIMUM VERSION REQUIREMENTS
The following minimum versions of RTDS firmware and software are

required:
GTWIF OS : 4.103 build D
GTWIF FPGA : 8068
RSCAD : 3.004
IEC 104 Master Station

GT Port Fiber Cable
PB5
ETHERNET SWITCH
Ethernet Cable
GTNET
Figure 7G.1: Typical GTNET104 Connection
7G.1 DESCRIPTION
The IEC 104 Master station initiates all IEC 104 communication by sending requests
to slave stations for updated data values. The term polling is used to refer to the
master station action requesting updated data from the slave stations. The master
station can also send messages to the slave stations to change the value of a parameter.
7G.2
GTNET104
In order to avoid ambiguity, the terms input and output are avoided here. Rather, the
terms status and control are used. Status signals refer to signals that are sent from
the slave station to the master station. Control signals refer to signals that are sent
from the master station to the slave station. In terms of the RTDS simulation case,
control signals are those that are used as input to a component in RSCAD/Draft and
status signals are those that are output from a component.
Control Signal:
Status Signal:
Master > Slave

Slave > Master
SIGNAL TYPES AND UPDATE FREQUENCY

The GTNET104 component can handle binary and Analogue Control and status
data. For complete details regarding the IEC 608705104implementation, please
see the document titled GTNET IEC 608705104ConfigurationInteroperability
Guide.pdf available through the RTDS website Client Area. The maximum number
of binary and analogue signals that can be handled by a single GTNET card are
Type
BINARY STATUS:
BINARY CONTROL:
ANALOGUE STATUS:
ANALOGUE CONTROL:
Qty.
1024
512
500
100
Component Input/Output Format

(32 x 32 bit words)
(16 x 32 bit words)
Binary Status points are mapped to IEC 608705104 Singlepoint information

M_SP_NA_1/M_SP_TB_1 address 10002023. Binary Control are mapped to IEC
608705104 Single command with tim tag CP56Time2a C_SC_TA_1 address
40004511, the corresponding monitored points are at address 20242535.
Analogue Status points are mapped to IEC 608705104 Measured value, short
floating point number with time tag CP56Time2a M_ME_TF_1 address 60006499.
Analogue Control points are mapped to IEC 608705104Set point command, short
floating point number with time tag CP56Time2a C_SE_TA_1 address 80008099,
the corresponding monitored points are at address 65006599.
In order to use the IEC 608705104 function on the RTDS, the GTNET104
controls component must be assigned to a PB5/GPC processor on the PB5/GPC card
to which the GTNET card is connected. The GTNET104 controls component is
responsible to oversee the exchange of data between the GTNET card and the
PB5/GPC processor.
Every millisecond the IEC 104 controls component latches all 32 Binary Status
words and generates a change map. The change map is generated by applying an
XOR function to the newest 32 Binary Status words and those from the previous
sample. The Binary Status words and change event words are then sent from the
PB5/GPC to the GTNET card using the GT I/O fiber port connection between the
two cards. The change event words are used within the GTNET to generate
7G.3
GTNET 104
spontaneous transmission messages. All changes within the same sample are
stamped with the same time. The IEC 608705104 master can obtain the most
recent information by polling the GTNET104 slave.
Operation of the IEC 608705104controls component for Analogue Status points
is somewhat similar to that of the Binary Status points. However, a change status for
the analogue signals is based on the most recent sample changing by more than a user
specified deadband value. Since 500 Analogue Status words are permitted, the
update frequency for the Analogue Status signals is 4 Hz. Every 0.25 seconds all
Analogue Status points are sampled, change events generated and the data
transferred from the PB5/GPC to the GTNET.
Control signals are sent to the GTNET from the IEC 608705104 Master. Binary
Control signals are transferred from the GTNET to the PB5/GPC card whenever a
new control signal is received from the IEC 104 master. Analogue Controls signals
are handled in a similar fashion as Analogue Status signals, are are updated on the
PB5/GPC only every 0.25 seconds.
7G.2 IEC 608705104 <> RTDS POINT MAPPING FILE
A points mapping text file is used to map IEC 608705104 data points to signal
names assigned in RSCAD/Draft. The points mapping text file contains a single line
for each mapping between the IEC 608705104 point number and the
corresponding RTDS variable name. The IEC 608705104 address can be
determined by adding the point number to the address offset for the various point
types. Binary Status points start at IEC 104 address 1000, Binary Control points start
at IEC 104 address 4000, Analogue Status points start at 6000 and Analogue Control
points start at address 8000. The points mapping text file is accessed during the
RSCAD/Draft compile and must be located in the same directory as the
RSCAD/Draft file for the simulation case. The text file name must have .txt as its
suffix. The user specifies the points mapping file name under the Fname parameter
in the RSCAD/Draft GTNET104 controls component.
Lines of text in the mapping file which begin with the # character are considered
comments. Binary Status, Binary Control, Analogue Status and Analogue Control
signals are mapped using the following format in the points mapping file. Note that
each mapping must use a single line of text.
BINARY STATUS POINTS
The BI section is used to map Binary Status points. The format of each entry is:
BI:
point_num
user_label
bitmap_name
bitmap_bit_num
where:
7G.4
GTNET104
point_num: The point number of the Binary Status point.
The range is 0 to 1023 which corresponds to IEC 608705104address 1000
to 1123.
the RTDS compiler.
bitmap_name: The name of the RTDS bitmap variable containing this point.
Typically, the bitmap_name is the wire label name assigned in RSCAD/Draft
to the integer output signal from the component producing the signal.
bitmap_bit_num: The position of the point within the signal bitmap_name.
Bit 0 is the rightmost (LSB) bit.
For example, the points file entries
map bits 0, 1 and 2 from the RSCAD/Draft signal named STATUS into Binary
Status points 50, 51, 52 which have IEC 608705104 addresses 1050, 1051 and
1052 respectively. The user labels STATUS00 . . . STATUS02 are only used to
identify these points within the text file.
BINARY CONTROL POINTS
The BO section is used to map Binary Control points. The format of each entry is:
BO: point_num user_label bitmap_name bitmap_bit_num default_state
where:
point_num: The point number of the Binary Control point. The range is
0 to 511 which corresponds to IEC 608705104 address 4000
to 4511.
the RTDS compiler.
bitmap_name: The name of the RTDS bitmap variable containing this
point. Typically, the bitmap_name is the wire label name assigned in
RSCAD/Draft to the integer input signal to a component.
bitmap_bit_num: The position of the point within the signal
bitmap_name. Bit 0 is the rightmost (LSB) bit.
7G.5
GTNET 104
default_state: The default value (0 or 1) for the point at the start of

simulation.
For example, the points file entry
BO: 0 TRIPA BRK 4 1
maps Binary Control point 0 to bit 4 of the RSCAD/Draft variable named BRK.
The user label TRIPA has been given to easily identify this point within the point
map text file. Bit 4 of the signal BRK has a default value of 1 at simulation startup.
ANALOGUE STATUS POINTS
The AI section is used to map Analogue Status points. The format of each entry is:
AI:
point_num variable_name deadband% [serializer_name]
where:
point_num: The point number of the Analogue Status point. The range
is 0 to 499 which corresponds to IEC 608705104 address 6000
to 6499.
the data point. The signal named variable_name must be obtained from
an output of a RSCAD/Draft component.
deadband: The deadband used to determine the required level of
change in the data point in order to generate a spontaneous event. The
deadband value is in %.
subsytems using the GTNET Analogue Status serializer component.
AI: 0 VBUSA 5% S1
maps RSCAD/Draft variable named VBUSA using the Analogue Status Serializer
component with name S1 to Analogue Status point 0 which is IEC 608705104
address 6000. A change of 5% or greater from the previous change event is required
to generate a status change.
ANALOGUE CONTROL POINTS
7G.6
GTNET104
The AO section is used to map Analogue Control points. The format of each
Analogue Control entry is:
AO: point_num variable_name default_value [serializer_name]
where:
point_num: The point number of the Analogue Control point. The
range is 0 to 99 which corresponds to IEC 608705104address 8000
to 8099.
the data point. The signal variable_name must be used as an input to
an RSCAD/Draft component.
default value: The default value for the signal.
subsytems using the GTNET Analogue Control Serializer component.
See below for more information regarding the use of the serializer
component.
AO: 0 VSETA 500 C1
maps the Analogue Control point 0 (IEC 608705104 address 8000) to an
RSCAD/Draft variable named VSETA using the Analogue Control Serializer
component with name C1. The signal VSETA is assigned the value 500.0 at the
start of the simulation case.
7G.7
GTNET 104
7G.3 RSCAD DRAFT COMPONENT AND PARAMETER ENTRIES
The
RSCAD
Draft
component
for
GTNET104
is
named
_rtds_GTNET_IEC104.def and can be found in the MLIB/RPC/CTLS directory
under the RSCAD installation directory. The following figures below illustrate the
menus used for the GTNET104 component.
Figure 7G.2: GTNET104 CONFIGURATION Menu
CONFIGURATION MENU ITEMS

Name The components name.
Port Indicates PB5/GPC GT I/O port that the GTNET104 is connected to.
Card The number of the GTNET card on the PB5/GPCs GT port peripheral chain.
1 refers to the first GTNET104 on the GT peripheral chain. The GTNET104 is
not daisychainable, so this parameter is fixed at 1. The GTNETs card number is
indicated on the seven segment display on the cards face plate.
Proc The controls processor to which the GTNET104 function is assigned.
Pri The priority of execution for the GTNET104 function in the assigned controls
processor.
7G.8
GTNET104
IEC 104 SETUP MENU ITEMS
Figure 7G.3: GTNET104 Component IEC104 SETUP Menu

Nmode Reserved for backwards compatibility.
NRACS If set to Yes the strobe signal required for the multirack serializer
component is made available and the strobe signal output connection appears. See
the section entitled Multirack Communication below for more information
regarding the multirack serializer component.
Sip1Sip4 Specifies the IP address of the station acting as the IEC 608705104
Master. The IP address is entered in 4 parts. For example, to enter the address
192.168.1.173, Sip1 is set to 192, Sip2 is set to 168, Sip3 is set to 1 and Sip4 is set
to 173. If the Master Station IP address is set to 0.0.0.0 then the GTNET104
responds to commands from any IEC 608705104master. Only one master station
may be connected to the GTNET104 at a time.
Sport Sets the TCP port number for IEC 608705104 communications. The
default port is 2404.
7G.9
GTNET 104
Fname The name of the point mapping text file. The extension is expected to be
.txt and should not be entered in this field. The file must be located in the same
directory as the RSCAD draft file for this case.
Trans IEC 608705104 Common Address of ASDU parameter.
7G.4 MULTIRACK COMMUNICATION
The GTNET104 component implements a mechanism to efficiently transfer
Analog Status and Control points between racks. The DNP Serializer component is
used to perform this function for the GTNET104 as well as the GTNETDNP
component. See section 7C.4 for details.
7G.10
Rev. 08: May 11
MULTIFUNCTION RELAY ELEMENTS
8.1 INTRODUCTION
Protection and Control system schemes for simulation using the RTDS can be
constructed using Component Builder. Multifunction relays can be made into one
control component with multithreading so the simulation time step remains at 50
or 60 usec. This chapter documents the general features of the multifunction relay
components.
8.2 MULTITHREADED COMPONENT
The idea behind a multithreaded component is that the component does not need
to process the whole algorithm every timestep. By default, the simulation will
execute the whole draft case every timestep and provide a solution for the controls
and power system . A component algorithm can be separated into individual blocks
of code processed independently of each other to create a multithreaded
component. The multithreaded component requires additional code to keep track
of the multithreaded timestep and adjust delays for timers when new sampled data
is available. This additional code will ensure the individual blocks of code are
executed sequentially, and restart the sequence when new sampled data is ready. The
code must also adjust the time delay that is used to service timers when the sequence
is restarted.
Normally a microprocessor based intelligent electronic device (IED) will use
sampled data every 8/16/32/ or 64 samples per cycle. A downsampler is used to
provide data at the correct number of samples per cycle for the algorithm. In an
example case with a nominal 60 Hz base sampling at a rate of 8 samples per cycle,
the control algorithm uses new data every 2.08333 ms. If the simulation timestep
is 50usec, then the main simulation will be executed 41 times between samples. This
means that it is possible to have 41 different threads executed sequentially every
2.08333 ms. This probably would not be an ideal application because the additional
code to keep track of the thread count, variables, inputs, outputs, etc... would push
the time step beyond a reasonable limit of 60 usec. If there are 5 threads in the
multithread cycle with an additional thread every new sample the normal delay
cycle between individual threads is 250 usec. The additional thread every sample is
normally used for the signal processing. This means the multithread cycle would
execute about 7 times between new samples. Keep in mind that some code will be
executed each time step and must be taken into consideration for overall execution
time of each thread. The sample rate is not always an integer value of the timestep
therefore new samples will occur with an accuracy limited to a few timesteps. This
means that the thread cycle will restart at different thread counts changing the amount
of delay between the executions of code within a thread. This delay can be adjusted
from the normal 250 usec to a temporary value whenever the new data sample
interrupts the thread cycle and restarts.
8.1
RELAYING
250.0
usec
0.0
5
4
3
2
1
0
79, timers, outputs

85, SAED
Z3, 68OOS
Z2, plots
Z1, phase selection
Input samples, seq.. components, directional
0.002083
Figure 1: MultiThreaded Timestep

If a timer is used in thread 1 the time between executions of thread 1 changes when
a new sample occurs indicated by the red line. When the control algorithm is ready
to read the new sample data, the multithread was executing thread 2. Because new
sample data is ready to be read the control algorithm has to move back to thread 0
and read in and process the new sampled data that will be used for the other threads.
When the multithread moves back to thread 1 and starts executing the code, only
3 main simulation timesteps have occurred. To properly service a timer in thread
1 the amount of delay added to the timer would have to be temporarily adjusted by
3/5 of the 250 usec (5 time steps) normally added.
8.3 CREATING A PROTECTION SYSTEM MODEL
The relaying components were created using basic protection theory and standard
techniques for processing digitally sampled data from the time domain. Essentially
sampled data is transferred into the phase domain using a DFT. The phasor
information is then evaluated against algorithms that can discern between normal
operating conditions and fault conditions. Control algorithms can then be processed
that will isolate the faulted portion of the power system. The same control algorithm
can then later restore the isolated portion of the power system when the fault
condition has been removed.
The multifunction relay models will be developed using the component builder and
by default will only run on the GPC hardware.
8.2
RELAYING
RELAY
DISTANCE
8.4 MULTIFUNCTION DISTANCE

CLASS:
FUNCTION:
RSCAD/Draft ICON:
RELAY FUNCTION
21,79,68,85,50BF, Z Calculation
_rtds_PN_21_v1.def
Introduction:
The multifunction distance relay is suitable for providing the distance protection
function on single breaker transmission lines with single or three pole tripping and
reclosing schemes. There is provision for communication aided tripping schemes as
well as an out of step function and breaker failure protection. A secondary arc
extinguish detection algorithm is also available to aid in high speed single pole auto
reclose schemes. Additional plot signals provide sufficient information to help
verify theoretical calculations with the simulation results.
Description:
The distance measuring zones include six impedance measuring loops; three
intended for phasetoground faults, and three intended for phasetophase faults.
8.3
RELAYING
The distance zones can be a MHO or QUAD characteristic. Additional impedance
measurements can include the positive, negative, and zero sequence components for
plotting purposes. Phase selection and directional control is included as well as the
control logic for reclosing, communication aided tripping, out of step detection,
breaker failure on open and close, and secondary arc detection. The system
frequency is determined using the instantaneous composite voltage comprised of Va
0.5*Vb 0.5*Vc. If the system frequency changes the sample rate is also changed
to ensure a constant 8 samples per cycle. The measured system frequency and rate
of change of frequency can be monitored. The absolute difference between the
composite voltage and the previous time step composite voltage is used to detect
disturbances in the voltage. If a disturbance is detected the frequency measurement
and sample rate adjustment is suspended for 3 cycles.
Operation:
The phase voltages and currents are connected to the 6 inputs of the DISTANCE
function. The positive sequence memory voltage is created inside the relay and an
input is also available for mutual coupling compensation as an import signal. The
RMS values are calculated and the instantaneous impedance is calculated for the
phasetophase, phasetoground,positive sequence, negative sequence, and zero
sequence. The distance elements are built using positive sequence memory
polarizing quantity when there is no reverse reach and the directly measured voltage
when reverse reach is enabled. The distance elements are directly supervised by a
directional element and a phase selection element.
The distance measuring zones for the phase to ground will be compensated. This
compensation factor can be calculated automatically according to: K0 = Z0 Z1 /
3*Z1 or can be manually entered as magnitude and angle values.
If selected the positive, negative, and zero sequence voltages and currents used for
the sequence impedance calculations can be monitored in runtime or imported into
the draft case as inputs to other controls components.
///////////////////////////////////////////////////////////////////////////////
// Processing Threads are:
// 0 Antialias filter, downsampler, DFT, fault detection, freq tracking with
//
dph/dt, other inputs,
// 1 pos seq. memory V ring filter, phasor rotation, prefault load currents for
//
ph selection, freq tracking averaging, plots, buffer frequency tracking
//
parameters, sequence components for 68 OOS
// 2 Phase selection, directional element
// 3 Zone 1 and plots
// 4 Zone 2 and plots
// 5 Zone 3 and partial 68 OOS
// 6 79 Element, 68 OOS, Trip Timers and Write Outputs
// 7 85 Element, Secondary Arc Element, 50BF
///////////////////////////////////////////////////////////////////////////////
See Also: Tutorial Chapter 8
8.4
RELAYING
Input signals for the DISTANCE function block
Signal
Description
Format
VA
A phase voltage
Float
VB
B phase voltage
Float
VC
C phase voltage
Float
IA
A phase current
Float
IB
B phase current
Float
IC
C phase current
Float
IZ0MRE
Zero sequence current from parallel

line (re part)
Float (import)
IZ0MIM

line (imaginary part)
Float (import)
nCB
Breaker status input signal name
Integer (import)
BLOCK
Block signal to disable 85 element
Integer
BLKCS
Block signal to disable carrier send
Integer
CR
Carrier received signal
Integer
CRG
Carrier guard received signal
Integer
Output signals for the DISTANCE function block

Signal
Description
Format
21start
Distance Element bits:

1 : Zone 1 start signal
4 : Zone 2 time delay operate signal
5 : Zone 3 time delay operate signal
Integer (word)
1P/3PT
Tripping Element bits:

1 : Trip A phase
2 : Trip B phase
3 : Trip C phase
4 : Trip 3 pole (general)
5 : Trip from 85 element
Integer (word)
RECL
Reclosing Element bits:

1 : Reclose signal
2 : Reset signal
3 : Cycling signal
4 : Lockout signal
Integer (word)
8.5
RELAYING
68B or 68T
Out of Step Element
Integer
Info
Relay word bits:

0 : 211_AB MHO/QUAD signal
1 : 211_BC MHO/QUAD signal
2 : 211_CA MHO/QUAD signal
3 : 211_AN MHO/QUAD signal
4 : 211_BN MHO/QUAD signal
5 : 211_CN MHO/QUAD signal
18 : 68 RHS outer signal
19 : 68 RHS inner signal
20 : 68 LHS outer signal
21 : 68 LHS inner signal
22 : Phase A selected signal
23 : Phase B selected signal
24 : Phase C selected signal
25 : Breaker Failure signal
26 : Block Reclose signal
27 : Internal LKD signal
28 : Secondary ARC Extinction signal
29 : Internal CB Aph Status signal
30 : Internal CB Bph Status signal
31 : Internal CB Cph Status signal
Integer (word)
CS
Carrier send signal
Integer
CRL
Carrier received signal
Integer
LCG
Carrier guard signal not present
Integer
8.6
RELAYING
Monitoring signal names (MMXU/MSQI):

The default signal names of the Monitoring signals for the DISTANCE function
block are shown next, the names can be changed. The maximum length of the signal
name is 8 characters, an optional suffix can be added for a maximum overall length
of 10 characters.
Signal
Description
Format
ZARE
A phaseground impedance (re)
Float
ZAIM
A phaseground impedance (im)
Float
ZBRE
B phaseground impedance (re)
Float
ZBIM
B phaseground impedance (im)
Float
ZCRE
C phaseground impedance (re)
Float
ZCIM
C phaseground impedance (im)
Float
ZABRE
A phaseB phase impedance (re)
Float
ZABIM
A phaseB phase impedance (im)
Float
ZBCRE
B phaseC phase impedance (re)
Float
ZBCIM
B phaseC phase impedance (im)
Float
ZCARE
C phaseA phase impedance (re)
Float
ZCAIM
C phaseA phase impedance (im)
Float
Z1RE
Positive sequence impedance (re)
Float
Z1IM
Positive sequence impedance (im)
Float
Z2RE
Negative sequence impedance (re)
Float
Z2IM
Negative sequence impedance (im)
Float
Z0RE
Zero sequence impedance (re)
Float
Z0IM
Zero sequence impedance (im)
Float
OZ0MRE
Mutual Coupling 3I0 Signal Name (re) Float
OZ0MIM
Mutual Coupling 3I0 Signal Name

(im)
Float
VARE
A phaseground voltage (re)
Float
VAIM
A phaseground voltage (im)
Float
VBRE
B phaseground voltage (re)
Float
VBIM
B phaseground voltage (im)
Float
VCRE
C phaseground voltage (re)
Float
VCIM
C phaseground voltage (im)
Float
IARE
A phaseground current (re)
Float
IAIM
A phaseground current (im)
Float
8.7
RELAYING
IBRE
B phaseground current (re)
Float
IBIM
B phaseground current (im)
Float
ICRE
C phaseground current (re)
Float
ICIM
C phaseground current (im)
Float
FREQ
Measured System Frequency
Float
DFREQ
Rate of Change of Frequency Hz/sec
Float
TRIG
Trigger signal indicates new samples

and restarts the processing thread
Integer
DIR
System directional control signal, logic Integer

1 indicates forward direction, logic 0
indicates reverse direction
K0MAG
Calculated Zero Sequence Compensation (magnitude)
Float
K0ANG
Calculated Zero Sequence Compensation (angle)
Float
SIR
Measured SIR Positive Sequence

source impedance / line impedane
Float
XR
Measured X/R Z1 source impedance
Float
Setting Parameters:
Setting parameters for the DISTANCE relay component will be described below.
CONFIGURATION:
Parameter
Range
Default
Unit
Description
iedName
10 character
RTDS
DIS
IED Name
fver
pn21_01
pn21_01
Firmware version of the relay component
freq
60, 50
60
hz
eFT
OFF, ON
ON
Enable Frequency Tracking to adjust

the sample rate.
adv
None, V by
1dt
None
In some cases the measured voltage

and current signals will be out of sync
by one timestep. In this case the adv
parameter may be set to delay the voltage one timestep.
n21
0, 1, 2, 3
Enable or Disable phasephase and

phaseground impedance elements
plots
NO, YES
NO
Enable or Disable Signal Monitoring
sfx
2 characters

plot signal names
8.8
RELAYING
e79
0, 1, 2,3
Enable or Disable the number of Reclose Attempts
eSA
OFF, ON
OFF
Enable Secondary Arc Extinction

Detection (e79 > 0)
eBF
OFF, ON
OFF
Enable 50BF Breaker Fail Detection
e68
Off, Block,
Trip
Off
Enable 68 OOS Detection
emutc
OFF, ON
OFF
Enable Mutual Coupling input and

compensation
KZANG
30.0 150.0
90.0
degrees
Characteristic Angle of mho element

(n21>=1 or e68 ==1)
SchTyp
OFF, PUTT, PUTT

POTT, DCB,
DTT
Communication aided tripping scheme
PROTECTION TRIP CONDITIONING (PTRC):

Parameter
Range
Default
Unit
Description
TrMod
3Pole,1Pole
3Pole
Tripping scheme
TrPlsTmms
50.0
2,000.0
150.0
msec
Minimum trip duration
POS/ZERO SEQ COMP: (n21>=1)

Parameter
Range
Default
Unit
Description
Z1M
0.001
9999.99
7.54
ohms
Positive sequence magnitude
Z1A
0.0 360.0
87.18
degrees
Positive sequence angle
Z0M
0.001
9999.99
25.6
ohms
Zero sequence magnitude
Z0A
0.0 360.0
73.59
degrees
Zero sequence angle
KZ0M
0.001
9999.99
0.3772
ohms
Mutual zero sequence magnitude

(emutc>0)
KZ0A
0.0 360.0
13.60
degrees
Mutual zero sequence angle (emutc>0)
k0calc
NO, YES
YES
Enable automatic zero sequence compensation calculation
k0Mag
0.001
9999.99
0.925
ohms
Manual override of zero sequence

compensation magnitude
k0Ang
360.0
360.0
18.38
degrees

compensation angle
8.9
RELAYING
DIRECTIONAL ELEMENT (RDIR): (n21>=1)
Parameter
Range
Default
Unit
Description
dV2
0.5 5.0
0.5
volts
Negative sequence voltage supervision
dI2
0.1 1.0
0.1
amps
Negative sequence current supervision
d2V0
1.0 10.0
1.0
volts
Zero sequence voltage supervision
d3I0
0.2 5.0
0.2
amps
Zero sequence current supervision
21 DISTANCE ELEMENTS (PDIS): (n21>=1)

Parameter
Range
Default
Unit
Description
D1
MHO,
QUAD
MHO
211 Element Type
IPP1
0.1 99.99
3.5
amps
Phasephase current supervision
IP1
0.1 99.99
2.0
amps
Phase current supervision
IR1
0.1 99.99
0.5
amps
Residual current supervision
D1R
0.020
250.000
6.032
ohms
Zone 1 Reach
D1RR
0.000
250.000
0.000
ohms
Zone 1 Reverse Reach
DirMod1
FWD, REV
FWD
211 Direction
D1RB
0.020
500.000
10.0
ohms
Zone 1 Right Blinder
D1RA
60.0 90.0
87.18
degrees
Right Blinder Angle
D1LB
0.020
500.000
10.0
ohms
Zone 1 Left Blinder
D1LA
60.0. 90.0
87.18
degrees
Left Blinder Angle
D2
MHO,
QUAD
MHO
212 Element Type
IPP2
0.1 99.99
1.732
amps
IP2
0.1 99.99
1.0
amps
IR2
0.1 99.99
0.25
amps
D2R
0.020
250.000
9.048
ohms
Zone 2 Reach
D2RR
0.000
250.000
0.000
ohms
DirMod2
FWD, REV
FWD
212 Direction
OpDlTmms2
10.0
999,999
200.0
msec
Zone 2 Time Delay
8.10
RELAYING
D2RB
0.020
500.000
14.0
ohms
D2RA
60.0 90.0
87.18
degrees
Right Blinder Angle
D2LB
0.020
500.000
14.0
ohms
Zone 2 Left Blinder
D2LA
60.0. 90.0
87.18
degrees
Left Blinder Angle
D3
MHO,
QUAD
MHO
213 Element Type
IPP3
0.1 99.99
1.732
amps
IP3
0.1 99.99
1.0
amps
IR3
0.1 99.99
0.25
amps
D3R
0.020
250.000
11.310
ohms
Zone 3 Reach
D3RR
0.000
250.000
0.000
ohms
DirMod3
REV
REV
213 Direction
OpDlTmms3
10.0
999,999
200.0
msec
Zone 3 Time Delay
D3RB
0.020
500.000
10.0
ohms
D3RA
60.0 90.0
87.18
degrees
Right Blinder Angle
D3LB
0.020
500.000
10.0
ohms
Zone 3 Left Blinder
D3LA
60.0. 90.0
87.18
degrees
Left Blinder Angle
52 BREAKER STATUS: (e79>0 or eBF>0)

Parameter
Range
nCB
variable
Abit
1 16
Bbit
Cbit
Default
Unit
Description
integer
Breaker Status Input Signal Name
Active bit number to control A phase

status
1 16
Active bit number to control B phase

status
1 16
Active bit number to control C phase

status
50BF BREAKER FAILURE (RBRF): (eBF>0)

Parameter
Range
Default
Unit
Description
FailTmms
75.0
10,000.0
200.0
msec
Open Failure Timer
8.11
RELAYING
DetValA
0.1 1.99
0.2
amps
Phase current Threshold
BFhTmms
100.0
10,000.0
2,000.0
msec
BF Maximum Trip Hold Timer
79 RECLOSER TIMERS (RREC): (e79>0)

Parameter
Range
BlkRec
variable
RclTmms
10.0
999,999
Rec1Tmms
Default
Unit
Description
integer
External Input Block Reclose Signal

Name
10,000.0
msec
Reset Lockout Timer
10.0
999,999
5,000.0
msec
Open Interval Timer 1
Rec2Tmms
10.0
999,999
5,000.0
msec
Rec3Tmms
10.0
999,999
5,000.0
msec
PlsTmms
50.0
2,000.0
150.0
msec
Close Pulse duration
ClsFlTmms
10.0
10,000.0
500.0
msec
Close Failure Timer
r3ph
NO, YES
NO
If 1pole? Reclose for Multiphase

Faults
SECONDARY ARC EXTINCTION: (eSA>0 and ttype>0)

Parameter
Range
Default
Unit
Description
SAV
5.0 99.99
10.0
volts
Recovery Voltage limit
SavTmms
10.0
5,000.0
50.0
msec
Arc Extinction Detection Dropout

Timer
reac
NO, YES
NO
Enable if shunt reactors are installed.

Angle checks are not used if shunt
reactors are installed.
SAA1
120.0 to
150.0
135.0
degrees
Phase A + Angle Limit
SAA2
120.0 to
150.0
135.0
degrees
Phase A Angle Limit
SAB1
0.0 to 30.0
15.0
degrees
Phase B + Angle Limit
SAB2
90.0 to 120.0 105.0
degrees
Phase B Angle Limit
SAC1
30.0 to 0.0
15.0
degrees
Phase C + Angle Limit
SAC2
120.0 to
90.0
105.0
degrees
Phase C Angle Limit
8.12
RELAYING
68 OUT OF STEP ELEMENT: (e68>0)
Parameter
Range
Default
Unit
Description
IP68
0.1 99.99
2.0
amps
IR68
0.1 99.99
0.5
amps
SwgTmms
10.0
10,000.0
100.0
msec
Out of Step Swing Timer
UnBlkTmms
200.0
10,000.0
200.0
msec
Blocking Reset Time
OLB68
0.02
500.00
14.0
ohms
Outer Left Blinder

*(OLB68 > ILB68)
ILB68
0.02
500.00
10.0
ohms
Inner Left Blinder
ORB68
0.02
500.00
14.0
ohms
Outer Right Blinder

*(ORB68 > IRB68)
IRB68
0.02
500.00
10.0
ohms
Inner Right Blinder
85 COMMUNICATION TIMERS: (type>0)

Parameter
Range
Default
Unit
Description
OpDlTmms
0.0
60,000.0
35.0
msec
Coordination time for scheme TRIP
DurTmms
0.0
60,000.0
100.0
msec
Minimum duration of CS signal
SecTmms
0.0
60,000.0
35.0
msec
Security timer for loss of CRG signal
UnBlkMod
Off,
NoRestart,
Restart
Off
Mode of unblocking logic, typically

for POTT schemes that use PLC as a
communication medium
85 POTT CURRENT REVERSAL: (type==2)

Parameter
Range
Default
Unit
Description
RvAMod
OFF, ON
OFF
Enable current reversal blocking logic

for permissive overreaching schemes
RvATmms
0.0
60,000.0
20.0
msec
Pickup time for current reversal declaration
RvRsTmms
0.0
60,000.0
60.0
msec
CS signal & Local Trip delay timer
8.13
RELAYING
85 POTT WEAK INFEED: (type==2)
Parameter
Range
Default
Unit
Description
WeiMod
OFF, ON
OFF
Enable weak infeed tripping logic for

permissive overreaching schemes
WeiTmms
10.0
60,000.0
10.0
msec
WEI CR signal delay timer
WD1Tmms
10.0
60,000.0
200.0
msec
Dropout time for Protection Operation

declaration
WD2Tmms
10.0
60,000.0
50.0
msec
Minimum Duration of ECHO Tx
WD3Tmms
10.0
60,000.0
200.0
msec
Maximum Duration of ECHO Tx
PhGndVal
10.0 99.99
50.0
volts
Phase voltage element supervison
DIRECTIONAL ELEMENT (RDIR):

Introduction:
The directional element is executed before the distance functions and verifies the
direction of faults. The fault direction supervises the distance functions according
to the direction setting of each zone. The directional element will not be used to
supervise any zone that has a reach setting offset from the origin.
Description:
The three sequence component impedances are used to determine the fault direction.
Determination of fault direction and phase selection supervises the three zones of
impedance elements.
Operation:
The directly measured fundamental phase voltages and currents are used to calculate
negative sequence impedance, zero sequence impedance. The positive sequence
memory voltage and directly measured current is used to calculate the positive
sequence impedance. The RMS voltage and current quantities are calculated and a
comparator is used to determine if the measured voltage and current is greater than
the thresholds. The negative and zero sequence elements have adjustable thresholds,
while the positive sequence element is fixed to 1.0 volts and 0.2 amps.
By default, the directional element is always set to the forward direction and the
impedance measurements are used to set the element to reverse if the thresholds are
exceeded. This allows the forward looking elements to operate properly if a bolted
3 phase fault occurs at the line terminals and is not cleared before the memory voltage
drops below the 1.0 volt threshold.
If all the phase currents exceed the zone 2 phase current supervision setting IP2,
the directional element will not use the negative and zero sequence elements. For
unbalanced faults, the negative sequence element voltage and current thresholds are
8.14
RELAYING
checked first, if there is enough voltage and current the angle measurement is
checked. If there is not enough negative sequence the zero sequence voltage and
current thresholds are checked, if there is enough voltage and current the angle
measurement is checked. If there is not enough zero sequence the positive sequence
will be used and if there is enough voltage and current the angle measurement is
checked. If the thresholds are exceeded, a forward fault declaration occurs when the
sequence impedance angles are within 90 degrees of the line impedance.
SOURCE IMPEDANCE MEASUREMENT:
Introduction:
The source impedance element is used to determine the system X/R ratio and the
source impedance versus the line impedance ratio (SIR).
Description:
The incremental positive sequence voltage and currents are used to determine the
source impedance and system X/R ratio. The prefault voltages and currents are
subtracted from the instantaneous voltages and currents for the calculations.
Operation:
positive sequence impedance. The positive sequence impedance is stored into a 15
cycle buffer and is only updated if all the phase currents are below the zone 2 IP2
current supervision setting. If any of the phase currents exceed the zone 2 phase
current supervision setting IP2 the oldest 3 cycles are used to calculate the
incremental positive sequence magnitude.
If the incremental change in positive sequence current exceeds 0.1 amps the X/R and
SIR calculations are made otherwise the values are set to 0.0.
PHASE SELECTION:
Introduction:
The phase selection element is used to verify the faulted phase for single line to
ground and multiphase fault conditions. The ground distance element (21N) may
falsely operate for multiphase to ground faults with high resistance. The phase
distance element (21P) may falsely operate for singlephase to ground faults where
the distance is close to the terminals and high fault capacity exists.
Description:
The three phase currents are used to determine the fault type. The determination of
fault direction and phase selection supervises the three zones of impedance
elements.
Operation (firmware version pn21_01):
The directly measured fundamental phase current symmetrical components are used
to determine the faulted phase. The phase selection algorithm checks the angle
difference between the negative sequence and zero sequence currents to determine
which phase is faulted. The residual current must be above the IR2 threshold, the
individual phase currents must be above the IP2 threshold, and no open pole
8.15
RELAYING
condition can be present before the phase selection will start. By default, the phase
to phase elements are disabled at the start of the phase selection algorithm. The
algorithm determines if more than one phase is involved in the fault and then turns
off the appropriate phase to phase elements. The angle limit is non adjustable and
is set to 40.0 degrees. If the angle difference is less than 10.0 degrees only one sample
is needed to select the phase. If the angle difference is less than 30.0 degrees and
greater than 10.0 degrees, two samples are needed to select the phase. If the angle
difference is less than 40.0 degrees and greater than 30.0 degrees, three samples are
needed to select the phase.
Angle Relationship of Negative and Zero Sequence Currents:
Faults / Currents AG selected
BG selected
CG selected
IA2 and
IA0
< 40.0
IB2 and
IB0
< 40.0
IC2 and
IC0
<40.0
The above angle relationship will also hold true for phase to phase to ground faults
and the phase selection logic may indicate a single phase fault for phase to phase
faults. For example the angle difference between the negative and zero sequence
currents for a CG fault will be the same for an ABG fault. The directly measured
fundamental phase voltage symmetrical components can be used to detect phase to
phase faults.
The angle of the zero sequence voltage can be a good indicator of a phase to phase
faults. The magnitude of zero sequence voltage must be greater than 10% of the
prefault positive sequence voltage before this check is made. The angle of zero
sequence voltage must be within +/20.0 degress of 120.0, 0.0, or 120.0 degrees for
an AB, BC, or CA fault.
If the level of zero sequence voltage is below 10% of the prefault positive sequence
voltage the angle difference between the positive and negative sequence voltages is
used to detect phase to phase faults. For example with an AB fault the positive and
negative sequence voltages for C phase should be in phase. The angle limit check
using positive and negative sequence voltages is set to +/ 60.0 degrees. The
individual phase selection logic must also be a logic 0 for this check to be valid. For
example A phase and B phase must not be selected and the positive and negative
sqeuence voltage for C phase must be within 60.0 degrees of each other.
Phase to Neutral 21 Supervision
Phase to neutral 21 element supervision logic is formed based on the above Phase
Selector Criteria. The neutral distance elements are only allowed to operate if the
faulted phase is not involved with the element:
21N_A Supervision = No BG Fault and no CG Fault
21N_B Supervision = No AG Fault and no CG Fault
21N_C Supervision = No AG Fault and no BG Fault
8.16
RELAYING
Phase to Phase 21 Supervision
Phase to Phase 21 element supervision logic is formed based on the above Phase
Selector Criteria. The phase distance elements are only allowed to operate if the
faulted phase is not involved with the element:
21P_AB Supervision = only CG fault has been detected
21P_BC Supervision = only AG fault has been detected
21P_CA Supervision = only BG fault has been detected
DISTANCE ELEMENT (PDIS): 21
Introduction:
The distance element is used to verify that the impedance of the system as measured
by the relay is within the characteristic as defined in the RX plane. The distance
protection function can be enhanced by enabling the communication scheme (85
element).
Description:
There are 3 zones of distance protection, zone 1 and zone 2 can be set forward or
reverse, while zone 3 is fixed in the reverse direction. The three zones of distance
protection can be be either a MHO or a QUAD characteristic. The zone 1 element
operates without time delay, while the zone 2 and zone 3 elements can operate with
a variable time delay.
Operation:
The fundamental phase voltages, currents, and positive sequence memory voltage
are created by the signal processing algorithm of the relay. The phase selection and
directional elements supervise the distance elements. RMS quantities of phase,
phasephase, and neutral current are compared to threshold settings to determine if
the function is allowed to operate.
Note: The directional element will not be used to supervise any zone that has an offset
reach setting.
The MHO characteristic is achieved by checking the angle between 2 vectors, the
operating and polarizing vectors. The shape of the MHO element can be adjusted
to produce a shape other than a circle. Increasing the characteristic angle to a value
greater than 90.0 will produce a lens shape. Decreasing the characteristic angle to
a value less than 90.0 will produce a tomato shape. The ground distance element is
compensated so that the measured impedance relates to the positive sequence
impedance. If mutual coupling from a parallel line needs to be compensated an
optional input and setting can be enabled to compensate for the mutual coupling.
The QUAD characteristic is achieved checking the reactance of the top and bottom
settings relative to the forward and reverse reach settings. The left hand and right
hand sides of the quad are determined using the real part of the measured impedance
relative to the slope of a line that intersects R with an angle normally equivalent to
the positive sequence line angle.
See chapter 8 of the tutorial manual for more information.
BREAKER STATUS: 52
Introduction:
8.17
RELAYING
The breaker status is used to verify the state of the circuit breaker for the recloser,
secondary arc extinction, and breaker failure elements.
Description:
The status of each phase of the breaker is necessary whenever the recloser or breaker
failure element is enabled. A bit encoded word is used as the input to the breaker
status function.
Operation:
The bit encoded word is read into the relay and the status of each phase determines
the general closed or open status as well the open pole condition, i.e. only one phase
is open.
BREAKER FAILURE (RBRF): 50BF
Introduction:
The breaker failure element is used to determine if a tripping command has been
completed successfully. For close failure logic see the 79 element.
Description:
The element uses the phase status of the breaker and measures the current through
each phase to determine if the breaker has failed to properly open within a specified
time limit.
Operation:
The breaker failure timer is initiated when the relay sends a trip command to the
breaker. If the measured current does not drop below the specified threshold the
breaker failure element will try to trip all 3 phases of the breaker and set the recloser
to lockout. The tripping output of the breaker failure element will be limited to a
maximum specified time.
RECLOSER ELEMENT (RREC): 79
Introduction:
The breaker relcosing element is used to determine if a reclosing command should
be issued following a trip command.
Description:
The element uses the status of each phase of the breaker and determines if the breaker
should close after a specified time when the phase or phases of the breaker have been
opened following a fault conditon. The recloser element can also use the secondary
arc extinction element to supervise the reclose command. Three reclose attempts can
be programmed with separate open intervals.
Operation:
The recloser element has three states that are used to follow the progress of the
recloser logic. The states are lockout, reset, cycle and the recloser can only be in one
state at a time.
The following conditions will cause the recloser to be in the lockout state. If not
enabled or if enabled and the breaker is manually opened the lockout state will be set,
8.18
RELAYING
an external input can also be used to set the lockout state. If the recloser has attempted
too many reclose commands the lockout state will be set. If a breaker fail condition
occurs or a reverse zone 3 operation occurs the lockout state will be set. If single pole
tripping is enabled and the recloser is set to block relcosing for multiphase faults
the lockout state will be set.
When the status of the breaker has been closed longer than the reset time the recloser
will go into the reset state and the number of auto reclose attempts will be set to zero.
When the reset state is high the recloser can attempt to close the breaker if a zone 1,
or 85 weak infeed trip condition has caused the breaker to open.
When the status of the breaker changes from closed to open and the recloser was in
a reset or cycling state the number of reclose attempts will increase by one. If this
number is above the allowed attempts the recloser will go to lockout. When the trip
command is reset, the recloser is allowed to go into the cycle state and the open
interval timer is started. The duration of the timer can vary depending on the reclose
attempt number. If secondary arc detection has been enabled and the arc has not been
extinguished the reclose attempt will be blocked and the lockout state will be set. A
zone 3 distance operation will also block the reclose attempt.
When the recloser sends a close attempt to the breaker a timer is started and the
breaker needs to change from open to close status before the timer expires. If the
breaker does not close before the timer expires a close fail condition is declared and
There will be a 3 phase trip command issued for the previously described conditions
of close failure and block of reclose due to the secondary arc not extinguished.
Four typical modes of reclosing can be set and are described as follows:
1 Singlepole trip and reclose for singleline to ground faults/threepole trip
and no reclose for multiphase faults.
This type of operation can be achieved by setting the relay to trip single pole and no
reclose for multiphase faults. (e79>0, ttype=3Pole and r3ph=No)
2 Singlepole trip and reclose for singleline to ground faults/threepole trip
and reclose for multiphase faults.
This type of operation can be achieved by setting the relay to trip single pole and
reclose for multiphase faults. (e79>0, ttype=3Pole and r3ph=Yes)
3 Threepole trip and reclose for all fault types.
This type of operation can be achieved by setting the relay to trip three pole and
enabling the recloser. (e79>0 and ttype=3Pole)
4 Threepole trip for all fault types with no reclose.
This type of operation can be achieved by setting the relay to trip three pole and
disabling the recloser. (e79=0 and TrMod=3Pole)
SECONDARY ARC DETECTION:
Introduction:
The secondary arc detection element is used to determine if the secondary arc has
been extinguished following a single pole trip operation. If the secondary arc is not
8.19
RELAYING
extinguished the reclosing command should be not issued and the reclose attempt
should be blocked.
Description:
The element uses the states of each phase of the breaker and determines if the breaker
should close after a specified time when the phase or phases of the breaker have been
open following a fault conditon. The recloser element can also use the secondary arc
extinction element to supervise the reclose command.
Operation:
On high voltage transmission lines a combination of single pole tripping and auto
relcosing schemes are often used to limit the effects of opening all three phases of
a line due to single line to ground faults along the line. When a single phase of a
transmission line is opened due to a fault condition the healthy phases of the
transmission line remain in service and induce voltage on the open phase via the
coupling effect caused by the capacitance and inductance between phases and
ground. This induced voltage has a magnitude and rate of rise that is often enough
to cause the fault condition to continue due to the fact that the air has been ionized
from the primary arc. A secondary arc will establish and eventually extinguish, once
the secondary arc has disappeared the induced voltage may or may not cause the arc
to reestablish. The capacitance of the line and the inductance of shunt reactors (if
installed) is used to determine the value of the induced voltage.
Operation without Shunt Reactors:
During open pole conditions without fault conditions the induced voltage vector on
the open phase will be 180 degrees out of phase from the normal balanced position
and bounded within the confines of the 2 healthy phases, refer to figure 3. If this
condition is met the secondary arc is extinguished and is declared by the algorithm.
The voltage threshold is set by the user and a dropout timer is also used to prevent
8.20
RELAYING
the element from dropping out due to the instability of the induced voltage.
VC
135
Vopen
Varc
VA n
135
Figure 2: Phase A open pole characteristic

If the two ends of the line were configured with different open intervals and SAED
was enabled for both ends a condition will occur where the SAED element will drop
out at the follow end, when the lead end recloses and energizes the open phase. If
we do not recognize this condition properly and remove the SAED from supervising
the reclose element we would leave the SAED element in service and it would have
dropped and block the reclose attempt. The measured voltage of the open phase and
zero sequence voltage can be used to determine if this condition occurs.
Operation with Shunt Reactors:
During open pole conditions without fault conditions the induced voltage vector on
the open phase will be at some off nominal frequency and changing in magnitude
when the secondary arc is extinguished. The algorithm can use the voltage threshold
setting and dropout timer settings to declare the secondary has been extinguished.
By running the simulation the open pole voltage magnitude peaks and valleys can
be seen and the user can select an appropriate voltage threshold and measure the time
between this threshold and the dropout timer accordingly, refer to figure 4.
8.21
RELAYING
Figure 3: Phase A open pole Voltage magnitude

OUT OF STEP ELEMENT (RPSB): 68
Introduction:
The out of step function is suitable for supervision of distance element protection
and can be used to block or allow tripping during power swings that may cause
instability.
Description:
The out of step element requires 3 phase voltage and current signals. The positive
sequence impedance is used to determine out of step conditions and is supervised by
the phase current and residual current.
Two sets of inner and outer blinders on the RX plane form the detection boundaries
for the out of step condition. The blinders are straight lines situated at the positive
sequence angle of the protected line. A timer is used to determine the speed of travel
for the positive sequence impedance along the RXplane. This technique allows the
out of step element to react to power swings that may look like 3 phase fault
conditions.
Operation:
The fundamental phase voltages and currents are used to calculate the positive
sequence impedance. If any phase current is greater than the set point the function
is allowed to operate. If there is residual current the system is operating in an un
balanced condition, therefore if the residual current is greater than the set point the
function is blocked.
Normally the blinder impedances are set so that two blinders are on the left hand side
of the origin and two blinders are on the right hand side of the origin. If the
8.22
RELAYING
impedance crosses the line formed by one of the outer blinder setting a timer is
started, the corresponding bit in the Info and Start output signals are activated. The
trajectory path that will operate the function is a path towards the origin.
If the impedance does not cross the inner blinder within a specified time delay the
Trip or Block signal will become active when the impedance crosses the inner
blinder. The output will have a minimum pulse width equivalent to the setting
parameter TrPlsTmms when set for Trip.
If the function is set for blocking mode of operation the output will be disabled after
the time specified by parameter UnBlkTmms. The unblock timer prevents the 68
from holding a block signal on for an indefinite time. If the system condition has
persisted for T>UnBlkTmms then we want the function output to reset to allow the
other protection device to operate without the 68 supervision.
COMMUNICATION AIDED TRIPPING (PSCH): 85
Introduction:
Protecting transmission lines against sustained faults can be enhanced when a
communication aided tripping scheme is used to provide local fault information to
the remote end. Information from the remote end enhances the tripping logic at the
local end and can be used to prevent unwanted local tripping or to provide accelerated
local tripping of the circuit breaker.
Description:
Different communication aided tripping schemes are used and the two types
commonly used are permissive schemes and blocking schemes. Each scheme has
benefits and dependabilities that must be evaluated before being used with a
protection scheme.
Operation:
Permissive schemes are typically faster than blocking schemes but the permissive
schemes typically require a signal from the remote end before a decision is made to
trip. This dependance on the remote end makes these schemes less dependable than
a blocking scheme. But this dependance does add security against false tripping of
the overreaching element because there is no accelerated local tripping if the signal
is not sent from the remote end.
Blocking schemes are typically slower than permissive schemes but these schemes
do not require a signal from the remote end before a decision is made to trip. This
independence from the remote end makes blocking schemes more dependable, but
reduces security against false tripping. The false trip can occur at the local end when
the overreaching element makes a decision to perform an accelerated local trip
because the blocking signal was not sent from the remote end due to a problem in the
communication equipment.
BLOCKING SCHEMES:
For blocking schemes the local end of a transmission line typically has an
overreaching zone 2 element that is allowed to bypass its local timer and trip if a
blocking signal has not been sent from the remote end. The local and remote reverse
8.23
RELAYING
looking zone 3 element is typically used to initiate the sending of the blocking signal
to prevent the local overreaching zone 2 element from accelerated tripping.
PERMISSIVE SCHEMES:
Permissive schemes have many implementations and variations but can be
categorized as permissive under reach transfer tripping (PUTT) or permissive over
reach transfer tripping (POTT). Forward looking zone 1 elements are used with
PUTT schemes and forward looking zone 2 elements are used with POTT schemes.
Reverse looking zone 3 elements are used with both schemes. Normally the
coordination timer for the local tripping is set to zero.
PUTT:
The PUTT scheme uses the forward looking zone 1 element to transfer the local
tripping information, which is typically set to only reach 80% of the transmission
line. The remote end zone 2 element is used with the permissive signal from the local
end to allow the remote end to bypass the overreaching timer and trip. The use of
this method could leave a sustained fault on the 20% of the transmission line
protected by the zone 2 element unless another alternate tripping path is enabled.
Possible reasons may be a slowly operating zone 2, the direct transfer trip (DTT) or
intertrip method provides the alternate trip path. If the local end sees a fault at 90%
of the line, the remote zone 1 element transfers the remote trip information to the
local end which only has a slow zone 2 element operating. When the local end
receives the remote trip information, as long as no reverse looking elements have
operated the coordination timer is started and local end trips after the timer expires
(normally set to zero).
POTT:
The POTT scheme provides the most coverage for various faults but needs to be
applied properly to prevent false tripping of the transmission line. The added
complexity of a POTT scheme adds security but removes dependability. The
forward looking zone 2 element overreaches the remote end and transfers the local
tripping information to the remote end. The remote end zone 2 element is used with
the permissive signal from the local end to allow the remote end to bypass the
overreaching timer and trip.
Because overreaching elements are used additional logic, can be enabled if necessary
to prevent maloperation of the scheme.
POTT CURRENT REVERSAL:
Current reversal logic should be enabled if faults behind the relay cause the remote
end to send the permissive signal to the local end, for example a parallel line
application. When a fault behind the local end is cleared, the current may reverse
directions and momentarily cause the local end to start sending a permissive signal
to the remote end. If the local end overreaching element operates momentarily
during the reversal the overreaching element time delay maybe bypassed because the
remote end will still be sending the permissive signal. To prevent this from
happening a reverse looking zone 3 local element is used to start a timer which blocks
the sending of the local permissive signal and blocks the local end from bypassing
8.24
RELAYING
the overreaching element timer. A dropout timer extends the local end blocking after
the reverse fault is cleared and is used to help coordinate the time it takes for the
remote end to stop sending the permissive signal.
POTT WEAK INFEED:
POTT schemes are very useful where weak infeed terminals exist. An operating
condition on the power system may prevent a protection from operating due to the
weak source condition behind the relay. If a fault occurs in front of the relay, the
system voltages and currents may not change very much and prevent the distance
elements from operating. If no fault conditions are detected the permissive signal
from the other end can not do any local tripping unless some alternate logic is
enabled, this alternate logic is called weak infeed tripping.
The weak infeed function uses undervoltage elements to detect the presence of a local
weak infeed fault. No protection elements should be operating or have operated in
the past 200ms or this logic is blocked. When the above condition occurs and a
permissive signal is received from the remote end, a timer is started and after a delay
the weak infeed condition is declared. After the weak infeed condition is declared,
the local end trips and sends (echoes) back the permissive signal to the remote end.
If weak infeed is enabled in both the local and remote ends a permissive signal could
potentially loop back indefinitely. A 200ms maximum echo duration timer is used
to prevent this loop back condition.
UNBLOCKING SCHEMES (PLC and POTT):
A unblocking scheme can be used to overcome the lower dependability of a POTT
scheme. This logic is normally enabled or used when the communication medium
is powerline carrier (PLC). The loss of guard signal is used by the unblocking
scheme to create a local carrier receive (CR) signal (permissive from the other end).
PLC communications continuously transmit a carrier guard signal (CRG) between
stations to signify that the communication link is operational. If the CRG signal
disappears longer than a predefinedtime the loss of guard is declared and the pusedo
carrier receive logic is active signifying that the remote end has sent a permissive
signal. This logic enables the permissive scheme to operate even if the line fault has
prevented the PLC equipment to properly transfer the trip information between
stations.
If the unblocking method is set to No Restart the loss of guard signal (LCG) will
not be activated and the CR signal will be held on until the guard signal is
reestablished for longer than 200ms.
If the unblocking method is set to Restart the LCG will be activated until the guard
signal is reestablished for longer than 200ms. The CR signal will only be active for
150ms.
8.25
RELAYING
CURRENT
RELAY
8.5 MULTIFUNCTION OVERCURRENT
CLASS:
FUNCTION:
RSCAD/Draft ICON:
RELAY FUNCTION
50P,50N,51/67P,51/67N,46,79, Breaker Fail
_rtds_PN_5051_67_46
Introduction:
The multifunction overcurrent relay is suitable for providing the protection
function on single breaker transmission feeder lines with three pole tripping and
reclosing schemes. There is provision for breaker failure protection. Additional plot
signals provides sufficient information to help verify theoretical calculations with
the simulation results.
Description:
The current measuring loops include instantaneous phase (50P), instantaneous
neutral (50N), time delayed directional phase (51/67P), time delay directional
neutral (51/67N), and time delayed directional negative sequence (46) elements.
There is also the control logic for reclosing, and breaker failure on open and close.
The system frequency is determined using the instantaneous composite voltage
comprised of Va 0.5*Vb 0.5*Vc. If the system frequency changes the sample rate
is also changed to ensure a constant 8 samples per cycle. The measured system
frequency and rate of change of frequency can be monitored. The absolute difference
between the composite voltage and the previous time step composite voltage is used
to detect disturbances in the voltage. If a disturbance is detected the frequency
measurement and sample rate adjustment is suspended for 3 cycles.
Operation:
8.26
RELAYING
The fundamental phase voltages and currents are fed into the 6 inputs of the PTOC
function. The RMS quantities are calculated and a comparator is used to determine
if the measured current is greater than the set point. If any phase current or residual
current is greater than the set point the comparator output causes the Start and Info
signals to become active. After a specified time delay the Trip signal will become
active. If the PTOC function is set to operate on residual current the residual current
is calculated according to: 3I0 = IA + IB +IC. If the PTOC function is set to operate
on negative sequence current the 3I2 current is calculated according to: 3I2 = IA +
IBa2 +ICa1, where a1 and a2 are the operators for symmetrical component theory.
The PTOC can be set to operate relative to the direction of the fault. Enabling of
directional control will require that current reversal conditions block operation of the
element for 2 cycles.
This relay model will use a widely employed method of directional control called the
90 deg 60 deg method for phase fault protection. This method uses the phasephase
voltage of the unfaulted phases to provide the polarizing quantity for the directional
unit. The 90 deg name comes from the fact that under normal system conditions and
when the power factor is 100%, the operating quantity is leading the polarizing
quantity by 90 degrees. During a single phase to ground fault the faulted current tends
to lag the phase voltage. This lagging phase angle will put the operating quantity into
the area where maximum torque will be produced with respect to the polarizing
quantity.
If the PTOC is configured for residual current operation, the zero sequence voltage
and current are used for directional sensitivity. For additional security with the
directional measurement the voltage can be augmented by the zero sequence current
multiplied by an offset impedance. This offset impedance should never be larger
than the zero sequence impedance and normally is several times smaller.
If the PTOC is configured for negative sequence current operation the negative
sequence voltage and current are used for directional sensitivity. For additional
security with the directional measurement the voltage can be augmented by the
negative sequence current multiplied by an offset impedance. This offset impedance
should never be larger than the negative sequence impedance and normally is several
times smaller.
Polarizing values are as follows.
Operation
Polarizing V
Polarizing I
Maximum Torque (default)
Phase A (67)
VBC
IA
I lags V by 60deg
Phase B (67)
VCA
IB
I lags V by 60deg
Phase C (67)
VAB
IC
I lags V by 60deg
Residual (67N)
V zero +
Voffset (option)
I zero
I lags V by 60deg
Negative (46)
V negative +
Voffset (option)
I negative
I lags V by 60deg
8.27
RELAYING
Van
Zero
Torque line
30deg
Ian (100% pf)

Max
Torque line
60deg
30deg
Vbc
60deg
Operate zone
Non operate zone
Figure 1: Phase A polarizing quantities

The setpoint for operation can be changed to a preset value by enabling and asserting
the binary input Multiple. This function maybe necessary for operating conditions
such as cold load pickup or transformer inrush.
The operation of the relay can be blocked by enabling and asserting the binary input
Ext Block.
The trip output is intended to be a 3phase trip and will have a minimum pulse width
equivalent to the setting parameter MinOpTmms. If the overcurrent condition lasts
longer than this setting, the trip output will reset when the overcurrent condition
resets. The 51P and 51N elements can be controlled by an external binary input to
use a second set of curve parameters. When enabled if bit 0 is asserted element 51P
will use the second curve parameters and if bit 1 is asserted element 51N will use the
second curve parameters.
Time Curve Parameters:
Characteristic
TR
IEC Standard Inverse
0.14
0.0
0.02
4.85
IEC Very Inverse
13.5
0.0
1.0
21.6
IEC Extremely Inverse
80.0
0.0
2.0
29.1
IEEE Moderately Inverse 0.0103
0.0228
0.02
0.97
IEEE Very Inverse
3.922
0.0982
2.0
4.32
IEEE Extremely Inverse
5.64
0.0243
2.0
5.82
8.28
RELAYING
The time required to operate for various inverse time characteristics is calculated
using equation 1.
A
t P TMS B
IP
Equation1: Inverse Characteristic Operate Time

The time for the disk to reset to the rest position is calculated using equation 2.
tr
TR
2
I
1
IP
Equation2: Inverse Characteristic ResetTime
Recloser Time Curve Parameters:

The 51P and 51N elements support the following Recloser Curves.
Characteristic
2 (135)
11.4161
0.488986
0.239257
1.84911
3 (140)
13.5457
0.992904
0.379882
1.76391
8 (113)
1.68546
0.158114
0.436523
1.78873
8+ (111)
1.42732
0.003704 0.366699
1.70112
8*
1.42302
0.007846 0.442626
1.42529
9 (131)
2.75978
5.10647
0.614258
1.0353
11 (141)
21.6149
10.6788
0.67185
2.69489
1 (102) not supported


8.29
RELAYING
A (101) not supported
B (117)
4.2286
0.008933
0.319885
1.7822
C (133)
8.76047
0.029977
0.380004
1.80788
D (116)
5.23168
0.000462
0.17205
2.17125
E (132)
10.7656
0.004284
0.249969
2.18261
11.9847
0.000324 0.688477
2.01174
F (163) not supported

G (121) not supported
H (122) not supported
J (164) not supported
KGround (165) not supported
KPhase (162)
L (107) not supported
M (118) not supported
N (104)
0.2825625 0.071079 0.464202
0.911551
0.001015
0.13381
0.998848
0.00227
15.4628
0.056438
0.345703
1.6209
P (115) not supported

R (105)
T (161) not supported
V (137) not supported
W (138)
Y (120) not supported
Z (134) not supported
The time required to operate for various Recloser Curve characteristics is calculated
using equation 3.
A
B sec onds
Time TMS
P
I
Pickup C
Equation3: Recloser Curve Characteristic Operate Time

The time for the element to reset is always instantaneous when using the relcoser
curves.
///////////////////////////////////////////////////////////////////////////////
// 0 Antialias filter, downsampler, DFT, fault detection, freq tracking with
8.30
RELAYING
// dph/dt, other inputs,
// 1 phph voltages, fault currents, and phase polarizing quantities
// 2 neutral and negative sequence polarizing quantities
// 3 Instantaneous Overcurrent (50P)
// 4 Instantaneous Overcurrent (50N), output for 50P&50N PIOC, CB status
// 5 Time delayed Overcurrent (51/67P)
// 6 Time delayed Overcurrent (51N), Breaker Failure
// 7 Time delayed Overcurrent (46), Reclosing Relay
///////////////////////////////////////////////////////////////////////////////
BREAKER STATUS: 52
Introduction:
The breaker status is used to verify the state of the circuit breaker for the recloser,
secondary arc extinction, and breaker failure elements.
Description:
The status of each phase of the breaker is necessary when the recloser or breaker
failure element is enabled. A bit encoded word is used as the input to the breaker
status function.
Operation:
The bit encoded word is read into the relay and the status of each phase determines
the general closed or open status as well as the open pole condition, i.e. only one
phase is open.
BREAKER FAILURE (RBRF): 50BF
Introduction:
The breaker failure element is used to determine if a tripping command has been
completed successfully. For close failure logic see the 79 element.
Description:
The element uses the phase status of the breaker and measures the current through
each phase to determine if the breaker has failed to properly open within a specified
time limit.
Operation:
The breaker failure timer is initiated when the relay sends a trip command to the
breaker. If the measured current does not drop below the specified threshold the
breaker failure element will try to trip all 3 phases of the breaker and set the recloser
to lockout. The tripping output of the breaker failure element will be limited to a
maximum specified time.
RECLOSER ELEMENT (RREC): 79
Introduction:
The breaker relcosing element is used to determine if a reclosing command should
be issued following a trip command.
8.31
RELAYING
Description:
The element uses the states of each phase of the breaker and determines if the breaker
should close after a specified time when the phases of the breaker have been open
following a fault condition and reclose initiation. Four reclose attempts can be
programmed with separate open intervals.
Operation:
The recloser element has three states that are used to follow the progress of the
recloser logic. The states are lockout, reset, cycle and the the recloser can only be
in one state at a time.
The following conditions will cause the recloser to be in the lockout state. If not
enabled or if enabled and the breaker is manually opened the lockout state will be set,
an external input can also be used to set the lockout state. If the recloser has attempted
too many reclose commands the lockout state will be set. If a breaker fail condition
occurs the lockout state will be set. If an element is enabled and set to block relcosing
When the status of the breaker has been closed longer than the reset time the recloser
will go into the reset state and the number of auto reclose attempts will be set to zero.
When the reset state is high the recloser can attempt to close the breaker if an element
is enabled and set to initiate the reclose.
When the status of the breaker changes from closed to open and the recloser was in
a reset or cycling state, the number of reclose attempts will increase by one. If this
number is above the allowed attempts the recloser will go to lockout. When the trip
command is reset, the recloser is allowed to go into the cycle state and the open
interval timer is started. The duration of the timer can vary depending on the reclose
attempt number.
When the recloser sends a close attempt to the breaker a timer is started and the
breaker needs to change from open to close status before the timer expires. If the
breaker does not close before the timer expires a close fail condition is declared and
There will be a 3 phase trip command issued for the previously described conditions
of close failure and block of reclose due to a breaker failure condition.
Input signals for the PTOC_51 function block
Signal
Description
Format
VA
A phase voltage
Float
VB
B phase voltage
Float
VC
C phase voltage
Float
IA
A phase current
Float
IB
B phase current
Float
8.32
RELAYING
IC
C phase current
Float
Multiple
Enable current start value multiplier
Integer
Ext Block
Block operation of the function
Integer
nCB
Breaker status input signal name
Integer (import)
n51PCurve
Phase/Neutral TOC Curve Control Input Signal Name (if 2 curves enabled)
Integer (import)
Output signals for the PTOC_51 function block

Signal
Description
Format
Trip
Trip signal from any phase
Integer
8.33
RELAYING
Info
Relay word bits:

0 : 50P_A trip signal
1 : 50P_B trip signal
2 : 50P_C trip signal
3 : 50N trip signal
7 : 51P reset signal
8 : 51N trip signal
9 : 51N reset signal
10 : 46 trip signal
11 : 46 reset signal
12 : 50P positive torque signal
13 : 50N positive torque signal
14 : 51P positive torque signal
15 : 51N positive torque signal
16 : 46 positive torque signal
17 : Breaker Failure signal
18 : Block Reclose signal
19 : Internal Lockout signal
20 : Initiate Reclose signal
21 : Internal CB Aph Status signal
22 : Internal CB Bph Status signal
23 : Internal CB Cph Status signal
24 :
.... (not used)
31 :
Integer (word)
Start
Start signal from timing function
Integer
Monitoring signal names (MSQI):

The default signal names of the Monitoring signals for the OVERCURRENT
function block are shown next, the names can be changed. The maximum length of
the signal name is 8 characters, an optional suffix can be added for a maximum
overall length of 10 characters.
Export/Plot signals for the PTOC_51 function block
Signal
Description
Format
Operate51P
Expected operate time (seconds)
Float
8.34
RELAYING
Rest51P
Expected reset time (seconds)
Float
Elapsed51P
Elapsed timer (seconds)
Float
AphTorq51P
Polarizing Torque (pu) + fwd rev
Float
BphTorq51P
Float
CphTorq51P
Float
Operate51N
Float
Reset51N
Float
Elapsed51N
Float
NphTorq51N
Float
Operate46
Float
Reset46
Float
Elapsed46
Float
NseqTorq46
Float
VARE
Float
VAIM
Float
VBRE
Float
VBIM
Float
VCRE
Float
VCIM
Float
IARE
Float
IAIM
Float
IBRE
Float
IBIM
Float
ICRE
Float
ICIM
Float
FREQ
Float
DFREQ
Float
Setting Parameters:
Setting parameters for the PTOC_51 function block
CONFIGURATION:
Parameter
Range
Default
Unit
Description
iedName
10 character
RTDS
PN
IED Name
fver
pn51_00
pn51_00
8.35
RELAYING
freq
60.0, 50.0
60.0
hz
adv
None, V by
1dt
None

e50
YES, NO
YES
Enable instantaneous phase and /or

neutral element
e51
YES, NO
YES
Enable inverse or definite phase and/or

neutral element
e46
YES, NO
YES
Enable inverse or definite negative sequence element
e79
0,1,2,3,4
Enable or Disable the number of Reclose Attempts
eBF
OFF, ON
OFF
Enable 50BF Breaker Fail Detection
plots
NO, YES
NO
Enable or Disable plotting
sfx
2 characters

plot signal names
eblk
Off, On
Off
Enable external blocking function
emult
Off, On
Off
Enable Mult. Starting Current Value
MTA
0.0 90.0
60.0
degrees
Maximum Torque Angle
zoff
0.0 250.00
0.0
ohms
Offset Z (< Z2 or Z0 of line)

Parameter
Range
Default
Unit
Description
TrPlsTmms
50.0
2,000.0
150.0
msec
50 OVERCURRENT ELEMENT (PIOC): (e50>0)

e50P
NO,YES
YES
Enable instantaneous Phase element
DirMod50P
OFF,
FWD,REV
FWD
Directional Control
StrVal50P
0.5 50.00
1.0
amps
Start Value ( Imeas >> setpoint)
StrValMult50P
0.5 5.0
1.0
Multiplier for setpoint current level
e50N
NO,YES
YES
Enable instantaneous Neutral element
DirMod50N
OFF,
FWD,REV
FWD
Directional Control
8.36
RELAYING
StrVal50N
0.5 50.00
1.0
amps
StrValMult50N
0.5 5.0
1.0
51/67 OVERCURRENT ELEMENT (PTOC): (e51>0)

e51P
NO,YES,
2 Curves
YES
Enable Time Overcurrent Phase element
DirMod51P(2)
OFF,
FWD,REV
FWD
Directional Control
TmACrv51P(2)
IEC_STD
IEC_VI
IEC_VI
IEC_EI
IEEE_MI
IEEE_VI
IEEE_EI
USER
DEFINITE
2 (135)
3 (140)
8 (113)
8+ (111)
8*
9 (131)
11 (141)
B (117)
C (133)
D (116)
E (132)
KPhs (162)
N (104)
R (105)
W (138)
Operating Curve Type
StrVal51P(2)
0.05 50.00
1.0
amps
TmMult51P(2)
0.01 10.00
0.5
Time Dial Multiplier
OpDlTmms51P(2) 10.0
100,000.0
500.0
msec
Operate Time Delay (TmACrv51P=7)
RsDlTmms51P(2) 100.0
100,000.0
850.0
msec
Reset Time Delay (TmACrv51P=7)
StrValMult51P(2)
0.5 5.0
1.0
pA51P(2)
0.0010
1000.0000
1.0
User defined A parameter

(TmACrv51P=6) ...
pB51P(2)
0.00 10.00
1.0
User defined B parameter
8.37
RELAYING
pP51P(2)
0.01 10.00
1.0
User defined P parameter
e51N
NO,YES,
2 Curves
YES
Enable Time Overcurrent Neutral element
DirMod51N(2)
OFF,
FWD,REV
FWD
Directional Control
TmACrv51N(2)
IEC_STD
IEC_VI
IEC_VI
IEC_EI
IEEE_MI
IEEE_VI
IEEE_EI
USER
DEFINITE
2 (135)
3 (140)
8 (113)
8+ (111)
8*
9 (131)
11 (141)
B (117)
C (133)
D (116)
E (132)
KPhs (162)
N (104)
R (105)
W (138)
StrVal51N(2)
0.05 50.00
1.0
amps
TmMult51N(2)
0.01 10.00
0.5
OpDlTmms51N(2)
10.0
100,000.0
500.0
msec
Operate Time Delay (TmACrv51N=7)
RsDlTmms51N(2) 100.0
100,000.0
850.0
msec
Reset Time Delay (TmACrv51N=7)
StrValMult51N(2) 0.5 5.0
1.0
pA51N
0.0010
1000.0000
1.0

(TmACrv51N=6) ...
pB51N(2)
0.00 10.00
1.0
8.38
RELAYING
pP51N(2)
0.01 10.00
1.0
n51PCurve
variable
CURVE5 integer
1P
Phase/Neutral TOC Curve Control Input Signal Name (bit 0 controls 51P2
and bit 1 controls 51N2)
46 OVERCURRENT ELEMENT: (e46>0)

DirMod46
OFF,
FWD,REV
FWD
Directional Control
TmACrv46
IEC_STD
IEC_VI
IEC_EI
IEEE_MI
IEEE_VI
IEEE_EI
USER
DEFINITE
IEC_VI
StrVal46
0.05 50.00
1.0
amps
TmMult46
0.01 10.00
0.5
OpDlTmms46
10.0
100,000.0
500.0
msec
Operate Time Delay (TmACrv46=7)
RsDlTmms4
6
100.0
100,000.0
850.0
msec
Reset Time Delay (TmACrv46=7)
StrValMult46 0.5 5.0
1.0
pA46
0.0010
1000.0000
1.0

(TmACrv46=6) ...
pB46
0.00 10.00
1.0
pP46
0.01 10.00
1.0
52 BREAKER STATUS: (e79>0 or eBF>0)

Parameter
Range
Default
Unit
Description
nCB
variable
CB1
integer
Abit
1 16

status
Bbit
1 16

status
Cbit
1 16

status
8.39
RELAYING
50BF BREAKER FAILURE (RBRF): (eBF>0)
Parameter
Range
Default
Unit
Description
FailTmms
75.0
10,000.0
200.0
msec
Open Failure Timer
DetValA
0.1 1.99
0.2
amps
Phase current Threshold
BFhTmms
100.0
10,000.0
2,000.0
msec
BF Maximum Trip Hold Timer
79 RECLOSER TIMERS (RREC): (e79>0)

Parameter
Range
BlkRec
control
variable
i79a
NO, YES
i79b
Default
Unit
Description
External Input Block Reclose Signal

Name
NO
50P initiates reclosing
NO, YES
NO
50N initiates reclosing
i79c
NO, YES
NO
51/67P initiates reclosing
i79d
NO, YES
NO
51/67N initiates reclosing
i79e
NO, YES
NO
46 initiates reclosing
RclTmms
10.0
999,999
10,000.0
msec
Reset Lockout Timer
Rec1Tmms
10.0
999,999
5,000.0
msec
Rec2Tmms
10.0
999,999
5,000.0
msec
Rec3Tmms
10.0
999,999
5,000.0
msec
Rec4Tmms
10.0
999,999
5,000.0
sec
PlsTmms
50.0
2,000.0
150.0
msec
Close Pulse duration
ClsFlTmms
10.0
10,000.0
500.0
msec
Close Failure Timer
tCF
0.01 10.0
0.50
sec
Close Failure Timer
Execution Time
GPC
2.626
us
8.40
RELAYING
DIFFERENTIAL
RELAY
8.6 MULTIFUNCTION DIFFERENTIAL
CLASS:
FUNCTION:
RSCAD/Draft ICON:
RELAY FUNCTION
87B,87T
_rtds_PN_87
Introduction:
The multifunctiondifferential relay is suitable for providing the protection function
on bus and transformers. Additional plot signals provide sufficient information to
help verify theoretical calculations with the simulation results.
Description:
The current measuring loops can include up to two 2 slope differential characteristics
(87B1 and 87B2), one transformer and one bus 2 slope differential characteristic
(87B1 and 87T), or a single bus or transformer differential element.
Operation:
The fundamental phase currents are fed into the 10 inputs of the differential function.
The sampled data is adjusted if necessary to compensate for ratio mismatch and
phase shifts. The operating quantity and restraining quantity is calculated for each
phase and applied to the 2 slope differential current characteristic. The transformer
protection element uses an additional measurement ratio of 2nd harmonic over
fundamental to prevent misoperation during transformer energization.
The operating quantity is the vector sum of each phase current, a DFT is used to
extract the fundamental magnitude and for transformer protection the 2nd harmonic
magnitude as well. The restraint quantity is calculated using the summation of every
connected CT current magnitude divided by onehalf.
The amount of restraint current determines the amount of operating current required
to operate. The operating quantity must be above the minimum operating value
setting or the relay will not operate. If the restraint current increases above the value
of IRSMIN calculated using ( IRSMIN = IOMIN * 1.0Slope1) the amount of operating
8.41
RELAYING
current necessary to make the relay operate increases along Slope1. If the restraint
current increases above the slope1\slope2 breakpoint calculated using
( IRS = IRSMIN * IRs) the amount of operating current necessary to make the relay
operate increases along Slope2. If the restraint current increases above the
slope2\high set breakpoint calculated using ( IORS = IRS * 1.0Slope2) the amount of
operating current necessary to make the relay operate does not increase beyond this
breakpoint value times the HiSet PU setting parameter.
I operate
S2\IOH breakpoint
IO High Set
Slope 2
Operate zone
S1\S2 breakpoint
Slope 1
Non operate zone
IOmin
IRsmin
I restraint
Figure 1: Two Slope Percentage Differential

///////////////////////////////////////////////////////////////////////////////
// 0 Antialias filter, downsampler, ratio correction factor,
//
Transformer Operate quantities
// 1 Bus 1 and Bus 2 Operate quantities
// 2 CT1 CT5 DFT
// 3 CT6 CT10 DFT
// 4 Bus 1 Protection
// 5 Transformer Protection
// 6 Bus 2 Protection
// 7 Write outputs
///////////////////////////////////////////////////////////////////////////////
Input signals for the PDIF_87 function block
Signal
Description
Format
nCT1A
A phase current
Float (import)
nCT1B
B phase current
Float (import)
nCT1C
C phase current
Float (import)
IA
A phase current
Float (import)
8.42
RELAYING
IB
B phase current
Float (import)
IC
C phase current
Float (import)
Output signals for the PDIF_87 function block

Signal
Description
Format
Trip Bus 1
Integer
Trip XFMR orTrip Bus 2
Integer
Info
Relay word bits:

Integer (word)
0 : 87B1_A trip signal
1 : 87B1_B trip signal
2 : 87B1_C trip signal
3 : 87T_A trip signal
4 : 87T_B trip signal
5 : 87T_C trip signal
6 : 87T_A 2nd harmonic block signal
7 : 87T_B 2nd harmonic block signal
8 : 87T_C 2nd harmonic block signal
9 : 87B2_A trip signal
10 : 87B2_B trip signal
11 : 87B2_C trip signal
12 :
.... (not used)
31 :
Start
Start signal from any 87 function
Integer

The default signal names of the Monitoring signals for the DIFFERENTIAL
function block are shown next, the names can be changed. The maximum length of
the signal name is 8 characters, an optional suffix can be added for a maximum
Signal
Description
Format
B1IAOP
Bus1 A Phase Operating (fund)
Float
B1IARS
Bus1 A Phase Restraining (fund)
Float
B1IBOP
Bus1 B Phase Operating (fund)
Float
B1IBRS
Bus1 B Phase Restraining (fund)
Float
B1ICOP
Bus1 C Phase Operating (fund)
Float
B1ICRS
Bus1 C Phase Restraining (fund)
Float
8.43
RELAYING
IOMINB1
Bus1 Minimum Operating current
Float
IRSMINB1
Bus1 Minimum Restraining current
Float
S1S2B1
Bus1 Slope1\Slope2 breakpoint
Float
IOHSB1
Bus1 Operating current High Setting
Float
TIAOP
XFMR A Phase Operating (fund)
Float
TIARS
XFMR A Phase Restraining (fund)
Float
TIA2ND
XFMR A Phase Operating (2nd harm)
Float
TIBOP
XFMR B Phase Operating (fund)
Float
TIBRS
XFMR B Phase Restraining (fund)
Float
TIB2ND
XFMR B Phase Operating (2nd harm)
Float
TICOP
XFMR C Phase Operating (fund)
Float
TICRS
XFMR C Phase Restraining (fund)
Float
TIC2ND
XFMR C Phase Operating (2nd harm)
Float
IOMINT
XFMR Minimum Operating current
Float
IRSMINT
XFMR Minimum Restraining current
Float
S1S2T
XFMR Slope1\Slope2 breakpoint
Float
IOHST
XFMR Operating current High Setting Float
B2IAOP
Bus2 A Phase Operating (fund)
Float
B2IARS
Bus2 A Phase Restraining (fund)
Float
B2IBOP
Bus2 B Phase Operating (fund)
Float
B2IBRS
Bus2 B Phase Restraining (fund)
Float
B2ICOP
Bus2 C Phase Operating (fund)
Float
B2ICRS
Bus2 C Phase Restraining (fund)
Float
IOMINB2
Bus2 Minimum Operating current
Float
IRSMINB2
Bus2 Minimum Restraining current
Float
S1S2B2
Bus2 Slope1\Slope2 breakpoint
Float
IOHSB2
Bus2 Operating current High Setting
Float
Setting Parameters:
Setting parameters for the PDIF_87 function block
CONFIGURATION:
Parameter
Range
Default
Unit
Description
iedName
10 character
RTDS
PN
IED Name
fver
pn87_00
pn87_00
8.44
RELAYING
freq
60.0, 50.0
eZones
60.0
hz
Bus 1, Bus 1 Bus 1

and XFMR, and
XFMR only, XFMR
Bus 1 and
Bus 2
Enable differential element
plots
NO, YES
Enable or Disable plotting
sfx
2 characters

plot signal names
NO
SYSTEM CONFIGURATION:
Parameter
Range
Default
Unit
Description
Bus1kV
1.01000.0
230.0
kV
Bus 1 Voltage / Winding 1
YD1
Y, Delta
Delta
Winding #1 Connection
XfmrWdg
2 wdg, 3wdg 2 wdg
Transformer Windings
XfmrkV
1.01000.0
115.0
kV
Transformer Bus Voltage / Winding 2
YD2
Y, Delta
Xfmr3kV
1.01000.0
33.0
kV
Transformer Bus Voltage / Winding 2
YD3
Y, Delta
Delta
Lead
Lags, Leads
Lags
Delta lags or leads Y

Parameter
Range
Default
Unit
Description
TrPlsTmms
50.0
2,000.0
150.0
msec
CT CONNECTIONS: (Bus 1 only)

Parameter
Range
Default
Unit
Description
aIP1
NC, Bus1
Bus1
Input 1 Connects to
aIP2
NC, Bus1
Bus1
Input 2 Connects to
aIP3
NC, Bus1
Bus1
Input 3 Connects to
aIP4
NC, Bus1
Bus1
Input 4 Connects to
aIP5
NC, Bus1
Bus1
Input 5 Connects to
aIP6
NC, Bus1
Bus1
Input 6 Connects to
aIP7
NC, Bus1
Bus1
Input 7 Connects to
aIP8
NC, Bus1
Bus1
Input 8 Connects to
aIP9
NC, Bus1
Bus1
Input 9 Connects to
aIP10
NC, Bus1
Bus1
Input 10 Connects to
8.45
RELAYING
CT CONNECTIONS: (Bus 1 and/or XFMR and 2 winding)
Parameter
Range
Default
Unit
Description
bIP1
NC, Bus1
Bus1
Input 1 Connects to
bIP2
NC, Bus1
Bus1
Input 2 Connects to
bIP3
NC, Bus1
Bus1
Input 3 Connects to
bIP4
NC, Bus1
Bus1
Input 4 Connects to
bIP5
NC, Bus1
Bus1
Input 5 Connects to
bIP6
NC, Bus1
Bus1
Input 6 Connects to
bIP7
NC, Bus1
Bus1
Input 7 Connects to
bIP8
NC, Bus1
Bus1
Input 8 Connects to
bIP9
,
Bus1/XF
Bus1/XFMR MR
Input 9 Connects to
bIP10
, XFMR
XFMR
CT CONNECTIONS: (Bus 1 and/or XFMR and 3 winding)

Parameter
Range
Default
Unit
Description
cIP1
NC, Bus1
Bus1
Input 1 Connects to
cIP2
NC, Bus1
Bus1
Input 2 Connects to
cIP3
NC, Bus1
Bus1
Input 3 Connects to
cIP4
NC, Bus1
Bus1
Input 4 Connects to
cIP5
NC, Bus1
Bus1
Input 5 Connects to
cIP6
NC, Bus1
Bus1
Input 6 Connects to
cIP7
NC, Bus1
Bus1
Input 7 Connects to
cIP8
,
Bus1/XF
Bus1/XFMR MR
Input 8 Connects to
cIP9
,XFMR
XFMR
Input 9 Connects to
cIP10
, XFMR
XFMR
CT CONNECTIONS: (Bus 1 and Bus 2)

Parameter
Range
Default
Unit
Description
dIP1
NC, Bus1
Bus1
Input 1 Connects to
dIP2
NC, Bus1
Bus1
Input 2 Connects to
dIP3
NC, Bus1
Bus1
Input 3 Connects to
dIP4
NC, Bus1
Bus1
Input 4 Connects to
dIP5
NC, Bus1
Bus1
Input 5 Connects to
dIP6
NC, Bus1,
Bus2
Bus1
Input 6 Connects to
8.46
RELAYING
dIP7
NC, Bus1,
Bus2
Bus1
Input 7 Connects to
dIP8
NC, Bus1,
Bus2
Bus1
Input 8 Connects to
dIP9
NC, Bus2
Bus2
Input 9 Connects to
dIP10
NC, Bus2
Bus2
87 BUS 1 DIFFERENTIAL ELEMENT:

LoSetB1
0.25 5.00
0.75
amps
IRsB1
2.0 8.0
4.0
puIRmin Slope 1 / Slope 2 Breakpoint
HighSetB1
0.1 5.0
1.0
puIORS2 Maximum Operating Current
Slope1B1
5.0 50.0
30.0
Slope 1
Slope2B1
35.0 150.0
50.0
Slope 2
Note1
Note2
Minimum Operating Current
IRmin=LoSetB1*(1.0/Slope1B1)
IORS2=(IRsB1*IRmin)*(1.0/Slope2B1)
87 TRANSFORMER DIFFERENTIAL ELEMENT:

LoSetT
0.25 5.00
0.75
amps
IRsT
2.0 8.0
4.0
HighSetT
0.1 5.0
1.0
Slope1T
5.0 50.0
30.0
Slope 1
Slope2T
35.0 150.0
50.0
Slope 2
PhStrT
5.0 50.0
12.0
2nd Harmonic Blocking
Note1
Note2
IRmin=LoSetT*(1.0/Slope1T)
IORS2=(IRsT*IRmin)*(1.0/Slope2T)
87 BUS 2 DIFFERENTIAL ELEMENT:

LoSetB2
0.25 5.00
0.75
amps
IRsB2
2.0 8.0
4.0
HighSetB2
0.1 5.0
1.0
Slope1B2
5.0 50.0
30.0
Slope 1
Slope2B2
35.0 150.0
50.0
Slope 2
Note1
Note2
CT 1 CT 10 PARAMETERS:
Parameter
Range
rCT1
10.02500.0 100.0
Default
Unit
Description
float
Turns Ratio : 1
8.47
RELAYING
Abit
variable
IA1
A phase Input Signal Name
Bbit
variable
IB1
B phase Input Signal Name
Cbit
variable
IC1
C phase Input Signal Name
rCT2
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA2
Bbit
variable
IB2
Cbit
variable
IC2
rCT3
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA3
Bbit
variable
IB3
Cbit
variable
IC3
rCT4
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA4
Bbit
variable
IB4
Cbit
variable
IC4
rCT5
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA5
Bbit
variable
IB5
Cbit
variable
IC5
rCT6
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA6
Bbit
variable
IB6
Cbit
variable
IC6
rCT7
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA7
Bbit
variable
IB7
Cbit
variable
IC7
rCT8
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA8
Bbit
variable
IB8
Cbit
variable
IC8
rCT9
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA9
Bbit
variable
IB9
Cbit
variable
IC9
8.48
RELAYING
rCT10
10.02500.0 100.0
float
Turns Ratio : 1
Abit
variable
IA10
Bbit
variable
IB10
Cbit
variable
IC10
Execution Time
GPC
2.892
us
8.49
RELAYING
GENERATOR
RELAY
8.7 MULTIFUNCTION GENERATOR
CLASS:
RELAY FUNCTION
FUNCTION:
87P,87N,50/51N,50/51P,46,64,40,32,AE,24,27,59,81,78,21,25,60
RSCAD/Draft ICON: _rtds_PN_GEN.def
Introduction:
The multifunction generator relay is suitable for providing the protection function
on synchronous machines. Differential elements for phase and neutral currents,
100% stator protection, loss of field protection, outofstep, volts per hertz, and
other additional relay elements provide comprehensive protection for the generator.
Additional plot signals provide sufficient information to help verify theoretical
calculations with the simulation results. An indepth look at generator protection can
be found in the references to this section and in particular chapter 8 of reference 3.
Description:
The relay samples the system voltages and currents at 16 samples per cycle and can
accept an external frequency signal to adjust the sampling rate, if the system
frequency changes the sample rate is also changed and the phase angles of the
voltages and currents are adjusted as well. If external frequency tracking in not
enabled the system frequency is determined using the change in angle of the positive
sequence voltage between samples using the following formula; w_rot = ((w_tan1
w_tan2)/(f_sample_t*6.283185307)).
The following protection elements are available in the relay:
DEVICE
DESCRIPTION
87P
Phase percentage restrained differential, can include unit stepup

transformer, and unit auxiliary transformer
8.50
RELAYING
87N
Ground differential for low impedance grounded generators
50/51N
Neutral Overcurrent Protection
50/51P
Phase Overcurrent Protection
64G
100% Stator Ground Detection for high impedance and resistance

grounded generators
40
LossofField Protection
32
Loss of Prime Mover Protection
AE
Accidental Energization Protection
24
Volts per Hertz Protection
46
Negative Sequence Overcurrent Protection
27
Undervoltage Element
59
Overvoltage Element
81
Over and Under Frequency Protection
81of
Off Nominal Frequency Time Accumulators for Steam Turbines
78
OutofStep Protection
21
Distance Backup Protection with Load Encroachment
25
SynchroCheck Element for Breaker Close Supervision
60
LossofPotential Logic
Operation:
The phase voltages and currents and neutral voltage and current are connected to the
14 inputs of the GENERATOR function. Additional inputs are also available for a
external frequency tracking signal and synchronization voltage signal. A 16 point
DFT is used to calculate the RMS values and the instantaneous impedance is
calculated for the phasetophase, phasetoground, positive sequence, negative
sequence, and zero sequence. The fundamental, 2nd, and 3rd harmonics are
calculated for the necessary protection elements. The breaker status signal is also
connected to an input to provide open or closed indication. A 2nd order butterworth
low pass filter is used for antialiasingand a filter is used to block DC on the analogue
signals.
///////////////////////////////////////////////////////////////////////////////
// 0 Antialias filter, downsampler, freq tracking sample rate adjusment,DFT for
//
fundamental voltage
// 1 DFT for 3rd harmonic voltage, 27,59,81,81 off nominal
// 2 DFT for currents 1 & 2, 60, 32
// 3 DFT for currents 3 and neutral V, part 87, 87N, 50N, 50P, 64, 40
// 4 87P DFT Fund and 2nd
// 5 87P, 51N, 51P, AE, 24, 46
// 6 78 outofstep, 21 backup, DFT for Vsync, 25
8.51
RELAYING
// 7 Timers and outputs
///////////////////////////////////////////////////////////////////////////////
Input signals for the GENERATOR function block
Signal
Description
Format
nCB
Circuit Breaker status signal name
Integer (import)
nVT1A
Float (import)
nVT1B
Float (import)
nVT1C
Float (import)
nVT2N
N phase voltage signal name
Float (import)
nVT3A
Sync voltage signal name (A phase)
Float (import)
nCT1A
A1 phase current signal name
Float (import)
nCT1B
B1 phase current signal name
Float (import)
nCT1C
C1 phase current signal name
Float (import)
nCT2A
Float (import)
nCT2B
Float (import)
nCT2C
Float (import)
nCT3A
Float (import)
nCT3B
Float (import)
nCT3C
Float (import)
nCT4N
N4 phase current signal name
Float (import)
nFsig
Frequency Tracking signal name
Float (import)
IN18
External Input for breaker CLOSE
Integer (wire)
IN19
External Input for breaker OPEN
Integer (wire)
Output signals for the GENERATOR function block

Signal
Description
Format
Trip
Integer
8.52
RELAYING
Info1
Relay word bits:

Integer (word)
3 : 87P_A 2nd harmonic block signal
4 : 87P_B 2nd harmonic block signal
5 : 87P_C 2nd harmonic block signal
6 : 87N_1 trip signal
7 : 87N_2 trip signal
8 : 50N trip signal
9 : 51N trip signal
10 : 51N reset signal
11 : 50P trip signal
12 : 51P trip signal
13 : 51P reset signal
14 : 64G_1 trip signal
15 : 64G_2 trip signal
16 : 40_1 trip signal
20 : Accidental Energization trip signal
21 : 24_1 alarm signal
23 : 46_1 alarm signal
31 : LossofPotential alarm signal
8.53
RELAYING
Info2
Relay word bits:

0 : 81of1 trip signal
6 : 78 outer blinder signal
7 : 78 inner blinder signal
8 : 78 Swing signal
9 : 78 Out of Step signal
10 : 78 trip signal
11 : 78 mho signal
12 : 211_AB trip signal
13 : 211_BC trip signal
14 : 211_CA trip signal
15 : 212_AB trip signal
16 : 212_BC trip signal
17 : 212_CA trip signal
18 : Load Encroachment signal
19 : 25 Slip Frequency signal
20 : 25 Minimum Voltage signal
21 : 25 Voltage Difference signal
22 : 25 Angle DIfference signal
23 : 25 Close Sealin signal
24 : 25 Breaker Close signal
25 :
.... (not used)
31 :
Integer (word)
Start
Start signal from any function
Integer
Close
Close signal from synchrocheck func- Integer

tion
Pushbuttons (internal):
Pushbuttons for the GENERATOR function block
PB
Description
Format
81b1
Reset off normal frequency accumulation timer 1
Integer
81b2
Integer
8.54
RELAYING
81b3
Integer
81b4
Integer
81b5
Integer
81b6
Integer
CLOSE
Manual Close of circuit breaker using synchrocheck

function
Integer
OPEN
Manual Close of circuit breaker using synchrocheck

function
Integer

The default signal names of the Monitoring signals for the GENERATOR function
block are shown next, the names can be changed. The maximum length of the signal
name is 8 characters, an optional suffix can be added for a maximum overall length
of 10 characters.
Signal
Description
Format
IAOP
87 A Phase Operating (fund)
Float
IARS
87 A Phase Restraining (fund)
Float
IBOP
87 B Phase Operating (fund)
Float
IBRS
87 B Phase Restraining (fund)
Float
ICOP
87 C Phase Operating (fund)
Float
ICRS
87 C Phase Restraining (fund)
Float
IOMIN
87 Minimum Operating current
Float
IRSMIN_1
87 Minimum Restraining current
Float
IRS2_1
87 Slope1\Slope2 breakpoint
Float
IOHS
87 Operating current High Setting
Float
UFB1AC
81 off nominal frequency Band 1 accumulation timer
Float
UFB2AC
Float
UFB3AC
Float
UFB4AC
Float
UFB5AC
Float
UFB6AC
Float
ZABRE
AB phasephase impedance (re)
Float
ZABIM
AB phasephase impedance (im)
Float
ZBCRE
BC phasephase impedance (re)
Float
ZBCIM
BC phasephase impedance (im)
Float
ZCARE
CA phasephase impedance (re)
Float
ZCIAM
CA phasephase impedance (im)
Float
8.55
RELAYING
VARE
Float
VAIM
Float
VBRE
Float
VBIM
Float
VCRE
Float
VCIM
Float
IARE
Float
IAIM
Float
IBRE
Float
IBIM
Float
ICRE
Float
ICIM
Float
V1ARE
Positive sequence VA phase (re)
Float
V1AIM
Positive sequence VA phase (im)
Float
V1BRE
Positive sequence VB phase (re)
Float
V1BIM
Positive sequence VB phase (im)
Float
V1CRE
Positive sequence VC phase (re)
Float
V1CIM
Positive sequence VC phase (im)
Float
V2ARE
Negative sequence VA phase (re)
Float
V2AIM
Negative sequence VA phase (im)
Float
V2BRE
Negative sequence VB phase (re)
Float
V2BIM
Negative sequence VB phase (im)
Float
V2CRE
Negative sequence VC phase (re)
Float
V2CIM
Negative sequence VC phase (im)
Float
V0RE
Zero sequence V0 (re)
Float
V0IM
Zero sequence V0 (im)
Float
V0RE3
Zero sequence V0 (re) (3rd harmonic)
Float
V0IM3
Zero sequence V0 (im) (3rd harmonic)
Float
VNRE
Neutral Voltage (re)
Float
VNIM
Neutral Voltage (im)
Float
VNRE3
Neutral Voltage (re) (3rd harmonic)
Float
VNIM3
Neutral Voltage (im) (3rd harmonic)
Float
Z1RE
Float
Z1IM
Float
FREQ
Measured Generator Frequency
Float
8.56
RELAYING
DIR
Directional Element
Integer
SYNFREQ
Measured System Sync Frequency
Float
VSARE
System Sync A phaseground voltage (re)
Float
VSAIM
System Sync A phaseground voltage (im)
Float
SLIPT
Slip Frequency Time to Zero degrees from angle limit Float
CLST
Elapsed Slip Frequency Time to Zero degrees from

angle limit when Breaker is asked to CLOSE
Float
Setting Parameters:
Setting parameters for the GENERATOR function block
CONFIGURATION:
Parameter
Range
Default
Unit
Description
iedName
10 character
RTDS
GEN
IED Name
fver
pn64_00
pn64_00
sfx
2 characters
User defined suffix can be added to plot

signal names
eFT
NO, Hz,
Rad/sec
Rad/sec
Enable External Frequency Tracking,

uses an external frequency signal
nFsig
variable
WM1
float
Frequency Input Signal Name
eUT
NO, YES
NO
Enable or Disable Step Up XFMR
ePri
NO, YES
NO
Enable use of Primary Voltage and Current signal names. Scaling is done automatically based upon the ratios
eExtCntrl
NO, YES
NO
Enable or Disable External OPEN/

CLOSE inputs
RELAY ELEMENTS:
Parameter
Range
Default
Unit
Description
freq
60.0, 50.0
60.0
hz
mmva
1e4
100.0
MVA
Rated MVA of the Machine
Vbsll
0.1
13.8
kV
Rated RMS LinetoLine Voltage
TrPlsTmms
50.0
2,000.0
150.0
msec
e87
NO, Gen,
Gen/TRF,
Gen/TRF/
UAT
NO
Enable or Disable Phase Differential
8.57
RELAYING
e87N
NO, YES
NO
Enable or Disable Neutral Differential
e5051N
NO, YES
NO
Enable or Disable Neutral Overcurrent
e64
NO, YES
NO
Enable or Disable 100% Stator Ground
e5051P
NO, YES
NO
Enable or Disable Phase Overcurrent
e40
NO, YES
NO
Enable or Disable LossofField
e32
NO, YES
NO
Enable or Disable Loss of Primc Mover
eAE
NO, YES
NO
Enable or Disable Accidental Energization
e24
NO, YES
NO
Enable or Disable Volts per hertz
e46
NO, YES
NO
Enable or Disable Negative Sequence

Overcurrent
e81
NO, YES
NO
Enable or Disable Frequency Elements
e81of
NO, YES
NO
Enable or Disable OffFrequency
e27
NO, YES
NO
Enable or Disable Undervoltage
e59
NO, YES
NO
Enable or Disable Overvoltage
e78
NO, YES
NO
Enable or Disable OutofStep
e21
NO, YES
NO
Enable or Disable Distance Backup
e25
NO, YES
NO
Enable or Disable Synchrocheck
STEP UP TRANSFORMER:
Parameter
Range
Default
Unit
Description
wdg1kV
1.01000.0
13.8
kV
Transformer Low Side Voltage
YD1
Y, Delta
wdg2kV
1.01000.0
115.0
kV
Transformer High Side Voltage
YD2
Y, Delta
Lead
Lags, Leads
Lags
Delta lags or leads Y
52 BREAKER STATUS:
Parameter
Range
Default
Unit
Description
nCB
variable
CB1
integer
Abit
1 16

status
Bbit
1 16

status
Cbit
1 16

status
8.58
RELAYING
VT 1 VT 3 PARAMETERS:
Parameter
Range
Default
Unit
Description
rVT1
1.010000
120.0
float
Turns Ratio : 1
nVT1A
variable
VA1
nVT1B
variable
VB1
nVT1C
variable
VC1
rVT2
1.010000
100.0
float
Turns Ratio : 1
nVT2N
variable
VN1
N phase Input Signal Name
rVT3
1.010000
100.0
float
Turns Ratio : 1
nVT3A
variable
VS1
Sync Voltage Input Signal Name
CT 1 CT 4 PARAMETERS:
Parameter
Range
Default
Unit
Description
rCT1
1.05000.0
1500.0
float
Turns Ratio : 1
nCT1A
variable
IA1
nCT1B
variable
IB1
nCT1C
variable
IC1
rCT2
1.05000.0
1500.0
float
Turns Ratio : 1
nCT2A
variable
IA2
nCT2B
variable
IB2
nCT2C
variable
IC2
rCT3
1.05000.0
200.0
float
Turns Ratio : 1
nCT3A
variable
IA3
nCT3B
variable
IB3
nCT3C
variable
IC3
rCT4
1.05000.0
100.0
float
Turns Ratio : 1
nCT4N
variable
IN1
N phase Input Signal Name
87P STATOR DIFFERENTIAL ELEMENT:

Parameter
Range
Default
Unit
Description
LoSetB1
0.25 5.00
0.75
amps
IRsB1
2.0 8.0
4.0
HighSetB1
0.1 5.0
1.0
Slope1B1
5.0 50.0
30.0
Slope 1
Slope2B1
35.0 150.0
50.0
Slope 2
8.59
RELAYING
PhStrT
Note1
Note2
5.0 50.0
12.0
2nd Harmonic Blocking
87N STATOR DIFFERENTIAL ELEMENT (low Z grounded):

Parameter
Range
Default
Unit
Description
StrVal87N1
0.5 50.00
1.0
amps
Start Value ( Ineutral >> setpoint)
OpDlTmms 10.0
87N1
500,000.0
50.0
msec
Operate Time Delay
StrVal87N2
0.5
amps
Start Value ( Ineutral >> setpoint)
25.0
msec
Operate Time Delay
0.5 50.00
OpDlTmms 10.0
87N2
500,000.0
100% STATOR GROUND ELEMENT (R and high Z grounded):

Parameter
Range
Default
Unit
Description
StrVal641
0.1 150.00
10.0
volts
Start Value ( Vneutral >> setpoint)
OpDlTmms 10.0
641
500,000.0
500.0
msec
Operate Time Delay
type642
3rd_87,
3rd_27
3rd_87
Type of 3rd harmonic element, can be

a differential or undervoltage type
StrVal642
0.1 20.00
2.5
volts
Start Value ( 3rd Harmonic Vdiff >>

setpoint or Vn_3 << setpoint)
ratio642
0.0 5.00
1.0
OpDlTmms 10.0
642
500,000.0
75.0
Differential Ratio Setting

msec
Operate Time Delay
50/51 NEUTRAL OVERCURRENT ELEMENT (PIOC/PTOC):

Parameter
Range
Default
Unit
Description
e50N
YES, NO
YES
StrVal50N
0.5 50.00
1.0
amps
e51N
YES, NO
YES
IEC_VI
TmACrv51N IEC_STD
IEC_VI
IEC_EI
IEEE_MI
IEEE_VI
IEEE_EI
USER
DEFINITE
8.60
RELAYING
StrVal51N
0.5 50.00
1.0
amps
TmMult51N
0.01 10.00
0.5
OpDlTmms51N
10.0
500,000.0
500.0
msec
Operate Time Delay (TmACrv51N=7)
RsDlTmms5
1N
100.0
500,000.0
850.0
msec
Reset Time Delay (TmACrv51N=7)
pA51N
0.0010
1000.0000
1.0

(TmACrv51N=6) ...
pB51N
0.00 10.00
1.0
pP51N
0.01 10.00
1.0
50/51 PHASE OVERCURRENT ELEMENT (PIOC/PTOC):

Parameter
Range
Default
Unit
Description
e50P
YES, NO
YES
StrVal50P
0.5 50.00
1.0
amps
e51P
YES, NO
YES
eV51
NO
V restraint
V control
NO
Enable Voltage Controlled Time O/C

(PVOC)
TmACrv51P
IEC_STD
IEC_VI
IEC_EI
IEEE_MI
IEEE_VI
IEEE_EI
USER
DEFINITE
IEC_VI
StrVal51P
0.5 50.00
1.0
amps
TmMult51P
0.01 10.00
0.5
OpDlTmms51P
10.0
500,000.0
500.0
msec
Operate Time Delay (TmACrv51P=7)
RsDlTmms5
1P
100.0
500,000.0
850.0
msec
Reset Time Delay (TmACrv51P=7)
pA51P
0.0010
1000.0000
1.0

(TmACrv51P=6) ...
pB51P
0.00 10.00
1.0
pP51P
0.01 10.00
1.0
8.61
RELAYING
40 LOSS OF FIELD EXCITATION ELEMENT:
Parameter
Range
Default
Unit
Description
d40Z1
0.1 100.00
10.0
Zone 1 Mho Diameter (typically 1.0

pu)
o40Z1
50.0 0.0
2.0
Zone 1 Offset (typically Xd/2)
OpDlTmms 0.0
40Z1
500,000.0
0.0
msec
Operate Time Delay
d40Z2
0.1 100.00
15.0
Zone 2 Mho Diameter (typically Xd)
o40Z2
50.0 10.0
2.0
Zone 2 Offset (typically Xd/2)
dir40ang
20.0 0.0
13.00
degrees
Zone 2 Directional Angle (arccos MIN

pf)
StrVal27P40
Z2
0.5 150.00
53.2
volts
Start Value ( Vpos << setpoint)
500.0
msec
Operate Time Delay
OpDlTmms 0.0
40Z2
500,000.0
32 LOSS OF PRIME MOVER ELEMENT:

Parameter
Range
Default
Unit
Description
StrVal32P1
2.0 2.0
0.05
pu
Level 1 ( Power >> setpoint)
OpDlTmms 0.0
32P1
500,000.0
0.0
msec
Operate Time Delay
StrVal32P2
0.02
pu
Level 2 ( Power >> setpoint)
1000.0
msec
Operate Time Delay
2.0 2.0
OpDlTmms 10.0
32P2
500,000.0
ACCIDENTAL ENERGIZATION ELEMENT:

Parameter
Range
Default
Unit
Description
StrVal50Pae
0.5 50.00
1.0
amps
StrVal27ae
0.5 150.00
55.0
volts LL
Start Value ( Vmeas << setpoint)
24 VOLTS PER HERTZ ELEMENT (PVPH):

Parameter
Range
Default
Unit
Description
StrVal24a
1.0 2.0
1.1
pu
Level 1 ( V/Hz >> setpoint)
OpDlTmms 100.0
24a
500,000.0
60000.0
msec
Operate Time Delay
TmACrv24b
DEFINI-
TE
DEFINITE
0.5
1.0
2.0
8.62
RELAYING
StrVal24b
1.0 2.0
1.2
pu
Level 2 ( V/Hz >> setpoint)
OpDlTmms 100.0
24b
500,000.0
6000.0
msec
Operate Time Delay/Time Dial Multiplier
RsDlTmms
24b
1000.0
msec
Reset Time Delay
10.0
500,000.0
46 NEGATIVE SEQUENCE OVERCURRENT ELEMENT (PTOC):

Parameter
Range
Default
Unit
Description
StrVal46a
0.02 1.0
0.08
pu
Level 1 ( Imeas >> setpoint)
OpDlTmms 100.0
46a
500,000.0
5000.0
msec
Operate Time Delay
StrVal46b
0.02 1.0
0.08
pu
Level 2 ( Imeas >> setpoint)
TmMult46b
100.0
500,000.0
10000.0
msec
Operate Time Delay/Time Dial Multiplier
RsDlTmms
46b
10.0
500,000.0
240000.0 msec
Reset Time Delay
81 UNDER/OVER FREQUENCY ELEMENT (PTUF/PTOF):

Parameter
Range
Default
Unit
StrVal27P81
20.0
200.00
33.2
volts LN Undervoltage Block Value ( Minimum

Vmeas phase >> setpoint)
StrVal81a
20.0 70.0
59.1
Hz
Level 1 ( Hz << setpoint)
OpDlTmms 30.0
81a
500,000.0
30.0
msec
Operate Time Delay
StrVal81b
62.0
Hz
Level 2 ( Hz >> setpoint)
100.0
msec
Operate Time Delay
20.0 70.0
OpDlTmms 30.0
81b
500,000.0
Description
81 OFF FREQUENCY ELEMENT (PTUF/PTOF):

Default
Unit
Description
OpDlTmms 0.0
81of
500,000.0
160.0
msec
Operate Time Delay for Accumulator
StrVal81u1
20.0 70.0
59.5
Hz
Band 1 Upper ( Hz << setpoint)
StrVal81l1
20.0 70.0
58.5
Hz
Band 1 Lower ( Hz >> setpoint)
msec
Preset Operational Time Band 1
OpDlTmms 10.0
3600,000 msec
81b1
9,000,000.0 .0
Operational Time Limit Band 1
StrVal81l2
Parameter
Range
PreOpDlTm 0.0
0.0
9,000,000.0
ms81b1
20.0 70.0
57.9
Hz
8.63
RELAYING
PreOpDlTm 0.0
0.0
9,000,000.0
ms81b2
msec
OpDlTmms 10.0
600,000.
81b2
9,000,000.0 0
msec
StrVal81l3
Hz
PreOpDlTm 0.0
0.0
9,000,000.0
ms81b3
msec
OpDlTmms 10.0
120,000.
81b3
9,000,000.0 0
msec
StrVal81l4
Hz
PreOpDlTm 0.0
0.0
9,000,000.0
ms81b4
msec
OpDlTmms 10.0
12,000.0
81b4
9,000,000.0
msec
StrVal81l5
Hz
PreOpDlTm 0.0
0.0
9,000,000.0
ms81b5
msec
OpDlTmms 10.0
2,000.0
81b5
9,000,000.0
msec
StrVal81l6
Hz
PreOpDlTm 0.0
0.0
9,000,000.0
ms81b6
msec
OpDlTmms 10.0
650.0
81b6
9,000,000.0
msec
20.0 70.0
20.0 70.0
20.0 70.0
20.0 70.0
57.4
56.9
56.5
56.0
27 PHASE UNDERVOLTAGE ELEMENT (PTUV):

Parameter
Range
Default
Unit
Description
StrVal27P1
0.5 200.0
59.75
volts
Level 1 ( Vmeas << setpoint)
OpDlTmms 10.0
27P1
500,000.0
1000.0
msec
Operate Time Delay
StrVal27P2
53.12
volts
Level 2 ( Vmeas << setpoint)
5.0
msec
Operate Time Delay, (used for Voltage

Control PTOC no time delay)
0.5 200.0
OpDlTmms 0.0
27P2
500,000.0
59 PHASE OVERVOLTAGE ELEMENT (PTOV):

Parameter
Range
Default
Unit
Description
StrVal59P1
0.5 200.0
73.0
volts
Fundamental ( Vmeas >> setpoint)
OpDlTmms 0.0
59P1
500,000.0
10.0
msec
Operate Time Delay
8.64
RELAYING
StrVal59P2
0.5 200.0
5.0
volts
Negative Sequence ( Vneg >> setpoint)
OpDlTmms 0.0
59P2
500,000.0
5.0
msec
Operate Time Delay
OUTOFSTEP ELEMENT (PPAM):

Parameter
Range
Default
Unit
Description
r78fwd
0.1 500.00
12.0
ohms
Forward Reach Reactance

*(typically 1.52.0 * Xt)
r78rev
0.1 500.00
12.0
ohms
Reverse Reach Reactance

*(typically 2.03.0 * Xd)
ORB78
0.2 500.00
14.0
ohms
Outer Blinder
*(ORB78 > IRB78)
IRB78
0.1 500.00
10.0
ohms
Inner Blinder
OpDlTmms 0.0
78a
500,000.0
50.0
msec
Out of Step Detect Time Delay
OpDlTmms 0.0
78b
500,000.0
0.0
msec
Out of Step OperateTime Delay
OpDlTmms 0.0
78c
500,000.0
1000.0
msec
Out of Step Trip Duration
IP78
0.25
amps
Positive Sequence Current Supervision
0.1 99.99
21 DISTANCE ELEMENTS (PDIS):

Parameter
Range
Default
Unit
Description
D1R
0.020
250.000
6.0
ohms
Zone 1 Reach
D1RR
0.000
25.000
0.0
ohms
Z1A
45.0 90.0
87.18
degrees
Zone 1 Maximum Torque Angle
Z1C
0, 30, +30
degrees
Zone 1 Transformer Compensation

Angle
OpDlTmms 10.0
21a
999,999
200.0
msec
Zone 1 Time Delay
D2R
0.020
250.000
6.0
ohms
Zone 2 Reach
D2RR
0.000
25.000
0.0
ohms
Z2A
45.0 90.0
87.18
degrees
Zone 2 Maximum Torque Angle
Z2C
0, 30, +30
degrees
Zone 2 Transformer Compensation

Angle
8.65
RELAYING
OpDlTmms 10.0
21b
999,999
200.0
msec
Zone 2 Time Delay
elblk
NO, YES
NO
Enable or Disable Load Encroachment
maxload
0.5 3.0
1.2
pu
Maximum Permissible Load
minpf
0.5 1.0
0.8
pu
Minimum Generator Power Factor
25 SYNCHROCHECK ELEMENT:
Parameter
Range
Default
Unit
Description
StrValAdiff
0.0 100.0
10.0
degrees
Maximum Angle Difference
StrValFdiff
0.0 3.0
0.5
Hz
Maximum Slip Frequency
StrValVdiff
0.0 20.0
5.0
Maximum Voltage Difference
FgenH
NO, YES
NO
Generator Frequency >> System Frequency
VgenH
NO, YES
NO
Generator Voltage >> System Voltage
SynComp
0, 30, +30
degrees
Transformer Compensation Angle
StrVal27S1
0.5 200.0
60.00
volts
Minimum Generator Voltage
StrVal27S2
0.5 200.0
60.00
volts
Minimum System Voltage
DeadBus
NO, YES
NO
Enable Dead Bus Synccheck Bypass
StrVal27S3
0.5 200.0
10.00
volts
Dead Bus Undervoltage Check
ebBrkrAdCls
NO, YES
NO
Enable or Disable Breaker Advance

Close Time Compensation
50.0
msec
Breaker Closing Time for breaker advance closing of zero slip
OpDlTmms25 5.0 5,000
60 LOSS OF POTENTIAL ELEMENT:

Introduction:
The loss of potential (60 LOP) element requires no settings and is always enabled.
The 60 LOP supervises the distance, outofstep, stator ground, volts per hertz,
voltage control O/C, and voltage restraint O/C functions.
Description:
The three sequence component currents and positive sequence voltage are used to
determine a loss of potential. Loss of potential is also declared if the positive
sequence voltage is less then 70 % of nominal.
Operation:
negative sequence impedance, zero sequence impedance. The positive sequence
voltage and sequence currents stored once per cycle. The RMS voltage and current
quantities are calculated and compared to the previous cycle measurements. If the
measured voltage is less than 90% of the voltage in the previous cycle and currents
8.66
RELAYING
have not changed by 0.1 amps a timer is started. The timer is also started if the
positive sequence voltage is less than 70% of nominal. A loss of potential condition
is declared after the timer has timed for 0.75 seconds. A loss of potential condition
is reset if the positive sequence voltage is greater than 43% of nominal and the
negative and zero sequence voltages are less than 5.0 volts.
Figure 1: Loss of Potential Logic

87P STATOR DIFFERENTIAL ELEMENT (PBDF):
Introduction:
The differential element is suitable for providing the protection function on the
generator and can include the unit and unitauxiallary transformers.
Description:
The relay provides one 2 slope percentage differential characteristic (87B1), the unit
stepup transformer and unitauxiallary transformer can be included in the
differential zone.
Operation:
The phase currents are fed into the 3 sets CT inputs of the differential function. The
sampled data is adjusted if necessary to compensate for ratio mismatch and phase
shifts. The operating quantity and restraining quantity is calculated for each phase
and applied to the 2 slope differential current characteristic. The transformer
protection element uses an additional measurement ratio of 2nd harmonic over
fundamental to prevent misoperation during transformer energization.
The operating quantity is the vector sum of each phase current, a DFT is used to
extract the fundamental magnitude and for transformer protection the 2nd harmonic
magnitude as well. The restraint quantity is calculated using the summation of every
connected CT current magnitude divided by onehalf.
8.67
RELAYING
The amount of restraint current determines the amount of operating current required
to operate. The operating quantity must be above the minimum operating value
setting or the relay will not operate. If the restraint current increases above the value
of IRSMIN calculated using ( IRSMIN = IOMIN * 1.0Slope1) the amount of operating
current necessary to make the relay operate increases along Slope1. If the restraint
current increases above the slope1\slope2 breakpoint calculated using
( IRS = IRSMIN * IRs) the amount of operating current necessary to make the relay
operate increases along Slope2. If the restraint current increases above the
slope2\high set breakpoint calculated using ( IORS = IRS * 1.0Slope2) the amount of
operating current necessary to make the relay operate does not increase beyond this
breakpoint value times the HiSet PU setting parameter.
I operate
S2\IOH breakpoint
IO High Set
Slope 2
Operate zone
S1\S2 breakpoint
Slope 1
Non operate zone
IOmin
IRsmin
I restraint
Figure 2: Two Slope Percentage Differential

87N STATOR DIFFERENTIAL ELEMENT (PBDF):
Introduction:
The neutral differential element is suitable for providing the ground fault function
on generators solidly grounded and connected with a low resistance to the system
ground.
Description:
The relay provide two elements (87N1 and 87N2), 100% ground fault coverage of
the stator winding cannot be achieved because the elements are current based.
Ground faults beyond the phase current CTs will not be detected.
Operation:
The phase currents and neutral current are fed into the CT inputs of the relay. The
relay calculates the residual current from the phase currents and adjusts if necessary
to compensate for ratio mismatch. The absolute difference between the residual and
neutral current is calculated and compared to the setting thresholds. If the difference
is greater than the thresholds a timer is started and if the difference remains longer
than the time delay the element operates.
8.68
RELAYING
Figure 3: 87N Stator Ground Logic

100% STATOR GROUND ELEMENT:
Introduction:
The 100% stator ground element is suitable for providing the ground fault function
on generators that are high impedance grounded with a high resistance or reactance
to the system ground. High resistance grounding is typically used and limits the
ground fault level to less than 10 amps primary.
Description:
The relay provides two elements (64G1 and 64G2) for 100% sensitivity to ground
faults. 100% coverage for ground faulta in the stator winding is achieved by using
a fundamental neutral overvoltage element and 3rd harmonic differential element.
Measurements of the 3rd harmonic must be done at full load and no load conditions
before setting of this element.
Operation:
The phase voltages and neutral voltage are fed into the VT inputs of the relay. The
relay calculates the 3rd harmonic residual voltage from the phase voltages and
calculates the fudamental and 3rd harmonic voltage from the neutral voltage.
Generators produce harmonics and predominately will produce 3rd harmonic, the
value of this 3rd harmonic and rate of change will vary depending on machine
construction and loading. The 3rd harmonic behaves like zerosequence and does
not pass through the transformer wyegrounded winding.
The 64G1 element uses the voltage produced across the generator neutral impedance,
this voltage is proprtional to the location of the fault in the winding. Faults from
100% down to 510% of the winding can be detected by measuring the fudamental
neutral voltage. The neutral voltage is calculated and compared to the setting
threshold. If the voltage is greater than the threshold a timer is started and if the
threshold is exceeded longer than the time delay the element operates. The
capacitive coupling between the primary and secondary winding of the unit
transformer may cause this element to operate for primary line to ground faults (3).
The time delay of this element should be coordinated with the primary fault clearing
times.
The 64G2 element by default uses the 3rd harmonic voltage measured at the neutral
point and the 3rd harmonic zero sequence voltage measured at the generator
8.69
RELAYING
terminals. The ratio of neutraltoterminal 3rd harmonic voltage is generally
constant with varying loads and a differential scheme can provide coverage near the
bottom of the winding. NOTE: The following steps must be completed before setting
this element.
1. Start the simulation and operate the generator at 0% load, then measure the 3rd
harmonic voltages from the neutral and terminal points using the monitoring from
the relay.
You can use the vector display in runtime or use the
rtds_sharc_ctl_RI2MA component to calculate the magnitude.
1. 1 3rd harmonic Terminal Voltage at 0% load = _________ volts
1. 2 3rd harmonic Neutral Voltage at 0% load = __________ volts
2. Operate the generator at 100% load and record the 3rd harmonic voltages.
2. 1 3rd harmonic Terminal Voltage at 100% load = _________ volts
3. Calculate the setting parameter ratio642 by adding the two neutral voltage
readings together and then adding the two terminal voltage readings together. The
sum of the neutral measurements is then divided by the sum of the terminal
measurements.
ratio642 = ( 1.2meas + 2.2meas ) / ( 1.1meas + 2.1meas )
ratio642 = _______________
4. Calculate the setting parameter StrVal642 using the following equation.
StrVal642 = 1.1 *( 0.1 + |ratio642*2.1meas 2.2meas| )
StrVal642 = __________ volts
5. Calculate the % of winding coverage when the machine is operated at 0% load.
This value should be greater than 15 %.
64G2min= ratio642 ratio642+1 StrVal642 ratio642+1 * 1.1meas + 1.2meas
64G2min= _____________%
6. Calculate the setting parameter StrVal641 to provide 95% winding coverage
with the 64G1 element using the following equation. If 64G2min is at least 15% an
overlap of 10% will be achieved with StrVal641 providing 95% winding coverage.
StrVal641 = (0.05 )*( Vbsll*577.35/rVT2)
StrVal641 = __________ volts
The 64G2 element can use the 3rd harmonic voltage measured at the neutral point
in an undervoltage scheme. NOTE: The following steps must be completed before
setting this element.
1. Start the simulation and operate the generator at 0% load, then measure the 3rd
harmonic voltages from the neutral point using the monitoring from the relay. You
can use the vector display in runtime or use the rtds_sharc_ctl_RI2MA component
to calculate the magnitude.
8.70
RELAYING
2. Calculate the setting parameter StrVal642 using the following equation.
StrVal642 = 0.5 * 1.1meas
StrVal642 = __________ volts
3. Calculate the setting parameter StrVal641 to provide 95% winding coverage
with the 64G1 element using the following equation.
StrVal641 = (0.05 )*( Vbsll*577.35/rVT2)
StrVal641 = __________ volts
Figure 4: 100% Stator Ground Logic

NEUTRAL OVERCURRENT ELEMENT:
Introduction:
The neutral overcurrent element is suitable for providing the backup ground fault
function on generators that are wyeconnected to the system ground.
Description:
The relay provides two elements (50N and 51N) to provide instantaneous and inverse
time characteristic for ground faults.
Operation:
The relay calculates the neutral current from the neutral connected CT and uses this
value for the protection elements. This element may not be suitable for high
impedance grounded or ungrounded generators. Because the ground current is
essentially the same for multiple units connected to a common bus this element can
only provide nonselective backup protection (3).
If the neutral current is above the StrVal50N setting the 50N element operates
without an intentional delay.
8.71
RELAYING
If the neutral current is above the StrVal51N setting the 51N element operates with
an intentional delay.
PHASE OVERCURRENT ELEMENT:
Introduction:
The phase overcurrent element is suitable for providing backup fault functions on
generators.
Description:
The relay provides two elements (50P and 51P) to provide instantaneous and inverse
time characteristic for faults. This element is normally used for small to medium
generators while the distance element is used on larger generators.
Operation:
The relay calculates the maximum phase current from the phase connected CT and
uses this value for the protection elements..
If the maximum phase current is above the StrVal50P setting the 50P element
operates without an intentional delay.
If the maximum phase current is above the StrVal51P setting the 51P element
operates with an intentional delay as long as there is no 60 LOP condition. An
additional setting eV51 allows this element to voltage controlled or voltage
restrained and is normally set to coordinate with the primary protection.
A voltage controlled O/C element is prevented from operating until the system
voltage is reduced to some value, typically at 80% of nominal.
A voltage restrained O/C element reduces the StrVal51P setting automatically as
the faulted voltage is reduced. The setting reduction is limited between 0.25 and 1.0
pu of the origirnal setting.
Time Curve Parameters:
Characteristic
TR
IEC Standard Inverse
0.14
0.0
0.02
4.85
IEC Very Inverse
13.5
0.0
1.0
21.6
IEC Extremely Inverse
80.0
0.0
2.0
29.1
IEEE Moderately Inverse 0.0103
0.0228
0.02
0.97
IEEE Very Inverse
3.922
0.0982
2.0
4.32
IEEE Extremely Inverse
5.64
0.0243
2.0
5.82
The time required to operate for various inverse time curve characteristics is
calculated using equation 1.
A
t P TMS B
p
I
IP
8.72
RELAYING
Equation1: Inverse Characteristic Operate Time
The time for the disk to reset to the rest position is calculated using equation 2.
tr
TR
2
I
1
IP
Equation2: Inverse Characteristic ResetTime

51V Pickup
(per unit of StrVal51P)
1.0
0.5
0.25
0.25
0.5
1.0
V fault
Figure 5: 51V Voltage Restraint Characteristic

LOSS OF FIELD EXCITATION ELEMENT:
Introduction:
The 40 Loss of Field Excitation element is suitable for providing the backup function
to the generator excitation controls.
Description:
The relay provides two offset mho elements (40Z1 and 40Z2) to provide excellent
high speed detection of loss of excitation. This method was first introduced in 1949
(1) by C.R. Mason and is widely used in some form or another in most generator
protection relays.
Operation:
The relay calculates the positive sequence impedance from the phase connected CTs
and VTs and uses this value for the protection elements.
Generators are normally operated at a slightly lagging power factor (p.f.) thus the
normal stable operation is in the 1st quadrant. The excitation field is adjusted for
normal stable operation, but when the excitation field is lost the generator must
absorb reactive power. When reactive power is absorbed by a synchronous generator
the operation is in the 4th quadrant, this area of operation is unstable and should be
avoided. When there is no excitation field and the system can sustain the voltage and
8.73
RELAYING
provide the necessary reactive power the machine will act as an induction generator,
otherwise loss of synchronism will occur. Overheating will also occur and can
damage the machine if this condition is not corrected.
+jQ Inductive Reactive into System

II
I
I Lag
+P Real Power
into System
I Lead
III
I Loss of Field
IV
jQ Capcitive Reactive into System
Figure 6: Synchronous Machine Operating Characteristic

Generators will have curves that show the capability of the machine during
overexcitation and underexcitation operation. Three capabilty curves will define
the thermal limits of the machine. These curves are the overheating limits of the rotor
windings, stator windings, and the stator iron. An additional limit is the steadystate
stability limit (SSSL) of the machine. A fifth curve will be defined by the minimum
excitation limit. Typical curves are shown in figure 7.
Reactive Power into System
+ MVAR
Rotor Winding Limit
Stator Winding Limit
Real Power into System

Minimum Excitation Limit
MVAR
Steady State Stability Limit

Stator Iron End Limit
Reactive Power into Generator
Figure 7: Synchronous Machine Capability Curves

The SSSL can be defined by the arc of an offset circle where the center and radius
is calculated with equations 3 and 4 where V is the generator LN voltage, Xs is the
total equivalent system impedance, and Xd is the unsaturated reactance.
8.74
RELAYING
1
1
1
Centeroffset V 2 (
)va
2
Xd Xs
Equation3: Center offset of SSSL curve
1
1
1
Radius V 2 (
)va
2
Xd Xs
Equation4:Radius of SSSL curve

The SSSL power curves need to be converted to secondary ohms to help set the relay,
but typically the relay Zone 1 is set with a diameter of 1.0 pu and offset from the orgin
to about 50% to 75% of the generator transient reactance Xd. This setting will
provide protection for complete loss of excitation. The operation of Zone 1 can be
time delayed or instantaneous with delays normally less than 200 msec.
d 40 Z 1
(vbsll *1e3) 2
mmva *1e6
d40Z1= __________ ohms

o 40 Z 1
Xd '
2.0 1.3333
o40Z1= __________ ohms

Negative Zone 2 Offset Operation:
To provide low excitation and parital loss of excitation the Zone 2 element is set with
a larger diameter but still typically offset from the orgin to about 50% to 75% of the
generator transient reactance Xd. Zone 2 diameter is typically set with a diameter
equal to the generator direct axis unsaturated reactance Xd. The operation of Zone
2 is time delayed to provide security against stable swings, the default is 0.5 seconds
or set according the manufacturers recommendation (2).
d 40 Z 2 Xd
d40Z2= __________ ohms

o 40 Z 2
Xd '
2.0 1.3333
o40Z2= __________ ohms

OpDlTmms40Z1= 0.05 seconds
8.75
RELAYING
Xd ' '
2 .0
Zone 1
d40Z1=1.0 pu
d40Z2=Xd
Zone 2
Figure 8: Loss of Field Operating Characteristic (Zone2 Negative Offset)

Positive Zone 2 Offset Operation:
Many loss of field relays now use a positive offset for Zone 2 which includes the
stepup transformer reactance, a directional element is used to block this zone under
normal operation, stable transient swings, and nearby faults (3). Zone 1 time delay
in this scheme is typically set for 0.20.3 seconds. Operation of the Zone 2 will be
time delayed typically 1.0 seconds, but will be accelerated if the system voltage drops
below a setpoint. The voltage element is typically set to operate below 87% nominal
for multimachine busses and 80% of nominal for single machine busses. This relay
will use the Zone 1 time delay setting for accelerated tripping, typically set to 0.25
seconds. The offset for Zone 1 is normally set to onehalf the generator transient
reactance, but the diameter is set differently than before. The directional unit is
typically set to the arccosine of the minimum rated power factor.
d 40 Z 1 1.1 * Xd
Xd '
0 .5
d40Z1 = __________ ohms

o 40 Z 1
Xd '
2 .0
o40Z1= __________ ohms

d 40 Z 2 1.1 * Xd Xt
d40Z2 = __________ ohms

o 40 Z 2 Xt
8.76
RELAYING
o40Z2 = __________ ohms
dir40ang = __________ deg ( typically min rated PF )
StrVal27P40Z2 = __________ volts ( 8087% of Vnom )
X
o40Z2=Xt
R
d40Z2=1.1*Xd + Xt
o40Z1= 0.5Xd
dir40ang
Zone 2
Zone 1
d40Z1=1.1*Xd 0.5Xd
Figure 9: Loss of Field Operating Characteristic (Zone2 Positive Offset)

32 LOSS OF PRIME MOVER:
Introduction:
The loss of prime mover element is suitable for providing the reverse power function
on generators connected to the system.
Description:
Two elements (32P1 and 32P2) are used to provide more or less sensitivity to reverse
or low power flow. When a synchrounous generator is connected to the system with
the field excited, power is produced from the torque supplied by the prime mover.
If the prime mover is removed the system will drive the unit as a synchronous motor.
The motoring of a steam turbine causes overheating and damage to the turbine
blades.
Operation:
The relay calculates the instantaneous value of power from the phase connected CT
and VT and uses this value for the protection elements.
The instantaneous value of power is compared to the setting thresholds. If the
measured value is greater than the thresholds a timer is started and if the threshold
is exceeded longer than the time delay the element operates.
Steam turbine and hydro turbine units require small amounts of reverse power to spin
the unit at synchrounous speed with no prime mover. Typical values of reverse power
are shown in percentage of nameplate ratings.
8.77
RELAYING
Steam turbines, condensing types
13%
Steam turbines, noncondensing types
3+%
Hydro turbines
0.2 2+%
Gas turbines
50+%
Setting this element requires consultation of the manufacturers nameplate ratings

and recommendations (4).
pu Motoring Power = Rated Motoring Power / Generator Rated Power
StrVal32P1 = __________ pu (typically (0.7 to 0.5) * (pu Motoring Power))
Set the time delay according to the manufacturers recommendation or between 20.0
to 30.0 seconds to prevent tripping during machine paralleling operations.
The level 2 element can be set to detect low forward power or overload conditions
by setting a positive value for Strval32P2.
Figure 10: Loss of Prime Mover Logic

ACCIDENTAL ENERGIZATION:
Introduction:
The accidental energization element is suitable for providing a backup function to
the reverse power function on generators.
Description:
The relay provides one element for accidental energization detection. Generators
can be damaged when improperly connected to the power system by closing the
breaker without properly starting or stopping the unit.
Operation:
The phasephase voltages are compared to the setting threshold if all 3 voltages are
less than the threshold the element is armed after 5.0 seconds. If any phasephase
voltage goes above the threshold the arming condition will reset. A time delay
dropout of 0.25 seconds will occur if the element was previously armed (5). The
maximum phase current is compared to the threshold and if the element is armed the
protection element will operate.
8.78
RELAYING
Figure 11: Accidental Energization Logic

24 VOLTS PER HERTZ (PVPH):
Introduction:
The volts per hertz element is suitable for providing overexcitation detection on
generators.
Description:
The relay provides two elements for volts per hertz detection, the first element
normally alarms and the second element trips. Generators can be damaged when
improperly connected to the power system by closing the breaker without properly
starting or stopping the unit.
Operation:
Generators are normally operated near the knee point of their saturation curve, the
field excitation control system provides the correct excitation current for the required
load. Overvoltage conditions cause the magnetic core to saturate disrupting the
normal flux pattern, overheating and damge to the generator will occur. The 60 LOP
element blocks this function during loss of potential conditions.
The relay uses the maximum phase voltage and calculates the ratio of volts per hertz
and compares this to the setting thresholds. If the thresholds are exceded longer than
the time delay the element operates. The first element uses a definite time delay
while the second element can be a definite time delay or inverse time characteristic.
The second element has a linear reset curve that can be set to match the cooling
characteristic of the machine (5).
To properly set this element the Manufacturers Overexcitation Generator Limit
Curve is required and Stepup Transfomer Overexcitation Limit Curve. A typical
2 level definite time delay scheme will alarm at 1.1 pu in about 60 seconds and trip
at 1.2 pu in about 6 seconds.
StrVal24a = __________ pu ( 110% of V/Hz )
OpDlTmms24a= 60.0 seconds
StrVal24b = __________ pu ( 120% of V/Hz )
OpDlTmms24b= 6.0 seconds
RsDlTmms24b = 10.0 seconds
8.79
RELAYING
The reset operation of the level 2 timer is a linear function based on ratio of operate
time versus reset time setting. This ratio is dynamically calculated and applied to the
level 2 timer when the element drops out (vhz_rr = t24op / rstime24b). The level 2
timer can be configured to operate for an inverse time characteristic:
TimeCurveA
TDM
2
VperHz
1
Pickup
sec onds
Inverse Curve A
1000
Time to Trip in Seconds
100
10
10 TDM
3
1
1
1.2
1.4
1.6
1.8
1
0.3
0.1
0.1
0.01
Multiple of V/Hz Pickup
Figure 12: Inverse Time Curve A

TimeCurveB
TDM
sec onds
VperHz
1
Pickup
Inverse Curve B
10000
1000
100
10 TDM
10
3
1
1
1
1.2
1.4
1.6
1.8
0.3
0.1
0.1
Figure 13: Inverse Time Curve B

TimeCurveC
TDM
VperHz
Pickup
0.5
sec onds
Inverse Curve C
1
10000
1000
100
10 TDM
10
3
1
0.3
1
1.2
1.4
1.6
1.8
2
0.1
0.1
Figure 14: Inverse Time Curve C

8.80
RELAYING
46 NEGATIVE SEQUENCE OVERCURRENT (PTOC):
Introduction:
The negative sequence overcurrent element is suitable for providing unbalance
detection on generators for alarm and tripping.
Description:
The relay provides two elements for unbalance detection, the first element normally
alarms and the second element trips. IEEE Standard C50.13:1977 defined the ability
of generators to withstand unbalance conditions in terms of negative sequence for
continuous and short term operation. Negative sequence crosses the air gap and
flows in the rotor or field as doublefrequency current. The current flows in the
surface of the rotor and through the retaining rings and rotor forging wedges and
causes heating. The generator will be severly damaged if the oveheating condition
exceeds the thermal limits.
Operation:
The continous withstand currents are between 5 10% and are dependant on machine
construction.
Type of Generator
Permissible I2 % Inom
Salient Pole
With connected amortisseur windings
With nonconnected amortisseur windings
10 %
5%
Cylindrical Rotor
Indirectly cooled
Directly cooled up to 960 MVA
961 to 1200 MVA
1201 to 1500 MVA
10 %
8%
6%
5%
Set the level 1 pickup equal to or slightly greater than the generators continous
withstand limit. Set the delay longer than the maximum system fault clearing time
to prevent nuisance alarms during normal fault clearing.
StrVal46a = __________ pu
OpDlTmms46a= 5.0 seconds
The level 2 element is used to protect the machine for the short withstand limit and
uses an inverse time curve to operate and reset.
The thermal limits are based upon the following equation where:
K I 22 t
Equation5: Negative Sequence Short Withstand Limit

K = constant established by generator design
8.81
RELAYING
t = time in seconds
I2 = RMS value of negative sequence current in p.u.
Typical values of K for older turbine generators are 30 40, but large generators can
have a K value of 5 10.
Set the level 2 pickup greater than the generators continous withstand limit. Set the
delay equal to the generators short time withstand constant.
The reset operation of the level 2 timer is a linear function based on ratio of operate
time versus reset time setting. This ratio is dynamically calculated and applied to the
level 2 timer when the element drops out (rr_46b = t46op / rstime46b). The operate
time is limited to a maximum of 1000 seconds and a minimum of 0.1 seconds.
StrVal46b = __________ pu
TmMult46b = __________
RsDlTmms46b = 240.0 seconds
46time
K
I 2
Ino min al
sec onds
46 Inverse Curve
10000.00
1000.00
100.00
10.00
0.01
0.10
1.00
1.00
10.00
0.10
100.00
100 K
75
50
40
30
20
10
5
2
0.01
I2 percentage of Inominal
Figure 15: Negative Sequence Time Curve

81 UNDER/OVERFREQUENCY (PTUF/PTOF):
Introduction:
The frequency element is suitable for providing under and overfrequency detection
on generators for tripping.
Description:
The relay provides two elements for over/underfrequency detection, the first element
is normally set for underfrequency and the second element for overfrequency.
Underfrequency conditions occur when the generator cant supply the necessary
load. The system voltage drops and the excitation will increase which causes
heating.
Operation:
The relay calculates the system frequency from the positive sequence voltage or will
use an external frequency signal such as the speed signal from the generator or some
form of PLL, etc. When the frequency exceeds the setting threshold a timer is started,
if the threshold exceeds the time delay setting the relay operates.
8.82
RELAYING
Figure 16: Frequency Element Logic

81 OFFFREQUENCY ACCUMULATION TIMERS (PTUF/PTOF):
Introduction:
The offfrequency element is suitable for providing underfrequency operation
accumulation timers for six bands of operation on generators according to IEEE
C37.106: 1987 Guide For Abnormal Frequency Protection for Power Generating
Plants, Steam Turbine Protection Scheme I.
Description:
Steam turbine blades are designed for continous operation under load at the rated
frequency. When the blades rotate operate under load at off nominal frequencies
metal fatigue occurs. This metal fatigue is cumulative and is permanent, operation
beyond the design limits of the machine can result in damage. The relay provides six
elements for offfrequency accumulation, the accumulation timers can be preset to
nonzero time for used turbines, the default is 0.0. The accumulation timers can also
be reset in Runtime with an individual pushbutton to the values of the preset, if no
preset is desired leave the presets to 0.0.
Operation:
The system frequency is measured and if the frequency is within a frequency band
a start timer begins timing. If the start timer threshold is exceeded the band
accumulation timer starts the relay alarms. The start timer is used to wait until the
system frequency stabilizes within a frequnecy band, IEEE recommends a setting of
10 cycles. If the accumulation timer exceeds the operational threshold limit for a
band the relay trips. The turbine manufacturers abnormal frequency operational
limits are needed to properly set this protection.
The accumulation timers are only allowed to operate when the generator is online and
the system frequency can be measured. The generator is online when the circuit
breaker is closed and there is no 27P1 operation.
8.83
RELAYING
Figure 17: OffFrequency Element Logic

27 UNDERVOLTAGE ELEMENT (PTUV):
Introduction:
The undervoltage element is suitable for providing detection of undervoltage
conditions.
Description:
The relay provides two elements for undervoltage detection with time delayed
operation. Undervoltage conditions are usually the result of a slow or improperly
cleared faults. Islanding of a system can also create undervoltage conditions if the
remaining generation can not support the load demand.
Operation:
The minimum phase voltage is chosen and compared to the setting thresholds. the
first element is normally set for 90 95% of nominal voltage with a time delay of
about 1 second. The second element is normally set for 80% of nominal voltage with
8.84
RELAYING
a quicker time delay. This 2nd element setting is also used for the voltage controlled
overcurrent element supervision, there is no intentional delay for the overcurrent
element supervision.
Figure 18: Undervoltage Element Logic

59 OVERVOLTAGE ELEMENT (PTOV):
Introduction:
The overvoltage element is suitable for providing detection of overvoltage
conditions and provding backup protection.
Description:
The relay provides two elements for overvoltage detection with time delayed
operation. Overvoltage conditions are usually the result of a sudden loss of load.
Small overvoltages cause large increases in excitation current and cause overheating.
Generators are designed to operate at small percentages of overvoltage but have
limited operational range at higher percentages of overvoltage (3).
105%
Continous
110%
30 min
115%
5 min
125%
2 min
Operation:
The maximum phase voltage is chosen and compared to the first threshold, the
negative sequence voltage is compared to the second threshold. The first element is
normally set for 106 110% of nominal voltage without any intentional time delay.
The second element detects negative voltages and should be coordinated with the
primary protection elements.
8.85
RELAYING
Figure 19: Overvoltage Element Logic
78 OUTOFSTEP ELEMENT (PPAM):
Introduction:
The outofstep element is suitable for providing detection of out of step (OOS)
conditions which cause the system electrical center to move into the unit transformer
and generator (3).
Description:
Sources that are connected together in an electrical power system normally operate
in synchronism resulting in normal stresses and power flow for the generators.
System conditions may cause the voltages of the sources to start swinging apart and
cause the system to become unstable. These unstable conditions result in large
currents and high torque on the shafts with damage to the generator and unit stepup
transformer. The out of step element is the primary protection element for these
conditions and is used to limit damage to the equipment.
Operation:
Outofstep conditions are different than short circuit conditions, the impedance
moves relatively slow during power swings but will move from the load point to the
fault point very fast during faults. The double blinder scheme consists of a mho
element, right and left blinder pairs, current supervision, and timers to detect the out
of step condition. The positive sequence impedance trajectory is used to detect the
electrical center moving into the machine or unit transformer. The rate of change
between two impedance measurements (blinders) detects the swing condition. As
the impedance moves past the inner blinder and enters into the mho the element
latches, the OOS tripping occurs when the impedance exits the mho the relay.
ORB78
IRB78
IRB78
ORB78
r78rev
r78fwd
InnerBlinder OuterBlinder
Figure 20: OutofStep Double Blinder Characteristic

Outofstep trip condition happens when:
1 Positive sequence impedance stays between ORB78 and IRB78 for
longer than OpDlTmms78a. The outofstep swing is declared.
8.86
RELAYING
2 Positive sequence impedance moves beyond IRB78 and further into the
mho characteristic diameter formed by r78rev and r78fwd settings. The
outofstep is sealed in.
3 Positive sequence impedance exits the mho charateristic.
outofstep tripping occurs.
Electrical Center
The
X B
r78rev
Zs
Xt
R
S
Xd
Z1
Z2
RAngle2
A
RAngle1=120
ORB78
IRB78
r78fwd
IRB78
ORB78
Figure 21:Double Blinder Typical Settings

The generator transient reactance (Xd), unit transformer reactance (Xt), system
impedance (ZS), and outofstep slip frequency is necessary to properly set this
element. A transient stability study is required to determine the outofstep slip
frequency due to the system specific nature of this variable. Figure 21: shows the
reccommeded settings for the double blinder settings (4).
Normally set the forward reach to 23times the generator transient reactance and the
reverse reach to 1.52 times the transformer reactance.
r 78 fwd 2 3 * Xd '
r78fwd = __________ ohms

r 78 rev 1.5 2 * Xt
r78fwd = __________ ohms

The inner blinder setting is set to detect all outofstep conditions. The angle of
separation between two sources is used to calculate the inner blinder setting. When
the angle of seperation exceeds 120 degrees normally the two sources will lose
synchronism. For example if the total impedance from AB was 20 ohms at 88
degrees, Z1 would be calculated by finding the hypotenuse of the right angle triangle
formed by 1/2 of ZAB = 10 and the opposite side value of the cot of 60 degrees * 10.0.
The square root of the opposite and adjacent sides is Z1 = 11.547 at 58 degrees.
Therefore the inner blinder would be 11.547 * cos 58 = 6.119 ohms.
IRB78 = __________ ohms
8.87
RELAYING
The outer blinder setting must be inside the maximum load with some safety margin
and must lie outside of the mho characteristic. If we seperate the outer blinder 70
degrees from the inner blinder, Rangle2 is 50 degrees. Z2 would be calculated by
finding the hypotenuse of the right angle triangle formed by 1/2 of ZAB = 10 and the
opposite side value of the cot of 25 degrees * 10.0. The square root of the opposite
and adjacent sides is Z2 = 21.445 at 23 degrees. Therefore the outer blinder would
be 21.445 * cos 23 = 19.74 ohms.
ORB78 = __________ ohms
The time to travel from the outer to inner blinder is determined by the maximum slip
frequency of the system and is calculated with the following equation (6). If the
maximum slip frequency has been determined to be 5 Hz, the time would be 2.333
cycles on a 60 Hz base. Setting the time delay to 2 cycles or 0.34 seconds will ensure
the maximum slip frequency can be detected.
Time
( Rangle1 Rangle 2) * Fnom ( Hz )

cycles
360 * Fslip ( Hz )
Equation6: Travel Time Between Double Blinder

OpDlTmms78a = __________ seconds
Figure 22: OutOfStep Element Logic

21 BACKUP DISTANCE ELEMENT (PDIS):
Introduction:
The distance element is suitable for providing detection of phase to phase and 3 phase
system faults.
Description:
Two zones of phase mho distance elements with forward reach, reverse reach,
stepup transformer compensation, and definite time delays are provided. This
8.88
RELAYING
element is normally used for large generators while the phase overcurrent element
is used on smaller to medium generators. The element uses the phase currents from
the CT connected to the generator terminals therefore to look into the generator the
reverse reach must be set. Because the VTs are normally connected to the generator
terminals the elements must be compensated to reach into the system beyond the unit
stepup transformer. Zone 1 normally reaches into the stepup transformer with a
short time delay, this will enable backup protection for low side transformer winding
and bushing phase to phase faults. Zone 2 would normally be set to reach through
the stepup transformer and out into the system with a longer time delay.
Operation:
For operation without transformer compensation the relays uses the instantaneous
phasephase voltages and currents for the mho characteristic calculations. For
operation where the elements will reach through a deltawye step up transformer the
relay will compensate based on the Z1C and Z2C settings. When the
transformer delta lags the wye set the compensation to 30 deg, and when the delta
leads set the compensation to +30 deg. The elements are blocked during 60 LOP
conditions.
30 deg
+30 deg
AB
AB_21P = Ib
VAB_21P = Vab Vbc
BC
IBC_21P = Ic
VBC_21P = Vbc Vca
CA
ICA_21P = Ia
VCA_21P = Vca Vab
AB
IAB_21P = Ia
VAB_21P = Vab Vca
BC
IBC_21P = Ib
VBC_21P = Vbc Vab
CA
ICA_21P = Ic
VCA_21P = Vca Vbc
Set the forward reach to include the transformer impedance and impedance into the
system where you want to reach to.
Set the reverse reach equal to at least the generator transient reactance Xd.
X
D2R
Zone2
Distance Element Blocked
D1R
Acos(minpf)
Z2A
Zone1
Z1A
D2RR
D1RR
Acos(minpf)
Zbase*maxload (ohms secondary)
8.89
RELAYING
Figure 23: Distance Element Characteristic
If the distance elements reach into the load area a load encroachment function may
be enabled to block the distance elements during heavy load conditions. Set the
maximum permissible load maxload to a value in p.u., and set the minimum power
factor minpf to the generators minimum power factor. An area above and below
the R axis bounded by the power factor angle and maximum positive sequence
impedance will prevent the distance element from operating.
Figure 24: Distance Element Logic

Introduction:
The synchrocheck element is suitable for providing the supervision of closing the
generator circuit breaker onto the power system.
Description:
Synchrocheckverifies that the voltages on the two sides of the supervised generator
circuit breaker are within set limits of magnitude, angle and frequency differences.
When two voltages are at different frequencies seperated by the circuit breaker the
voltage difference across the breaker contacts changes from a minimum to a
maximum as the two voltages slip in and out of phase with respect to each other.
When the two voltages are nearly equal in magnitude the voltage across the open
breaker will be near zero when the system become in phase, resulting in zero angle
8.90
RELAYING
difference between the voltages. As the system slip out of phase the voltage
difference and angle difference increase with the maximum when the systems are
180 degrees apart. The time that the two voltages stay within an angle above and
below the in phase 0.0 degree condition is:
Time
1
360
* Fslip ( Hz )
2 x
sec onds
Equation7: Travel Time Between Angle Limit

where phase angle difference is in degrees; and slip frequency difference is in Hz,
the time to zero degrees would be 1/2 of the time calculated.
Slip Frequency > 0.0Hz
Slip Frequency < 0.0Hz
V System
StrValAdiff
StrValAdiff
V Generator
270
90
180
Figure 25: Synchrocheck Element Angle Check

Operation:
The relay calculates the frequency, magnitude, and angle of the generator voltage and
system voltage. The synchrocheck logic supervises the closure of the open circuit
breaker and provides a close pulse to the breaker control, an internal push button is
used to manually CLOSE and OPEN the circuit breaker in runtime. The element
adjusts for the phase shift in voltages across a deltawye connected stepup
transformer.
If the synchronization voltage is phase shifted due to stepup transfomer the relay
will compensate out the phase shift when the setting SyncComp is used. If the low
side delta lags the system voltage by 30 degrees, set this to 30. If the low side delta
leads the system voltage by 30 degrees, set this to +30.
The frequency difference is compared to the setting parameter StrValFdiff to
determine if the slip frequency is within the limit. The logic can also be set to ensure
that the generator frequency is higher than the system frequency.
The voltage magnitude of the generator and system is compared to the setting
parameters StrVal27S1 and StrVal27S2 to determine if there is sufficient voltage
to operate the element.
8.91
RELAYING
The voltage difference is compared to the setting parameter StrValVdiff to
determine if the voltage across the open breaker is within the limit. The logic can
also be set to ensure that the generator voltage is higher than the system voltage.
The angle difference is compared to the setting parameter StrValAdiff to determine
if the angle difference between the two voltages is within the limit.
The synchrocheck element can be enabled to operate if the system voltage is
Dead. The system voltage is compared to the setting parameter StrVal27S3 to
determine if the bus voltage is below a certain level. If the system voltage is below
this setting the bus is considered denergized therefore the synchrocheck logic is
bypassed to allow the circuit breaker to be closed.
The synchrocheck element seals in the CLOSE command and waits for the element
checks to be satisfied before the relays issues the output. The sealin is reset when
the output is asserted or when the OPEN command is issued.
8.92
RELAYING
Figure 26: Synchrocheck Element Logic
The logic can also be set to ensure that the generator breaker is closed at exactly zero
slip by calculating the time to close the breaker in advance of zero degrees as shown
in figure 25. The setting parameter OpDlTmms25 is used when the breaker
advance closing is enabled. The time to reach 0 degrees from the setting
StrValAdiff is calcuated and then used to determine the time to CLOSE the breaker.
A timer is started when the angle difference is within the limit and increase as the
angle decreases towards 0. If the time required to close the breaker is within the time
to reach 0 degrees the breaker can be closed, if not the relay sets the monitored signal
CLST to 9999999.0 or the elapsed time to the breaker CLOSE command will be
displayed. The time to reach zero degrees can also be monitored and is called
SLIPT, the difference of these two signals will be the breaker advance closing time
setting parameter OpDlTmms25. In the following figure 27 the 1st plot shows the
generator voltage and system sync voltage, the 2nd plot shows the CLOSE signal and
50 ms later the breaker closes. The third plot shows the voltage difference across the
open circuit breaker and it shows the voltage approach zero as the two voltages slip
into synchronisim, the breaker is closed at zero degrees.
MACVA1 N-30
20
V
k
-20
CLOSE
BRK1
Vdiff
1
-1
1.28215
1.33045
1.37875
1.42704
1.47534
Figure 27: Synchrocheck Breaker Advance Close Plot
8.93
RELAYING
REFERENCES:
1. C.R. Mason, A new Loss of Excitation Relay for Synchronous Generators,
AIEE Trans., vol. 68, pp. 12401245, 1949.
2. John Berdy, Loss of Excitation Protection for Modern Synchronous Generators,
IEEE Trans., vol. PAS94, No.5, pp. 14571463, 1975.
3. J.Lewis Blackburn, Protective Relaying Principles and Applications 2nd
Edition, Marcel Dekker Inc., Chapter 8, Generator Protection, pp. 231273, 1998.
4. SEL, 300G User Manual, SEL Inc., Chapter 2, Relay Element Settings, pp.
1107, 20070706.
5. GE Multilin, G60 User Manual GEK113415, GE Multilin, Chapter 5, Settings,
pp. 1192, 2007.
6. IEEE/PSRC, Power Swing and OutofStep Considerations on Transmission
Lines, IEEE/PSRC WG D6, pp. 159, 20050719.
Execution Time
GPC
4.100
us
8.94
Rev. 03: December 09
8A
MULTIFUNCTION CONTROL ELEMENTS
8A.1 INTRODUCTION
constructed using the UDC or Component Builder tools. Multifunction controls
can be made into one control component with multithreading. This chapter
documents the general features of the multifunction controls components.
8A.1
CONTROL
CONTROL
BREAKER
8A.2 MULTIFUNCTION BREAKER CONTROL COMPONENT

CLASS:
FUNCTION:
RSCAD/Draft ICON:
CONTROL FUNCTION
Control, Status, 25
_rtds_BreakerControl.def
Introduction:
The multifunction breaker control component is suitable for providing control and
status of power system breakers. Integrated synchrocheck and zero crossing
detection of currents with time delay pickup and dropout of status signals is also
included, preinsertion control is also available.
Description:
The measuring loops can provide the phasor information in real and imaginary
values, frequency in hz, breaker advance close timers. Internal pushbuttons created
in runtime provide 1 pole or 3 pole control and external trip and close inputs provide
access for external controls.
Operation:
The input voltage signals are passed through DC blocker and a low pass filter with
a cutoff frequency of 1/3 the sample rate in samples per second. The sampled data
8A.2
CONTROL
is adjusted using linear interpolation to compensate for sampling that should occur
between timesteps. The sampled data is fed into an 8 point DFT used to extract the
fundamental phase domain information. The frequency of the voltage inputs is
determined using a zero crossing detector. If the V1 frequency changes the sample
rate is also changed and the phase angles of the voltages are also adjusted.
Internal pushbutton control the breaker and preinsertion resistors, but the
component can use external signals to operate the breaker. The Control output
signal is a integer word that is used to control the power system breaker. The Status
output signal is an integer word that is used to indicate the status of the breaker and
preinsertion breaker and the internal trip and close commnads.
The main breaker status can also be supervised with the phase current zerocrossing.
Power system switches such as breakers and faults switches normally do not change
state instantaneously and are not considered OPEN until after the first zerocrossing
has occurred after an open command. The component can monitor each pahse
current and control the status using this information instead of the control
information.
Input signals for the Breaker Control component
Signal
Description
Format
Trip
External TRIP signal
Integer
Close
External CLOSE signal
Integer
V1
Voltage 1 signal
Float
V2
Voltage 2 signal
Float
IA
A phase current signal
Float
IB
B phase current signal
Float
IC
C phase current signal
Float
Output signals for the Breaker Control component

Signal
Description
Format
Control
Breaker control signal
Integer
Status
Breaker status signal
Integer
V1 Re/im
Voltage Signal 1 (fundamental)
Complex
V1 Freq.
V1 Frequency
Float
V2 Re/im
Voltage Signal 2 (fundamental)
Complex
V2 Freq.
V2 Frequency
Float

The default signal names of the Monitored signals are shown next, the names can be
changed. The maximum length of the signal name is 8 characters, an optional suffix
can be added for a maximum overall length of 10 characters.
8A.3
CONTROL
Signal
Description
Format
SLIPT
System Slip Time to Zero Degrees
Float
CLST
Breaker Close Time
Float
Setting Parameters:
Setting parameters for the BREAKER CONTROL component
CONFIGURATION:
Parameter
Range
Default
Unit
Description
name
10 character
CB1
Component Name
freq
60.0, 50.0
60.0
hz
TrMod
3Pole,1Pole
3Pole
Tripping scheme
eExtCntrl
NO, YES
NO
Enable External Trip and Close inputs
eIx
NO, YES
NO
Enable Current Zero Crossing Check
e25
NO, YES
NO
Enable Synchrocheck function
Vbsll
0.1
13.8
kV
ePri
NO, YES
NO
Enable use of Primary Voltage and Current signal names. Scaling is done automatically based upon the ratios
ePre
NO, YES
NO
Enable Preinsertion Resistor Control
sfx
2 characters

signal names
52 BREAKER STATUS:
Parameter
Range
Default
Unit
Description
stat
Open,
Closed
Closed
Breaker Status Initial Condition
OpDlTmmsAA
0.0
500,000.0
50.0
msec
A/3ph phase Operate Time Delay Pickup 52a
OpDlTmmsAB
0.0
500,000.0
50.0
msec
A/3ph phase Operate Time Delay Dropout 52b
OpDlTmmsBA
0.0
500,000.0
50.0
msec
B ph phase Operate Time Delay Pickup

52a
OpDlTmmsB 0.0
B
500,000.0
50.0
msec
B ph phase Operate Time Delay Dropout 52b
OpDlTmmsCA
0.0
500,000.0
50.0
msec
C ph phase Operate Time Delay Pickup

52a
OpDlTmmsC 0.0
B
500,000.0
50.0
msec
C ph phase Operate Time Delay Dropout 52b
OpDlTmmsP 10.0
re
500,000.0
100.0
msec
Preinsertion Operate Time
8A.4
CONTROL
Abit
fixed
Active bit number to control A/3ph

phase status
Bbit
fixed

status
Cbit
fixed

status
PreAbit
fixed
Preinsertion Bit for A/3ph phase status
PreBbit
fixed
Preinsertion Bit for B ph phase status
PreCbit
fixed
Preinsertion Bit for C ph phase status
Trip/Reclose Input and Status:

Parameter
Range
Default
Unit
Description
TAbit
1 32
Active bit number to A phase Trip Input
TBbit
1 32
Active bit number to B phase Trip Input
TCbit
1 32
Active bit number to C phase Trip Input
T3bit
1 32
Active bit number to 3 phase Trip Input
RCbit
1 32
Active bit number to Close Input
TRstat
fixed
Bit number to control TRIP status output
TRstat
fixed
Bit number to control CLOSE status

output
Description
Parameter
Range
Default
Unit
StrValAdiff
0.0 100.0
10.0
degrees Maximum Angle Difference
StrValFdiff
0.0 3.0
0.5
Hz
Maximum Slip Frequency
StrValVdiff
0.0 20.0
5.0
Maximum Voltage Difference
FgenH
NO, YES
NO
V1 Frequency >> V2 Frequency check
VgenH
NO, YES
NO
V1 Voltage >> V2 Voltage check
StrVal27S1
0.5 200.0
60.00
volts
Minimum V1 Voltage
StrVal27S2
0.5 200.0
60.00
volts
Minimum V2 Voltage
DeadBus
NO, YES
NO
Enable Dead Bus (V2) Synccheck Bypass
StrVal27S3
0.5 200.0
10.00
volts
Dead Bus (V2) Undervoltage Check
ebBrkrAdCls
NO, YES
NO
Enable or Disable Breaker Advance

Close Time Compensation
OpDlTmms25 5.0 5,000
50.0
msec
Breaker Closing Time for breaker advance closing of zero slip
p25bit1
Slip Frequency Check OK
fixed
8A.5
CONTROL
p25bit2
fixed
10
Minimum Voltage Check OK
p25bit3
fixed
11
Voltage Difference Check OK
p25bit4
fixed
12
Angle Difference Check OK
p25bit5
fixed
13
SyncCheck Close Sealin
p25bit6
fixed
14
SyncCheck Close Signal
Default
Unit
Description
VT PARAMETERS:
Parameter
Range
rVT1
1.010000.0 120.0
float
Turns Ratio : 1 (V1)
rVT2
1.010000.0 100.0
float
Turns Ratio : 1 (V2)
Introduction:
The synchrocheck element is suitable for providing the supervision of closing a
circuit breaker connecting two power systems.
Description:
Synchrocheck verifies that the voltages on the two sides of the supervised circuit
breaker are within set limits of magnitude, angle and frequency differences. When
two voltages are at different frequencies seperated by the circuit breaker the voltage
difference across the breaker contacts changes from a minimum to a maximum as the
two voltages slip in and out of phase with respect to each other. When the two
voltages are nearly equal in magnitude the voltage across the open breaker will be
near zero when the system become in phase, resulting in zero angle difference
between the voltages. As the system slip out of phase the voltage difference and
angle difference increase with the maximum when the systems are 180 degrees apart.
The time that the two voltages stay within an angle above and below the in phase 0.0
degree condition is:
Time =
1
360
* Fslip ( Hz )
2 x
sec onds
Equation1: Travel Time Between Angle Limit

where phase angle difference is in degrees; and slip frequency difference is in Hz,
the time to zero degrees would be 1/2 of the time calculated.
8A.6
CONTROL
Slip Frequency > 0.0Hz
Slip Frequency < 0.0Hz
V System
StrValAdiff
StrValAdiff
V Generator
270
90
180
Figure 1: Synchrocheck Element Angle Check

Operation:
The relay calculates the frequency, magnitude, and angle of the V1 voltage and V2
voltage. The synchrocheck logic supervises the closure of the open circuit breaker
and provides a close pulse to the breaker control, an internal push button is used to
manually CLOSE and OPEN the circuit breaker in runtime. The element does not
adjust for phase shifts in voltages between phases, therefore the same phase voltages
must be used.
The frequency difference is compared to the setting parameter StrValFdiff to
determine if the slip frequency is within the limit. The logic can also be set to ensure
that the generator frequency is higher than the system frequency.
The voltage magnitude of the generator and system is compared to the setting
parameters StrVal27S1 and StrVal27S2 to determine if there is sufficient voltage
to operate the element.
The voltage difference is compared to the setting parameter StrValVdiff to
determine if the voltage across the open breaker is within the limit. The logic can
also be set to ensure that the generator voltage is higher than the system voltage.
The angle difference is compared to the setting parameter StrValAdiff to determine
if the angle difference between the two voltages is within the limit.
The synchrocheck element can be enabled to operate if the V2 voltage is Dead.
The V2 voltage is compared to the setting parameter StrVal27S3 to determine if
the bus voltage is below a certain level. If the V2 voltage is below this setting the
bus is considered denergized therefore the synchrocheck logic is bypassed to allow
the circuit breaker to be closed.
The synchrocheck element seals in the CLOSE command and waits for the element
checks to be satisfied before the relays issues the output. The sealin is reset when
the output is asserted or when the OPEN command is issued.
8A.7
CONTROL
Figure 2: Synchrocheck Element Logic

The logic can also be set to ensure that the breaker is closed at exactly zero slip by
calculating the time to close the breaker in advance of zero degrees as shown in figure
25. The setting parameter OpDlTmms25 is used when the breaker advance closing
is enabled. The time to reach 0 degrees from the setting StrValAdiff is calcuated
and then used to determine the time to CLOSE the breaker. A timer is started when
the angle difference is within the limit and increase as the angle decreases towards
0. If the time required to close the breaker is within the time to reach 0 degrees the
breaker can be closed, if not the relay sets the monitored signal CLST to 0.0 or the
elapsed time to zero when the breaker CLOSE command is issued. The time to reach
zero degrees at any given frequency less than the maximum allowable slip can also
be monitored and is called SLIPT. In the following figure 27 the 1st plot shows
the generator voltage and system sync voltage, the 2nd plot shows the CLOSE signal
8A.8
CONTROL
and 50 ms later the breaker closes. The third plot shows the voltage difference across
the open circuit breaker and it shows the voltage approach zero as the two voltages
slip into synchronisim, the breaker is closed at zero degrees.
If the slip frequency is small such that the time required to rotate around is greater
than 30.0 seconds the breaker advance close time is bypassed and the breaker is
closed if all other conditions are met.
MACVA1 N-30
20
V
k
-20
CLOSE
BRK1
Vdiff
1
-1
1.28215
1.33045
1.37875
1.42704
1.47534
Figure 3: Synchrocheck Breaker Advance Close Plot
Execution Time
GPC
0.812 us
1.804 us
without Synchrocheck
with Synchrocheck
8A.9
CONTROL
CONTROL
TAP CHANGER
8A.3 MULTIFUNCTION TAP CHANGER CONTROL COMPONENT

CLASS:
FUNCTION:
RSCAD/Draft ICON:
CONTROL FUNCTION
Control, Status, OLTC
_rtds_OLTC.def
Introduction:
The multifunction tap changer control component is suitable for providing control
and status of power system transformers with on load tap changers. Integrated
automatic or manual mode with load current compensation and over voltage, under
voltage, and over current blocking functions.
Description:
The measuring loops can provide the phasor information in real and imaginary
values, frequency in hz, breaker advance close timers. Internal pushbuttons created
in runtime provide manual control and external auto/man input switch betweeen
automatic and manual mode. The internal reset pushbutton is used to reset the control
if it becomes blocked.
Operation:
The input signals are passed through DC blocker and a low pass filter with a cutoff
frequency of 1/3 the sample rate in samples per second. The sampled data is adjusted
using linear interpolation to compensate for sampling that should occur between
timesteps. The sampled data is fed into an 8 point DFT used to extract the
fundamental phase domain information. The frequency of the voltage inputs is
determined using a zero crossing detector. If the V1 frequency changes the sample
rate is also changed and the phase angles of the voltage and current are also adjusted.
Internal pushbuttons control the manual Tap UP and Tap DOWN when manual mode
is selected. The regulation of voltage in automatic mode is used to provide a near
constant voltage at the setpoint, the system can also use the load current to help
compensate the voltage deviation from the setpoint. The Info output signal is a
integer word that is used to indicate the status of the tap changer logic. The
8A.10
CONTROL
Blocked output signal is used to indicate the tap changer is blocked and is not
regulating the voltage setpoint.
Input signals for the Tap Changer Control component
Signal
Description
Format
VA
Voltage 1 signal
Float
IA
Current 1 signal
Float
Auto Man
1 Auto, 0 Manual
Integer
pos
Tap Position signal from TFR
Integer
V gain
Voltage 1 gain signal
Float
Output signals for the Tap Changer Control component

Signal
Description
Format
dn
Tap Down control signal
Integer
up
Tap Up control signal
Integer
Blocked
Tap Changer Blocked status signal
Integer
Info
Tap Changer Information bits:

0 : Tap UP signal
1 : Tap DOWN signal
2 : Automatic Mode signal
3 : Manual Mode signal
4 : System Ready signal
5 : Maximum Tap Position signal
6 : Minimum Tap Position signal
7 : Maximum Tap Operations signal
8 : Tap Operation Timeout signal
9 : Sucessive Tap Operations signal
10 : Under Voltage block signal
11 : Over Voltage block signal
12 : Over Current block signal
13:
.... (not used)
31:
Integer (word)

The default signal names of the Monitored signals are shown next, the names can be
changed. The maximum length of the signal name is 8 characters, an optional suffix
can be added for a maximum overall length of 10 characters.
8A.11
CONTROL
Signal
Description
Format
VARE
V1 phaseground voltage (re)
Float
VAIM
V1 phaseground voltage (im)
Float
VPU
V1 phaseground voltage (pu)
Float
IARE
I1 phaseground current (re)
Float
IAIM
I1 phaseground current (im)
Float
IPU
I1 phaseground voltage (pu)
Float
upCNT
Tap UP operations
Integer
dnCNT
Tap DOWN operations
Integer
opCNT
Tap TOTAL operations
Integer
posVal
Tap Position
Integer
FREQ
Float
TRIG
System Sampling Indication
Integer
MW
Measured fundamental MW
Float
MVAR
Measured fundamental MVAR
Float
Setting Parameters:
Setting parameters for the TAP CHANGER CONTROL component
CONFIGURATION:
Parameter
Range
Default
Unit
Description
name
10 character
TC1
Component Name
Tmva
1e4
1200.0
MVA
Rated MVA of the Transformer
Vbsll
0.1 1.0e6
13.8
kV
freq
60.0, 50.0
60.0
hz
tapCh
Pos Table,
Step/Limit
Pos
Table
Tap Changer (type cannot be Linear)
edge
Rising Edge, Rising

Falling Edge Edge
Tap Changer Trigger Output Type
eLCC
NO, YES
NO
Enable Load Current Compensation
ePN
NO, YES
NO
Enable 27, 59, 50 Elements
ePri
NO, YES
NO
Enable use of Primary Signal names
eExtGain
NO, YES
NO
Enable External Voltage Gain
adv
None,
V by 1dt,
I by 1dt
V by 1dt
Enable Delay Input Signal to align

V&I
8A.12
CONTROL
plots
NO, YES
sfx
2 characters
NO
Enable Monitoring

signal names
TAP OPERATION:
Parameter
Range
Default
Unit
Description
OpTmmsPulse
200.0
60,000.0
5000.0
msec
Tap Changer Up/Down Operation Pulse
OpTmmsSuccess
200.0
60,000.0
5000.0
msec
Tap Changer Up/Down Operation Timeout
nTapOperOffset
0 9999999 0
Total Tap Operations Initial Count
nTapOperMax
0 9999999 9999
Maximum Tap Operations Allowed (0

disables)
SucOperCnt
0 60
Successive Operations Count (0

diasbles)
OpTmminSu- 1 60
cOper
min
Tap Changer Successive Operation

Timeout
dv
0.5 10.0
2.5
% of V nominal before tap operation
setpoint
0.8 1.2
1.0
pu
Regulation Set point of V nominal
OpTimeFactor
1.0 100.0
1.0
Tap Changer Auto Operation Time Factor
ATdnpoint
0.9 1.5
1.2
pu
Accelerated Tap Down Set point of V

nominal
Kvcom
0.0 0.10
0.01
pu
V compensation based on k * Ipu
maxvcom
0.03 0.15
0.10
pu
Maximum V compensation based on k *

Ipu
TAP CHANGER A: (tapCh=1)

Parameter
Range
Default
Unit
Description
noTaps
1 50
10
Number of TAP positions
TR1
1 50
Starting Tap position
maxTap
1 50
10
Upper Tap position limit
minTap
1 50
10
Lower Tap position limit
TAP CHANGER B: (tapCh=2)

Parameter
Range
Default
Unit
Description
step
0.00001
0.1
0.01
pu
Step Size
TR2
0.7 1.4
1.0
pu
Starting Tap position
8A.13
CONTROL
limH
0.7 1.4
1.2
pu
Upper Tap position limit
limL
0.7 1.4
0.8
pu
Lower Tap position limit
Default
Unit
Description
CT/VT PARAMETERS:
Parameter
Range
rVT1
1.010000.0 2000.0
float
Turns Ratio : 1
rCT1
1.010000.0 600.0
float
Turns Ratio : 1
27, 59, 50 ELEMENTS:

Parameter
Range
Default
Unit
Description
StrVal27P1
0.5 200.0
49.815
volts
Start Value (pickup PTUV)
StrVal59P1
0.5 200.0
83.0
volts
Start Value (pickup PTOV)
StrVal50P
0.05 50.0
6.0
amps
Start Value (pickup PIOC)
TAP CHANGER WITHOUT LOAD CURRENT COMPENSATION:

The TAP CHANGER CONTROL will automatically adjust the tap position of the
OLTC to keep the voltage at the specified setpoint. The measured voltage is
compared to the setpoint and |deviation| must be greater than the parameter dv
for a tap operation to be considered. There is a minimum time for the deviation to
exist before the tap operation is called for. The operating time delay is porpational
to the amount of deviation. If a deviation is greater than the accelerated tap down
parameter ATdnpoint the operating time delay is bypassed for a quick tap down.
If the condition still exists the operating time delay(s) are bypassed at 25% of the
delay until the condition ceases.
dv1 = Vsetpoint Vmeasured
OperateTimeDelay = OpTimeFactor * ((10.0 * dv)|dv1|)
8A.14
CONTROL
Operate Time for time factor = 1

1
10
100
Operate Time Delay in Seconds
0.5%
1.0%
80.1
1.5%
60.1
2.5%
40.1
4.0%
5.0%
20.1
0.1
Voltage Deviation in %
Figure 1: Operate Timeout for DV settings

TAP CHANGER WITH LOAD CURRENT COMPENSATION:
The TAP CHANGER CONTROL operates in the same manner as described for
operation without load compensation except the voltage deviation is adjusted with
a compensation voltage. The compensation voltage is calculated by multipling the
pu load current by the constant Kvcom. The compensation voltage is added to the
setpoint before the voltage deviation is calculated. The compensation is limited
to a maximum set by parameter maxvcom.
Vcom = Kvcom * (ImeasuredInominal)
dv1 = (Vsetpoint + Vcom) Vmeasured
OperateTimeDelay = OpTimeFactor * ((10.0 * dv)|dv1|)
8A.15
CONTROL
TAP CHANGER BLOCKING OPERATION:
The TAP CHANGER CONTROL will be blocked from operating in either manual
or automatic mode if certain system checks fail when the tap changer is in service.
The system will be blocked for the following conditions and must be reset using the
reset pushbutton before a tap operation can occur:
1 Maximum tap operation check is enabled and the total operations exceed the
setting.
2 The expected tap position does not match the actual tap position indication for
the OLTC.
3 The sucessive tap operation check is enabled and the number of tap operation
exceeds the setting within the specified time.
The system will be temporarily blocked for the following conditions and returns to
normal after the condition ceases:
1 Voltage is below the specified under voltage setting.
2 Voltage is above the specified over voltage setting.
3 Current is above the specified over current setting.
Execution Time
GPC
0.907 us
8A.16
Rev. 01: April 11
8B
MULTIFUNCTION METER ELEMENTS
8B.1 INTRODUCTION
constructed using the UDC or Component Builder tools. Multifunction meters can
be made into one control component with multithreading. This chapter documents
the general features of the multifunction metering components.
8B.1
METERING
METER
SEQUENCE
8B.2 MULTIFUNCTION SEQUENCE COMPONENT

CLASS:
FUNCTION:
RSCAD/Draft ICON:
METERING FUNCTION
Positive, Negative, Zero
_rtds_PN_SEQ
Introduction:
The multifunction sequence component is suitable for providing the symmetrical
component information related to 3 phase set of instantaneous values such as voltage
or current. Plot signals provide sufficient information to help verify theoretical
calculations with the simulation results.
Description:
The measuring loops can provide the phasor information, positive, negative, and
zero sequence information as plot signals in real and imaginary values.
Operation:
The fundamental phase signals are fed into the 3 inputs of the component. The input
signals are passed through a low pass filter with a cutoff frequency of 1/3 the sample
rate in samples per second. The sampled data is adjusted using linear interpolation
to compensate for sampling that should occur between timesteps.The sampled data
is fed into an 8 point DFT used to extract the fundamental phase domain information.
The system frequency is determined using the instantaneous composite voltage
If selected the phasor values for the inputs are plotted as export signals. If selected
the positive, negative, and zero sequence values are calculated and plotted as export
signals. The plot signals can be monitored in runtime or imported into the draft case
as inputs to other controls components.
8B.2
RELAYING
Input signals for the PN_SEQ function block
Signal
Description
Format
A phase signal
Float
B phase signal
Float
C phase signal
Float

The default signal names of the Monitoring signals for the SEQUENCE
COMPONENT are shown next, the names can be changed. The maximum length
of the signal name is 8 characters, an optional suffix can be added for a maximum
Signal
Description
Format
ARE
A phaseground (re)
Float
AIM
A phaseground (im)
Float
BRE
B phaseground (re)
Float
BIM
B phaseground (im)
Float
CRE
C phaseground (re)
Float
CIM
C phaseground (im)
Float
V1ARE
Positive sequence A phase (re)
Float
V1AIM
Positive sequence A phase (im)
Float
V1BRE
Positive sequence B phase (re)
Float
V1BIM
Positive sequence B phase (im)
Float
V1CRE
Positive sequence C phase (re)
Float
V1CIM
Positive sequence C phase (im)
Float
V2ARE
Negative sequence A phase (re)
Float
V2AIM
Negative sequence A phase (im)
Float
V2BRE
Negative sequence B phase (re)
Float
V2BIM
Negative sequence B phase (im)
Float
V2CRE
Negative sequence C phase (re)
Float
V2CIM
Negative sequence C phase (im)
Float
V0RE
Zero sequence (re)
Float
V0IM
Zero sequence (im)
Float
FREQ
Float
DFREQ
Float
Setting Parameters:
8B.3
METERING
Setting parameters for the SEQUENCE COMPONENT will be described below.
CONFIGURATION:
Parameter
Range
Default
Name
10 character
SeqComp
Component Name
freq
60, 50
60
hz
sfx
2 characters

plot signal names
Unit
Description
Execution Time
GPC
0.996
us
8B.4
RELAYING
METER
IMPEDANCE
8B.3 MULTIFUNCTION IMPEDANCE COMPONENT

CLASS:
FUNCTION:
RSCAD/Draft ICON:
METERING FUNCTION
Positive, Negative, Zero Impedance
_rtds_PN_ZCALC
Introduction:
The multifunction impedance component is suitable for providing the symmetrical
component information related to a pair of 3 phase sets of instantaneous values such
as voltage and current. Plot signals provide sufficient information to help verify
theoretical calculations with the simulation results.
Description:
The measuring loops can provide the phasor information, positive, negative, zero
sequence, and impedance information as plot signals in real and imaginary values.
Operation:
The fundamental phase signals are fed into the 6 inputs of the component. The input
signals are passed through a low pass filter with a cutoff frequency of 1/3 the sample
rate in samples per second. The sampled data is adjusted using linear interpolation
to compensate for sampling that should occur between timesteps.The sampled data
is fed into an 8 point DFT used to extract the fundamental phase domain information.
The magnitude of the positive, negative, and zero sequence voltage component is
used to determine which is the best signal to use for the frequency tracking. The
system frequency is determined using the instantaneous composite voltage
8B.5
METERING
The distance measuring zones for the phase to ground will be compensated. This
compensation factor can be calculated automatically according to: K0 = Z0 Z1 /
3*Z1 or can be manually entered as magnitude and angle values. A compensation
factor can also be included for a parallel line where mutual coupling exists between
the lines.
If selected the phasor values for the inputs are plotted as export signals. If selected
the positive, negative, and zero sequence values are calculated and plotted as export
signals for both voltage and current. If selected the phasetoneutral,
phasetophase, positive sequence, negative sequence, and zero sequence
impedance values are calculated and plotted as export signals. The plot signals can
be monitored in runtime or imported into the draft case as inputs to other controls
components.
Input signals for the PN_ZCALC function block
Signal
Description
Format
VA
A phase voltage signal
Float
VB
B phase voltage signal
Float
VC
C phase voltage signal
Float
IA
A phase current signal
Float
IB
B phase current signal
Float
IC
C phase current signal
Float
IZ0MRE

line (re)
Float (import)
IZ0MIM

line (im)
Float (import)
Impedance calculation signal names (MSQI):

The default signal names of the Monitoring signals for the IMPEDANCE
Signal
Description
Format
ZARE
A phaseground impedance (re)
Float
ZAIM
A phaseground impedance (im)
Float
ZBRE
B phaseground impedance (re)
Float
ZBIM
B phaseground impedance (im)
Float
8B.6
RELAYING
ZCRE
C phaseground impedance (re)
Float
ZCIM
C phaseground impedance (im)
Float
ZABRE
AB phasephase impedance (re)
Float
ZABIM
AB phasephase impedance (im)
Float
ZBCRE
BC phasephase impedance (re)
Float
ZBCIM
BC phasephase impedance (im)
Float
ZCARE
CA phasephase impedance (re)
Float
ZCIAM
CA phasephase impedance (im)
Float
Z1RE
Float
Z1IM
Float
Z2RE
Negative sequence impedance (re)
Float
Z2IM
Negative sequence impedance (im)
Float
Z0RE
Zero sequence impedance (re)
Float
Z0IM
Zero sequence impedance (im)
Float
K0MAG
Calculated Zero Sequence Compensation (magnitude)
Float
K0ANG
Calculated Zero Sequence Compensation (angle)
Float

The default signal names of the Monitoring signals for the IMPEDANCE
Signal
Description
Format
VARE
Float
VAIM
Float
VBRE
Float
VBIM
Float
VCRE
Float
VCIM
Float
IARE
Float
IAIM
Float
IBRE
Float
IBIM
Float
ICRE
Float
ICIM
Float
8B.7
METERING
V1ARE
Positive sequence VA phase (re)
Float
V1AIM
Positive sequence VA phase (im)
Float
V1BRE
Positive sequence VB phase (re)
Float
V1BIM
Positive sequence VB phase (im)
Float
V1CRE
Positive sequence VC phase (re)
Float
V1CIM
Positive sequence VC phase (im)
Float
V2ARE
Negative sequence VA phase (re)
Float
V2AIM
Negative sequence VA phase (im)
Float
V2BRE
Negative sequence VB phase (re)
Float
V2BIM
Negative sequence VB phase (im)
Float
V2CRE
Negative sequence VC phase (re)
Float
V2CIM
Negative sequence VC phase (im)
Float
V0RE
3V Zero sequence (re)
Float
V0IM
3V Zero sequence (im)
Float
I1ARE
Positive sequence IA phase (re)
Float
I1AIM
Positive sequence IA phase (im)
Float
I1BRE
Positive sequence IB phase (re)
Float
I1BIM
Positive sequence IB phase (im)
Float
I1CRE
Positive sequence IC phase (re)
Float
I1CIM
Positive sequence IC phase (im)
Float
I2ARE
Negative sequence IA phase (re)
Float
I2AIM
Negative sequence IA phase (im)
Float
I2BRE
Negative sequence IB phase (re)
Float
I2BIM
Negative sequence IB phase (im)
Float
I2CRE
Negative sequence IC phase (re)
Float
I2CIM
Negative sequence IC phase (im)
Float
I0RE
3I Zero sequence (re)
Float
I0IM
3I Zero sequence (im)
Float
FREQ
Float
DFREQ
Float
Setting Parameters:
Setting parameters for the SEQUENCE COMPONENT will be described below.
CONFIGURATION:
Parameter
Range
Default
Name
10 character
SeqComp
Unit
Description
Component Name
8B.8
RELAYING
freq
60, 50
60
hz
adv
None, V by
1dt
None

zeroseq
NO, YES
YES
Enable or Disable zero sequence compensation for phaseground impedance

calculation
emutc
OFF, ON
OFF
Enable Mutual Coupling input and

compensation
plots
NO, YES
NO
Enable or Disable Signal Monitoring
sfx
2 characters

plot signal names
POS/ZERO SEQ COMP: (zeroseq==1)

Parameter
Range
Default
Unit
Description
Z1M
0.001
9999.99
7.54
ohms
Positive sequence magnitude
Z1A
0.0 360.0
87.18
degrees
Positive sequence angle
Z0M
0.001
9999.99
25.6
ohms
Zero sequence magnitude
Z0A
0.0 360.0
73.59
degrees
Zero sequence angle
KZ0M
0.001
9999.99
0.3772
ohms
Mutual zero sequence magnitude

(emutc>0)
KZ0A
0.0 360.0
13.60
degrees
Mutual zero sequence angle (emutc>0)
k0calc
NO, YES
YES
Enable automatic zero sequence compensation calculation
k0Mag
0.001
9999.99
0.925
ohms

compensation magnitude
k0Ang
360.0
360.0
18.38
degrees

compensation angle
Execution Time
GPC
1.401
us
8B.9
METERING
METER
PHASOR MEASUREMENT
8B.4 MULTIFUNCTION PHASOR MEASUREMENT COMPONENT

CLASS:
FUNCTION:
RSCAD/Draft ICON:
METERING FUNCTION
Positive, Negative, Zero Impedance
_rtds_PMU_v1
Introduction:
symmetrical component information related to a pair of 3 phase sets of instantaneous
values of voltage and current. Eight PMUs are included in 1 component and operate
independently.
Description:
The measuring loops can provide the phasor information for the voltage, current,
positive, negative, and zero sequence (voltage and current), as plot signals in real and
imaginary or magnitude and angle values. If all signals are selected each PMU will
provide a total of 12 phasors, the measured frequency, and rate of change of
frequency.
Operation:
The signals are fed into the 6 inputs of the component. The input signals are passed
through a low pass filter with a cutoff frequency of 1/3 the sample rate in samples
per second. The sampled data is adjusted using linear interpolation to compensate
8B.10
RELAYING
for sampling that should occur between timesteps. The sampled data is fed into an
8 point DFT used to extract the fundamental phase domain information. The system
frequency is determined using the instantaneous composite voltage comprised of Va
0.5*Vb 0.5*Vc. If the system frequency changes the sample rate is also changed
to ensure a constant 8 samples per cycle. The measured system frequency and rate
of change of frequency can be monitored. The absolute difference between the
composite voltage and the previous time step composite voltage is used to detect
disturbances in the voltage. If a disturbance is detected the frequency measurement
and sample rate adjustment is suspended for 3 cycles.
The following reporting rates are supported for each PMU
System frequency
Reporting rates
50 Hz
60Hz
1
2
5
10
25
50
1
2
4
5
10
12
15
20
30
60
When a frame interrupt occurs the PMU waits 4 more sample periods until the DFT
is executed in the same timestep when the 4th sample point was taken. The PMU
then processes the phasor information in a 5 timestep thread which means there is
a 250 usec latency before all the phasor information is processed with a simulation
timestep of 50 usec
AC Input signals for each PMU (n = 18)
Signal
Description
Format
nVTA(n)
Float
nVTB(n)
Float
nVTC(n)
Float
nCTA(n)
Float
nCTB(n)
Float
nCTC(n)
Float
8B.11
METERING
Ouput signals for each PMU
Signal
Description
Format
PM1
Integer
PM2
Integer
PM3
Integer
PM4
Integer
PM5
Integer
PM6
Integer
PM7
Integer
PM8
Integer
1PPS
Pulse per second trigger
Integer
Setting Parameters:
Setting parameters for the PMU COMPONENT will be described below.
CONFIGURATION:
Parameter
Range
Default
Unit
Description
Name
10 character
PMU1
Component Name
freq
60, 50
60
hz
nPMU
0 8
adv
None,
V by 1dt
V by 1dt
eAngM
NO, YES
NO
nAngDiff

(PMUxPMUy)
sfx
2 characters

plot signal names
ePri
NO, YES

YES
Parameter
Range
Default
Unit
Description
p(n)STN
10 character
PMU1
PMU Station Name
p(n)IDC
165534
p(n)OUTF
An & Bn,
Cn & Phi
An & Bn
names can be changed. The maximum length of the signal name is 8 characters, an
8B.12
RELAYING
optional suffix can be added for a maximum overall length of 10 characters. Twelve
phasors can be selcted per PMU. The phasor is can be configured with one of the
following signals: NO;VA;VB;VC;IA;IB;IC;V1;V2;V0;I1;I2;I0
(n = 18)
Signal
Description
Format
PM(n)phs1
PM(n)phs2
PM(n)phs3
PM(n)phs4
PM(n)phs5
PM(n)phs6
PM(n)phs7
PM(n)phs8
PM(n)phs9
PM(n)phsA
PM(n)phsB
PM(n)phsC

VA or VB or VC or IA or IB or IC or
V1 or V2 or V0 or I1 or I2 or I0
Float
PMU(n)freq
float (Hz)
PMU(n)dfreq
float (Hz/s)
Execution Time
GPC
237 us + 1162 us PMU + 201 us if eAngM is enabled
PB5
201 us + 811 us per PMU + 175 us if eAngM is enabled
8B.13
Rev. Dec 2012
COMTRADE PLAYBACK
( _rtds_PLAYBACK.def )
The RTDS simulator can be used to playback captured COMTRADE waveforms.

COMTRADE represents a common format for transient data exchanged in the power
system industry. Developed by the IEEE Power System Relaying Committee, the
COMTRADE format is important in the field of protective relay testing and study.
Although the primary application of the RTDS simulator is to simulate the operation
of power systems and study events initiated by the user during a test series, it is also
useful to be able to play back previously stored waveforms. For example, if stored
waveforms representing a particular disturbance are available, a playback facility
enables the replay of such waveforms into devices under test. Typically, the stored
waveforms might originate from a transient fault recorder in the real system or from
an independently run transient simulation program.
IEEE Standard COMTRADE Format 1991 and 1999 revisions are currently
supported.
9.1 COMTRADE FILES AND DATA FORMAT
Each COMTRADE event can have up to 4 files associated with it, namely the header
file, the configuration file, the data file and the information file. Each of the 4 files
carries with it different information.
All files associated with a particular stored COMTRADE event have the same file
name but are assigned a different file extension. The basic form of the files is as
shown :
<filename>.extension
The Header File is an optional file which contains basic information about the stored
case. Normally this is a text file which is used simply to describe the case at hand.
The header file is denoted as <filename>.hdr
The Configuration File contains information needed by the playback system in order
to properly interpret the stored transient data. This information includes things such
as the sampling rates, number of channels, system frequency, etc. The configuration
file is not an optional file and must be included if proper playback is to be achieved.
9.1
COMTRADE PLAYBACK
The configuration file is denoted as <filename>.cfg
The Data File contains the data values for each channel for each sample point. The
numbers stored in the data file represent scaled values of the actual quantities
recorded or produced during data capture. Conversion factors specified in the
configuration file define how the stored points are converted to produce actual
engineering units. The data file is not an optional file and must be included if proper
playback is to be achieved. The data file is denoted as <filename>.dat
The Information File is an optional file which contains additional information that
producers and users of the COMTRADE data records may wish to communicate or
exchange in addition to that contained in the minimal data set. The information file
is denoted as <filename>.inf
The RTDS simulator COMTRADE playback facility is concerned only with the two
mandatory files, that is, the configuration file and the data file. These two files must
exist in the users RSCAD working directory whenever the playback facility is
utilized. Both ASCII and BINARY type data file formats are supported.
9.2 RTDS FILES
Data points are read from the .dat file and scaled according to the information in the
.cfg file. The scaled data points are then stored in a file with the same base name as
the comtrade data files with a .cnv filename extension. The .cnv file is
automatically generated during the RSCAD/Draft compile process. Once generated,
the .cnv file contains columns of ASCII data and can be plotted using a plotting
software package.
A .par file is also created during the compile process. This file is created for
reference only. The format of the .par file is as shown.
t , lpfc, #pnts, pfcop
where:
t simulation time step in secs.
lpfc last data point in the prefault cycle
#pnts total number of data points read from .dat file
pfcop prefault cycle operation, 0=auto, 1=none, 2=manual
9.3 LINEAR INTERPOLATION
Stored data associated with a particular channel in the COMTRADE data file
corresponds to a sample taken at a specified instant in time. The elapsed time
between successive samples is referred to as the sample time. Because the RTDS
9.2
COMTRADE PLAYBACK
simulator will not necessarily be run at the same sampling rate ( ie: it may be shorter
or longer than the stored sampling rate ), some data preprocessing must be
performed. As part of the preprocessing, linear interpolation is applied between
successive points stored in the original <filename>.dat file. The chosen RTDS
simulation time step t is used as a basis for the linear interpolation function.
The data points from the .cnv file are written to memory on the RTDS. The RTDS
simulator performs the linear interpolation and the interpolated data points and
played back.
Figure 1 illustrates how the interpolated output would look with respect to the
original data from the .dat file for a particular case.
time
t
sample time
Data points read from .dat file

Data points computed by the RTDS
Figure 1: Interpolated Output
9.4 DATA SCALING

Comtrade analogue channel information from a .cfg file typically appears in a format
as shown below for 1991 format.
An,ch_id,ph,ccbm,uu,a,b,skew,min,max,chratio
and below for 1999 format.
An,ch_id,ph,ccbm,uu,a,b,skew,min,max,primary,secondary,PS
where:
9.3
COMTRADE PLAYBACK
An channel index number
ch_id channel identifier
ph phase identifier
ccbm circuit component being monitored
uu channel units
a channel multiplier
b channel offset
skew time skew
min minimum data value allowed
max maximum data value allowed
chratio primary to secondary conversion ratio
primary CT or PT primary ratio
secondary CT or PT secondary ratio
PS indicates whether primary side values P or secondary side values S
are stored in the data file.
Data read from the .dat file is scaled by the channel multiplier (a) and channel offset
(b) from the .cfg file.
scaled data = .dat value * a + b
The scaled data is further processed based on the gain implied by the units (uu) and
the primary to secondary ratio (chratio).
scaled data = scaled data * gain / chratio
The scaled data is stored in the .cnv file.
Scaling of digital channels is not required.
The data from the .cnv file is converted to a sixteen bit number and stored in
memory on the RTDS. Two 16bit numbers are stored in one external memory
location ( this helps expand the available memory space for data storage ). The
maximum data memory locations available for a GPC or PB5 type processor is 128K.
Since two data points are stored in one data memory location, a maximum of 256K
data points could be played back using one processor. One comtrade component can
playback up to 10 comtrade channels, the available memory on the processor is
shared between the channels. Therefore, for example, if eight channels of data are
used, each channel could have a maximum of 32K data points. If more memory is
required, a second comtrade component could be used and assigned to a second
processor.
9.4
COMTRADE PLAYBACK
9.5 OPERATING IN PRETRANSIENT ( PREFAULT ) CYCLE MODE
Normally the event stored in the COMTRADE file represents a transient condition
on the power system. In some cases a short interval of steady state ( or pre transient )
operation preceeds the event being considered. The RTDS playback facility includes
a feature which allows operation in the pre transient state for an undetermined period
of time. When the transient event is to be applied, transition from the pre transient
or prefault mode to transient (run mode) can be initiated. The transition from
prefault to run mode is triggered using a control signal name. The control signal
name is created using controls components and entered in the CSIG parameter in the
CONFIGURATION tab. For prefault operation, the control signal must be 0, and
for run operation, the control signal must be 1. When the comtrade component is
switched to run mode, the entire stored waveform is played back.
When creating the .cnv file, the RTDS compiler software attempts to define the first
cycle of data and assign this as the prefault interval. Operation in prefault mode
can be useful when interconnected external equipment is being initialized.
The algorithm used to define the pretransient cycle is as follows
Compute and store initial slope
scan for 2 zero crossings from the start of the data list
if initial slope is negative then
scan for two consecutive points of which the first is
larger than the first point in the .cnv file and the
second is less than the first point in the .cnv file.
if initial slope is positive then
scan for two consecutive points of which the first is
less than the first point in the .cnv file and the
second is greater than the first point in the .cnv file.
If the PREFAULT CYCLE algorithm detects that the frequency of the prefault
cycle if different by more than 10 Hz from the base frequency indicated in the
COMTRADE.CFG file, a warning message is issued. If no prefault cycle can be
detected, an Error message is issued and the user is advised to set the PRE variable
to NONE.
A prefault cycle can be specified manually by the user. Selecting Manual for the
PRE variable creates a menu for the user to enter the last data point of the prefault
cycle.
Once the stored event has been played back, all signal levels are immediately forced
to 0.0. Output will remain in this state until the mode is switched back to prefault
mode, or the case is restarted.
9.5
COMTRADE PLAYBACK
9.6 PLAYBACK
The RTDS COMTRADE playback component uses one digital signal processor. Up
to 10 independent channels can be supported through a single playback component.
It is possible to place more than one playback component on a subsystem page in
RSCAD/Draft. It is also possible to place playback components on different
RSCAD/Draft pages. If more than one COMTRADE component is included in a
playback case, one control signal can be used to simultaneously trigger all
components into run mode.
9.7 RSCAD DRAFT COMPONENT AND PARAMETER ENTRIES
The RSCAD Draft component used for playback of COMTRADE files can be found
in the RSCAD Protection & Automation library tab with name _rtds_PLAYBACK.
The figures below illustrate the menus used for RTDS COMTRADE playback.
Within the CONFIGURATION menu the following items must be specified

NAME Each COMTRADE component requires a unique name. This is used for
crossreferencing variables between RSCAD/Draft and RSCAD/RunTime.
DF The name of the COMTRADE file set ( without an extension ).
NCH The number of channels that are to be played back. A maximum of 10
channels can be specified for each comtrade component used.
PRE Set to Auto to have the RTDS software attempt to find the prefault cycle.
Set to No to have all outputs set to 0.0 while the component is in prefault mode.
9.6
COMTRADE PLAYBACK
If Manual is selected as the prefault cycle , a new menu tab MANUAL
PREFAULT CYCLE will appear with parameter entry as shown.
MPFC the user can define the prefault cycle by entering the last data point of the
prefault cycle. For example, if a .dat file contains data for a 60 Hz waveform with
a sample time of 83secs. There are 200 data points/cycle. If we want the first cycle
of data to be continuously played back in prefault mode, the MPFC parameter
would be set to 200.
CSIG a control signal is required to switch the comtrade component from prefault
to run mode. The control signal is created using control components. If the control
signal is an integer 0, the comtrade component will run in prefault mode. If the
control signal is an integer 1, the comtrade component will be in run mode.
prtyp the target processor to execute the comtrade component must be selected.
For each channel, a SIGNAL # tab will be created. Each tab contains the parameters
as discussed below.
CTC1 The comtrade file channel number to be played back must be specified.
9.7
COMTRADE PLAYBACK
UG1 Indicates whether the units in the .cfg file are to be used to scale the data. Valid
units from the .cfg file are kV, kA, KILO, uV, UA, mV, mA, Milli, MA, MV, mega,
amp, volt, A, V.
MUG1 If the UG1 parameter above is set to No then the value entered for the
MUG1 parameter is used for scaling.
PS1 The chratio is the primary to secondary ratio. Setting this parameter to Yes
will scale the data according to the chratio in the .cfg file. Sometimes the ratio is not
included in the .cfg file and the ratio can be entered manually.
Note: In IEEE comtrade versions prior to 1997, the primary to secondary ratio was
referred to as the chratio. The chratio was displayed as primary:secondary separated
by a colon. Versions after 1997, the ratio is referred to as the primary to secondary
ratio and is separated by commas.
SC1 This parameter defines the primary to secondary ratio to be applied for internal
signal scaling if the chratio is not being read from the .cfg file.
TS1 This parameter can be used to introduce a time shift of the signal being
considered. If no shift is required then TS1 should be left at 0.0. If a skew value exists
for the channel, the skew value will be added to the time shift entered.
SNS the signal name given to the comtrade channel is read from the .cfg file if this
parameter is set to Auto. Alternatively, setting this parameter to Manual allows
the user to define the signal name.
SN1 if the above parameter SNS is set to Manual, the comtrade channel is
assigned the signal name entered in this menu.
9.8 SENDING COMTRADE SIGNALS TO AN EXTERNAL DEVICE

Typically comtrade play back is used to send some prerecorded transient event to
an external device. Each comtrade channel can be assigned a signal name. This
signal name can then be used as input to an I/O control component. For example,
analogue signals could be named in the comtrade component and then used as input
to a GTAO component. Similarly with digital I/O, reading and writing of digital
signals can be done using the controls components. Manually assign a signal name
to the comtrade channels as shown.
9.8
COMTRADE PLAYBACK
Comtrade channels 1,2, and 3 have been given the names VA,VB and VC. These
signals are then input to the GTAO control component.
Signal scaling is done in the GTAO component menus provided.
9.9

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REAL TIME DIGITAL SIMULATOR

CONTROLS LIBRARY MANUAL

EXAC2 AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20

5 COMPLEX NUMBER MATH FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1

7A.2 GSSE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7A.2

8.6 MultiFunction Differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.36

Rev. 02: Oct 04

1.1 INTRODUCING THE REALTIME DIGITAL SIMULATOR ( RTDS )

3PC PROCESSOR CARDS

SHARC Control Component Representation

Simple Automatic Voltage Regulator

1.3 LIST OF CONTROLS LIBRARY FUNCTION BLOCKS (BY GROUP)

RTDS TECHNOLOGIES INC.

Fixed Rate Limits

RTDS TECHNOLOGIES INC.

TIMER AND COUNTER GROUP

Phase Locked Loop (type1)

SIGNAL GENERATOR GROUP

Exponential Load Calculation

Rev. 02: Oct. 04

CONTROLS COMPILER USAGE

input signals are identified by

Processor number and priority can be displayed in RSCAD/Draft by a left clickand

RTDS TECHNOLOGIES INC.

RTDS TECHNOLOGIES INC.

Node Voltage N2 and Branch Current I12

IMPORT/EXPORT components are

SOURCE MODEL: MONITORING SUBMENU

RTDS TECHNOLOGIES INC.

Information regarding the allocation and ordering

A list of all input and output variables and their

The default Batch file for RSCAD/RunTime. This

One such file for each subsystem. The _r# refers

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Signals S1 and S2 may be monitored using RSCAD/RunTime

Create > Plot

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RSCAD/Draft Input Components

Select one of these

front panel analogue output port

6 channel 16 bit A/D input board

Read signal from digital input port

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Same case as above run

FLOATING POINT RESOLUTION

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RTDS RACK BACKPLANE

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Signal S3 based on S2(t), S2(t) based on S1(t)

Signal S3 based on S2(t), S2(t) based on S1(tt)

Proc=1 (3PC 1A) Proc=1 (3PC 1A)

Proc=4 (3PC 2A)

Proc #1 (3PC 1A)

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Rev. 03: Aug 07

Control components are accessed from RSCAD/Draft 3PC_Controls library. The

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2 or 3 Input Summing Junction

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2 or 3 Input Multiplication Junction