ISSN 10637397, Russian Microelectronics, 2010, Vol. 39, No. 3, pp. 210219. Pleiades Publishing, Ltd., 2010.

Original Russian Text A.S. Korotkov, M.M. Pilipko, D.V. Morozov, J. Hauer, 2010, published in Mikroelektronika, 2010, Vol. 39, No. 3, pp. 230240

CIRCUIT ANALYSIS AND SYNTHESIS

DeltaSigma Modulator with a 50MHz Sampling Rate

Implemented in 0.18m CMOS Technology
A. S. Korotkova, M. M. Pilipkoa, D. V. Morozova, and J. Hauerb
a
b

St. Petersburg State Technical University, St. Petersburg, Russia

Fraunhofer Institute for Integrated Circuits, Erlangen, Germany
email: korotkovr@phf.spbstu.ru
email: johann.hauer@iis.fraunhofer.de
Received February 16, 2009

AbstractThe results are presented of a design effort concerned with a deltasigma modulator with a 50
MHz clock rate and a 128 oversampling ratio. Its prototype is fabricated in 0.18m CMOS technology and
is powered by a 1.8V unipolar supply. It provides a 9bit resolution, while consuming 33 mW of power.
DOI: 10.1134/S106373971003008X

1. INTRODUCTION
Tracking analogtodigital converters (ADCs)
using deltasigma modulation compare favorably
with the other types of ADC in terms of power con
sumption and size [1, 2]. Deltasigma ADCs have
recently become popular in mobile phones. For exam
ple, singleconversion receivers with zero intermedi
ate frequency employ a deltasigma ADC resolution
of 812 bits to convert constant signal levels in the
communication channel.
Deltasigma ADCs are based on the concept of
delta modulation, in which a continuous signal under
goes clocked conversion into a sequence of voltage
pulses, whose height represents the sign of the incre
ment of the original signal at each clock instant, rela
tive to the preceding value of the signal. If a signal has
a uniform spectrum or contains a constant compo
nent, its conversion involves a deltasigma modulator,
which operates in oversampling mode, i.e., well above
the Nyquist rate, and therefore requires a decimation
filter. This tends to be implemented as a standard
design, e.g., a finiteimpulseresponse filter. However,
the performance of a deltasigma ADC is mainly
determined by its deltasigma modulator, since the
latter is solely responsible for analogtodigital con
version, the decimation filter reducing output pulse
rate and doing serialtoparallel code conversion. This
consideration explains why designing a deltasigma
modulator plays such an important part in building a
deltasigma ADC. Theoretical research on delta
sigma modulators was reviewed by Korotkov and
Telenkov [1]. Note that a deltasigma modulator can
be implemented from a programmable analog inte
grated circuit [3] or as an applicationspecific inte
grated circuit (ASIC).
This paper describes a newly designed deltasigma
modulator having a clock rate of 50 MHz, an oversam

pling index of 128, a dynamic range of 56 dB, and a

supply voltage of 1.8 V. The device is fabricated as an
ASIC by the UMC 180 nm mixedmode/RF 1P6M
process.
The paper is organized as follows. Section 2
describes the structure of the deltasigma modulator,
designed as a balanced switchedcapacitor (SC) cir
cuit; it also deals with the configurations of its main
units. Section 3 presents simulation results for the
modulator as a whole and for each of its main units,
obtained at the circuit and the component level,
respectively. Section 4 presents test results for the
actual modulator. The conclusions are given in Sec
tion 5.
2. STRUCTURE OF THE DELTASIGMA
MODULATOR
Secondorder deltasigma modulators are proba
bly the most common category of the device, superior
in dynamic range to firstorder circuits. At the core of
any deltasigma modulator lie integrators; they are
usually implemented in CMOS technology as SC cir
cuits. An example of a circuit configuration proposed
for such an integrator can be found in a paper by
Rogatkin [4]. Its feasibility was substantiated by com
puter simulation using Cadence Design Systems soft
ware.
Figure 1 shows a block diagram of a secondorder
balanced deltasigma modulator [5, 6]. Its balanced
input port comprises an inverting and a noninverting
terminal, designated in+ and in, respectively; its
unbalanced output port is designated out. The modu
lator is made up of two integrators, a comparator I3,
and feedback loops. These include switches s1 and s2
for applying one of two reference node voltages, vref +
and vref, depending on comparatoroutput polarity

210

in out+

ph1
ph1

C5

C7

C9

out vref
vref+

I3

I2

ph1
ph2
ph2

C6

in+ out

ph2
ph2

agnd

C3

agnd
in

ph1
ph1

C2

in+

ph2

211

S1

ph2
ph1

I1

ph1
C1

ph2

agnd

DELTASIGMA MODULATOR WITH A 50MHz SAMPLING RATE

in+ out

in+

in out+

in

out

out

ph1

ph1
agnd

ph1
agnd

agnd

C4

ph2

C10

C8
ph2

ph2
S2

out vref+
vref

Fig. 1. Structure of the secondorder balanced deltasigma modulator.

vdd
M5

M7

M3

M4

vbp

vbp
M1

M9

in

vbn

vbn

vb1
M11

M8

M2

in+

out

M6

out+
M10

M13

vcmfb1

vcmfb1

M12

vss

Fig. 2. Operational transconductance amplifier.

and relevant arm. The integrators are based on ampli

fiers I1 and I2, respectively, and use twophase SC cir
cuits, with the respective phases denoted by ph1 and
ph2. The node whose voltage corresponds to the dc
operating point is designated agnd.
When used as a part of a deltasigma modulator, an
operational amplifier (opamp) is not expected to have
resistive load, so its output impedance does not need
to be small. Moreover, there is no output voltage fol
lower in most opamps designed for the purpose, for
which reason these do not belong to voltage sources,
but rather fall in the category of voltagecontrolled
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current sources, or operational transconductance

amplifiers (OTAs). (The categories and features of on
chip amplifiers in current use are treated in detail in a
survey by Korotkov and Morozov [7].) It is important
that an OTA intended for insertion into a deltasigma
modulator have an adequate bandwidth and a suffi
ciently high voltage gain at the lower frequencies,
because the former property determines the modula
tor bandwidth, and the latter makes for lower quanti
zation noise.
Figure 2 represents an OTA that makes a balanced
circuit with respect to both input and output, with the
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KOROTKOV et al.
agnd

212

vcm1

ph2

ph2

ph2

out

ph1

C4

ph1

C2

ph1

vcmfb1

ph1
C3

out+

C1

ph2

Fig. 3. Feedback loop.

parts forming the reference voltages being omitted [5].

In Fig. 2, vdd and vss designate supplyvoltage nodes;
vb1, vbn, vbp, and vcmfb1 designate referencevoltage
nodes; in+ and in refer to an inverting and a nonin
verting input terminal, respectively; and out+ and
out to an inverting and a noninverting output termi
nal, respectively. The OTA contains two input transis
tors, M1 and M2; two current mirrors based on the
transistors M3 and M5 and the transistors M4 and M6,

respectively; two pairs of output transistors, M7M9

and M8M10, respectively; two transistors, M11 and
M12, for commonmode voltage rejection at the out
put; and a current source built around the transistor
M13. The current mirrors provide the reference volt
ages at vb1, vbn, and vbp.
For the OTA in Fig. 2, the voltage gain AV is found
to be given by

gm1 gm5 gm7 gm9

A V = 
 ,
g m3 ( g m 7 g D9 g D11 + g m 9 g D5 g D7 + g m 7 g m 9 sC L )
where gmi is the transconductance of the ith and
(i + 1)th transistors with i = 1, 3, 5, 7, 9; gDi is the
channel conductance of the ith and (i + 1)th transis
tors with i = 5, 7, 9, 11; CL = C L+ = C L are the load
capacitances connected to the noninverting and
inverting output nodes; and p is the complex frequency.
Figure 3 depicts a feedback loop that delivers a suit
able signal to the vcmfb1 node in Fig. 2 [5, 8]. The
nodes out and out+ are respectively connected to an
inverting and a noninverting output terminal of the
OTA. The voltage at vcmfb1 is produced by a resistive
divider built around the SCs C1 and C2 (between out+
and out). The capacitors C3 and C4 are introduced
for feedback smoothing; they are superior to C1 and
C2 in value. When calculating the integrator, account
should be taken of the contribution made by the
capacitor pairs C1, C3 and C2, C4 to the respective
loads of the noninverting and the inverting output ter
minal. Current mirrors provide the reference voltage
at vcm1.
SC circuits may suffer from clock feedthrough via
the parasitic capacitances of the switching MOSFETs.
Adding appropriate MOSFETs to the integrator
switches has been proposed as a measure to reduce the
phenomenon [9]. This approach is illustrated by
Fig. 4. It uses vc+ and vc to denote nodes to which

clock pulses of opposite polarity are applied; Wn and

Ln to denote the channel width and length, respec
tively, of an nMOSFET; and Wp and Lp to denote
those of a pMOSFET. The switch is built around the
transistors M1 and M2, with the M3, M5 and M4, M6
pairs added to suppress clock feedthrough. Each addi
tional transistor has its source and drain terminals
connected together to form a capacitor made up of the
gatesource and gatedrain parasitic capacitances
connected in parallel. The respective parasitic capaci
tances of each main MOSFET and the appropriate
additional MOSFET cancel each other out to suppress
clock feedthrough if the channel of the latter MOS
FET is as long and half as wide as that of the former;
the way clock pulses are applied is essential.
Figure 5 presents the circuit configuration of the
comparator, whose purpose is to produce output
binary codes. It is a balanced circuit with respect to the
input. The comparator consists of the following units,
connected in series: an input stage built around the
transistors M1M7, a bistable cell based on the tran
sistors M8M17 and on a switch that is clocked by the
phase ph2, CMOS inverters using the transistors
M18M25, and the Dtype flipflop I1.
The transistors M1M5 form a differential stage
with a balanced output port at n+ and n. The transis

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vc+

Wn/Ln

M6

M1

M2

DELTASIGMA MODULATOR WITH A 50MHz SAMPLING RATE

2Wn/Ln

213

vss

Wn/Ln

2
M4

M3

2Wp/Lp

Wp/Lp
vc

M5

Wp/Lp
vdd

Fig. 4. CMOS switch with added MOSFETs.

vdd
M4

vcmfb2

n+

M8 M9

M10 M11

nx

nx+

M8
ph2
M7

M18

M22

M19

M23

I1
D

in

vdd

M3

M2

M12

ph2

M13

in+
nq+

M20

M24

M21

M25

out

vss

Q
M1

nq
ph1
ph2
vb2

M5

M14 M15

M16M17

vss

Fig. 5. Comparator.

tors M6 and M7 are diodeconnected to make a lim

iter for the output. The nodes vcmfb2 and vb2 are used
to connect a feedback loop and a bias voltage source,
respectively. The feedback is provided by a similar cir
cuit to that in Fig. 3; however, the nodes out+ and
out are connected to the nodes n+ and n in the com
parator (Fig. 5), and the nodes vcm1 and vcmfb1 are
replaced with vcm2 and vcmfb2, respectively. Current
mirrors provide the reference voltages at vcm2 and vb2.
The circuit configuration of the bistable cell is as in
[8]. In Fig. 5, n+ and n make up its input port, and
nq+ and nq refer to its output port. Again, ph1 and
ph2 denote the respective phases of the clocking
scheme. The phase ph1 is designed to produce appro
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priate voltages at nq+ and nq. During the phase ph2,

the switch closes to connect n+ and n together and to
make the cell change state; as a result, the voltages at
nx+ and nx become equal to that at vdd. The switch
concerned is as in Fig. 4.
Each output terminal of the bistable cell is con
nected to two CMOS inverters in series, which provide
buffering and ensure that the output terminals have the
same capacitive load. The inverter based on M22 and
M23 has its output terminal connected to the data
input of the Dtype flipflop, which is edgetriggered
by the ph2 pulses. The flipflop is designed in a stan
dard fashion.
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3. SIMULATION OF THE DELTASIGMA

MODULATOR
The performance of a deltasigma modulator is
mainly evaluated in terms of its signaltonoise ratio
(SNR). This property is calculated from the output
spectrum, which has to be simulated over tens of thou
sands of periods for the input signal. With oversam
pling, it is not feasible to simulate a deltasigma mod
ulator at component level, the clock rate being more
than 100 times as high as the maximum input fre
quency. The reason for the considerable length of
computing time required in that case is that the differ
ential equations employed have to be integrated with a
stepsize equal to the smallest time constant of the cir
cuit components. This explains why circuitlevel
(conductancematrix) simulations are so popular
when dealing with deltasigma modulators [10, 11].
They indeed take reasonable computing time.
A feature of circuitlevel simulations is that they
assume a particular signal being applied to the modu
lator. If s(t) = Umsint is selected, the output
sequence will show repeatability, reflecting the period
icity of the quantization noise. This implies more har
monic components in the output spectrum. The cor
relation between the quantization noise and the input
signal in this case makes it impossible to attenuate the
additional harmonic components by averaging. Nev
ertheless, the noisesignal correlation can be reduced

by adding white noise to the input, a method called

randomization [12]. It is recommended that the rms
value of the white noise lie between onethird and one
times the value of the least significant bit of the ADC.
Since a deltasigma modulator is merely the first unit
in an ADC, the value of the least significant bit for the
ADC should be obtained from a wellknown equation
for the dynamic range DR of an Nbit ADC:
DR = 6.02N + 1.76 (dB)
With DR = 56 dB, this equation implies N = 9 for
the deltasigma modulator considered.
The circuitlevel simulation of the deltasigma
modulator (Fig. 1) involved the construction of a spe
cific equivalent network for each of the two phases, as
in [10, 11]. Each of the OTAs was represented by a
twoterminal model based on voltagecontrolled volt
age sources. It was described in terms of the respective
gains of the first and the second stage, the input and
the output conductances, and the capacitances and
conductances that determined the frequencies associ
ated with the first and the second pole. Each switch
was represented by a conductance whose value was
subject to change with state. Conductance and capac
itance matrices were constructed from equivalent net
works. The capacitances were assigned the following
values:

C1 = C2 = 2 pF; C3 = C4 = 8 pF; C5 = C6 = 1.6 pF; C7 = C8 = 0.8 pF; C9 = C10 = 4.8 pF.

subject to the condition C1/C3 = 1/4 and C5/C7 =
2/1 [13].
The reference voltages at vref + and vref were 1.8
and 0 V, respectively, and 0.9 V relative to agnd. The
voltage at agnd was half as high as the supply voltage,
and so was equal to 0.9 V. The output spectrum was
computed by a 220point discrete Fourier transform.
Figure 6 displays the simulated output spectrum of
the deltasigma modulator at Um = 0.45 V and /2=
200 kHz. As noted above, the quantization noise is
correlated with the input in this case. Accordingly,
white noise was then added to the same sinusoidal sig
nal, with its rms value set to the value of the least sig
nificant bit, namely, 1.8 mV. The latter was calculated
as the ratio of 2Um to the total number of quantization
levels, which was 29. Figures 7 and 8 represent the
input and output spectra, respectively.
Figure 9 shows output SNR against input signal
strength for the deltasigma modulator, its dynamic
range being 66 dB.
The circuitlevel simulation yielded the following
values for the OTA model parameters. The respective
gains of the first and the second stage were 25 and 40.
The input and output conductances were 10 nS and 2
mS, respectively. The capacitance and conductance
associated with the first pole were 0.3 pF and 940 nS,

respectively. Those associated with the second pole

were 0.3 pF and 700 S, respectively. The switches
were found to have a conductance of 2.5 mS or 10 nS
when closed or open, respectively.
The OTA (Fig. 2) and the comparator (Fig. 5) were
simulated with Cadence Design Systems software.
Figure 10 presents the magnitude response and the
phase response for the OTA, which was found to have
a 60dB gain, a 500MHz unitygain frequency, and a
50degree phase margin. Its current consumption was
estimated at 8 mA. The MOSFET channel widths and
lengths (Fig. 2) in micrometers were taken to be as fol
lows: W1/L1 = W2/L2 = 400/0.4; W3/L3 = W4/L4 =
75/0.4; W5/L5 = W6/L6 = 150/0.4; W7/L7 = W8/L8 =
450/0.4; W9/L9 = W10/L10 = 450/1; W11/L11 = W12/L12 =
50/0.4; W13/L13 = 30/2. The fabrication process
selected was such as to produce the transistors M1
M12 with reduced threshold voltages. The feedback
loop (Fig. 3) had C1 = C2 = 0.2 pF and C3 = C4 =
1 pF. The switches were as in Fig. 4, with Wn = 1 m,
Ln = 0.35 [mu]m, Wp = 4 m, and Lp = 0.35 m.
In the comparator (Fig. 5), the MOSFET channel
widths and lengths in micrometers were taken to be as
follows: W1/L1 = W2/L2 = 50/1; W3/L3 = W4/L4 = 40/1;
W5/L5 = 16/2; W6/L6 = W7/L7 = 10/0.24; W8/L8 =
W11/L11 = 3/0.4; W9/L9 = W10/L10 = W12/L12 = W13/L13

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DELTASIGMA MODULATOR WITH A 50MHz SAMPLING RATE

215

0
20

dB

40
60
80
100

120
102

103

104
105
Frequency, Hz

106

107

Fig. 6. Simulated output spectrum of the deltasigma modulator with a sinusoidal input.

0
20

40
60
80
100
120
102

103

104
105
Frequency, Hz

106

107

Fig. 7. Input spectrum of the deltasigma modulator in the case of the sinusoidal signal of Fig. 6 with additive white noise.

= 0.9/0.4; W14/L14 = W17/L17 = 1.8/0.4; W15/L15 =

W16/L16 = 0.54/0.4; W18/L18 = W20/L20 = 1.6/0.24;
W19/L19 = W21/L21 = 0.8/0.24; W22/L22 = W24/L24 =
3.2/0.24; W23/L23 = W25/L25 = 1.6/0.24. The fabrica
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tion process selected was such as to produce the tran

sistors M1M4 and M6M25 with reduced threshold
voltages. The capacitor values of the feedback loop
were set as with the OTA.

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KOROTKOV et al.
0

20

dB

40

60
80

100

120 2
10

103

104

105
Frequency, Hz

106

107

Fig. 8. Simulated output spectrum of the deltasigma modulator in response to the input displayed in Fig. 7.

4. TESTING A PROTOTYPE
OF THE DELTASIGMA MODULATOR
Figure 11 presents a photograph of a prototype chip
layout for the deltasigma modulator, implemented in
0.18m CMOS technology. The prototype was tested
in the arrangement shown in Fig. 12 (the contact pads
are designated as in Fig. 11). The contact pads vddd

70

The output bit stream was recorded with an Agilent

16702A digital logic analyzer, and was processed with
MATLAB. Testing was performed at a 50MHz clock
rate on a 200kHz balanced sinusoidal signal with
amplitude variable between 0.05 and 0.45 V. Figure 13
shows the output spectrum for a 0.45V input, com
puted by a 220point discrete Fourier transform. Note
the close agreement with the simulated spectrum in
Fig. 8. The second harmonic should be caused by the
input generator. The inferior performance of the pro
totype compared with its simulation model is mainly
attributable to the internal noise of the modulator
components, clock feedthrough, instrumentation
noise, and fabricationprocess spread.

Output SNR, dB.

60
50
40
30
20
10
0
10
70

and vssd were used to connect the power supply of a

50MHz onchip digital clock, which was connected
to the clock pad with the pd pad grounded. In produc
ing appropriate reference voltages for the OTAs and
the comparator, it was possible to set the current
through the currentmirrorbased circuits by means of
an on or offchip current source, with the cib pad
connected to the ground or the positive rail, respec
tively (the offchip source was connected to ib). At the
output the logic 1 voltage level, 1.8 V, was set by a volt
age source connected to v3io.

60

50 40 30 20
Input signal strength, dB

10

Fig. 9. Simulated output SNR vs. input signal strength for

the deltasigma modulator.

A measured relationship of output SNR to input

amplitude yielded a dynamic range of 56 dB, implying
a 9bit resolution. The prototype was found to con
sume 33 mW of power.
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DELTASIGMA MODULATOR WITH A 50MHz SAMPLING RATE

217

70
60
50
dB

40
30
20
10
0
10
210
180
Degrees

150
120
90
60
30
0
100

101

102

103

104

105

106

107

Hz
Fig. 10. Simulated magnitude response and phase response for the OTA.

Fig. 11. Prototype chip layout for the deltasigma modulator.

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108

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KOROTKOV et al.

218

1.8 V 1.8 V
0.9 V
+
+

vdd

vref+

agnd

1.8 V
+

vref

vddd

in+

v3io

in

out

1.8 V
+

vss

ib

vssd

cib

pd

Agilent 16702A
Logic Analysis
System

clock

Fig. 12. Test setup for the prototype deltasigma modulator.

20

dB

40

60

80

100

120
102

103

104

105
Frequency, Hz

106

107

Fig. 13. Example of a measured output spectrum from the prototype deltasigma modulator.

5. CONCLUSIONS
The results are presented of a design effort con
cerned with a switchedcapacitor balanced delta
sigma modulator with a 50MHz clock rate and a 128

oversampling index. Its prototype is fabricated in a

0.18[mu]m CMOS technology, powered by a 1.8V
unidirectional supply. When tested on balanced sinu
soidal signals with amplitude reaching 0.45 V, the pro
totype shows a 56dB dynamic range, implying 9bit

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DELTASIGMA MODULATOR WITH A 50MHz SAMPLING RATE

resolution. It consumes 33 mW of power. The tests

have substantiated its computer simulations and pro
vided evidence for the feasibility of the design.

7.

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