ADC R2013 Lab Manual PDF

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EC6311 Analog and Digital Lab
RAJALAKSHMI INSTITUTE OF TECHNOLOGY

CHENNAI 600 124
DEPARTMENT
of
ELECTRONICS AND COMMUNICATION ENGINEERING
Regulation 2013
Academic Year: 2014-2015
EC6311 ANALOG AND DIGITAL LABORATORY

STUDENT MANUAL
Faculty In-charge
Mr.S.Rajalingam /AP/ECE
Mr.L.Franklin Telfer/AP/ECE
Mr.V.S.Vignesh/AP/ECE
Lab Assistant
Ms.T.Jeevitha
Semester 03
Department of ECE
Rajalakshmi Institute of Technology
www.Vidyarthiplus.com
Page 1
Semester 03
Department of ECE
Page 2
SYLLABUS
EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS:
1. Frequency Response of CE / CB / CC amplifier
2. Frequency response of CS Amplifiers
3. Darlington Amplifier
4. Differential Amplifiers- Transfer characteristic.
5. CMRR Measurement
6. Cascode / Cascade amplifier
7. Determination of bandwidth of single stage and multistage amplifiers
8. Spice Simulation of Common Emitter and Common Source amplifiers
LIST OF DIGITAL EXPERIMENTS

9. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa
10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
11. Design and implementation of Multiplexer and De-multiplexer using logic gates
12. Design and implementation of encoder and decoder using logic gates
13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
14. Design and implementation of 3-bit synchronous up/down counter
15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
Semester 03
Department of ECE
Page 3
Semester 03
Department of ECE
Page 4
SL NO
LIST OF EXPERIMENTS
1.
2.
3.
4.
5.
6.
7.
8.
LIST OF ANALOG EXPERIMENTS

Introduction
- Study of electronic components [ Active and Passive]
- Study of Signal Generator, CRO, Bread board and Regulated Power supply
- Study of transistor parameters using Transistor Data Sheets
Design and Analysis of Common Emitter Amplifier
- To Determine a. DC characters tics b. AC characteristics c. Gain d. Bandwidth
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier(Additional)
Design and Analysis of Common Collector Amplifier
- To Determine a. DC characteristics b. AC characteristics c. Gain d. Bandwidth
Design and Analysis of Common Base Amplifier
Design and Analysis of Darlington Amplifier
Design and Analysis of Common Source Amplifier
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier (Additional)
Design and Analysis of Cascade Amplifier
Design and Analysis of Cascode Amplifier
Design and Analysis of Differential Amplifier
- To Determine a. Transfer characteristics b. CMRR
13.
14.
Pspice Simulation of Common Emitter Amplifier

a. Gain b. Bandwidth
Pspice Simulation of Common source Amplifier
a. Gain b. Bandwidth
LIST OF DIGITAL EXPERIMENTS
Introduction
- Study of Digital IC's using IC data sheets
- Study of IC trainer Kit
Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa
Design and implementation of 4 bit binary Adder/ Subtractor and
BCD adder using IC 7483
Design and implementation of Multiplexer and De-multiplexer using logic gates
Design and implementation of encoder and decoder using logic gates
15.
Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
16.
17.
Design and implementation of 3-bit synchronous up/down counter

Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
9.
10.
11.
12.
Semester 03
Department of ECE
Page 5
Semester 03
Department of ECE
Page 6

INDEX
S.No
Date
Experiment Names
Pg No
Faculty Sign
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
Semester 03
Department of ECE
Page 7

Common Emitter Amplifier circuit diagram
CE Amplifier without Feedback :
CE Amplifier with Feedback:
Semester 03
Department of ECE
Page 8

COMMON EMITTER AMPLIFIER
EXPERIMENT: 01
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using voltage divider bias and to
determine its:
a. DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product
2. REQUIREMENTS:
S.no
Requirement
Name
Transistor [Active]
Resistor [Passive]
Components
Range
BC 107
61k, 10k, 1k,
4.7k
Quantity
1
1,1,1,2
Capacitor [Passive]
10f, 100f
2,1
Signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
6
supply
7
8
Semester 03
Regulated power
Bread Board
Accessories
Connecting Wires
Department of ECE
Single strand
1
as required
Page 9

DESIGN PROCEDURE:
Given specifications:
VCC= 10V, I C=1.2mA, AV= 30, hFE= 100
(i) To calculate RC:
The voltage gain is given by,
AV= -hfe (RC|| RF) / hie
h ie = re
re = 26mV / IE = 26mV / 1.2mA = 21.6
hie = 150 x 21.6 =3.2K
Apply KVL to output loop,
VCC= IC RC + VCE+ IE RE ----- (1)
Where VE = IE RE (IC= IE)
VE= VCC / 10= 1V
Therefore RE= 1/1.2x10-3=0.8K= 1K
VCE= VCC/2= 5V
From equation (1), R C= ( Vcc - VCE - IE RE / IC ) = ________
(ii) To calculate R1&R2:

S=1+ (RB/RE)
Where RE = 1 K and S = 9
RB= (S-1) RE= (R1 || R2) =1K
RB=( R 1R2 ) /( R1+ R2) ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC (R2 / R1+ R2 )------- (3)
Solving equation (2) & (3),
R1= ____ & R2= ______
(iii) Input coupling capacitor :

Xci= Rif / 10= 2.4 (since XCi << Rif)
Ci = 1/ 2fXCi = _____
(iv) Output coupling capacitor:
XCO= Rof /10= 5.2
CO = 1/ 2fXCO = _____
Semester 03
Department of ECE
Page 10

3.
THEORY:
A common emitter amplifier is type of BJT amplifier which increases the voltage level of the
applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 K) and a fairly high
output resistance. Therefore it is generally used to drive medium to high resistance loads. It is
typically used in applications where a small voltage signal needs to be amplified to a large
voltage signal like radio receivers.
The input signal Vin is applied to base emitter junction of the transistor and amplifier output
Vo is taken across collector terminal. Transistor is maintained at the active region by using the
resistors R1,R2 and Rc. A very small change in base current produces a much larger change in
collector current. The output Vo of the common emitter amplifier is 180 degrees out of phase
with the applied the input signal Vin.
4.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for at least 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi) dB
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
where f1 lower cut-off frequency
f2 upper cut-off frequency
Semester 03
Department of ECE
Page 11

a. DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
ii)
Open circuit the capacitors since it blocks DC voltage
iii)
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
iv)
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
= _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
Semester 03
Department of ECE
Page 12
b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
i.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
ii.
By increasing the amplitude of the input signal find maximum input voltage
V
MSH
across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
MODEL GRAPH:
Semester 03
Department of ECE
Page 13

5. TABULATION [Without Feedback ] :
Input voltage (Vin=V MSH/2) =____________V
S. NO
FREQUENCY [Hz]
OUTPUT VOLTAGE [ VO]
GAIN= 20 log Vo/Vin
in Volts
dB
1.
2.
100
3.
500
4.
600
5.
800
6.
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
Department of ECE
Page 14

With Feedback :
Input voltage (Vin=V MSH/2) =____________ V
S. NO
FREQUENCY [Hz]
OUTPUT VOLTAGE [
VO] in Volts
GAIN= 20 log ( vo/vin )

dB
1.
0
2.
100
3.
500
4.
600
5.
800
6.
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
Department of ECE
Page 15
WORKSHEET
Semester 03
Department of ECE
Page 16
6. RESULT:
INFERENCE:
The Common Emitter Amplifier was constructed and the following results were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
Semester 03
Department of ECE
Page 17
Common Collector Amplifier Circuit Diagram:
MODEL GRAPH:
Semester 03
Department of ECE
Page 18

COMMON COLLECTOR AMPLIFIER
EXPERIMENT: 02
DATE:
1. OBJECTIVE:
To Design and Construct a Common collector Amplifier and to determine its:
a. DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product using frequency response curve
2.
REQUIREMENTS:
S.No
Requirement
Range
Quantity
BC 107
Signal Generator
0-3MHz
CRO
0-30MHz
Regulated power supply
0-30 V
Single strand
as required
Name
Transistor [Active]
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Bread Board
Accessories
Semester 03
Connecting Wires
Department of ECE
Page 19
Design of Common collector amplifier:
VCC= 15V, I C=1.2mA, hie = 2.1k hFE= 75 hib= 27.6
(i)
To calculate Zb ( Device input impedance )

Zb = hie + hfe ( RE || RL)
Assume RE = 4.7 K and RL= 3.3 K
Zb = 2.1k + 75 (4.7 K || 3.3 K) = __________
(ii)
To calculate Zi ( Input Impedance )

Zi = R1 || R2 || Zb
Assume R1= R2= 10k
Zi = _______
(iii) To Calculate Voltage gain Av :

Av = [ ( RE || RL ) / ( hib + ( RE || RL) ) ]
Av = _____
3. THEORY:
Semester 03
Department of ECE
Page 20

A common collector amplifier is a unity gain BJT amplifier used for impedance matching and as
a buffer amplifier.
Circuit Operation :
When a positive half-cycle of the input signal is applied to Base emitter
junction of transistor the forward bias voltage Vbe is increased, which in turn increases the base
current Ib of transistor. Since emitter current Ie is directly proportional to I b the voltage drop across
the Emitter Ve= IeRe is increased, hence, output voltage Vo is increased, thus, we get positive halfcycle of the output. It means that a positive-going input signal results in a positive going output
signal and, consequently, the input and output signals are in phase with each other. Similarly the
negative half cycle of input signal produces negative going output signal.
Characteristics of a CC Amplifier
1. high input impedance (20-500 K )
2. low output impedance (50-1000 )
3. high current gain of (1 + ) i.e. 50 500
4. voltage gain of less than 1 (unity)
5. power gain of 10 to 20 dB
6. no phase reversal of the input signal
4. PROCEDURE:
5. The voltage gain is calculated as Av = 20log (V0/Vin)
Where
f1 - lower cut-off frequency

f2 - upper cut-off frequency
Semester 03
Department of ECE
Page 21

a.
DC ANALYSIS:
Steps:
i)
ii)
iii)
iv)
generator
junction. VBE
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
Procedure:
i.
ii.
Apply input signal Vin = 1 V of 1Khz frequency to the CC amplifier using the
V MSH across VBE at which the sinusoidal signal gets distorted during the
V MSH = _________ volts
Semester 03
Department of ECE
Page 22

5. TABULATION
Input voltage (Vin=V MSH /2) =____________ volts
S. NO
FREQUENCY
OUTPUT VOLTAGE
[Hz]
[ VO] in Volts
1.
2.
100
3.
500
4.
600
5.
800
6.
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
GAIN= 20 log vo/vin dB
Department of ECE
Page 23

WORKSHEET
Semester 03
Department of ECE
Page 24
6. RESULT:
INFERENCE:
The common collector amplifier was constructed and input resistance and gain were determined.
The results are found to be as given below
a) Gain of the amplifier (in dB) :
b) Bandwidth of the amplifier (in Hz) :
c) Gain-Bandwidth product (GBWP) :
CONCLUSION:
Semester 03
Department of ECE
Page 25
Common Base Amplifier Circuit Diagram:
MODEL GRAPH:
Semester 03
Department of ECE
Page 26

COMMON BASE AMPLIFIER
EXPERIMENT:03
DATE:
1. OBJECTIVE:
To Design and Construct a Common Base Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Semester 03
Connecting Wires
Department of ECE
Single strand
as required
Page 27

DESIGN PROCEDURE:
Given Transistor specifications:
hie = 2.1k ; hfe = 75 ; hfb =0.987
i) To find Device input impedance :
hib = ( hie / (1+ hfe))
hib = ____
ii) To find Circuit input impedance (Zi) :
Zi = hib || Re ,Where Re= 2.2 k
Zi = _____
iii) To find Circuit output impedance (Zo) :
Zo = Rc ; where Rc = 4.7 k
iv) To find Voltage Gain (Av) :

Av = [ hfb (Rc || RL) / hib ]
Where RL= 10k
Av = _____
Semester 03
Department of ECE
Page 28

3. THEORY:
A common base amplifier is type of BJT amplifier which increases the voltage level of the
The Common base amplifier typically has good voltage gain and relatively high output
impedance. But the Common base amplifier unlike CE amplifier has very low input impedance which
makes it unsuitable for most voltage amplifier. It is typically used used as an active load for a
cascode amplifier and also as a current follower circuit.
Circuit Opeartion:
A positive-going signal voltage at the input of a CB pushes the transistor emitter in a positive
direction while the base voltage remains fixed, hence Vbe reduces. The reduction in VBE results in
reduction in VRC, consequently VCE increases. The rise in collector voltage effectively rises the output
voltage. The positive going pulse at the input produces a positive-going output, hence the there is no
phase shift from input to output in CB circuit. In the same way the negative-going input produces a
negative-going output.
4. PROCEDURE:
2. Determine the Q-point of the CB amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using
AC analysis.
incremental steps and note down the corresponding output voltage Vo for atleast 20
5. The voltage gain is calculated as Av = 20log (V0/Vi)
where f1 lower cut-off frequency
f2 upper cut-off frequency
Semester 03
Department of ECE
Page 29

a.
DC ANALYSIS:
Steps:
i)
generator
junction. VBE
ii)
iii)
iv)
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
Procedure:
i.
ii.
V MSH = _________ volts
Semester 03
Department of ECE
Page 30

5. TABULATION
Input voltage (Vin=V MSH / 2) =____________V
S. NO
FREQUENCY
[Hz]
17.
18.
100
19.
500
20.
600
21.
800
22.
OUTPUT VOLTAGE
[ VO] in Volts
GAIN= 20 log Vo/ vin

dB
900
23.
1 KHz
24.
100 KHz
25.
500 KHz
26.
600 KHz
27.
700 KHz
28.
800 KHz
29.
900 KHz
30.
1 MHz
31.
1.1 MHz
32.
1.5 MHz
Semester 03
Department of ECE
Page 31

WORKSHEET
Semester 03
Department of ECE
Page 32

6. RESULT:
INFERENCE:
The Common base amplifier was constructed and input resistance and gain were determined. The
results are found to be as given below
CONCLUSION:
Semester 03
Department of ECE
Page 33

Darlington Amplifier Circuit Diagram:
MODEL GRAPH:
Semester 03
Department of ECE
Page 34

DARLINGTON AMPLIFIER
EXPERIMENT:04
DATE:
1. OBJECTIVE:
To Design and Construct a BJT amplifier using Darlington pair and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BC 107
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
Bread Board
Accessories
8
Semester 03
Connecting Wires
Department of ECE
Single strand
as required
Page 35

DESIGN PROCEDURE:
VCC= 12V, IC=1.2mA, AV= 30, f1 = 300 HZ, f2 = 500KHZ, hFE= 150
Assume R2 = 10K and Ic = 1mA.
Since voltage amplification is done in the Darlington transistor amplifier circuit, we assume
equal drops across VCE and load resistance RC. The ICQ = 1mA is assumed.
Drop across Re is assumed to be 1V.
The drop across VCE with a supply of 1.2 V is given by
12 1 = 1V.
It is equal to VRC & VCE = 5.5V x RC
Therefore, Rc = 5.5 K (4.7 K) ; IC = 1mA
(ii) To calculate R1&R2:
S=1+ (RB/RE)
RB= (S-1) RE= (R1 || R2) =1K
RB=( R 1R2 ) /( R1+ R2) ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC (R2 / R1+ R2 )------- (3)
Solving equation (2) & (3),
Since R2=10k , the other resistor is found to be, R1= 47k
(iii) To Find Cin :
Cin = * 1 / 2f1 (Zi / 10) ]
Where Zi = ( RB || hie ) = 1.1K and
f1 = Lower cut-off frequency= 25HZ
= 57.9F
(iv) To Find CO :
C0 = * 1 / 2f2 ( (RC + RL) / 10) ]
Where RC = 9K; RL = 90K and
f2 = Upper cut-off frequency= 500KHZ
= 64 F
Semester 03
Department of ECE
Page 36

3. THEORY:
The Darlington transistor (often called a Darlington pair) is compound structure consisting of
two bipolar transistors connected in such a way that the First transistor does current
amplification of input signal and then it will be fed to the second transistor which performs
voltage amplification.
This configuration gives a much higher gain than each transistor taken separately and, in the
case of integrated devices, can take less space than two individual transistors because they can use
a shared collector. The Darlington amplifier typically has a relatively high input resistance (1 - 10 K)
and a fairly high output resistance. Therefore it is generally used to drive medium to high resistance
loads. It is typically used in applications where a small voltage signal needs to be amplified to a large
4. PROCEDURE:
2. Determine the Q-point of the Darlington amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to Darlington amplifier using AC
analysis.
where f1 - lower cut-off frequency
Semester 03
Department of ECE
Page 37

a.
DC ANALYSIS:
Steps:
i)
generator
junction. VBE
ii)
iii)
iv)
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
Procedure:
i.
ii.
V MSH = _________ volts
Semester 03
Department of ECE
Page 38
5. TABULATION
S. NO
FREQUENCY
[Hz]
1.
2.
100
3.
500
4.
600
5.
800
6.
OUTPUT VOLTAGE
GAIN= 20 log Vo/Vin
[ VO] in Volts
dB
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
Department of ECE
Page 39
WORKSHEET
Semester 03
Department of ECE
Page 40
6. RESULT:
INFERENCE:
The Darlington amplifier was constructed and the results are found to be
a. Gain of the amplifier :
b. Bandwidth of the amplifier :
c. Gain-Bandwidth product :
CONCLUSION:
Semester 03
Department of ECE
Page 41
Common Source Amplifier Circuit Diagram:
MODEL GRAPH:
Semester 03
Department of ECE
Page 42

COMMON SOURCE AMPLIFIER
EXPERIMENT:05
1.
DATE:
OBJECTIVE:
To Design and Construct a Common source amplifier using the bootstrapped gate resistance
and to determine its:
a.
b.
c.
d.
e.
2.
DC Characteristics
Gain -Bandwidth Product
REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BFW10
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Semester 03
Connecting Wires
Department of ECE
Single strand
as required
Page 43

DESIGN ANALYSIS :
Given :
VDD = 20 V, IDSS = 5mA, ID = 1.5 mA,
i) To Find the voltage across the Gate-source region (VGS)
VGS = ID RS
Assume RS = 3.3K,
VGS = 1.5mA x 3.3K = _____
ii) To find Voltage Across Drain to Source (VDS)
VDS= VDD - ID ( RD + Rs) ; Where RD= 3.3 K
= 20V 1mA ( 3.3 K + 3.3 K)
= ________
iii) To Find input
impedance :
Zi = RG ; Assume RG = 1M
iv) To Find output impedance :
ZO = RD ||
Semester 03
Department of ECE
Page 44

3. THEORY
There are three basic types of FET amplifier or FET transistor namely common source
amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a
voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating the current going
to the load.
ii) As a voltage amplifier, input voltage modulates the amount of current flowing through the
FET, changing the voltage across the output resistance according to Ohm's law.
However, the FET device's output resistance typically is not high enough for a reasonable
transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally
zero). Another major drawback is the amplifier's limited high-frequency response. Therefore, in
practice the output often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output and frequency
characteristics
4. PROCEDURE:
2. Determine the Q-point of the CS amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using
AC analysis.
Semester 03
Department of ECE
Page 45

a. DC ANALYSIS:
Steps:
i)
generator
junction. VBE
ii)
iii)
iv)
1. VGS :
= ____________
2. VDS
= ____________
3 ID
= _______

Procedure:
i.
ii.
Apply input signal Vin = 1 V of 1Khz frequency to the CS amplifier using the
V MSH = _________ volts
Semester 03
Department of ECE
Page 46

5. TABULATION
Input voltage (Vin=V MSH/2) =____________V
S. NO
FREQUENCY
[Hz]
1.
2.
100
3.
500
4.
600
5.
800
6.
OUTPUT VOLTAGE [
VO] in Volts
GAIN= 20 log Vo/Vin

dB
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
Department of ECE
Page 47

WORKSHEET
Semester 03
Department of ECE
Page 48
6. RESULT:
INFERENCE:
The common Source amplifier was constructed and input resistance and gain were determined. The
a) Gain of the amplifier (in db) :
b) Bandwidth of the amplifier (in HZ) :
c) Gain-Bandwidth product (GBWP) :
CONCLUSION:
Semester 03
Department of ECE
Page 49
Cascade amplifier Circuit Diagram:
MODEL GRAPH:
Semester 03
Department of ECE
Page 50

CASCADE AMPLIFIER
EXPERIMENT:06
1.
DATE:
OBJECTIVE:
To Design and Construct a Cascade Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
2. REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BC 107
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
Bread Board
Accessories
8
Semester 03
Connecting Wires
Department of ECE
Single strand
as required
Page 51

DESIGN PROCEDURE:
VCC= 14 V, IC1=1.2mA, RL = 40K hFE= 100
(i) To calculate R5 :
Assume VE1 = 5V , VCE1 = VCE2 = 3V;
VB2 = VC1 = VE1 + VCE1 = 5V + 3V = 8V
VE2 = VB2 VBE = 8V 0.7V = 7.3V
VR5 = Vcc VE2 VCE2 = 14V 7.3V 3V = 3.7V
Choose R5 = RL / 10 = 40K / 10 = 4K ;
IC2 = ( VR5 / R5 ) = 3.7V / 3.9K = 1000A
(ii) To calculate R6 :
VR6 = VE2 / IC2 = 7.7K;
IC2 = VE2 / R6 = 7.3V / 8.2 K = 890A
(iii) To calculate R1, R2 , R3 & R4:
Voltage across resistor R3 is given by
VR3 = Vcc VC1 = 14V 8V = 6V
R3 = VR3 / IC1 = 6V / 1mA = 6K
R4 = VE1 / IC1 = 5V/ 1mA = 4.7K
Voltage across resistor R2 is given by
VR2 = VE1 VBE = 5V + 0.7V =5.7V
R2 = 10 R4 = 4.7 K
VR1 = VCC VB1 = 14V + 5.7V =8.3V
R1 = [ VR1 x R2 / VR2] = 68.4 K
Semester 03
Department of ECE
Page 52

3. THEORY:
A cascade is type of multistage amplifier where two or more single stage amplifiers are
connected serially. Many times the primary requirement of the amplifier cannot be achieved with
single stage amplifier, because Of the limitation of the transistor parameters. In such situations more
than one amplifier stages are cascaded such that input and output stages provide impedance
matching requirements with some amplification and remaining middle stages provide most of the
amplification. These types of amplifier circuits are employed in designing microphone and
loudspeaker.
4. PROCEDURE:
2. Determine the Q-point of the amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using AC analysis.
Semester 03
Department of ECE
Page 53

a. DC ANALYSIS:
Steps:
v)
generator
junction. VBE
vi)
vii)
viii)
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )

Procedure:
iii.
iv.
signal generator between base emitter junction of the transistor.Find the
processwhich can be seen in the CRO. The amplitude obtained at this point
V MSH = _________ volts
Semester 03
Department of ECE
Page 54

5. TABULATION
Input voltage (Vin=V MSH/2) =____________ volts
S. NO
FREQUENCY
[Hz]
1.
2.
100
3.
500
4.
600
5.
800
6.
OUTPUT VOLTAGE
[ VO] in Volts
GAIN= 20 log Vo/Vin

dB
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
Department of ECE
Page 55

WORKSHEET
Semester 03
Department of ECE
Page 56
6. RESULT:
INFERENCE:
The Cascade amplifier was constructed and input resistance and gain were determined. The results
are found to be as given below
CONCLUSION:
Semester 03
Department of ECE
Page 57
Cascode amplifier Circuit Diagram:
MODEL GRAPH:
Semester 03
Department of ECE
Page 58

CASCODE AMPLIFIER
EXPERIMENT: 07
DATE:
1. OBJECTIVE:
To Design and Construct a Cascode Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
2. REQUIREMENTS:
S.No.
Requirement
Name
Range
Quantity
Transistor [Active]
BC 107
Resistor [Passive]
61k,
4.7k
Capacitor [Passive]
10f, 100f
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Components
10k,
1k,
1,1,1,2
2,1
Equipment
Bread Board
Accessories
8
Semester 03
Connecting Wires
Department of ECE
Single strand
as required
Page 59

DESIGN PROCEDURE:
VCC= 20V, IC =1.2mA, AV= 30, , RL = 90K ;
Transistor Parameters: hFE= 50 , hie = 1.2K and hib= 24
Rc = RL / 10 = 90k / 10 = 9K
(ii) To calculate RE:
Assume VCE1 = VCE2 = 3V, and VE = 5V;
The voltage drop across collector resistor is given by,
VRC = VCC - VCE1 - VCE2 VE
= 20V 3V 3V- 5V
VRC = 9V
RE = VE / IE ; Where IE = Ic = 1.1mA
RE = 4.5K
(iii) To Calculate Bias Resistors R1, R2, R3 :
a. R3 = 10 RE = 47K
b. Voltage Across the base of Transistor 1 is given by,
VB1 = VBE + VE
VB1 = 5V + 0.7V = 5.7V
I3 = (VB1/ R3) = 5.7V / 47K = 121 A
c. Voltage Across the base of Transistor 2 is given by
VB2 = VBE2 + VE + VBE2
= 5V + 3V + 0.7V
= 8.7V
d. Voltage across resistor R2 is given by
VR2 = VB2 - VB1
VR2 = 8.7V 5.7V = 3V
e. The resistor R2 is given by R2 = (VR2 / I3 ) = (3V / 121A)
R2 = 24.8K
f. Resistor R1 = [VCC - VB2 / I3 ]
= [ 20V 8.7V / 121 A]
= 93.4 K
Determination of Capacitor Values:
To Find C1 :
C1 = * 1 / 2f1 (Zi / 10) ]
Where Zi = ( R3 || R2 ) = 1.1K and
= 57.9F
To Find C2 :
C2 = * 1 / 2f1 (hie2 / 10) ] = 53 F
Where hie2= 1.2 K and f1 = Lower cut-off frequency= 25HZ;
Semester 03
Department of ECE
Page 60

To Find C3 :
C3 = * 1 / 2f1hib ]
Where hib= 24 and
= 256F
To Find C4 :
C4 = * 1 / 2f1 ( (RC + RL) / 10) ]
Where RC = 9K; RL = 90K and
= 0.64 F
THEORY:
The cascode configuration has one of two configurations of multistage amplifier. In each case
the collector of the leading transistor is connected to the emitter of the following transistor. The
arrangement of the two transistors is shown in the circuit diagram. The cascode amplifier consists of
CE stage connected in series with CB stage. The arrangement provides a relatively high input
impedance with low voltage gain for the first stage to ensure the input miller capacitance is at a
minimum, whereas the following CB stage provides an excellent high frequency response.
Features:
1. It provides high voltage gain and has high input impedance.
2. It provides high stability and has high output impedance
PROCEDURE:
incremental steps and note down the corresponding output voltage Vo for atleast 20 different
values for the considered range.
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking frequency on xaxis and gain in dB on y-axis.,
Semester 03
Department of ECE
Page 61

a.
DC ANALYSIS:
Steps:
ix)
generator
x)
xi)
junction. VBE
xii)
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
Procedure:
v.
vi.
signal generator between base emitter junction of the transistor.Find the
processwhich can be seen in the CRO. The amplitude obtained at this point
V MSH = _________ volts
Semester 03
Department of ECE
Page 62
5. TABULATION
S. NO
FREQUENCY
[Hz]
1.
2.
100
3.
500
4.
600
5.
800
6.
OUTPUT VOLTAGE
GAIN= 20 log Vo/Vin
[ VO] in Volts
dB
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
600 KHz
11.
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
Department of ECE
Page 63
WORKSHEET
Semester 03
Department of ECE
Page 64
6. RESULT:
INFERENCE:
The Cascode amplifier was constructed and input resistance and gain were determined. The results
are found to be as given below
CONCLUSION:
Semester 03
Department of ECE
Page 65

Differential amplifier Circuit Diagram:
Common Mode :
Differential Mode :
Semester 03
Department of ECE
Page 66

DIFFERENTIAL AMPLIFIER
EXPERIMENT: 08
DATE:
1. OBJECTIVE:
To Design and Construct a Differential Amplifier using BJT and to determine its:
a.
b.
c.
d.
Transfer Characteristics
Gain of the amplifier in common mode
Gain of the amplifier in differential mode
CMRR (Common Mode Rejection Ratio)
2. REQUIREMENTS:
S.No.
Requirement
Name
Transistor [Active]
Range
Quantity
BC 107
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
Bread Board
Accessories
8
Connecting Wires
Single strand
as required
3. THEORY:
A differential amplifier is a type of electronic amplifier that amplifies the difference
between two voltages but does not amplify the particular voltages. The need for differential
amplifier arises in many physical measurements where response from D.C to many MHZ is
required. It is also used in input stage of integrated amplifier.
Semester 03
Department of ECE
Page 67

DESIGN PROCEDURE:
VCC= 12V, IC=1.2mA, VCE = 5V
Assume Q1 = Q2
Where Q1 = Transistor 1 and Q2 = Transistor 2.
The Collector resistance Rc1 is given by using KVL at the transistor 1
Vcc = IcRc1 VCE Ie1Re1
Rc1 = (Vcc + VCE + Ie1Re1 ) / Ic,
Where VCE = 5V and Ic = 1.2mA, Ie1 = Ic/10 and assume Re1 = 470
Now Rc1 = 1k .
MODEL GRAPH:
Differential amplifier Transfer Characteristics:
Semester 03
Department of ECE
Page 68

The output signal in differential amplifier is proportional to the difference between the two
input signals.
Vo = Ad (V1 V2 ).
Where V1,V2 are the input voltages and Ad is the differential gain.
If V1 = V2, then output voltage is zero. A non zero output voltage is obtained if V1 and V2
are not equal.
i)
The difference mode input voltage is defined as Vd = (V1-V2)
ii)
iii)
The common mode input voltage is defined as the Vcm= (V1+V2)/2

The CMRR is defined as the ratio of the differential gain Ad to common mode gain
Ac and is generally expressed in dB.
CMRR= 20 log10 ( Ad / Ac)
4. PROCEDURE:
2. Determine the Q-point of the Differential amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using
AC analysis.
4. Determine the Transfer characteristics of Differential amplifier by plotting the graph for
normalized differential input voltage [ (Vb1 Vb2) / VT ] vs. Normalized collector current [ Ic / Io].
5. Calculate the voltage gain of differential amplifier for differential mode
as Ad = 20log (V0/Vi) , Where Vi = V1 V2
6. Calculate the voltage gain of differential amplifier for Common mode
as AC = 20log (V0/Vi) , Where Vi = (V1+ V2 / 2 )
7. Find the Common mode rejection ratio of differential amplifier using the formula given
below.
CMRR= 20 log10 ( Ad/Ac)
Where Ad- Differential mode gain in dB
Ac Common Mode gain in dB
Semester 03
Department of ECE
Page 69

a.
DC ANALYSIS:
Steps:
i)
generator
junction. VBE
ii)
iii)
iv)
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the operating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
Procedure:
vii.
viii.
V MSH = _________ volts
Semester 03
Department of ECE
Page 70

5. TABULATION
a. Transfer Characteristics Calculation:
S.no
Input Voltage
Vi = (Vb1 Vb2) in Volts
Output Current
Ic2 in Ampere
1.
2.
3.
4.
5.
6.
b. CMRR Calculation:
To Find Differential Gain (Ad ) :
S. NO
INPUT
VOLTAGE
in volts
OUTPUT VOLTAGE [ VO] in

Volts
Differntial gain in dB
Ad = 20log (V0/Vi)
Where Vi = Vi1 Vi2
33.
Vi1
34.
Vi2
To Find Common Mode Gain (AC ) :

S. NO
INPUT
VOLTAGE
in volts
1.
Vi1
2.
Vi2
Semester 03
OUTPUT VOLTAGE [ VO]

in Volts
Department of ECE
Common mode gain in dB

AC = 20log (V0/Vi)
where Vi = (V1+ V2 / 2 )
Page 71
WORKSHEET
Semester 03
Department of ECE
Page 72
6. RESULT:
INFERENCE:
The Differential amplifier was constructed and input resistance and gain were determined. The
d) Trans-Conductance of Differential amplifier ( in millisiemens) :
e) Differential mode gain in dB
f)
Common Mode Gain in dB
g) CMRR in dB
CONCLUSION:
Semester 03
Department of ECE
Page 73
WORKSHEET
Semester 03
Department of ECE
Page 74
SPICE SIMULATION USING PSPICE
Semester 03
Department of ECE
Page 75

Common Emitter Amplifier circuit diagram
CE Amplifier without Feedback :
CE Amplifier with Feedback:
Semester 03
Department of ECE
Page 76

COMMON EMITTER AMPLIFIER
EXPERIMENT: 01
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice simulation tool and to
determine its:
a. Gain of the amplifier
b. Bandwidth of the amplifier
c. Gain -Bandwidth Product
2. REQUIREMENTS:
S.no
Requirements
Quantity
PC
Pspice Software
THEORY:
A common emitter amplifer is type of BJT amplifier which increases the voltage level of the
The CE amplifier typically has a relatively high input resistance (1 - 10 K) and a fairly high
output resistance. Therefore it is generally used to drive medium to high resistance loads. It is
typically used in applications where a small voltage signal needs to be amplified to a large
The input signal Vin is applied to base emitter junction of the transistor and amplifier output
Vo is taken across collector terminal. Transistor is maintained at the active region by using the
resistors R1,R2 and Rc. A very small change in base current produces a much larger change in
collector current. The output Vo of the common emitter amplifier is 180 degrees out of phase
with the applied the input signal Vin.
Semester 03
Department of ECE
Page 77
WORKSHEET
Semester 03
Department of ECE
Page 78

3. PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results were determined:
CONCLUSION:
Semester 03
Department of ECE
Page 79

Common source Amplifier circuit diagram
CS Amplifier:
Semester 03
Department of ECE
Page 80

COMMON SOURCE AMPLIFIER
EXPERIMENT: 02
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice simulation tool and to
determine its:
a. Gain of the amplifier
b. Bandwidth of the amplifier
c. Gain -Bandwidth Product
2. REQUIREMENTS:
S.no
Requirements
Quantity
PC
Pspice Software
THEORY:
There are three basic types of FET amplifier or FET transistor namely common source
amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a
voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating the current going
to the load.
ii) As a voltage amplifier, input voltage modulates the amount of current flowing through the
FET, changing the voltage across the output resistance according to Ohm's law.
However, the FET device's output resistance typically is not high enough for a reasonable
transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally
zero). Another major drawback is the amplifier's limited high-frequency response. Therefore, in
practice the output often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output and frequency
characteristics
Semester 03
Department of ECE
Page 81
WORKSHEET
Semester 03
Department of ECE
Page 82
3. PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results were determined:
CONCLUSION:
Semester 03
Department of ECE
Page 83

WORKSHEET
Semester 03
Department of ECE
Page 84
DIGITAL EXPERIMENTS
Semester 03
Department of ECE
Page 85
Semester 03
Department of ECE
Page 86

DESIGN AND IMPLEMENTATION OF CODE CONVERTERS
EXPERIMENT:
DATE:
1. OBJECTIVE:
To design and verify the truth table of the following code converters
a. Binary to Gray converter
b. Gray to Binary converter &
c. BCD to Excess3 &
d. Excess3 to BCD.
2. REQUIREMENTS:
S. No.
1.
2.
3.
3. THEORY:
Components / Equipments
Digital IC trainer
NOT, AND, OR, Ex-OR Gate
Connecting wires
Specifications
Quantity
---
IC7404,7408,7432,7486
---
Binary to GRAY Converter:
1 in each
Sufficient
numbers
By representing the ten decimal digits with a four bit Gray code, we have another form
of BCD code. The Gray code however can be extended to any number of bits and conversion
between binary code and Gray code is sometimes useful. The following rules apply for conversion:
1. The MSB in the Gray code is the same as the corresponding bit in the binary number.
2. Going from left to right, add each adjacent pair of binary bits to get the next Gray code bit.
Disregard carries.
GRAY to Binary Converter:
To convert from Gray code to binary code, A similar method is used, at there are some
differences. The following rules apply:
1. The MSB in the binary code is the same as the corresponding digit in the Gray code
2. Add each binary digit generated to the gray digit in the next adjacent position Disregard
carries.
Semester 03
Department of ECE
Page 87

TRUTH TABLE FOR BINARY TO GRAY CODE CONVERTER:
|
Binary input
Gray code output
B3
B2
B1
B0
G3
G2
G1
G0
Semester 03
Department of ECE
Page 88

K-Map for G3:
G3 = B3
K-Map for G2:
K-Map for G1:
Semester 03
Department of ECE
Page 89

K-Map for G0:
Binary to GRAY Logic Diagram :
Semester 03
Department of ECE
Page 90

TRUTH TABLE FOR GRAY CODE TO BINARY CONVERTOR:
|
Gray Code
Binary Code
G3
G2
G1
G0
B3
B2
B1
B0
Semester 03
Department of ECE
Page 91
K-Map for B3:
B3 = G3
K-Map for B2:
K-Map for B1:
Semester 03
Department of ECE
Page 92

K-Map for B0:
GRAY to Binary LOGIC DIAGRAM
Semester 03
Department of ECE
Page 93

TRUTH TABLE FOR BCD TO EXCESS-3 CONVERTOR:
|
BCD input
Excess 3 output
B3
B2
B1
B0
G3
G2
G1
G0
Semester 03
Department of ECE
Page 94

K-Map for E3:
E3 = B3 + B2 (B0 + B1)
K-Map for E2:
K-Map for E1:
Semester 03
Department of ECE
Page 95

K-Map for E0:
BCD TO EXCESS-3 Convertor Logic Diagram
Semester 03
Department of ECE
Page 96

TRUTH TABLE FOR EXCESS-3 TO BCD CONVERTOR:
|
Excess 3 Input
BCD Output
B3
B2
B1
B0
G3
G2
G1
G0
K-Map for A:
A = X1 X2 + X3 X4 X1
Semester 03
Department of ECE
Page 97

K-Map for B:
K-Map for C:
K-Map for D:
Semester 03
Department of ECE
Page 98

EXCESS-3 TO BCD convertor Logic diagram:
4. PROCEDURE:
1. Connections are given as per the circuit diagram (Binary to GRAY).
2. Switch on the power supply.
3. Verify the truth table given for different inputs.
4. Repeat the above procedures for other converters.
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Department of ECE
Page 100
5. Results:
INFERENCE:
Thus the truth tables for Binary to Gray, Gray to Binary and BCD to Excess3 converters were
verified.
CONCLUSION:
Semester 03
Department of ECE
Page 101
Semester 03
Department of ECE
Page 102

DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER / SUBTRACTOR USING IC 7483
EXPERIMENT: 10
DATE:
1. OBJECTIVE:
To study the 4 bit binary adder/subtractor using IC7483.
2. REQUIREMENTS:
S.No.
Name of the apparatus
Specifications
Quantity
Digital Trainer kit
OR gate
IC 7432
AND gate
IC 7408
Binary Adder / Subtractor
IC 7483
Connecting wires
some
3. THEORY:
The full adder/sub tractors are capable of adding/subtracting only two single digit binary
numbers along with a carry input. But in practice we need to add/subtract binary numbers, which
are much longer than just one bit. To add/subtract two n-bit binary numbers we need to use the nbit parallel subtractor/adder.
Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input
binary numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is
the input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power
supply and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001
and the B inputs and the input carry to five toggle switches. The five outputs are applied to indicator
lamps. Perform the addition of a few binary numbers and check that the output sum and output
carry give the proper values. Show that when the input carry is equal to 1, it adds 1 to the output
sum.
Binary subtractor :
The subtraction of two binary numbers can be done by taking the 2s
complement of the subtrahend and adding it to the minuend. The 2s complement can be obtained
by taking the 1s complement and adding. To perform A-B, we complement the four bits of B, add
them to the four bits of A, and add 1 through the input carry. The four XOR gates complement the
bits of B when the mode select M=1(because x 0 x ) and leave the bits of B unchanged when
M=0(because x 0 x ) .Thus , when the mode select M is equal to 1, the input carry C0 is equal 1
and the sum output is A plus the 2s complement of B. when M is equal to 0, the input carry is equal
to 0 and the sum generates A+B.
Semester 03
Department of ECE
Page 103

Functional symbol for IC 7483:
Operand1
Operand2
B3 B2 B1 B0
A3 A2 A1 A0
C4
C0
4 bit IC 7483
O/P
Pin Diagram of IC7483:
Semester 03
Department of ECE
Page 104

Circuit Diagram for 4-bit Binary adder/subtractor:
4-BIT BINARY ADDER:
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4-BIT BINARY SUBTRACTOR
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TRUTH TABLE FOR BCD ADDER:
BCD SUM
CARRY
S4
S3
S2
S1
K MAP
Y = S4 (S3 + S2)
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LOGIC DIAGRAM OF BCD ADDER
4. PROCEDURE:
1.
2.
3.
4.
Connections are given as per the circuit diagram.

Set mode M =0 such that the circuit will operate in addition mode.
Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.
Repeat the same step in step 3 by keeping M=1 such that circuit will operate in subtraction
mode.
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5. RESULTS:
INFERENCE:
Thus the 4 bit Binary Adder / Subtractor using IC7483 is been implemented for both addition
and subtraction and the corresponding truth tables are verified.
CONCLUSION:
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DESIGN AND IMPLEMENTATION

OF
MULTIPLEXER AND DEMULTIPLEXER USING LOGIC GATES
EXPERIMENT: 11
DATE:
1. OBJECTIVE:
To design and implement multiplexer and demultiplexer using logic gates
2. REQUIREMENTS :
S.No.
Specification
Quantity
Digital Trainer kit
OR gate
IC7432
AND gate
IC7411
NOT gate
IC7404
Connecting wires
3. THEORY:
Multiplexer:
It has a group of data inputs and a group of control inputs. The control inputs are
used to select one of the data inputs and connected to the output terminal. It selects one
information out of many information lines and directed to a single output line.
Demultiplexer:
Demultiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the
control of selection signals. Fig shows a 1-line to 2-line Demultiplexer circuit. Construct this
circuit; connect an LED to each of the outputs D0 and D1. Set the select signal S to logic 1 or
logic 0, and toggle the input I between logic 1 and logic 0. Which output followed the input
when S = 1 and S = 0.
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4:1 MULTIPLEXER:
BLOCK DIAGRAM
Circuit Diagram:
Truth Table:
Semester 03
S1
S0
I0
I1
I2
I3
Department of ECE
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1:4 DEMULTIPLEXER:
BLOCK DIAGRAM
:
Circuit Diagram:
Truth Table:
Selection Lines
Semester 03
OUTPUT V0
S1
S0
D0=Di
D1= Di
D2= Di
D3= Di
Department of ECE
Page 113
TRUTH TABLE:
8X1 Multiplexer
S0
S1
D0
D1
D2
D3
O/P
LOGIC DIAGRAM FOR 8:1 MULTIPLEXER:
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Department of ECE
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1X8 De-Multiplexer:
LOGIC DIAGRAM FOR 1X8 DEMULTIPLEXER:
TRUTH TABLE
1:8 DEMULTIPLEXER:
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PIN DIAGRAM FOR IC 74150:
PIN DIAGRAM FOR IC 74154:
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4. PROCEDURE:
1. Connections are given as per in the circuit diagram.

2. Inputs are given through the logic switches.
3. Outputs are noted and verified with truth table
5. RESULTS
INFERENCE :
Thus the truth table of multiplexer and demultiplexer was studied and verified using logic
gates.
CONCLUSION:
6. VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
What is a multiplexer?
What are the applications of multiplexer?
What is the difference between multiplexer & demultiplexer?
In 2n: 1 multiplexer how many selection lines are used?
Draw a 2 to 1 multiplexer circuit
Draw a 1 to 2 demultiplexer circuit.
Semester 03
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Page 117
Semester 03
Department of ECE
Page 118

DESIGN AND IMPLEMENTATION OF ENCODER
EXPERIMENT:12.a.
DATE:
1. OBJECTIVE:
To construct and verify the 8 X 3 Encoder using logic gates.
2. REQUIREMENTS:
S. No
Specification
Quantity
1.
Digital IC trainer kit
2.
OR Gate
IC7432
3.
Connecting Wires
Sufficient Numbers
3. THEORY:
Digital Computers, Microprocessors and other digital systems are binary operated
whereas our language of communication is in decimal numbers and alphabetical characters
only. Therefore, the need arises for interfacing between digital system and human operators.
To accomplish this task, Encoder is used.
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Department of ECE
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Encoder
Lgic Diagram:
Truth Table:
INPUT
OUTPUT
D0
D1
D2
D3
D4
D5
D6
D7
Outputs:
A = D4 + D5 + D6 + D7
B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7
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4. PROCEDURE:
1. Construct the circuit as per the diagram
3. Apply the necessary input and observe the outputs to verify the truth table.
5. RESULTS:
INFERENCE:
Thus an 8 x 3 encoder is constructed and verified.
CONCLUSION:
6. REVIEW QUESTIONS:
1. Draw the basic block diagram of a practical decoder.
2. What is the need for decoder?
3. Name the procedure involved in decoding.
4. Give some practical applications where decoding is necessary.
5. List the advantages of decoding.
Semester 03
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Page 121
Semester 03
Department of ECE
Page 122

DESIGN AND IMPLEMENTATION OF DECODER
EXPERIMENT:12.b
DATE:
1. OBJECTIVE :
To construct and verify the decoder / driver along with seven segment LED display unit and
verify the results.
2. REQUIREMENTS :
S. No.
1.
2.
3.
4.
5.
Specification
Quantity
Decoder
IC 7447
Seven Segment Display
Common Anode
Resistors
330
IC Trainer Kit
---
Connecting Wires
---
Required
numbers
3. THEORY:
The 7-segment LED display is the most popular display device used in digital systems.
To use this device the data that is in the BCD form has to be changed suitably. For this
purpose a BCD to 7-segment decoder is required. The IC7447 is a BCD to 7-segment pattern
converter. . The 7447 converts the four input bits (BCD) to their corresponding 7-segment
codes. The outputs of the 7447 are connected to the 7-segment display.
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Connection Circuit Diagram:
4. PROCEDURE:
1.
2.
3.
Connect the circuit as per circuit diagram.

Apply the inputs to the IC7447(A,B,C&D).
Observe the output and verify the result.
5. RESULTS:
INFERENCE :
A decoder / driver unit along with 7 segment display unit is constructed and the
results were verified.
CONCLUSION:
6. REVIEW QUESTIONS:
1. Draw the basic block diagram of a practical decoder.
2. What is the need for decoder?
3. Name the procedure involved in decoding.
4. Give some practical applications where decoding is necessary.
5. List the advantages of decoding.
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Page 124
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER
EXPERIMENT: 13
DATE:
1 . OBJECTIVE:
To construct and verify the synchronous up/down counters.
2. REQUIREMENTS:
S. No.
Specification
Quantity
1.
Digital IC trainer kit
----
2.
JK Flip-Flop, AND Gate
IC 7473,7408
2,1
3.
Connecting wires
----
Sufficient Nos
3. THEORY:
Synchronous Counter
Clock input is applied simultaneously to all flip-flops. The output of the first FLIP-FLOP is
connected to the input of second FLIP-FLOP and so on.
Design of synchronous counter
Step 1: Find the number of flip-flops required. For an n-bit counter, n- flip-flops is
required.
Step 2: Write the count sequence in tabular form.
Step 3: Determine the flip-flop inputs, which must be present for the desired next State
from the present state using excitation table of flip-flops.
Step 4: Prepare K-map for each flip-flop input in terms of flip-flop output as input
Variables. Simplify the K-map and obtain the minimized expressions.
Step 5: Connect the circuit using the flip-flops.
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Department of ECE
Page 125

CIRCUIT DIAGRAM:
Design of 3-bit synchronous up:
Design of 3-bit synchronous down counter:
Pin Diagram
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Department of ECE
Page 126

Truth Table:
3 Bit Synchronous UP
Counter
3 Bit Synchronous DOWN

Counter
Clock
Q2
Q1
Q0
Clock
Q2
Q1
Q0
4. PROCEDURE:
1. The connections are made as per the circuit diagram.
3. The input is given at the appropriate terminal and corresponding output is observed
and truth table is verified.
5. RESULTS:
INFERENCE:
Thus the counters were constructed and their truth tables verified.
CONCLUSION:
6. REVIEW QUESTIONS
1.
2.
3.
4.
5.
Semester 03
Name any four flip-flop used to construct the counter.

Draw the basic block diagram of a practical 4-bit counter.
What is MOD 5 counter?
What is the need for counters?
Give some practical applications of counters.
Department of ECE
Page 127
Semester 03
Department of ECE
Page 128

IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO SHIFT REGISTERS
EXPERIMENT: 14
DATE:
1. OBJECTIVE:
To implement the 4 bit shift register using flip flops and to study the operations in the
following modes.
(i)
(ii)
(iii)
(iv)
Serial in serial out

Serial in parallel out
Parallel in parallel out
Parallel in serial out
2. REQUIREMENTS:
S.No.
Digital Trainer kit
D Flip Flop
Connecting wires
Range
Quantity
1
IC 7474
2
some
3. THEORY:
SHIFT REGISTER:
A register is a device capable of storing a bit. The data can be serial or parallel. The
register can convert a data from serial to parallel and vice versa shifting then digits to left and right is
the important aspect for arithmetic operations,
A register capable of shifting its binary information either to the right or to the left is
called a shift register. An N bit shift register consists of N flip-flops and the gates that control the
shift operation. A shift register can be used in four different configurations depending upon the way
in which the data are entered into and taken out of it. These four configurations are:
a.
b.
c.
d.
Serial-input, Serial-output
Parallel-input, Serial-output
Serial-input, parallel-output
Parallel-output, parallel-output
The serial input is a single line going to the input of the leftmost flip-flop of the register. The
serial output is a single line from the output of the rightmost flip-flop of the register, so that the
bits stored in the register can come out through this line one at a time.
The parallel output consists of N lines, one for each of the flip-flops in the register, so the
information stored in the register can be inspected through these lines all at once.
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Department of ECE
Page 129
PIN DIAGRAM:
Logic Diagram for Serial in Serial out:
Semester 03
Department of ECE
Page 130

Logic Diagram for Serial in Parallel Out:
Logic Diagram for Parallel In Parallel Out
Logic Diagram for Parallel in Serial out
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Page 132

TRUTH TABLE FOR PISO SHIFT REGISTER:
CLK
Q3
Q2
Q1
Q0
O/P
4. PROCEDURE:
1. The flip-flop is connected using connecting wires as shown in the circuit.
2. The flip flop are then reset to zero internally with the help of reset to set inputs.
3. The bits are shifted in by giving suitable clock input.
4. Thus the truth table is then verified.
5.
RESULTS:
INFERENCE:
Thus the operation of 4 bit shift register for SISO, SIPO, and PIPO was
studied and verified.
CONCLUSION:
Semester 03
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Page 133

VIVA QUESTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
What do you understand by Operating point?

Why do we choose the Q point at the center of the load line?
Name the two techniques used in the stability of the q point .explain.?
Define stability factor &Give the expression for stability factor?
List out the different types of biasing.
What do you meant by thermal runway?
Why transistor is called as a current controlled device?
Define current amplification factor?
What are the requirements for biasing circuits?
When does a transistor act as a switch?
What is biasing?
What is an operating point?
What is d.c load line?
Explain about the various regions in a transistor?
Explain about the characteristics of a transistor?
Why the operating point is selected at the Centre of the active region?
What is an amplifier?
What is small signal amplifier?
What is a Darlington pair?
Define Common Mode Rejection Ratio.
What is meant by Differential Amplifier?
What do you mean by balanced and unbalanced output?
What are the methods of improving CMRR?
Give few applications of differential amplifier
What are the advantages of double tuned over single tuned?
List the four differential amplifier configurations
What are the advantages and disadvantages of single-stage amplifiers?
Why gain falls at HF and LF?
Why the gain remains constant at MF?
Explain the function of emitter bypass capacitor, Ce?
How the band width will effect as more number of stages are cascaded?
Define frequency response?
What is the phase difference between input and output waveforms of a CE amplifier?
What is early effect?
What is the difference between FET and BJT?
FET is unipolar or bipolar?
What are the advantages and disadvantages of common base amplifier?
Why the gain remains constant at MF?
Define frequency response?
What is the phase difference between input and output waveforms of a CB amplifier?
What are the applications of CB amplifier?
What is the difference between FET and BJT?
Semester 03
Department of ECE
Page 134

43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
FET is unipolar or bipolar?

Draw the symbol of FET?
What are the applications of FET?
FET is voltage controlled or current controlled?
Draw a hybrid model for a BJT. (2)
What is the relationship between bandwidth and rise time? (2)
What are the high frequency effects? (2)
If the rise time of a BJT is 35 nano seconds, what is the bandwidth that can be obtained
using this BJT? (2)
Explain the usefulness of the decibel unit. (2)
Define the term bandwidth of an amplifier? (2)
State various capacitances in the hybrid model? (2)
Define the term bandwidth of an amplifier? (2)
Why it is not possible to use the h- parameters at high frequencies? (2)
What do you mean by the half power or 3 db frequencies? (2)
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Page 135
DATA SHEETS
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Department of ECE
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NPN general purpose transistors BC107; BC108; BC109
FEATURES
APPLICATIONS
amplification.
DESCRIPTION
NPN transistor in a TO-18; SOT18 metal package.

PNP complement: BC177.
Semester 03
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QUICK REFERENCE DATA
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EC6311 Analog and Digital Lab

RAJALAKSHMI INSTITUTE OF TECHNOLOGY

EC6311 ANALOG AND DIGITAL LABORATORY

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

LIST OF DIGITAL EXPERIMENTS

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

LIST OF ANALOG EXPERIMENTS

Pspice Simulation of Common Emitter Amplifier

Design and implementation of 3-bit synchronous up/down counter

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

CE Amplifier with Feedback:

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

(ii) To calculate R1&R2:

(iii) Input coupling capacitor :

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

It is the procedure to find the operating region of transistor

Open circuit the capacitors since it blocks DC voltage

= _______ (REVERSE BIAS)

4. Ic( Ic = (Vcc VCE ) / Rc) =________

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

b. Maximum signal handling capacity :

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

OUTPUT VOLTAGE [ VO]

GAIN= 20 log Vo/Vin

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

GAIN= 20 log ( vo/vin )

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Common Collector Amplifier Circuit Diagram:

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Regulated power supply

Rajalakshmi Institute of Technology

EC6311 Analog and Digital Lab

Design of Common collector amplifier:

To calculate Zb ( Device input impedance )

To calculate Zi ( Input Impedance )

(iii) To Calculate Voltage gain Av :