INVENTIVE

DFT Compression flow in

RTL Compiler
Sandeep Bhatia
Cadence Design Systems
Session 3.7

What is Test Compression?

Test Compression is the technique of reducing the test

data volume and test application time (TAT) while
retaining test coverage.
Every test compression solution requires
Compression logic via hardware on the designs inputs and
outputs
de-compressor on the scan input side
response compactor on the scan output side
ATPG capabilities to work with compression logic

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Why do we need Test Compression:

Increase in the number of test patterns
Transition fault testing requires 3-5x more patterns than stuck-at
fault testing

Newer chips with more pins and functionality but older

ATE equipment.
Less pins
Not enough buffer memory

Low-cost ATE - reduced pin count testers

Keep down test cost

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Test Data Volume v/s Technology Node

Relative test data volume

140
120
100

Other
Bridging test
At-Speed tests
Stuck-at tests

80
60
40
20
0
180 nm 150 nm 130 nm 90 nm

65 nm

Technology Node

Reference www.elecdesign.com
4

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Tester memory

Free space

Stimulus Data

MBIST + Boundary + Mixed-Signal

+ Functional Tests

Response Data
Stimulus Data

MBIST + Boundary + Mixed-Signal

+ Functional Tests

100011010111010001

001011010111011111101110110

110011010111010001101110001

DeCompressor

100011010111010001010101011

100110101110101010
001011010111011111
001010010011010111
110011010111010001
101110010111011101

1011100101110111011110001110

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Compressor

Response Data

Tester memory

Scan Vectors

Comparison of Full vs Compressed Scan

RC 7.1 Compression Structures

Supported for both ATPG and Diagnostics
Compressed Input Stream

Input Side:
Fan-out only or

Chip

XOR Spreader

Space Expander
(Spreader Network)

Output Side:
Space compactor

Masking

Masking

Space Compactor
(XOR Trees)
Compressed Output Stream
6

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Masking

Optional X-state
masking

Test Compression Structures

De-compressor:
Insert a simple scan fan-out (broadcast) or combinatorial linear
(XOR) spreader to decompress the test stimulus from a small
number of scan in pins to a large number internal scan
channels.

Compactor:
Insert a combinatorial linear (XOR) space compactor on the
internal scan channel outputs allowing the test responses to be
compressed down to a fewer number of scan out pins.
Optionally can insert masking logic to block Xs from entering
the compressor using a wide1 style masking.

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

X- Masking

Output Compression ratios and ATPG results are degraded by

the capture of unknown (X) states
Sources of X-states

Un-modeled ATPG logic: RAMs, mixed signal logic, black boxes etc.
Non-scan flops that get corrupted during scan operation
Flops on paths slower than tester launch-capture cycle
Unintended consequences of last minute design changes

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Example of Test Time Reduction

Original design:
200K flops with10 scan chains
20K flops per chain

10K test patterns with 100 ns shift clock

Test application time = 20 sec.
20K bits X 100 ns x 10K patterns

Design with 10X Test Compression:

Configure 200K flops into 100 compression mode scan chains
Max. scan chain length = 2K bits
Test application time = 2 sec.
2K x 100 ns x 10K patterns

10X reduction

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Example Test Data Volume Reduction

1 bit for input data (0,1)

2 bits for output data (0,1,X,Z)

Original design
Input Stim Data = 2 Gbits
10K patterns X 10 scan in pins X 20K bits scan depth X 1 bit

Output response Data = 4 Gbits

10K patterns X 10 scan in pins X 20K bits scan depth X 2 bit

Total = 6 Gbits of storage on tester

Design with 10X Test Compression

Input Stim Data = 200 Mbits
10K patterns x 10 scan in pins x 2K bits scan depth X 1 bit

Output response Data = 400 Mbits

10K X 10 X 2K bits scan depth X 2 bits

Total = 600 Mega-Bits of storage on tester

10X reduction
10

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How Much Test Compression Do I Need?

11

Original Design: 6Gb of test data and 20 sec. ATE time for scan test
10 X compression: 90% reduction (600 Mb, 2 sec)
20 X compression: 95% reduction (300 Mb,1 sec)
50 X compression: 98% reduction (120 Mb, 0.4 sec)
100X compression: 99% reduction (60 Mb, 0.2 sec)
Real Benefits start diminishing somewhere between 50-100X while
P&R and ATPG complexity kick in.
Non-Scan vectors (MBIST, Functional, I/O, etc.) dominate test time
and memory at higher compression

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Flow

12

Emphasis on Ease of use

Similar to Full-Scan design flow
Integrated into RTL Compiler Synthesis
Links into ET ATPG through setup files

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Flow

1. Build Full Scan Chains

Complex full chains constraints (head, tail, body )

Segments (fixed, floating, preserved, abstract)
Mixed clock domains, lockup latches
Low power
Physical aware scan chain design
Incremental scan chain synthesis (selective building of chains)
Detailed chain reports

2. Compress Full Scan Chains

13

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Test Compression Gate level Flow

Read Libraries and Netlist
Define full-scan chain DFT setup

define_dft shift_enable
define_dft test_clock
set_attr dft_dont_scan
set_attr dft_controllable
define_dft test_mode

Define the compression control pins

etc

define_dft xxx_segment

Set Other Parameters

Run the DFT rule checks,
Fix any DFT Violations

fix_dft_violations

Build Full Scan Chains

connect_scan_chains

Compress Full Scan Chains

Write ET ATPG Files
Save Netlist

14

define_dft scan_chain

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check_dft_rules

compress_scan_chains
write_et library -compression
Full-scan
Pin Assign
File

Compression
Pin Assign
Files

Compression Verification and ATPG

write_et command
Use the write_et command to generate the necessary
script files to:
Verify test structures and create ATPG test vectors
run NCVerilog to simulate the test vectors for fullscan and
compression test modes.

15

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Compression Results
(smaller is better)
1800

Relative Test cycles

1600
1400
1200

Full-scan

1000

XOR Spreader

800
Compression
broadcast

600
400
200
0
1x

5x

10x

20x

40x

Compression ratio

16

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60x

80x

Compression Results
(smaller is better)
400

Relative Test cycles

350
300
Full-scan

250

XOR Spreader

200

Compression
broadcast

150
100
50
0
1x

5x

10x

20x

40x

Compression ratio

17

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60x

80x

Target v/s Actual Compression

Advantage of Effective Masking
(higher is better)
120

Compression ratio

100
80
Target
With Masking

60

Without Masking
40
20

0
1

18

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Masking v/s No masking

(higher is better)
Compression Results
70

Compression ratio

60
50
40

with masking

30

without masking

20
10
0
1

4
Experiment

19

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Conclusion

DFT Compression
Can be very effective in reducing Test Cost
Test Application Time
Test Data Volume

Ease of use similar to Full-Scan DFT/ATPG flow

X-Masking is very critical to get efficient compression

20

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Co-Authors acknowledgement

21

Vivek Chickermane
Brian Foutz
Pradeep Nagaraj
Vinayak Kadam

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

compress_scan_chains command:
rc> compress_scan_chains -ratio <integer>
[-chains <actual_scan_chain>+]
[-decompressor < broadcast | xor >]
[-master_control <test_signal>]
[-auto_create |
[-comp_enable <test_signal>]
[-spread_enable <test_signal>]]
[-mask
[-auto_create |
[-mask_load <test_signal>]
[-mask_enable <test_signal>]
[-mask_clock <port|pin>]
[-mask_sdi <port|pin>]
[-mask_sdo <port|pin> -shared_output]]
[-preview] [-inside <instance>] [<design>]

23

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Test Data Volume

Reference www.elecdesign.com
24

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write_et command

25

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Target v/s Actual Compression Ratio

Compression Results

Compression ratio

25
20
15

Target
with masking

10

without masking

5
0
1

2
Experiment

26

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Benefits of XOR-based Compression:

Inserted and validated as part of the synthesis flow
Non-proprietary, combinational (simple), and efficient technology
(Optional) Insertion of X-state masking logic:
ATPG generates mask data and special scan sequences to load
masks prior to scan unload, as required
ATPG selects and applies mask on a scan cycle basis during scan

ATPG support for all fault models including, IDDQ, stuck-at,

transition, pattern faults
Enables on-line (one pass) diagnostics methodology
The data collected during the test can be used for diagnostics
without having to rerun the test to collect full scan data.
diagnose the failure information of the compressed test set
allows important statistical data to be gathered during
production in support of yield analysis.
This helps to ramp the yield as quickly as possible and increase
profits.
27

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Target v/s Actual Compression Ratio

70

Compression ratio

60
50
Target

40

With Masking
30

Without Masking

20
10
0
1

3
Experiment

28

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Masking v/s No masking

Compression Results
70

Compression ratio

60
50
40

with masking

30

without masking

20
10
0
1

4
Experiment

29

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

Dealing with X-States

Output Compression ratios and ATPG results are degraded by

the capture of unknown (X) states
Sources of X-states

30

Un-modeled ATPG logic: RAMs, mixed signal logic, black boxes etc.
Non-scan flops that get corrupted during scan operation
Flops on paths slower than tester launch-capture cycle
Unintended consequences of last minute design changes

Mask X-source with a test point => flow bottleneck!

2007 Cadence Design Systems, Inc. All rights reserved worldwide.

X- Masking

Mask logic prevents Xs from scan channels

to enter the Response Compactor

31

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32

2007 Cadence Design Systems, Inc. All rights reserved worldwide.