UNIT II:

Structural and
Gate Level Modeling of
Combinational Circuits

CpE 425 Digital Systems Design

Unit Outline

Verilog modules

Combinational circuits in Verilog

Structural modeling

Test modules

CpE 425 Digital Systems Design

Module Declaration

Basic building block/partition in Verilog

Does not necessarily correspond to a physical partition in
final implementation (can be used as a logical or functional
partition)
Module declaration made into three main parts:

Module name unique identifier to a module

Ports external interface of a module

Body functional/structural description of the module

CpE 425 Digital Systems Design

Module Declaration
inputs

module

outputs

modulemodule_name(portslist);
body
endmodule

CpE 425 Digital Systems Design

Module Declaration

CpE 425 Digital Systems Design

Exercise

Create a module declaration of a Half Adder circuit.

CpE 425 Digital Systems Design

Instantiation

Larger modules can be built by instantiating smaller

modules in the body of the larger module.
This modularity is especially helpful in creating larger
designs which can be broken down into smaller and more
manageable components.
The instance_name corresponds to a unique name for a
specific instance of a certain module (different names for
different instances of the same module)
The port_mapping describes the connection of the ports
of the smaller module to internal signals or even the ports
of the larger module.

CpE 425 Digital Systems Design

Instantiation
top
f

sub1

UNIT_1

sub1
UNIT_0

CpE 425 Digital Systems Design

Wire

Internal signals can be created using the wire data type.

Wire data type can have the following values: 0, 1, x, z

wirewire_name;

top
f

sub1

w1

UNIT_0
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sub1

UNIT_1
9

Gate Primitives

Verilog has built-in modules for modeling simple gates.

Modules have variable number of input ports.

Available gates: and, nand, or, nor, xor, xnor, not

in_0
in_1
in_2

Instantiation Example:

in_x

F
.
.
.

and

andinstance_name(F,in_0,in_1,,in_x);
Output first in the port map

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Exercise

Create a Full Adder module using the previous Half Adder

module.

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Buses

A collection of signals can be labeled with the same name

and differentiated via an index.

c[2]
m

sub1

x
y
z

c[1]
c[0]

b[2]
b[1]
b[0]

sub2

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Explicit Port-mapping

As the number of ports increases, it may be tricky to keep

track of port ordering when instantiating modules.
Explicit port-mapping explicitly specifies which external
signal is connected to a port.
c[2]

sub1

x
y
z

c[1]
c[0]

b[2]
b[1]
b[0]

sub2

sub1blk1(m,c[2],c[1],c[0]);

sub1blk1(.y(c[1]),
.a(m),
.x(c[2]),
.z(c[0])
);
.self_port (external_wire)

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Exercise
Create a Verilog description of a 4-input majority function that
outputs a '1' (representing true) if the number of 1s at the
inputs are more than the number of 0s; otherwise the output is
'0' (representing false).
Input:

A [3:0]

Output:

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Testbench

A testbench is a special module that can test another

module.
Also known as a test fixture.
Module to be tested (Unit Under Test, UUT) is instantiated
in the testbench module and is fed with stimuli, which is
generated by behavioral constructs.
A testbench has no ports (because this won't be interfaced
externally anyway).
tb_sub1
f
stimulus
generator

UUT
a

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sub1

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Testbench: Module Instantiation

tb_sub1
f
stimulus
generator

UUT
a
b

sub1

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Stimulus Generator

Behavioral constructs such as initial and always can be

used to generate stimuli.
Initial statement is similar to a program: each line is
sequentially evaluated and only run once.

By default, statements are evaluated concurrently.

To separate statements in time, use delay (#).

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References

Douglas J. Smith, VHDL & Verilog Compared & Contrasted

Plus Modeled Example Written in VHDL, Verilog and C
M. Morris Mano and Michael D. Ciletti, Digital Design with
an Introduction to the Verilog HDL, 5th edition.
www.asic-world.com

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