M.tech Vlsi

DETAILED
SYLLABUS
for
M Tech Degree Course
(Semester System)
VLSI DESIGN AND EMBEDDED SYSTEMS

w.e.f 2012-2013
COURSE STRUCTURE VR10
DEPARTMENT OF
ELECTRONICS & COMMUNICATION
ENGINEERING
VELAGAPUDI RAMAKRISHNA
SIDDHARTHA ENGINEERING COLLEGE

(AUTONOMOUS)
(Sponsored by Siddhartha Academy of General & Technical Education)
VIJAYAWADA 520 007
2
M.Tech (VLSI Design & Embedded Systems) VR10
VELAGAPUDI RAMAKRISHNA
SIDDHARTHA ENGINEERING COLLEGE

(Autonomous)
Kanuru, Vijayawada 520 007
(Approved by AICTE, Accredited by NBA, and ISO 9001: 2008 Certified)
(Affiliated to Jawaharlal Nehru Technological University Kakinada, Kakinada)
Academic Regulations for M.Tech (VR10) w.e.f. 2010-2011
(Common to all branches)

1.
Introduction
2.
Programmes Offered
3.
Duration of the Programme
4.
Minimum Instruction Days
5.
Eligibility Criteria for Admission
6.
Programme Structure
7.
Medium of Instruction
8.
Syllabus
9.
Eligibility Requirement for Appearing Semester End Examinations

and Condonation
10. Examinations and Scheme of Evaluation

11. Conditions for Pass and Award of Credits for a Course
12. Revaluation
13. Readmission Criteria
14. Break in Study
15. Eligibility for Award of M.Tech. Degree
16. Conduct and Discipline
17. Malpractices
18. Other matters
19. Amendments to Regulations
Dept .of Electronics and Communication Engineering V.R Siddhartha Engineering College: Vijayawada - 7
3
1. INTRODUCTION
Academic Programmes of the college are governed by rules and regulations as
approved by the Academic Council, which is the highest Academic body of the
Institute. These academic rules and regulations are effective from the academic year
2010-11, for students admitted into two year PG programme offered by the college
leading to Master of Technology (M.Tech) in various specializations offered by
respective departments as given in Table 1.
2. PROGRAMMES OFFERED
Presently, the college is offering Post Graduate programmes in Engineering with the
following specializations:
Table 1: List of Specializations
S.No
Specialization
1.
Structural Engineering
2.
Computer Science and Engineering
Communication Engineering and
3.
Signal Processing
4.
Telematics
5.
VLSI Design & Embedded Systems
6.
Power System Engineering
7.
CAD/CAM
8.
9.
Thermal Engineering
Computer Science & Technology
Department
Civil Engineering
Electronics & Communication
Engineering
Electrical & Electronics
Engineering
Mechanical Engineering
Information Technology
3. DURATION OF THE PROGRAMME

The duration of the programme is two academic years consisting of four semesters.
A student is permitted to complete the postgraduate programme in a stipulated time
frame of 4 years from the date of joining. Otherwise he/she shall forfeit his/her seat
in M.Tech Programme and the admission shall stand cancelled.
4. MINIMUM INSTRUCTION DAYS
Each semester, normally consists of a minimum of 90 instruction days with about 30
to 35 contact periods per week.
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5. ELIGIBILITY CRITERIA FOR ADMISSION

The eligibility criteria for admission into M.Tech programme are as per the
guidelines of APSCHE .
5.1 CATEGORY A Seats:
These seats will be filled by the Convener, PGECET.
5.2 CATEGORY B Seats :
These seats will be filled by the College as per the guidelines of APSCHE.
6. PROGRAMME STRUCTURE
Every specialization of the M.Tech programme shall have six theory courses and two
practical / term paper / seminar courses in each of first and second semesters. A major
project is offered in third and fourth semesters.
6.1 Course Code and Course Numbering Scheme
Course Code consists of eight characters in which the first four are alphabets and
rest are numerals. First four characters are described in Tables 2 and 3.
Table 2: First and Second Character Description
First Two
Characters
Name of the Department
CE
Civil Engineering Department
CS
Computer Science and Engineering Department
EC
Electronics & Communication Engineering Department
EE
Electrical & Electronics Engineering Department
ME
Mechanical Engineering Department
IT
Information Technology
Third and fourth characters represent specialization offering as mentioned in Table

No. 3.
5
Table 3: Third and Fourth Character Description
Next Two
Characters
SE
CS
SP
TM
VE
PS
CC
TE
Name of the Specialization

Structural Engineering
Communication Engineering and Signal Processing
Telematics
Power Systems Engg.
CAD/CAM
Thermal Engineering
Computer Science & Technology
CS
Fifth and sixth characters represent semester number and syllabus version number of
the course offered.
Seventh character represents course type, as per Table No. 4
Table 4: Course Type Description
Seventh Character
Description
Theory course
Lab course
Eighth character represents course number as described in figure1 below. However,

few courses are given distinct codes.
For example, in MECC 1051 course, the course is offered by Mechanical
Engineering Department (ME) in CAD/CAM specialization offered in the first
semester (1), the course syllabus version number (0), the course is of lab type (5) and
the course number is (1), as given in figure2 below.
Department
Code
Specialization Semester
Code
Number
Version Course
Number Type
Course
Number
Figure 1: Course Code Description
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6.2 Scheme of Instruction for 1st and 2nd Years

The scheme of instruction and exact syllabi of all postgraduate programmes are
given separately.
6.3 Contact Hours and Credits
The Course Credits are broadly fixed based on the following norms:
Lectures One Lecture period per week is assigned one credit.

Tutorials - Two tutorial periods per week are assigned one credit.
Practical Three periods per week are assigned two credits
Seminar/Mini Project shall have 2 credits.
Major project shall have 24 credits.
However, some courses are prescribed with fixed number of credits depending on the subject
complexity and importance.
6.4 Theory / Tutorial Classes

Each course is prescribed with fixed number of lecture periods per week.
During lecture periods, the course instructor shall deal with the concepts of the
course. For certain courses, tutorial periods are prescribed, to give exercises to
the students and to closely monitor their learning ability.
6.5
Laboratory Courses
A minimum prescribed number of experiments have to be performed by the
students, who shall complete these in all respects and get each experiment
evaluated by teacher concerned and certified by the Head of the Department
concerned at the end of the semester.
6.6
Programme Credits
Each specialization of M.Tech programme is designed to have a total of 80

credits, and the student shall have to complete the courses and earn credits as
per the requirements for the award of degree.
7. MEDIUM OF INSTRUCTION
The medium of instruction and examination is English.
8. SYLLABUS
As approved by the concerned BOS and the Academic Council.
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9. ELIGIBILITY REQUIREMENT FOR APPEARING SEMESTER END

EXAMINATION AND CONDONATION
a)
Regular course of study means a minimum average attendance of 75% in all the
courses computed by totaling the number of periods of lectures, tutorials, practical
courses and project work as the case may be, held in every course as the
denominator and the total number of periods attended by the student in all the
courses put together as the numerator.
b) Condonation of shortage in attendance may be recommended by respective Heads of

Departments on genuine medical grounds, provided the student puts in at least 65%
attendance in each subject and provided the Principal is satisfied with the
genuineness of the reasons and the conduct of the student.
c)
Students, having shortage of attendance, shall pay Rs.20/-per every period of

attendance shortage subject to a minimum of Rs.500/-.
d) Minimum of 50% aggregate marks must be secured by the candidates in the internal
examinations conducted for theory, practice and lab courses, to be eligible to write
semester end examinations. However, if the student is eligible for promotion based
on the attendance, in case necessary, a shortage of internal marks up to a maximum
of 10% may be condoned by the Principal based on the recommendations of the
Heads of the Departments.
e) Students having shortage of internal marks up to a maximum of 10% shall have to
pay Rs.1000/- towards condonation fee for shortage of internal marks.
f) A student, who does not satisfy the attendance and/or internal marks requirement,
shall have to repeat that semester.
g) Eligible candidates who failed to register for all papers for the semester-end
examinations shall not be permitted to continue the subsequent semester and has to
repeat the semester for which he/she has not registered for semester end
examinations.
h) Calculation of attendance for the re-admitted candidates who were detained for want
of internal marks / attendance or who had break in study for various reasons:
i.
No. of classes conducted will be counted from the day 1 of the semester
concerned, irrespective of the date of payment of tuition fee.
ii.
They should submit a written request to the Principal of the college, along
with a challan paid towards tuition & other fee, for re-admission before the
commencement of class work.
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iii.
Student should come to know about the date of commencement of class work
of the semester into which he/she wishes to get re-admission. The
information regarding date of commencement of class work for each
semester is available in the college notice boards/website.
10. EXAMINATIONS AND SCHEME OF EVALUATION

10.1 Internal Examinations:
10.1.1 Theory Courses
Each course is evaluated for 40 marks (a+b)
a) The internal evaluation shall be made based on the two midterm examinations,
conducted in every theory course in a semester each for 20 marks. The midterm
marks shall be awarded giving a weightage of 2/3rd in the examination in which
the student scores more marks and 1/3rd for the examination in which the student
scores less marks. Each midterm examination shall be conducted for duration of
90 minutes with 4 questions to be answered out of 5 questions.
b) The remaining 20 marks are awarded through continuous evaluation of
assignments / term paper in each subject as notified by the teacher at the

beginning of the semester.
Students shall be informed regarding the comprehensive assignment/project during first
week of semester and they have to submit completed assignment on or before 12th week of
semester.
10.1.2 Laboratory Courses: 25 marks
For Laboratory courses there shall be continuous evaluation during the

semester for 25 internal marks. The distribution of internal marks are given
below:
Sl.No.
1
2
3
Table 5: Distribution of Marks

Criteria
Day to Day work
Record
Internal Examination
Marks
10
05
10
10.1.3 Seminar/ Term paper: 25 marks
The distribution of internal marks for the seminar/ term paper is given below:
9
Table 6: Distribution of Marks

Sl.No.
1
2
Criteria
Report
Seminar & Viva voce
Marks
15
10
10.1.4 Major Project: (50 marks each in 3rd & 4th semesters)
The continuous internal evaluation for 50 marks allocated for the project
work in each semester of 3rd & 4th shall be on the basis of two seminars by each
student on the topic of his/her project evaluated by project review committee &
day to day assessment by the supervisor in each semester. The project review
committee consists of Head of Department, respective internal guide and three
senior faculty members of the department. The distribution of marks is as follows.
Table 7: Continuous Internal Assessment in Each Semester
Sl.No.
1
2
Criteria
Two seminars
Day to day assessment
Marks
15+15
20
10.2 Semester End Examinations

10.2.1 Theory Courses: 60 marks
The semester end examinations shall be conducted for 3 hours duration at the
end of the semester. The question paper shall be given in the following
pattern.
There shall be two questions from each unit with internal choice. Each
question carries 15 marks. Each course shall consist of four units of syllabus.
10.2.2 Lab Courses: 50 marks

35 marks are allotted for experiments/job works, 10 marks for viva-voce
examination and 5 marks for record.
10.2.3 Seminar/ Term paper: 50 marks
There shall be a seminar presentation. For Seminar/Term paper, a student
under the supervision of a faculty member, shall collect the literature on a
topic and critically review the literature and submit it to the Department in a
report form and shall make an oral presentation before the Departmental
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Committee. The Departmental Committee consists of Head of the
Department, supervisor and two other senior faculty members of the
department. For Seminar/Term paper the evaluation is done for 50 marks
internally. A candidate has to secure a minimum of 50% to be declared
successful.
10.3 Major Project:
The work on the project shall be initiated in the beginning of the second year
and the duration of the project is two semesters. Every candidate shall be required to
submit thesis or dissertation after taking up a topic approved by the Project Review
Committee.
a) A Project Review Committee (PRC) shall be constituted with Head of the
Department as chair person, two senior faculty members of the concerned
department.
b) The candidate has to submit, in consultation with his/her project supervisor, the
title, objective and plan of action of his/her project work to the Project Review
Committee for its approval before the second semester end examinations. After
obtaining the approval of the Committee the student can initiate the Project
work after the second semester end examinations.
c) If a candidate wishes to change his/her supervisor or topic of the project he/she
can do so with approval of the PRC. However, the Project Review Committee
(PRC) shall examine whether the change of topic/supervisor leads to a major
change of his/her initial plans of project proposal. If so, his/her date of
registration for the project work starts from the date of change of Supervisor or
topic as the case may be.
d) After approval of the topic by the Project Review Committee, the candidate
shall be required to submit status report in four stages. The first one in the
middle of 3rd semester, second one at the end of 3rd semester, third one in the
middle of 4th semester and the final report in the form of draft copy of thesis for
the approval of PRC to the Head of the Department and shall make an oral
presentation before the PRC.
e) Due weightage will be given to the papers published from the thesis submitted
in the order of International Journal, National Journal, International conference
and National conference while evaluating the thesis.
f) Three copies of the Project Thesis certified by the supervisor shall be submitted
to the College.
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g) The thesis shall be adjudicated by one external examiner selected by the

Principal. For this, Head of the Department shall submit a panel of five
examiners, who are eminent in the field.
h) The viva-voce examination shall be conducted by a board consisting of the
supervisor, Head of the Department and the external examiner. Head of the
Department shall coordinate and make arrangements for the conduct of vivavoce examination. If any candidate gets less than 50% marks in the viva-voce
examination, he/she shall revise and resubmit the project work and reappear for
viva-voce examination when next conducted.
In a special case, if any candidate does not submit his/her thesis due to ill health or any
other reason permitted by the head of the institution, he/she will be given another
chance to attend for the viva-voce examination conducted separately at a later date, if
the expenditure for conducting the viva-voce is completely borne by the candidate.
11. CONDITIONS FOR PASS AND AWARD OF CREDITS FOR A COURSE

11.1 Conditions for Pass and Award of Grades & Credits:
a) A candidate shall be declared to have passed in individual Theory/Drawing
course if he/she secures a minimum of 50% aggregate marks (Internal &
semester end examination marks put together), subject to a minimum of 40%
marks in semester end examinations.
b) A candidate shall be declared to have passed in individual lab/project course if
he/she secures a minimum of 50% aggregate marks (Internal & semester end
examination marks put together), subject to a minimum of 50% marks in
semester end examinations.
c)
If a candidate secures minimum of 40% marks in theory courses in the

semester end examinations and 40% - 49% of the total marks in the semester
end examinations and internal evaluation taken together in some theory
courses and secures an overall aggregate of 50% in all theory courses of that
semester he/she declared to be passed in the theory courses of that semester.
d) The student has to pass the failed course by appearing the examination when
offered next, as per the requirement for award of the degree.
e) On passing a course of a programme, the student shall earn assigned credits in
that Course.
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11.2 Method of Awarding Letter Grades and Grade Points for a Course.
A letter grade and grade points will be awarded to a student in each course based
on his/her performance as per the grading system given below.
Table 8: Grading System for individual subjects/labs
Theory/Drawing Lab/Project
Grade Points
Letter Grade
85-100%
85-100%
10
Ex
75-84%
75-84%
9
A+
70-74%
70-74%
8
A
65-69%
65-69%
7
B+
60-64%
60-64%
6
B
50-59%
55-59%
5
C
40-49%
50-54%
4
D
< 40%
< 50%
0
F (Fail)
11.3 Calculation of Semester Grade Points Average (SGPA)* and award of
division for the program.
The performance of each student at the end of the each semester is indicated
in terms of SGPA. The SGPA is calculated as below:
(CR X GP)
CR
(for all courses passed in the semester)
where CR= Credits of a course
GP = Grade points awarded for a course
*SGPA is calculated for the candidates who passed all the courses in that semester.
SGPA =
11.4 Calculation of Cumulative Grade Point Average (CGPA) for Entire

programme.
The award of division for M.Tech. programmes for the candidates who were
admitted into respective programmes during the year 2010-2011 and later is as
shown in the following table.
The CGPA is calculated as below:
CGPA =
(CR X GP)
CR
(for entire programme)
where CR= Credits of a course
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GP = Grade points awarded for a course
Table 9: Award of Division
CGPA
8
6.5 - <8
5.5 - <6.5
4 - <5.5
DIVISION
First Class with distinction
First Class
Second Class
Pass class
For the purpose of awarding first class with Distinction CGPA obtained within 2
years shall be considered.
Detained and break-in study candidates are not eligible for the award of First Class
with Distinction.
For the purpose of awarding First, Second and Pass Class, CGPA obtained in
the examinations appeared within the maximum period allowed for the completion
of course shall be considered.
11.5 Transitory Regulations
A candidate, who is detained or discontinued in the semester, on readmission shall
be required to pass all the courses in the curriculum prescribed for such batch of
students in which the student joins subsequently. However, exemption will be
given to those candidates who have already passed in such courses, in the earlier
semester(s) as approved by Board of Studies and ratified by Academic Council.
11.6 Consolidated Grade Card
A consolidated grade card containing credits & grades obtained by the candidate
will be issued after completion of the two year M.Tech Programme.
12. REVALUATION
As per the notification issued by the Controller of Examinations, the students can
submit the applications for revaluation, along with the fee receipt for revaluation of
his/her answer script(s) of theory course(s), if he/she is not satisfied with marks
obtained.
The Controller of Examinations shall arrange for revaluation of those answer
script(s) by a second external examiner.
Better marks of the two will be taken into consideration.
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13. READMISSION CRITERIA
A candidate, who is detained in a semester due to lack of attendance/marks, has to
obtain written permission from the Principal for readmission into the same semester
after duly fulfilling all the required norms stipulated by the college in addition to
paying an administrative fee of Rs. 1,000/14. BREAK IN STUDY
Student, who discontinues the studies for what so ever may be the reason, can get
readmission into appropriate semester of M.Tech programme after break-in study only
with the prior permission of the Principal of the College provided such candidate shall
follow the transitory regulations applicable to such batch in which he/she joins. An
administrative fee of Rs. 2000/- per each year of break in study in addition to the
prescribed tuition and special fee has to be paid by the candidate to condone his/her
break in study.
15. ELIGIBILITY FOR AWARD OF M.TECH. DEGREE
The M.Tech. Degree shall be conferred on a candidate who has registered and earned
all the prescribed 80 credits.
16.
CONDUCT AND DISCIPLINE
Students shall conduct themselves within and outside the premises of the institute in a
manner befitting the students of our institution.
As per the order of Honorable Supreme Court of India, ragging in any form is considered
a criminal offence and is banned. Any form of ragging will be severely dealt with.
The following acts of omission and/or commission shall constitute gross violation of the
code of conduct and are liable to invoke disciplinary measures with regard to ragging.
i. Lack of courtesy and decorum; indecent behavior anywhere within or outside the
campus.
ii. Willful damage or distribution of alcoholic drinks or any kind of narcotics to
fellow students / citizens.
Possession, consumption or distribution of alcoholic drinks or any kind of narcotics or
hallucinogenic drugs.
Mutilation or unauthorized possession of library books.
Noisy and unseemly behavior, disturbing studies of fellow students.
Hacking computer systems (such as entering into other persons areas without prior
permission, manipulation and/or damage of computer hardware and software or any other
cyber crime etc.)
Students are not allowed to use cell phones in the campus.
Plagiarism of any nature is prohibited.
Any other act of gross indiscipline as decided by the college from time to time.
15
17.
Commensurate with the gravity of offense, the punishment may be reprimand, fine,
expulsion from the institute / hostel, debarment from examination, disallowing the use of
certain facilities of the institute, rustication for a specified period or even outright
expulsion from the institute, or even handing over the case to appropriate law
enforcement authorities or the judiciary, as required by the circumstances.
For an offence committed in (i) a hostel (ii) a department or in a class room and (iii)
elsewhere, the Chief Warden, the Head of the Department and the Principal, respectively,
shall have the authority to reprimand or impose fine.
Cases of adoption of unfair means and/or any malpractice in an examination shall be
reported to the Principal for taking appropriate action.
Unauthorized collection of money in any form is strictly prohibited.
Detained and break in study candidates are allowed into the campus for academic
purposes only with permission from Authorities.
Misconduct committed by a student outside the college campus but having the effect of
damaging, undermining & tarnishing the image & reputation of the institution will make
the student concerned liable for disciplinary action commensurate with the nature &
gravity of such misconduct.
The Disciplinary Action Committee constituted by the Principal, shall be the authority to
investigate the details of the offence, and recommend disciplinary action based on the
nature and extent of the offence committed.
Grievances Appeal Committee (General) constituted by the Principal shall deal with
all grievances pertaining to the academic / administrative /disciplinary matters.
All the students must abide by the code and conduct rules of the college.
MALPRACTICES
The Principal shall refer the cases of malpractices in internal assessment tests and
Semester-End Examinations, to a Malpractice Enquiry Committee, constituted by him/her
for the purpose. Such committee shall follow the approved scales of punishment. The
Principal shall take necessary action, against the erring students based on the
recommendations of the committee.
Any action on the part of candidate at an examination trying to get undue advantage in the
performance or trying to help another, or derive the same through unfair means is
punishable according to the provisions contained hereunder. The involvement of the Staff,
who are in charge of conducting examinations, valuing examination papers and
preparing/keeping records of documents relating to the examinations in such acts
(inclusive of providing incorrect or misleading information) that infringe upon the course
of natural justice to one and all concerned at the examination shall be viewed seriously
and recommended for award of appropriate punishment after thorough enquiry.
18. OTHER MATTERS

18.1 The physically challenged candidates who have availed additional
examination time during their B.Tech/PGECET examinations will be given
additional examination time on production of relevant proof/documents.
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18.2 Students who are suffering from contagious diseases are not allowed to attend classes
and appear either internal or semester end examinations.
18.3 The students who participated in coaching/tournaments held at State/National /
International levels through University / Indian Olympic Association during end
semester examination period will be promoted to subsequent semesters till the entire
course is completed as per the guidelines of University Grants Commission Letter
No. F.1-5/88 (SPE/PES), dated 18-08-1994.
18.4 The Principal shall deal with any academic problem, which is not covered under these
rules and regulations, in consultation with the Heads of the Departments in an
appropriate manner, and
subsequently such actions shall be placed before the
academic council for ratification. Any emergency modification of regulation,
approved in the Heads of the Departments Meetings, shall be reported to the
academic council for ratification.
19.
AMENDMENTS TO REGULATIONS
The Academic Council may, from time to time, revise, amend or change the
regulations, schemes of examination and/or syllabi.
17
ELECTRONICS AND COMMUNICATION ENGINEERING
Curriculum, Scheme of Examination and Syllabi
For M.Tech Degree Program
in
w.e.f. 2012-2013
FIRST SEMESTER
Code
ECVE 1001
ECVE 1002
ECVE 1003
ECVE 1004
ECVE 1005/1
ECVE 1005/2
ECVE 1005/3
ECVE 1005/4
ECVE 1006/1
ECVE 1006/2
ECVE 1006/3
ECVE 1006/4
ECVE 1051
ECVE 1052
Subject
Principles of Embedded Systems
System Design with FPGA Architectures
CMOS Digital IC Design
Microcontrollers for Embedded System
Design
Semiconductor Device Modeling
Fabrication Technology
Verilog HDL
Advanced Digital Signal Processing
DSP Processors & Architectures
Advanced Data Communications
Advanced Computer Architecture
Real Time UML
VLSI Design Lab
Seminar
4
4
4
0
0
0
4
4
4
40
40
40
60
60
60
100
100
100
40
60
100
40
60
100
40
60
100
0
24
3
03
2
2
28
25
25
290
50
50
460
75
75
750
L: Lecture
P: Practice
C: Credits
I: Internal Assessment
E: End Examination
T: Total Marks
18
in
w.e.f. 2012-2013
SECOND SEMESTER
Code
ECVE 2001
ECVE 2002
ECVE 2003
ECVE 2004
ECVE 2005/1
ECVE 2005/2
ECVE 2005/3
ECVE 2005/4
ECVE 2006/1
ECVE 2006/2
ECVE 2006/3
ECVE 2006/4
ECVE 2051
ECVE 2052
Subject
Low Power VLSI Design

Digital System Testing and Testable
Design
Hardware- software Co- design
RTOS for Embedded Applications
Semiconductor Memory Design
System-on-Chip Architecture
Physical Design Automation
High Speed Digital Design
Networking & Internetworking using
Microcontrollers
CMOS Analog & Mixed Signal Design
VLSI Signal Processing
Fault Tolerant and Critical Safety Design
Embedded Systems Lab
Term paper
40
60
100
40
60
100
4
4
0
0
4
4
40
40
60
60
100
100
40
60
100
40
60
100
0
24
3
03
2
2
28
25
25
290
50
50
460
75
75
750
L: Lecture
P: Practice
C: Credits
I: Internal Assessment
E: End Examination
T: Total Marks
19
in
w.e.f. 2012-2013
THIRD & FOURTH SEMESTERS
Subject Code
ECVE 3051
Subject
Title
Project
Work
Credits
24
Evaluation
III Semester
IV Semester
Int.
Ext.
Int.
Ext.
50
-50
200
Total : 300 Marks
20
ECVE 1001
PRINCIPLES OF EMBEDDED SYSTEMS
Lecture : 4 Hrs/ Week
Credits : 4
Internal Assessment:
Final Examination :
40
60
Course Objectives
To identify hardware and software for an embedded system.
To use Embedded C for real time applications
To apply RTOS concepts for solving multi task applications
Learning Outcomes
Upon completion of the course students will be able to
understand the working of various communication architectures and protocols in an
embedded system
understand various capabilities of Embedded C and execute basic programs using it
understand RTOS features and case studies and analyze them for real time
applications
UNIT I
Embedded Computing - Introduction, Complex systems and microprocessors, The
embedded system design process, Formalism for system design, Model train controller,
CPU: Introduction, Programming input and output, Supervisor mode, Exceptions, and
Traps, Co-processors, Memory system mechanism; CPU performance and CPU power
consumption, Design example: Data compressor.
UNIT II
Bus-based Computer Systems - Introduction, The CPU bus, Memory devices, I/O devices,
Component interfacing, Designing with microprocessors, Development and debugging,
System-level performance analysis, Program design and analysis, Models of programs,
Assembly, Linking and loading, Basic compilation techniques, Program optimization,
Program-level performance analysis, Software performance optimization, Program-level
energy and power analysis, Analysis and optimization of program size, Program validation
and testing, Software modem.
UNIT III
Hardware Accelerators and Networks Processors - Introduction, CPUs and accelerators,
Multiprocessor performance analysis, Design examples: Digital still cameras, and video
accelerator. Distributed embedded architectures, Networks for embedded systems, Network-
21
based design, Internet-enabled systems, Vehicles as networks, Sensor networks, Design
example- Elevator controller.
UNIT IV
Introduction to Real Time Operating Systems - OS and RTOS basics, Tasks and task
states, Tasks and data, Semaphores and shared data, Message queues, Mailboxes and pipes,
Timer functions, Events, Memory management, Interrupt routines in an RTOS environment,
Round robin, Round robin with interrupts, Function queue scheduling architecture, Real
time operating system architecture.
Text Books
1. Wayne Wolf, Computers as Components: Principles of Embedded Computing
System Design, Morgan Kaufmann publishers. (Unit-I, II, III)
2. David Simon, An Embedded Software Primer, Pearson Education. (Unit-IV)
References
1. Frank Vahid, Embedded System Design, J Wiley, India.
2. K V K K Prasad, Embedded Real Time Systems: Concepts, Design Programming,
Dreamtech Press.
22
ECVE 1002
SYSTEM DESIGN WITH FPGA ARCHITECHTURES
Credits : 4
Final Examination:
40
60
Course Objectives
To study different architectures of FPGA.
To design sequential and arithmetic circuits.
Learning Outcomes
design sequential system, while avoiding the effects of timing and hazards.
determine chip architectures and basic technologies that are needed to achieve the
programmability.
develop designs for programmable architectures.
understand the design of floating point operations.
UNIT I
Logic Design Fundamentals - Hazards in combinational networks, Mealy sequential
network design, Design of a Moore sequential network, Equivalent states and reduction of
state tables, Sequential networks timing, Setup and hold times, Synchronous design, Tristate
logic and buses.
Design of Networks For Arithmetic Operations Design of a serial adder with
accumulator, State graphs for control networks, Design of a binary multiplier,
Multiplication of signed binary numbers, Design of a binary divider.
UNIT II
Digital Design with SM Charts - State machine charts, Derivation of SM charts,
Realization of SM charts, Implementation of dice game, Alternative realization for SM
charts using microprogramming, Linked state machines.
UNIT III
Designing With Programmable Gate Arrays and Complex Programmable Logic
Devices - XILNX 4000 series FPGAs, Designing with FPGAs, XILINX 4000 series
FPGAs, Using a one-hot state assignment, Altera complex programmable logic devices
(CPLDs), Altera FLEX 10K series CPLDs.
UNIT IV
Floating Point Arithmetic Representation of the floating point numbers, Floating-point
multiplication, Other floating-point operations.
23
Case Studies UART Design, Description of the MC68HC05 microcontroller, Design of
microcontroller CPU, Completion of the microcontroller design.
Text Books
1. Charles H Roth (1998), Jr. Digital System Design Using VHDL, International
Thomson Publishing. (UNIT I - IV).
References
1. Stephen M. Trimberger (2007), Field Programmable Gate Array Technology
Springer International Edition, First Indian Reprint.
2. Michel John Sebastian Smith (2000), Application Specific Integrated Circuits,
Pearson Education, First Indian reprint.
3. Wayne Wolf (2009), FPGA-based System Design, Pearson Education, First
Impression.
4. Stephen D. Brown, Robert J Francis, Jonathan Rose, Ivonko G. Vranesic (2007),
Field Programmable Gate Arrays, Springer International Edition, First Indian
Print.
24
ECVE 1003
CMOS DIGITAL IC DESIGN
Credits : 4
Final Examination:
40
60
Course Objectives
To evaluate the performance of CMOS Inverter in terms of area, power and speed.
To study the design of combinational logic gates considering basic design issues.
To study the design of sequential logic gates with various clocking strategies.
To develop an interest in timing issues of synchronous digital circuits.
Learning Outcomes
demonstrate different design parameters in the design of CMOS digital designs.
apply the concepts of combinational logic circuits for designing combinational logic
for a subsystem with various design specifications.
apply design concepts in designing sequential logic circuits.
understand timing issues in digital circuits.
UNIT I
The CMOS Inverter - Static CMOS inverter, Static behaviour, Performance of CMOS
inverter: Dynamic behaviour, Power, Energy, and energy- delay, Technology scaling and its
impact on the inverter metrics.
UNIT II
Designing Combinational Logic Gates in CMOS - Static CMOS design Complementary
CMOS, Ratioed logic, Pass transistor logic, Dynamic CMOS design, Dynamic logic: Basic
principle, Speed and power dissipation of dyanamic logic, Issues in dynamic design,
Cascading dynamic gates.
UNIT III
Designing Sequential Logic Circuits - Introduction, Static latches and registers, Dynamic
latches and registers, Pipelining: An approach to optimize sequential circuits, Non-bistable
sequential circuits, Choosing a clocking strategy.
UNIT IV
Timing Issues in Digital Circuits - Timing classification of digital systems, Synchronous
interconnect, Synchronous design, Clock synthesis and synchronization using a phase
locked loop, Future directions and perspectives.
25
Text Books
1. Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolic, (2003) Digital
Integrated Circuits: a Design Perspective, Pearson Education, 2nd Edition.
References
1. J. Uyemura (1992), Circuit Design for CMOS VLSI, Kluwer.
2. A. Kang and Leblebici, CMOS Digital Integrated Circuits, 2nd Ed., McGraw-Hill,
1999.
26
ECVE 1004
MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN
Lecture
Credits
:
:
4 Hrs/ Week
4
Final Examination:
40
60
Course Objectives
To study
architecture of various microcontrollers
on chip peripherals of various microcontrollers
interfacing of peripherals with various microcontrollers using Assembly and high
level languages
Learning outcomes
understand architecture and features of 8051 microcontroller
develop real time controller based system using 8051 microcontroller.
understand features and architecture of 16-bit microcontrollers.
design hardware and software for minimum microcontroller based system
UNIT I
Intel 8051/8031 Family Architecture - 8051 microcontroller, Internal and External
memories, Counters and timers, Synchronous serialcum-asynchronous serial
communication. USART interface in Intel 8051, Interrupts. Basic assembly language
programming. Instruction set Data transfer, Arithmetic, Logical operations. Program flow
control instructions, Interrupt control flow (RETI instruction).
UNIT II
Real Time Control: Interrupts - Interrupt handling structure of MCU, Interrupt latency
and interrupt deadline, Multiple sources of interrupts, Non-maskable interrupt sources,
Enabling or disabling of the sources, Interrupt structure in Intel 8051.
Real Time Control - Timers: Programmable timers in MCUs, Free running counter and
Real time control, Interrupt interval and density constraints.
Programming Framework - Assembly and C programming: Programming basics,
Structure of CPU registers and internal RAMs, Programming in assembly language,
Assemblers, Saving CPU status during interrupts, Passing parameters, Control structures,
Computing branch destination at run time, Programming in C and use of GNU tools.
Software Building Blocks - Stacks, Queue, Table, Strings, State machine, Key parsing.
27
UNIT III
16-bit Microcontrollers - 8096/80196 Family: Hardware, Memory map in Intel 80196
family MCU system, I/O ports, Programmable timers and high speed outputs and inputs
captures, Interrupts, Instructions.
PIC Microcontrollers - PIC microcontrollers overview and features, PIC 16c6X/7X, FSR,
PIC Reset Actions, PIC oscillatory connections, Memory organization, Instructions,
Addressing modes, I/O ports, Interrupts in PIC 16C61/71, Timers, ADCs.
UNIT IV
ARM-32 Bit MCUs - Introduction to 16/32 bit processors, ARM architecture and
Organisation, ARM/Thumb programming model, ARM/Thumb Instruction set,
Development tools.
Microcontroller Application Development Tools - Development phase of a
microcontroller based system, Software development cycle and applications, Software
development tools, Exemplary IDE-micro vision and tool from Keil, Emulator and in-circuit
emulator (ICE), Target board, Device programmer.
Text Books
1. Rajkamal. (Oct.2009), Microcontrollers: Architecture, Programming, Interfacing
and System Design, Pearson Education India. (UNIT I, II, III & IV)
2. Ajay Deshmukh Microcontrollers Theory and Applications, Tata McGraw-Hill
Publishers.(UNIT III)
References
1. Mohammed Ali Mazidi and Janice Gillispie Mazidi, (2008), The 8051
Microcontroller and Embedded Systems, Pearson Education Asia, New Delhi.
2. Andrew N Sloss (2003), ARM System Developers Guide: Designing and
Optimizing System Software, Morgan Kaufmann publishers.
28
ECVE 1005/1
SEMICONDUCTOR DEVICE MODELING
Credits : 4
Final Examination:
40
60
Course Objectives
To learn basics of semiconductor device physics
To should understand the BJT and MOSFET device characteristics.
Learning outcomes
understand the concepts of semiconductor device physics.
analyze the BJT and MOSFET device characteristics.
UNIT I
Energy bands in solids, Electrons and holes densities in equilibrium, Excess carriers - Nonequilibrium situation, Mobility of carriers, Charge transport in semiconductors, Continuity
equation.
UNIT II
Introduction to BJT, Operation of BJT at high frequencies, Design of high frequency
transistors, Second order effects in BJTs, Variation of beta with collector current, High
injection in collector, Heavy doping in emitter, Non-conventional BJTs, Hetero-junction
bipolar BJTs.
UNIT III
Metal-semiconductor junction, Energy band diagram of M-S junction, Current-voltage
characteristics of M-S junction, Ohmic contacts, Junction field effect transistor, Smallsignal parameters of JFETs, The MESFETs, The Hetero- junction FETs.
UNIT IV
Introduction to MOSFETs, Effect of gate and drain voltages on carrier mobility in the
inversion layer, Channel length modulation, MOSFET break down and punch-through, Subthreshold current, MOSFET scaling, Non-uniform doping in channel, Threshold voltage of
short channel MOSFETs, Small-signal analysis, Other MOSFETs configuration.
Text Books
1. Nandita Das Guptha , Amitava Das Guptha, Semiconductor Devices Modelling
and Technology, Prentice Hall India.(UNIT I - IV)
29
References
1. Ben G. Streetman (2000), Solid State Electronic Devices, 5th edition, Pearson
Education Asia.
2. Yannis Tsividis and Colin McAndrew, Operation and Modeling of The MOS
Transistor 3/e, Oxford University Press.
30
ECVE 1005/2
FABRICATION TECHNOLOGY
Credits : 4
Final Examination:
40
60
Course Objectives
To learn different steps involved in fabrication
To learn fabrication procedure and equipment used during various processing steps.
Learning outcomes
describe various fabrication steps involved in IC fabrication.
understand the process of crystal growth, wafer preparation, epitaxial growth.
understand significance of thin and thick oxidation in fabrication process.
understand the development of metallic interconnects through lithography,
metallization, etching.
UNIT I
Crystal Growth and Wafer Preparation Introduction, Electronic grade silicon,
Czochralski crystal growing, Silicon shaping, Processing considerations.
Epitaxy Introduction, Vapor phase epitaxy, Molecular beam epitaxy, Silicon-oninsulators, Epitaxial evaluation.
UNIT II
Oxidation Introduction, Growth mechanism and kinetics, Thin oxides, Oxidation
techniques and systems, Oxide properties, Redistribution of dopants at interface, Oxidation
of polysilicon, Oxidation induced defects.
Lithography Introduction, Optical lithography, Electron lithography, X-Ray lithography,
Ion lithography.
Reactive Plasma Etching Introduction, Plasma properties, Feature size control and
anisotropic etch mechanisms, Reactive plasma etching techniques and equipment.
UNIT III
Dielectric and Polysilicon Film Deposition Introduction, Deposition processes,
Polysilicon, Silicon dioxide, Silicon nitride, Plasma assisted depositions.
Diffusion Introduction, Models of diffusion in solids, Measurement techniques, Diffusion
in polycrystalline silicon, Diffusion in SiO2.
UNIT IV
Ion Implantation Introduction, Range theory, Implantation equipment, Annealing,
Shallow junctions, High-energy implantation.
31
Metallization Introduction, Metallization applications, Metallization choices, Physical
vapor deposition, Patterning.
Text Books
1. S.M.Sze, VLSI Technology, 2/E Tata McGraw-Hill. (UNIT I - IV)
References
1. Yasuo Tarui (1986), VLSI Technology: Fundamentals and Applications, SpringerVerlag.
2. Plummer (2001), Silicon VLSI Technology: Fundamentals, Practice, and
Modeling, Pearson Education India.
3. S. K. Ghandhi, VLSI Fabrication Principles: Silicon and Gallium Arsenide (Wiley,
New York, 1983)
32
ECVE 1005/3
VERILOG HDL
Credits : 4
Final Examination:
40
60
Course Objectives
To develop ability to use hardware description language, simulation, and logic
synthesis tools in the design and verification of digital circuits.
Learning Outcomes
Upon Completion of the course the students will be able to
understand the programming and flow of the HDL
understand the System Verilog simulation and synthesis.
UNIT I
Overview of digital design with Verilog HDL- Evolution of CAD, Emergence of HDLs,
Typical HDL based design flow, Trends in HDL, Hierarchical modeling concepts- Design
methodologies, Modules and instances, Components of simulation, Design block and
stimulus block, Basic concepts Lexical conventions, Data types, System tasks, Compiler
directives.
UNIT II
Modules and ports Module definition, Port declaration, Connecting ports, Hierarchical
names. Gate level modeling Gate types, Gate delays, Data flow modeling - Implicit
continuous assignment, Implicit net declaration, Delays, Expressions, Operators and
operands, Operator types, Examples.
UNIT III
Behavioral modeling Structured procedure, Procedural assignment, Timing control,
Conditional statements, Multiway branching, Loops, Sequential and parallel blocks, General
blocks. Tasks and functions, Useful modeling techniques Assign and deassign, Force and
release, Overriding parameters, Conditional compilation and execution, Timer scales.
UNIT IV
Timing and delays Types of delay models, Path delay modeling, Timing checks, Delay
back-annotation, Switch level modeling MOS, CMOS and bidirectioanl switches, User
defined primitives, Logic synthesis with Verilog HDL.
33
Text Books
1. Samir Palnitkar, Verilog HDL, Second Edition, Sun Microsystems Inc. (UNIT IIV)
References
1. Stephen D Brown (2007), Fundamentals of Digital Logic with Verilog Design
Tata MC Graw Hill, Special Indian Edition.
2. Andrew Rushton(2001), VHDL for Logic Synthesis, Wiley Publications.
34
ECVE 1005/4
ADVANCED DIGITAL SIGNAL PROCESSING
Credits : 4
Final Examination:
40
60
Course Objectives
To Understand basics of adaptive system, weight vectors, gradient and Mean square
error functions
To Know basics of some of algorithms and error handling functions
To be acquainted with different LMS algorithms and applications
To be acquainted with Recursive Mean Square Estimation Random variables and
kalman filters
Learning Outcomes
To demonstrate basics of adaptive system, Gradient and mean square error functions
To Compute properties of Kalman filtering
UNIT I
Multirate Signal Processing - Introduction, Decimation by a factor D, Interpolation by a factor
I, Sampling rate conversion by a rational factor I/D, Implementation of sampling rate
conversion: Polyphase filter structures, Interchange of filters and down samplers/up samplers,
Polyphase structures for decimation and interpolation filters, Direct form and polyphase FIR
structures with time varying coefficients.
UNIT II
Multirate FIR Filter Design - Multistage implementation of sampling rate conversion, Design
of FIR filters for sampling rate conversion, Applications of multirate signal processing: Design
of phase shifters, interfacing of digital system with different sampling rates, Subband coding of
speech signals, Filter bank implementation: Digital filter banks, Two channel filter
banks(QMF), Tree structured filter banks, Uniform DFT filter banks , Decimated filter banks.
UNIT III
Power Spectrum Estimation - Estimation of spectra from finite duration observations of a
signals, The periodgram,Use DFT in power spectral estimation, Non-parametric methods for
[ower spectrum estimation: Bartlett, Welch and Blackman and Tukey Methods, Comparison of
performance of non-parametric power spectrum estimation methods.
UNIT IV
Parametric Method Of Power Spectrum Estimation - Parametric methods for power
spectrum estimation, Relationship between auto correlation and model parameters, AR(AutoRegressive) model parameters: Yule-Walker, Burg and unconstrained least squares methods,
35
Sequential estimation, Moving Average (MA) and ARMA models for power spectrum
estimation, Minimum variance spectral estimates, Pisarenko harmonic decomposition method,
MUSIC algorithm.
Text Books
1.
John G Proakis, Dimitris G Manolakis, Digital Signal Processing: Principles,
Algorithms and Applications, Fourth Edition, Prentice Hall India. (UNIT I-IV)
References
1.
2.
3.
4.
Sophocles.J.Orfamadis. (1988), Optimum Signal Processing: An introduction 2nd

edition, McGraw Hill, Newyork.
S.Thomas Alexander. (1986), Adaptive Signal Processing-Theory and
Applications, Springer Verlag.
Bernard Widrow, Samuel D.Strearns. (2005), Adaptive Signal Processing, Pearson
Education.
Simon Haykins, Tuley Adali (2010), Adaptive Signal Processing: Next Generation
Solutions, Wiley Publications.
36
ECVE 1006/1
DSP PROCESSORS AND ARCHITECTURES
Credits : 4
Final Examination:
40
60
Course Objectives
Ability to discuss and map architectures, interfacing peripherals and instruction set of
DSP Processors according to the problem statements for real time applications.
Should have a clear idea in choosing computational accuracy factors for
DSP processor based real time implementations
Learning Outcomes
gain knowledge on computational accuracy issues and architectures of DSP devices.
demonstrate knowledge of internal architecture, memory and peripheral devices for a
DSP processor.
understand the implementation of applications for FFT algorithms using DSP
processors
2. UNIT I
Introduction to Digital Signal Processing- Introduction, A digital signal-processing system,
The sampling process, Discrete time sequences. Discrete Fourier Transform (DFT) and Fast
Fourier Transform (FFT), Linear time invariant systems, Digital filters, Decimation and
interpolation, Analysis and design tool for DSP Systems MATLAB, DSP using MATLAB.
Computational Accuracy in DSP Implementations -Number formats for signals and
coefficients in DSP systems, Dynamic range and precision, Sources of error in DSP
implementations, A/D conversion errors, DSP computational errors, D/A conversion errors,
Compensating filter.
UNIT II
Architectures for Programmable DSP Devices - Basic architectural features, DSP
computational building blocks, Bus architecture and memory, Data addressing capabilities,
Address generation unit, Programmability and program execution, Speed issues, Features
for external interfacing.
Programmable Digital Signal Processors - Commercial digital signal-processing devices,
Data addressing modes of TMS320C54XX DSPs, Data addressing modes of
TMS320C54XX processors, Memory space of TMS320C54XX processors, Program
control, TMS320C54XX instructions and programming, On-chip peripherals, Interrupts of
TMS320C54XX processors, Pipeline operation of TMS320C54XX processors.
37
UNIT III
Implementations of Basic DSP Algorithms - The Q-notation, FIR filters, IIR filters,
Interpolation filters, Decimation filters, PID controller, Adaptive filters, 2-D Signal
processing.
Implementation of FFT Algorithms - An FFT algorithm for DFT computation, A butterfly
computation, Overflow and scaling, Bit-reversed index generation, An 8-Point FFT
implementation on the TMS320C54XX, Computation of the signal spectrum.
UNIT IV
Interfacing Memory and I/O Peripherals to Programmable DSP Devices - Memory
space organization, External bus interfacing signals, Memory interface, Parallel I/O
interface, Programmed I/O, Interrupts and I/O, Direct memory access (DMA).
A Multichannel buffered serial port (McBSP), McBSP Programming, a CODEC interface
circuit, CODEC programming, A CODEC-DSP interface example.
Text Books
1. Avatar Singh and S.Srinivasan. (2004), DSP Processors and Architectures,
Thomson Publications. (Units-I,II & IV)
2. Lapsley et al. (2000), DSP Processor Fundamentals, Architectures & Features, S.
Chand & Co. (Unit-III )
References
1. B. Venkataramani and M. Bhaskar. (2002), Digital Signal Processors, Architecture,
Programming and Applications TMH.
2. Jonatham Stein. (2005), Digital Signal Processing, John Wiley.
38
ECVE 1006/2
ADVANCED DATA COMMUNICATIONS
Credits : 4
Final Examination:
40
60
Course Objectives
Ability to develop, specify, assemble, commission, assess and manage data and
telecommunication systems, networks and interfaces for telecommunication
companies, organizations, banking, financial and commercial applications
Learning Outcomes
understand the various digital communication techniques
know classification of data communications, interfaces and modems
acquaint with error detection and correction
acquaint with data link control and data link protocols
understand the circuit switching- space division switches- time division switches.
gain basic understanding and ability to time division multiplexing (TDM),
synchronous time division multiplexing.
UNIT I
Digital Modulation - Introduction, Information capacity bits, Bit rate, Baud, and M-ARY
coding, ASK, FSK, PSK, QAM, BPSK, QPSK, 8PSK, 16PSK, 8QAM, 16QAM, DPSK
methods, Band width efficiency, Carrier recovery, Clock recovery.
UNIT II
Basic Concepts of Data Communications, Interfaces and Modems - Data
communication- Components, Networks, Distributed processing, Network criteriaApplications, Protocols and standards, Standards organizations- Regulatory agencies, Line
configuration- Point-to-point- multipoint, Topology- Mesh- Star- Tree- Bus- Ring- Hybrid
topologies, Transmission modes- Simplex- Half duplex- Full duplex, Categories of
networks- LAN, MAN, WAN and internetworking, Digital data transmission- Parallel and
serial, DTE- DCE interface- Data terminal equipment, Data circuit- Terminating
equipment, Standards EIA 232 interface, Other interface standards, Modems- Transmission
rates.
UNIT III
Error Detection and Correction - Types of errors- Single- bit error, CRC (Cyclic
Redundancy Check) - Performance, Checksum, Error correction- Single-bit error
correction, Hamming code.
39
Data Link Control - Stop and wait, Sliding window protocols.
Data Link Protocols - Asynchronous protocols, Synchronous protocols, Character
oriented protocol- Binary synchronous communication (BSC) - BSC frames- Data
transparency, Bit oriented protocols HDLC, Link access protocols.
UNIT IV
Switching - Circuit switching- Space division switches- Time division switches- TDM
bus- Space and time division switching combinations- Public switched telephone network,
Packet switching- Datagram approach- Virtual circuit approach- Circuit switched
connection versus virtual circuit connection, Message switching.
Multiplexing - Time division multiplexing (TDM), Synchronous time division
multiplexing, Digital hierarchy, Statistical time division multiplexing.
Text Books
1. B. A.Forouzan. (2009), Data Communication and Computer Networking, 4th ed.,
TMH. (UNIT-II, III, & IV).
2. W. Tomasi. (2008), Advanced Electronic Communication Systems, 5 ed., PEI.
(UNIT-I).
References
1. Prakash C. Gupta. (2006), Data Communications and Computer Networks, PHI.
2. William Stallings. (2007), Data and Computer Communications, 8 th ed., PHI.
3. T. Housely. (2008), Data Communication and Tele Processing Systems, 2 nd
Edition, BSP.
40
ECVE 1006/3
ADVANCED COMPUTER ARCHITECTURE
Lecture
Credits
:
:
4 Hrs/ Week
4
Final Examination:
40
60
Course Objectives
To introduce instruction level parallelism in high performance processors.
To introduce cache principles and optimization techniques.
To study reliability and failure statistics of RAID system.
Learning Outcomes
evaluate cost performance and reliability of RAID system.
describe quantitative evaluation of multi-threading.
survey the limitations of instruction-level parallelism & thread-level parallelism.
understand the optimization techniques of cache performance.
UNIT I
Fundamentals of Computer design - Introduction, Classes of computers, Defining
computer architecture, Trends in technology, Trends in cost, Trends in power in integrated
circuits, Dependability, Measuring, Reporting and summarizing performance, Quantitative
principles of computer design.
Instruction-Level Parallelism and its Exploitation - Concepts and challenges, Basic
compiler techniques for exposing ILP reducing branch costs with prediction, Overcoming
data hazards with dynamic scheduling, Dunamic scheduling: Examples and algorithm,
Hardware based speculation, Exploiting ILP using multiple issue and static scheduling,
Exploiting ILP using dynamic scheduling, Multiple issue and speculation, Advanced
techniques for instruction delivery and speculation.
UNIT II
Limitations on Instruction Level parallelism: Introduction, Studies of the limitations of
ILP, Limitation on ILP for realizable processors, Crosscutting issues: Hardware versus
software speculation, Multithreading: using ILP support to exploit thread Level
parallelism.
Multiprocessors and Thread Level parallelism: Introduction, Symmetric shared memory
architectures, Performance of symmetric shared memory multiprocessors, Distributed
shared memory and directory based coherence, Synchronization: The basics, Models of
memory consistency: An introduction, Crosscutting issues.
41
UNIT III
Memory Hierarchy Design - Introduction, Eleven advanced optimization of cache
performance, Memory technology and optimizations, Protection: Virtual memory and
virtual machines, The design of memory hierarchies.
UNIT IV
Storage Systems - Introduction, Advanced topics in disk storage, Definition and examples
of real faults and failures, I/O performance, Reliability measures and benchmarks, A little
queuing theory, Crosscutting issues, Designing and evaluating an I/O system.
Text Books
1. L. Hennessy & David A. Patterson, Morgan Kufmann Computer Architecture- A
Quantitative Approach 4th edition (An Imprint of Elsevier). (UNIT I- IV)
References
1. Kai Hwang and A. Briggs Computer Architecture and Parallel Processing
International Edition McGraw-Hill.
Dezso Sima, Terence Fountain, Peter Kacsuk, Advanced Computer Architectures,
Pearson.
42
ECVE 1006/4
REAL TIME UML
Lecture
Credits
:
:
4 Hrs/ Week
4
Final Examination:
40
60
Course Objectives
To introduce the syntax, semantics and pragmatics of UML, and how to integrate it
with the Unified Process.
To create a requirements model using UML class notations and use-cases based on
statements of user requirements.
To create the OO design of a system from the requirements model in terms of a
high-level architecture description, and low-level models of structural organization
and dynamic behavior using UML class, object, and sequence diagrams.
Learning Outcomes
articulate requirement models using use cases.
development of structural and behavioral diagrams for different views supported by
UML
development of patterns and frameworks and their applications in architecture and
design tasks
UNIT I
Introduction to the World of Real-time and Embedded Systems - Real-time systems,
Time, Performance, and Quality of service, Systems engineering vs. software engineering,
Architecture, The rapid object-oriented process for embedded systems (ROPES) process,
MDA and platform-independent models, Scheduling model-based projects, Model
organization principles, Working with model-based projects.
Object Orientation with UML 2.0 Structural Aspects - Object orientation with UML,
Objects, Classes and interfaces, Relations, Packages, Components and subsystem.
UNIT II
Object Orientation with UML 2.0 Dynamic Aspects - Behavior and the UML, Types of
behavior, Behavior primitives: Actions and activities, Behavior and the single object,
Interactions.
Requirements Analysis of Real Time Systems Requirements, Use cases, Detailing the
use cases.
43
UNIT III
Analysis: Object Domain Analysis The Object discovery process, Connecting the object
model with the use case model, Key strategies for object identification, Identify object
associations, Object attributes, Discovering candidate Classes, Class diagrams.
Analysis: Defining Object Behavior Object behavior, Defining object state behavior,
Interactions, Defining operation.
UNIT IV
Architectural Design Overview of design, Architectural design, Software meets
Hardware: Deployment architecture in UML, Concurrency and resource design.
Text Books
1. Bruce Powel Douglass, Real Time UML: Advances in the UML for Real Time
Systems, Third edition, Pearson Publications. (UNIT I- IV)
References
1. Meilir Page-Jones: Fundamentals of Object Oriented Design in UML, Pearson
Education.
2. Pascal Roques: Modeling Software Systems Using UML2, WILEY-Dreamtech India
Pvt. Ltd.
3. Atul Kahate: Object Oriented Analysis & Design, The McGraw-Hill Companies.
4. Mark Priestley: Practical Object-Oriented Design with UML,TATA McGrawHill.
5. Appling UML and Patterns: An introduction to Object Oriented Analysis and
Design and Unified Process, Craig Larman, Pearson Education.
44
ECVE 1051
VLSI DESIGN LAB
Practical : 3 Hrs/ Week
Credits : 2
Final Examination:
25
50
Course Objective
To describe digital circuits using Verilog HDL
To verify functionality of designed circuits using function simulator.
To perform Timing simulation for critical path time calculation.
To synthesis the designed digital circuits
To use Place and Route techniques for major FPGA/CPLD vendors such as
Xilinx, Altera and Actel etc.
Learning Outcomes
get acquainted with Programmable logic design flow.
implement designed digital circuits using FPGA and CPLD devices.
List of Experiments
Task #1 Design 16-bit data path and control unit for the following instruction set
Memory reference instructions - load word (lw) and store word (sw).
Arithmetic logic instructions add, subtract, and, or, slt.
Branch instructions branch equal (beq) and jump (jmp).
1.
2.
3.
4.
5.
Design a 16-bit ALU for Task #1

Design a 16-bit register file for Task #1
Design data path and control logic for memory reference instructions
Design data path and control logic for arithmetic & logic instructions
Design data path and control logic for branch instructions
Task #2 Design of communication and signal processing sub modules.

6. Design of 8-bit LFSR
7. Design of 4 bit multiply and accumulate unit
8. Design of a hardware multiplier
9. Design of filter
10. Design an Huffman coder
Task #3 Design CMOS circuits with given specifications, completing the design flow
mentioned below:
45
a. Draw the schematic and perform the following
i. DC analysis
ii. Transient analysis
b. Draw the layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the design
e. Verify & optimize for time, power and area to the given constraint
.
11. CMOS inverter with 0.25 micrometer technology, Vdd=2.5V to achieve a
propagation delay of 50psec with best possible power dissipation and minimizing
area.
12. CMOS XOR gate with 0.25 micrometer technology, Vdd=2.5V to achieve a
propagation delay of 50psec with best possible power dissipation and minimizing
area.
Text books
1. L. Hennessy & David A. Patterson (1998), Computer Organization and Design:
The Hardware/Software Interface 2nd edition, Morgan Kufmann Publishers.
2. Samir Palnitkar, Verilog HDL, Second Edition, Sun Microsystems Inc.
3. J.Rabaey (1996), Digital Integrated Circuits: a Design Perspective, PHI
46
ECVE 2001
LOW POWER VLSI DESIGN
Credits : 4
Final Examination:
40
60
Course Objectives
To introduce the students to the fundamentals of
low power design limitations
deep submicron processes
concept of device models of MOS and BJT
design of low power circuits and thorough analysis and evaluation
Learning Outcomes
understand the importance of low power design.
get exposure on limitations of power supply voltage, threshold voltage scaling.
characterize device models
evaluate quality measure of sequential circuits
UNIT I
Low Power CMOS VLSI Design - Introduction, Sources of power dissipation, Static
power dissipation, Active power dissipation.
Circuit Techniques for Low Power Design - Introduction, Designing for low-power,
Circuit techniques for leakage power reduction.
UNIT II
Low Voltage Low Power Adders - Introduction, Standard adder cells, CMOS adders
architectures, Low voltage low power esign techniques, Current mode adders.
Low Voltage Low Power Multipliers - Introduction, Overview of multiplication, Types of
multiplier architectures, Braun multiplier, Baugh-Wooley multiplier, Booth multiplier,
Wallace tree multiplier.
UNIT III
Low Voltage Low Power Static RAM - Basics of SRAM, Memory cell, Precharge and
equalization circuit, Decoder, Address transition detection, Sense amplifier, Output latch,
Low power SRAM technologies.
Low Voltage Low Power Dynamic RAM - Types of DRAM, Basics of DRAM, Self
refresh circuit, Half voltage generator, Voltage down converter, Future trends and
developments of DRAM.
47
UNIT IV
Low- Voltage Low Power Read-Only Memories - Introduction, Types of ROM, Basics,
Physics of floating gate nonvolatile devices, Floating gate memories, Basics of ROM, Low
power ROM technology.
Text Book
1. Kiat Seng Yeo, Kaushik Roy ,Low Voltage, Low Power VLSI Subsystems, TATA
McGraw-Hil.
References
1. Yeo Rofail,Gohl (2002), CMOS/BiCMOS ULSI Low Voltage, Low Power,
Pearson Education Asia 1st Indian reprint.
2. J.Rabaey (1996), Digital Integrated Circuits: a Design Perspective, PHI.
48
ECVE 2002
DIGITAL SYSTEM TESTING AND TESTABLE DESIGN
Credits : 4
Final Examination:
40
60
Course Objectives
To know the faults in system and reasons for occurrence of such faults.
To test stuck at faults and bridging faults
To generate test pattern of BIST and to know its architecture.
Learning Outcomes
analyze the response of the system to ascertain whether it behaves correctly after
manufacturing
test objectives to ensure product quality and diagnosis & repair.
understand the constraints of economics.
UNIT I
Fault Modeling - Logical fault models, Fault detection and redundancy, Fault equivalence
and fault location, Fault dominance, Single and multiple stuck-at fault model.
Fault Simulation - General fault simulation techniques, Fault simulation for combinational
circuits, Fault sampling.
UNIT II
Testing for Single Stuck at Faults ATG for SSFs in combinational circuits, ATG for
SSFs in sequential circuits.
Testing for Bridging Faults The bridging fault model, Detection of non-feedback
bridging faults, Detection of feedback bridging faults, Bridging fault simulation, Test
generation for bridging faults.
UNIT-III
Design for Testability: Testability, Adhoc design for testability techniques, Controllability
and observability by means of scan registers, Generic scan based design.
Compression Techniques - General aspects of compression techniques, Ones-count
compression, Transition-count compression, Parity-check compression, Syndrome testing,
Signature analysis.
49
UNIT-IV
Built-In Self Test - Test pattern generation for BIST, Generic off-line BIST architectures,
Specific BIST architecture.
Text Books
1. M. Abramovici, M.A. Breuer and A.D. Friedman ( 1996), Digital Systems and
Testable Design", Jaico Publishing House.
References
1. Parag K Lala (2002), Digital Circuit Testing and Testability, Achedamic Press.
2. M.L. Bushnell and V.D. Agrawal (2002), "Essentials of Electronic Testing for
Digital, Memory and Mixed-Signal VLSI Circuits", Kluwar Academic Publishers.
3. A.L. Crouch (2002), "Design for Test for Digital ICs and Embedded Core Systems",
Prentice Hall International.
50
ECVE 2003
HARDWARE-SOFTWARE CO-DESIGN
Credits : 4
Final Examination:
40
60
Course Objectives
To appreciate the importance of co-design and identify application areas where it is
used.
To identify the required co-synthesis algorithms, prototyping and emulation
architectures for co-design Environment.
To get familiarized with the types of languages or software used for design,
specification, verification when working in co-design environment.
To get familiarized with tools and techniques to be used for compilation of co-design
based design.
Learning Outcomes
demonstrate knowledge of architectural languages and co-synthesis algorithms for
co-design.
demonstrate knowledge of prototyping and emulation systems and target
architectures.
demonstrate knowledge of compilation tools and techniques for embedded processor
architectures and also design issues and system level specification languages for the
co-design.
UNIT I
Co-Design issues - Co- design Models, Architectures, Languages, A generic co-design
methodology.
Co-Synthesis Algorithms - Hardware software synthesis algorithms: Hardware Software
partitioning distributed system co-synthesis.
UNIT II
Prototyping and Emulation - Prototyping and emulation techniques, Prototyping and
emulation environments, Future developments in emulation and prototyping architecture
Specialization techniques, System communication infrastructure.
Target Architectures - Architecture specialization techniques, System communication
infrastructure, Target architecture and application system classes, Architecture for control
dominated systems (8051 architectures for high performance control), Architecture for data
dominated systems (ADSP21060, TMS320C60), Mixed systems.
51
UNIT III
Compilation Techniques and Tools for Embedded Processor Architectures - Modern
embedded architectures, Embedded software development needs, Compilation technologies,
Practical consideration in a compiler development environment.
Design Specification and Verification - Design, Co-design, The co-design computational
model, Concurrency coordinating Concurrent computations, Interfacing components,
Design verification, Implementation verification, Verification tools, Interface verification.
UNIT IV
Languages for System Level Specification and Design-I - System level specification,
Design representation for system level synthesis, System level specification languages.
Languages for System Level Specification and Design-II - Heterogeneous
specifications and multi-language co-simulation the Cosyma system and Lycos system.
Text Books
1. Jorgen Staunstrup. (2009), Hardware / Software Co- Design Principles and
Practice Wayne Wolf, Springer (UNIT I - IV).
References
1. Jean-Michel Berge (1997), Hardware/Software Co-Design and Co- Verification,
Kluwer Publications.
52
ECVE 2004
RTOS FOR EMBEDDED APPLICATIONS
Lecture
Credits
:
:
4 Hrs/ Week
4
Final Examination:
40
60
Course Objectives
To introduce Linux for embedded applications.
To give introduction the concepts of embedded real time programming.
To understand features and characteristics of Linux for embedded and real time
applications.
Learning Outcomes
Apply RTOS functions to implement embedded applications
Use and get acquaint to debugging embedded software tools.
Understand fundamentals of device drivers
Illustrate real time programming concepts.
UNIT I
The Embedded and Real Time Space - Introducing Linux - features, protected mode
architecture, the Linux process model, the Linux file system, the root user, the /user
hierarchy, the shell.
UNIT II
The Host Development Environment - Cross development tools, The GNU tool chain,
Configuring and building the kernel.
Debugging Embedded Software- The target setup, GDB, Debugging a sample program,
The Host as a debug environment, Adding programmable set point and limit.
UNIT III
Kernel Modules and Device Drivers - Kernel modules, Linux Device Drivers, Internal
driver structure, The hardware, Debugging kernel code, Building driver into the kernel
Embedded Networking: Sockets, A sample example, A remote thermostat, Embedded web
servers.
UNIT IV
Introduction to Real Time Programming - Polling vs. interrupts, Tasks, Scheduling,
Kernel services, Inter task communication, Problem with solving the resource sharing
problem Priority inversion, Interrupts and exceptions, Critical sections.
53
Textbook
1. Doug Abbott. (2003) Linux for Embedded and Real Time Applications, Newnes
publishers. (UNIT I, II, III & IV)
References
1. Rob Williams (2006), Real Time System Development, Linacre House, Oxford.
2. Michael Beck (1998), Linux Kernel Internals, Addison Wesley.
54
ECVE 2005/1
SEMICONDUCTOR MEMORY DESIGN
Credits : 4
Final Examination:
40
60
Course Objectives
To introduce to different memory structures, architectures, technologies.
To introduce to memory cell structures for different memories.
To provide the knowledge of sense amplifier and address decoding circuits in
memories.
Learning Outcomes
demonstrate memory cell structures and fabrication technologies.
describe application-specific memories and architectures.
demonstrate the working principle of sense amplifier circuit and its performance.
understand the significance of memory constituent sub-circuits.
UNIT I
Introduction to CMOS Memories - Classification and characterization of CMOS
memories, Random access memories, Sequential access memories, Content addressable
memories, Special memories and combinations.
UNIT II
Memory Cells - Dynamic one-transistor-one-capacitor random access memory cell,
Dynamic three-transistor random access memory cell, Static four-transistor random access
memory cell, Read only memory cells, Shift-register cells, Content addressable memory
cells.
UNIT III
Sense Amplifiers - Sense circuits, Sense amplifiers in general, Differential voltage sense
amplier, Current sense amplifiers, Offset reduction, Non-differential sense amplifiers.
UNIT IV
Memory Constituent Subcircuits - Array wiring, Reference circuits, Decoders, Output
buffers, Input receivers, Clock circuits, Power lines.
Text Books
1. Tegze P. Haraszti (2000), CMOS Memory Circuits, Kluwer Academic Press.
(UNIT I IV)
55
References
1. A.K Sharma, Semiconductor Memories Technology, Testing and Reliability,
IEEE Press.
2. Luecke Mize Care, Semiconductor Memory Design & Application, Mc-Graw Hill.
56
ECVE 2005/2
SYSTEM-ON-CHIP ARCHITECTURE
Credits : 4
Final Examination:
40
60
Course Objective
To develop ability to analyze and understand the state of art ARM processor used in
the industry.
To develop ability to analyze the architectural aspects for ARM processor core in
terms of assembly level programming and the high level languages.
To analyze the memory management issues for similar processor core.
To identify the applications where the ARM processor can be implemented.
Learning Outcomes
understand of the ARM processor architecture.
understand of the ARM instruction set architecture and write assembly programs and
high level languages for ARM architectures.
understand of the memory organization and interfacing issues.
UNIT I
Introduction to Processor Design - Abstraction in hardware design, MUO a simple
processor, Processor design trade off, Design for low power consumption.
ARM Processor as System-on-Chip - Acorn RISC machine Architecture inheritance
ARM programming model ARM development tools 3 and 5 stage pipeline ARM
organization ARM instruction execution and implementation ARM co-processor
interface.
UNIT II
ARM Assembly Language Programming - ARM instruction types data transfer, data
processing and control flow instructions ARM instruction set Co-processor instructions.
Architectural Support for High Level Language - Data types Abstraction in software
design Expressions Loops Functions and procedures Conditional statements Use of
memory.
UNIT III
Memory Hierarchy - Memory size and speed On-chip memory Caches Cache designAn example Memory management
Architectural Support for System Development - Advanced microcontroller bus
architecture ARM memory interface ARM reference peripheral specification
Hardware system prototyping tools Armulator Debug architecture.
57
UNIT IV
Architectural Support for Operating System - An introduction to operating systems
ARM system control coprocessor CP15 protection unit registers ARM protection unit
CP15 MMU registers ARM MMU architecture Synchronization Context switching
input and output.
Text Books
1. Steve Furber (2000), ARM System On Chip Architecture, 2nd ed., Addison
Wesley Professional. (UNIT I - IV).
References
1. Michael J Flynn, Wayne Luk, Computer System Design: System On Chip, Wiley
India Edition.
2. Prakash Rashinkar, Peter Paterson and Leena Singh L. (2001), System On Chip
Verification Methodologies and Techniques, Kluwer Academic Publishers.
3. Ricardo Reis (2004), Design of System On a Chip: Devices and Components 1st
ed., Springer.
58
ECVE 2005/3
PHYSICAL DESIGN AUTOMATION
Lecture
Credits
:
:
4 Hrs/ Week
4
Final Examination:
40
60
Course Objectives
To give clear idea about the VLSI design cycle and physical design cycle.
To design an IC by considering the fabrication process and its impacts
To understand the fabrication process of an IC.
Learning Outcomes
understand the working of physical design flow.
understand entire process for fabrication.
understand design and automation of the FPGAs and MCMs.
UNIT I
VLSI Physical Design Automation - VLSI design cycle , Physical design cycle, New
trends, Design styles, System packaging styles, Historical perspectives, Existing design
tools.
Fabrication Process and Its Impact - Fabrication materials, Fabrication of VLSI circuits,
Design rules, Layout of the basic design, Scaling methods, Status of fabrication process,
Issues related to fabrication process, Future of fabrication process, Tools and process
development.
UNIT II
Data Structures and Basic Algorithms - Complexity issues and NP-hardness, Basic
algorithms, Basic data structures, Graph algorithms for physical design.
UNIT III
Partitioning - Introduction to partitioning, Problem formulation, Classification of
partitioning algorithm, Group migration algorithm, Simulated annealing and evolution,
Other partitioning algorithm, Performance drive partitioning.
Floor Planning and Placement Floor planning, Chip Planning, Pin assignment,
Integrated approach, Placement.
UNIT IV
Routing and Automation of FPGAs and MCMs - Global routing, Detailed routing, Clock
routing, Power and ground routing, Compaction, Physical design automation of the FPGAs
and MCMs.
59
Text Books
1. Naveed A. Sherwani (1999), Algorithms for VLSI Physical Design Automation",
Kluwer Academic Publications, Third Edition.
Reference
1. S.H.Gerez (1998), Algorithms for VLSI Design Automation, Wiley Publication.
2. Sadiq M. Sait and Habib Youssef (1999), VLSI Physical Design Automation:
Theory and Practice by World Scientic Publishers, Singapore/New-Jersey, USA.
(Also published by McGraw-Hill Book Co., Europe, December 1995).
60
ECVE 2005/4
HIGH SPEED DIGITAL DESIGN
Lecture : 4 Hrs/Week
Credits : 4
Internal Assessment : 40
External Assessment : 60
Course Objectives
To study the high speed transmission lines.
To design the power distribution network and signaling circuits.
To study timing convention and synchronization.
Learning outcomes
understand the interconnect characteristics.
apply the design concepts to power distribution network and signaling circuits.
understand the timing and synchronization of clock signals.
UNIT I
Modeling and Analysis of Wires - Geometry and electrical properties of resistance,
capacitance and inductance, Electrical models of wires, Simple transmission lines - Lossless
LC transmission lines, Lossy LRC transmission lines, Special transmission lines.
UNIT II
Power Distribution - Power supply network - Local regulation - IR drops - Area bonding
On-chip bypass capacitors - Symbiotic bypass capacitors - Power supply isolation, Noise
sources in digital system - Power supply noise - Cross talk - Intersymbol interference.
UNIT III
Signaling Convention and Circuits - Signaling modes for transmission lines -Signaling
over lumped transmission media - Signaling over RC interconnect - Driving lossy LC lines Simultaneous bi-directional signaling, Terminations, Transmitter and receiver circuits.
UNIT IV
Timing Convention and Synchronization - Timing fundamentals - Timing properties of
clocked storage elements Encoding timings: Signals and events, Open loop timing - Level
sensitive clocking, Pipeline timing. Closed oop timing, Clock distribution, Synchronization
failure and metastability.
Text Books
1. William J. Dally & John W. Poulton; Digital Systems Engineering, Cambridge
University Press, 1998 (UNIT I IV)
61
References
1. Howard Johnson & Martin Graham(1993), High Speed Digital Design: A
Handbook of Black Magic, Prentice Hall PTR.
2. Masakazu Shoji(1996), High Speed Digital Circuits, Addison Wesley Publishing
Company.
3. Jan M, Rabaey (2003), et all; Digital Integrated Circuits: A Design Perspective ,
Second Edition, Prentice Hall.
62
ECVE 2006/1
NETWORKING & INTERNETWORKING USING
MICROCONTROLLERS
Credits : 4
Final Examination:
40
60
Course Objectives
To gain knowledge about on-chip network modules of different microcontrollers.
To gain knowledge in building network devices.
To get acquainted with interfacing LAN controller with various microcontrollers
Learning Outcomes
Upon completion of the course the students will be able to
develop a network using RS-232 standard
integrate network protocols into an embedded processor to establish network.
use LAN controller in establishing embedded network
understand different layers of TCP/IP module of easy ethernet.
UNIT I
The Essence of Microcontroller Networking RS-232 - RS-232 standard operating
procedure, Voltage conversion considerations.
Implementing RS-232 with a Microcontroller - Basic RS-232 hardware, Building a
simple microcontroller RS-232 transceiver, RS-232 interface hardware, A microcontroller
DCE device, Writing some simple RS-232 firmware, A bit of RS-232 transmit code, RS232 receive code.
Writing RS-232 microcontrollers routines in BASIC and Building, RS-232 communication
hardware: Basic RS-232, Instructions.
UNIT II
Microcontroller USART - Interrupt driven USART code.
I2C Serial Protocol: I2C basics and bus, I2C ACKS and NAKS, I2C addressing, PIC I2C
salve-transmitter mode code.
UNIT III
Ethernet: Basics, CS8900A-CQ - Reset overview, Media interface overview, Transmit
process overview, Receive process overview, External storage overview, Status indicator,
MAC engine, Ethernet engine, Hardware. PIC microcontroller, ICSP interface, Developing
easy Ethernet CS8900A Firmware, Setting up the PIC16F877 microcontroller, Carving up
the PIC16F877s memory resources, Easy ethernet CS8900A macros, Defining the
CS8900A-CQ packet page register set.
63
Unit IV
Writing the CS8900A-CQ Firmware - Reset the CS8900A-CQ, Load the CS8900A-CQ
basic parameters, Load the CS8900A-CQ individual address register set, Enable the
CS8900A-CQ transmitter and receiver, The main service loop, A frame under the
microscope, The art of ARP
TCP and easy Ethernet CS8900A - The physical layer, Data link layer, Network layer,
Transport layer, Application layer, Coding TCP/IP for the easy ethernet CS8900A
Text Book
1. Fred Eady. (Oct.2004), Networking and Internetworking with Microcontrollers,
Elsevier Inc. (UNIT I, II, III & IV)
References
1. Andrew N Sloss ARM System Developers Guide: Designing and Optimizing
System Software, Morgan Kaufmann Publishers, 2011
2. Crystal LAN ISA Ethernet Controller, CS8900A Datasheet
64
ECVE 2006/2
CMOS ANALOG & MIXED SIGNAL DESIGN
Lecture
Credits
:
:
4 Hrs/ Week
4
Final Examination:
40
60
Course Objectives
To study the basics of MOS transistor
To design amplifiers and current mirror circuits.
To study the feedback and frequency compensation techniques.
Learning outcomes
understand the characteristics of MOS transistor.
apply the concepts to different amplifier and current mirror circuits.
understand the feedback topologies and frequency compensation techniques.
UNIT I
Basic MOS Device Physics - MOS transistors- modeling in linear, saturation and cutoff
region, V/I characteristics, MOS device capacitances, MOS small signal model, Long
channel versus short channel devices.
UNIT II
Single Stage Amplifiers and Current Mirrors - Common source, common gate and
source follower stages- Cascode and folded cascode structures- Frequency response, MOS
current mirrors-sources.
UNIT III
MOS Differential Amplifiers and Operational Amplifiers - Single ended and differential
operation, Basic differential pair, Common mode response, Frequency response- CMOS
operational amplifiers - One-stage op-amps and two stage op-amps
UNIT IV
Feedback and Frequency Compensation - General considerations, Feedback topologies,
Stability and frequency compensation- Nonlinearity and mismatch in MOS differential
circuits.
Text Books
1. Behzad Razavi (2002), Design of Analog CMOS Integrated Circuits Tata-Mc
GrawHill. (UNIT I IV)
65
References
1. David A Johns & Ken Martin (2001), Analog Integrated Circuit Design John
Wiley and Sons.
2. Philip Allen & Douglas Holberg (2002), CMOS Analog Circuit Design, Oxford
University Press.
66
ECVE 2006/3
VLSI SIGNAL PROCESSING
Credits : 4
Final Examination:
40
60
Course Objectives
To introduce the basic methodologies and techniques in VLSI architectures for
digital signal processing and communication systems.
To provide hands-on VLSI system design experience using hardware description
language (HDL) and commercial EDA tools (Synopsys).
To design the architecture for the various signal processing applications and their
performance, area and energy efficiencies.
To present real-life case studies of communication system integrated circuit (IC)
design and implementations.
To provide the design methodologies and different algorithms for fast convolution.
Learning Outcomes
Understand design and optimization of signal processing systems used in
telecommunications, compression, encryption and coding applications
Understand the basic methodologies and techniques in VLSI architectures for digital
signal processing and communication systems.
Implement signal processing systems in "systems on a chip" designs for state-of-theart FPGAs or ASIC
Choose the architecture for the various signal processing applications and their
performance, area and energy efficiencies.
UNIT I
Introduction to DSP - Typical DSP algorithms, DSP algorithms benefits, Representation of
DSP algorithms
Pipelining and Parallel Processing - Introduction, Pipelining of FIR digital filters, Parallel
processing, Pipelining and parallel processing for low power
UNIT II
Retiming - Introduction Definitions and properties Solving system of inequalities
Retiming techniques
Folding - Introduction -Folding transform - Register minimization techniques Register
minimization in folded architectures folding of multirate systems
Unfolding - Introduction An algorithm for unfolding Properties of unfolding Critical
path, Unfolding and retiming Applications of unfolding
67
UNIT III
Systolic Architecture Design - Introduction Systolic array design methodology FIR
systolic arrays Selection of scheduling vector Matrix multiplication and 2D systolic
array design Systolic design for space representations contain delays
Fast Convolution - Introduction Cook-Toom algorithm Winogard algorithm Iterated
convolution Cyclic convolution Design of fast convolution algorithm by inspection,
Algorithmic strength reduction in filters and transforms Parallel FIR filters, DCT &
inverse DCT.
UNIT IV
Pipelined and Parallel Recursive and Adaptive Filters Pipeline interleaving in digital
filters, Pipelining in 1 st order IIR digital filters, Pipelining in higher-order IIR digital filters,
Parallel processing for IIR filters, Combined pipelining and parallel processing for IIR
filters.
Text Books
1. Keshab K. Parthi. (1998), VLSI Digital Signal Processing- System Design and
Implementation, Wiley Inter Science. (Units: I - IV)
References
1. Jose E. France, Yannis Tsividis. (1994) Design of Analog Digital VLSI Circuits
for Telecommunications and Signal Processing, Prentice Hall.
2. Medisetti V. K . (1995), VLSI Digital Signal Processing, IEEE Press (NY), USA.
68
ECVE 2006/4
FAULT TOLERANT AND CRITICAL SAFETY DESIGN
Credits : 4
Final Examination:
40
60
Course Objectives
To learn general abstraction of the system description and failures.
To introduce to reliability theory.
To study major techniques for hardware fault tolerance.
To deal with self checking circuits
Learning Outcomes
analyze failures, failure sources and their effects in a system.
understand reliability measures.
understand the significance of hardware, software, and time redundancies.
apply various design techniques for self checking circuits.
UNIT I
Basic Safety Technology Principles for Processing Systems - Risk definition and
analysis, Risk and consequences, Risk assessment, Risk graphics, Requirement classes, Risk
acceptability, Standard institutes and the role of standards and norms
Developing Safety-Critical Computer Systems: General Concepts - General abstract
system description: Description, System correctness and failure probability.
Faults Fault Sources Fault Effects Basic principles, Failures and faults, Fault
sources, Significance of fault sources, Fault effects.
UNIT II
Circuit Measures to Increase Reliability Reliability Parameters, Probability of Failure,
Mean Life Time, Mean Repair Time, Mean Time Between Failures, Availability, Failure
Rate, Reliability Models for System Devices, Redundant System with Different Failure
Rates, Replacement of Redundant System Components by Single System Components.
UNIT III
Fault Tolerant Design of Digital Systems - The importance of fault tolerance, Basic
concepts of fault tolerance, Static redundancy, Dynamic redundancy, Hybrid redundancy,
Self purging redundancy, Sift-out modular redundancy, 5MR reconfiguration scheme,
Fault tolerant design of memory systems using error correcting codes, Time redundancy,
Software redundancy, Fail-soft operation, Practical fault tolerant systems-FTMP, SIFT,
C.vmp, FTBBC.
69
UNIT IV
Self-Checking and Fail-Safe Logic - Introduction, Design of totally self checking
checkers, Self checking Sequential machines, Partially self checking circuits, Strongly fault
secure circuits, Fail safe design , Totally self checking PLA design.
Text Books
1. Josef Borcsok (2009), Electronic Safety Systems, Laxmi Publications Pvt Ltd.
(UNITS I & II)
2. Parag K. Lala (1985),Fault Tolerant and Fault Testable Hardware Design, BS
Publications. (UNITS III & IV)
References
1. Charles E. Stroud (2002), A Designer's Guide to Built-In Self-Test, Kluwer
Academic Publications.
2. Alexander Miczo (2003), Digital Logic Testing and Simulation, Second Edition
Wiley Publications.
70
ECVE 2051
EMBEDDED SYSTEMS LAB
Practical : 3 Hrs/ Week
Credits : 2
Final Examination:
25
50
Course Objectives
To train the students in writing the programs for 8051, PIC & ARM7 processor
using assembly or C language for various on-chip and off-chip peripherals with
and without RTOS.
Learning Outcomes
Upon completion of the course, students will be able to write
programs and use 8051, PIC and ARM7 microcontrollers for various applications.
1. Programs on 8051 instruction set.
2. Programs on 8051 peripherals
3. Programs on PIC instruction set.
4. Programs on PIC peripherals
5. Programs to read sensor and display values on PC.
6. Programs on ARM controller on chip peripherals.
7. Programs on I2C device interface (Memory)
8. Programs on I2C device interface(RTC)
9. Programs on multitasking using RTOS.
10. Program to implement semaphore for task switching using RTOS.
11. Programs to implement priority scheduling and OS time delay functions by writing 3
different tasks (using ARM controller).
12. Program to transfer data using Ethernet port.
71

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DETAILED

VLSI DESIGN AND EMBEDDED SYSTEMS

COURSE STRUCTURE VR10

SIDDHARTHA ENGINEERING COLLEGE

VIJAYAWADA 520 007

SIDDHARTHA ENGINEERING COLLEGE

Academic Regulations for M.Tech (VR10) w.e.f. 2010-2011

(Common to all branches)

Duration of the Programme

Minimum Instruction Days

Eligibility Criteria for Admission

Eligibility Requirement for Appearing Semester End Examinations

10. Examinations and Scheme of Evaluation

VLSI Design & Embedded Systems

Power System Engineering

3. DURATION OF THE PROGRAMME

5. ELIGIBILITY CRITERIA FOR ADMISSION

These seats will be filled by the Convener, PGECET.

5.2 CATEGORY B Seats :

Name of the Department

Civil Engineering Department

Computer Science and Engineering Department

Electronics & Communication Engineering Department

Electrical & Electronics Engineering Department

Mechanical Engineering Department

Third and fourth characters represent specialization offering as mentioned in Table

Name of the Specialization

Eighth character represents course number as described in figure1 below. However,

Figure 1: Course Code Description

6.2 Scheme of Instruction for 1st and 2nd Years

Lectures One Lecture period per week is assigned one credit.

6.4 Theory / Tutorial Classes

Each specialization of M.Tech programme is designed to have a total of 80

9. ELIGIBILITY REQUIREMENT FOR APPEARING SEMESTER END

b) Condonation of shortage in attendance may be recommended by respective Heads of

Students, having shortage of attendance, shall pay Rs.20/-per every period of

10. EXAMINATIONS AND SCHEME OF EVALUATION

assignments / term paper in each subject as notified by the teacher at the

For Laboratory courses there shall be continuous evaluation during the

Table 5: Distribution of Marks

10.1.3 Seminar/ Term paper: 25 marks

Table 6: Distribution of Marks

10.2 Semester End Examinations

10.2.2 Lab Courses: 50 marks

g) The thesis shall be adjudicated by one external examiner selected by the

11. CONDITIONS FOR PASS AND AWARD OF CREDITS FOR A COURSE

If a candidate secures minimum of 40% marks in theory courses in the

11.4 Calculation of Cumulative Grade Point Average (CGPA) for Entire

CONDUCT AND DISCIPLINE

18. OTHER MATTERS

Low Power VLSI Design

Sophocles.J.Orfamadis. (1988), Optimum Signal Processing: An introduction 2nd

Design a 16-bit ALU for Task #1

Task #2 Design of communication and signal processing sub modules.

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