Jingyu Hu E-mail: jingyuhu2009@yahoo.

com
42010 Blacow Rd. Apt 305 Tel.: (510) 585-8996
Fremont CA 94538

Objective: seeking IC layout design position

Summary of Qualifications
• Ten years experience in CUPIO library, analog/mix-signal and EEPROM layout
design, verification and extraction.
• Familiar with Virtuoso, Composer, Dracular and Calibre.

Work Experience
Oct. 2007 – Oct. 2009, Sr. Analog layout design at KeyASIC Inc. Santa Clara CA.
USA
• 3 CUPIO libraries layout from scratch with 0.13um 1P6M, 1P7M and 1P8M technology
• Performed IO cells floor plan and layout.
• Performed Post-layout netlist extraction and simulation
• Performed Test chip floor plan, whole chip LVS & DRC and tapeout procedure
• RF IO cell library with 0.15um 1P6M technology
• Performed IO cells floor plan and layout
• Performed Post-layout netlist extraction
• Performed Test chip floor plan, integration verification and tapeout procedure
• Multiple high voltages (32v/6v/5v/3.3v) IO cell library with 0.13um 1P6M high voltage
technology
• Performed IO cells floor plan, cell size optimization and layout

May 2006 – Aug. 2007 Analog Layout Design Engineer at ESS Technology Kelowna
BC, CANADA
• Responsible for Full-Custom analog layout design in following projects
• Performed 12 bits differential inputs; high-speed flashADC layout from scratch
• Performed Director Sampling Mixer (DSM) block of TV tuner layout from scratch
• Performed high performance audio dec layout from scratch

Mar. 2002 – Jun. 2005, Sr. Layout Design Engineer at AnalogIP Inc. Fremont CA,
USA
• Responsible for Full-Custom analog/mix-signal layout design in two projects using
Virtuoso
• Four generations USB2.0 transceiver PHY layer IP project by using 0.25um 1P4M,
0.18um 1P6M TSMC and SMIC technology
• Block level layout design; post-layout netlist extraction
• Performed different operational amplifiers and current mirrors
• Performed bandgap reference voltage layout
• Performed Charge Pump Phase-Locked Loop
 • Performed top-level integration, whole chip DRC & LVS check and tapeout
procedure
• Ethernet 10/100 base transceiver PHY layer IP project using 1P4M 0.25um TSMC
technology
• Block level layout design; post-layout netlist extraction
• Performed bandgap reference, comparator, current mirror, input and output
buffers of twist pair, Charge Pump Phase-Locked Loop
• Performed top-level integration and tapeout procedure

May, 1997 – Feb, 2002, Sr. Layout Design Engineer at Integrated Circuit
Technology Corp. San Jose, CA, USA
• Responsible for full custom layout design using Virtuoso in CPLDs and low power
PLDs using 0.8um, 0.6um and 0.35um UMC double poly EEPROM technology
• Performed global high voltage charge pump, local high voltage charge pump,
EEPROM array, sense amplifier, voltage and current reference and power-up
reset layout from scratch
• Performed top-level integration
• Ran whole chip DRC and LVS clearance using Dracular.

Education:
Sep., 1984 – Jul. 1989 B. Sc in Electrical Engineering of East China Normal University

REFERENCE: Available upon request.