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PRODUCT OVERVIEW
PRODUCT OVERVIEW
S3C8454 MICROCONTROLLER
The S3C8454 single-chip microcontroller is fabricated using a highly advanced CMOS process. Its design is
based on the powerful SAM87RC CPU core. Stop and Idle power-down modes were implemented to reduce
power consumption. The size of the internal register file is logically expanded, increasing the addressable on-chip
register space to 1040 bytes. A flexible yet sophisticated external interface is used to access up to 64-Kbytes of
program and data memory. The S3C8454 is a versatile microcontroller that is ideal for use in a wide range of
general-purpose applications such as CD-ROM/DVD-ROM drives.
Using the SAM87RC modular design approach, the following peripherals were integrated with the SAM87RC
CPU core:
Five configurable 8-bit general I/O ports
One 2-bit general I/O ports
Full-duplex serial data port with one synchronous operating modes
Two 8-bit timers with interval timer
Two 16-bit timers/counters with PWM operating modes or capture modes
One voltage level detector pin
Four embedded chip selection pins (CS0CS4) or normal I/O ports
Two programmable 8-bit PWM modules with corresponding output pins
A/D converter with 4 selectable input pins
OTP
The S3C8454 microcontroller is also available in OTP(One Time Programmable) version, S3P8454
The S3P8454 microcontroller has an on-chip 4K-byte one-time-programmable EPROM instead of masked ROM.
The S3P8454 is comparable to S3C8454, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS88C4504/P4504
FEATURES
CPU
Memory
External Interface
ADC
SIO
Interrupts
PWM
8-bit Timers
16-bit Timer/Counters
40 C to + 85 C
Package Types
Operating frequency
1-2
S3C8454/P8454
PRODUCT OVERVIEW
BLOCK DIAGRAM
External Address/Data
(A0-A7)
(A8-A15)
(D0-D7)
SAM8 BUS
SO
SI
SCK
Port 1
P1.0-P1.4
P1.5-P1.7/
SI, SO, SCK
Port 2
P2.0-P2.7/
INT0-INT7
Port 3
P3.0-P3.7/
TDCK, TCCK
TDCAP, TCCAP
TCOUT, TDOUT
PWM0, PWM1
Watchdog
Timer
Port4/
Chip
Selection
Logic
SAM87 RC CPU
Timers
A and B
TCCK
TDCK
TCOUT
TDOUT
P0.0-P0.3
P0.4-P0.7/
ADC0-ADC3
Port 5
Port I/O
& Interrupt
Control
P4.0-P4.7/
CS0-CS4
Port 0
Timers
C and D
1040-Byte
Register File
Serial
Port
SAM8 BUS
AVSS
(Internal)
AVREF
A/D
Converter
ADC0/P0.4ADC3/P0.7
4-Kbyte
ROM
VDD1, VSS1
VDD2, VSS2
PWM
Module
PWM0 PWM1
1-3
PRODUCT OVERVIEW
KS88C4504/P4504
PIN ASSIGNMENT
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PM
DM
RD
WR
VLD
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
CS1/P4.5
CS0/P4.4
VDD1
VSS1
XOUT
XIN
EA
P4.3
P4.2
RESET
P4.1
P4.0
PWM1/P3.7
PWM0/P3.6
TDOUT/P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
KS88C4504
80-QFP
(Top View)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P1.5/SI
P1.6/SO
P1.7/SCK
P2.0/INT0
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
P2.5/INT5
P2.6/INT6
P2.7/INT7
P3.0/TDCK
P3.1/TCCK/
P3.2/TDCAP
P3.3/TCCAP
P3.4/TCOUT
1-4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D7
D6
D5
D4
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
S3C8454/P8454
PRODUCT OVERVIEW
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PM
DM
RD
WR
VLD
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
CS1/P4.5
CS0/P4.4
VDD1
VSS1
XOUT
XIN
EA
P4.3
P4.2
RESET
P4.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
KS88C4504
80-TQFP
(Top View)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P1.5/SI
P1.6/SO
P1.7/SCK
P2.0/INT0
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
P2.5/INT5
P2.6/INT6
P2.7/INT7
P3.0/TDCK
P3.1/TCCK/
P3.2/TDCAP
P3.3/TCCAP
P3.4/TCOUT
TDOUT/P3.5
PWM0/P3.6
PWM1/P3.7
P4.0
1-5
PRODUCT OVERVIEW
KS88C4504/P4504
PIN DESCRIPTIONS
Table 1-1. S3C8454/P8454 Pin Descriptions
Pin
Name
Pin
Type
Pin Description
Circuit
Type
Pin
Number
Share
Pins
P0.0P0.7
I/O
2, 3
5654,
51, 4946
ADC0
ADC3
P1.0P1.7
I/O
4538
SI, SO,
SCK
P2.0P2.7
I/O
3730
INT0
INT7
P3.0P3.7
I/O
3, 5
2922
TDCK
TCCK
TDCAP
TCCAP
TDOUT/
TDPWM
TCOUT/
TCPWM
PWM0
PWM1
P4.0P4.7
I/O
3, 5
21, 20,
18, 17,
118
CS0CS3
1-6
S3C8454/P8454
PRODUCT OVERVIEW
Pin
Type
Pin
Description
Circuit
Type
QFP Pin
Number
Share
Pins
I/O
WAIT
ADC0ADC3
4946
P0.4P0.7
AVREF
50
PWM0, PWM1
23,22
P3.6, P3.7
INT0INT7
3730
P2.0P2.7
TCCK, TDCK
28,29
P3.1/P3.0
TCCAP,TDCAP
26,27
P3.3/P3.2
WAIT
P5.0
RESET
19
EA
16
VDD1, VSS1
12,13
VDD2, VSS2
53, 52
XIN, XOUT
15, 14
P5.0P5.1
I/O
40,39,38
P1.5/P1.6
P1.7
A0A15
6580
D0D7
I/O
5764
PM,DM
1, 2
RD,WR
3, 4
CS0CS3
118
P4.4P4.7
TCOUT,TDOUT
25, 24
P3.4, P3.5
VLD
NOTE: VDD1 must be connected to VDD2 in users application circuit, VSS1 & VSS2 also.
1-7
PRODUCT OVERVIEW
KS88C4504/P4504
PIN CIRCUITS
Table 1-2. Pin Circuit Assignments for the S3C8454/P8454
Circuit Number
Circuit Type
Input
I/O
I/O
Port 0, 1, 3, 4, and 5
I/O
P2 (INT0INT7)
I/O
Output
I/O
1-8
S3C8454 Assignments
RESET pin
S3C8454/P8454
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
(Typical 240 k)
Input
VDD
Data
I/O
Output
Disable
Vss
Normal
Input
ADC Port
Selection
ADC In
Pull-Down
Enable
Enable ADC
1-9
PRODUCT OVERVIEW
KS88C4504/P4504
VDD
Pull-Up
Enable
VDD
Data
I/O
Output
Disable
Normal
Input
SCK Input
Noise
Filter
VDD
Pull-Up
Resistor
Pull-Up
Enable
VDD
Data
I/O
Output
Disable
Vss
External
Interrupt
Input
Noise Filter
Normal
Input
1-10
S3C8454/P8454
PRODUCT OVERVIEW
VDD
Pull-Up
Resistor
Pull-Up
Enable
VDD
Selection bits
for ports or
other function
Data
I/O
Output
Disable
Vss
Input
Other
Function
VDD
In
Out
1-11
PRODUCT OVERVIEW
KS88C4504/P4504
VDD
Data
I/O
Output
Disable
Normal
Input
1-12
S3C8454/P8454
18
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, S3C8454 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
Absolute maximum ratings
D.C. electrical characteristics
A.C. electrical characteristics
I/O capacitance
Oscillation characteristics
Oscillation stabilization time
18-1
ELECTRICAL DATA
S3C8454/P8454
Symbol
Conditions
VDD
Rating
Unit
0.3 to + 6.5
Input voltage
VI
Output voltage
VO
I OH
18
mA
60
+ 30
+ 100
18-2
I OL
mA
TA
40 to +85
TSTG
65 to +150
S3C8454/P8454
ELECTRICAL DATA
Symbol
VDD
Conditions
Min
Typ
Max
Unit
f OSC = 25 MHz
(instruction clock = 6.25 MHz)
4.5
5.5
f OSC = 12 MHz
(instruction clock = 3 MHz)
2.7
5.5
VDD
0.2 VDD
VIH1
0.51 VDD
VIH2
XIN
VDD 0.5
VIH3
Test, RESET
VIL1
VIL2
XIN
VIL3
Test, RESET
0.2VDD
VOH
VDD= 5 V
IOH = 1 mA
VDD 1.0
IOH = 100 uA
VDD 0.5
0.8VDD
0.4
VOL1
VDD = 5 V
IOL = 2 mA
All output pins except port 2
0.4
VOL2
VDD = 5 V
IOL = 15 mA, port 2
0.5
1.0
ILIH1
VIN = VDD
All input pins except XIN
ILIH2
VIN = VDD
XIN
ILIL1
VIN = 0 V
All input pins except XIN and
20
RESET
ILIL2
VIN = 0 V,
20
XIN, RESET
Output high leakage
current
ILOH
VOUT = VDD
All I/O pins and output pins
ILOL
VOUT = 0 V
All I/O pins and output pins
RL1
30
46
80
120
240
320
Ports 0-5, TA = 25 C
RL2
TA = 25 C, RESET only
18-3
ELECTRICAL DATA
S3C8454/P8454
Symbol
IDD1
IDD2
IDD3
Conditions
Min
Typ
Max
Unit
VDD = 5 V 10 %
20 MHz oscillation
20
40
mA
VDD = 2.7 V
12 MHz oscillation
14
16
110
220
Stop mode;
VDD = 5 V 10 %
LVD enable, TA = 25 C
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Symbol
Conditions
Min
Typ
Max
Unit
tINTH,
tINTL
VDD = 5 V
180
nS
tRSL
VDD = 5 V
1000
nS
NOTES:
1. The unit tCPU means one CPU clock period.
2. The oscillator frequency is the same as the CPU clock frequency.
tINTL
tINTH
0.8 VDD
0.2 VDD
18-4
S3C8454/P8454
ELECTRICAL DATA
tRSL
RESET
0.2 VDD
Symbol
Input capacitance
CIN
Output capacitance
Conditions
f = 1 MHz; unmeasured
pins are connected to VSS
Min
Typ
Max
Unit
10
pF
COUT
I/O capacitance
CIO
Symbol
VDDDR
IDDDR
Conditions
Min
Typ
Max
Unit
5.5
50
NOTES:
1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped.
2. Supply current does not include drawn through internal pullup resistors and external output current loads.
18-5
ELECTRICAL DATA
S3C8454/P8454
Oscillation
Stabilization
Time
Reset
Occurs
~
~
Normal
Operating
Mode
Stop Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instrction
RESET
0.2 VDD
NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.
tWAIT
18-6
S3C8454/P8454
ELECTRICAL DATA
Symbol
Conditions
Resolution
Total accuracy
VDD = 5 V
Min
Typ
Max
Unit
bit
LSB
ILE
Conversion time = 5 us
DLE
AVREF = 5 V
EOT
AVSS = 0 V
EOB
0.5
tCON
17
170
VIAN
AVss
AVREF
RAN
1000
AVREF
2.5
VDD
Analog ground
AVSS
VSS
VSS+ 0.3
IADIN
AVREF = VDD = 5 V
10
uA
Analog block
IADC
AVREF = VDD = 5 V
mA
AVREF = VDD = 3 V
0.5
1.5
mA
AVREF = VDD = 5 V
When power down mode
100
500
nA
Conversion time
current (2)
(1)
NOTES:
1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.
2. IADC is an operating current during A/D conversion.
18-7
ELECTRICAL DATA
S3C8454/P8454
VDD
Reference
Voltage
Input
R
AVREF
10 pF
+
-
C 103
VDD
Analog
Input Voltage
ADC0-ADC3
S3C8454
C 101
VSS
NOTE:
The symbol 'R' signifies an offset resistor with a value of from 50 to 100.
If this resistor is omitted, the absolute accuracy will be maximum of 3 LSBs.
Figure 18-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
18-8
S3C8454/P8454
ELECTRICAL DATA
Symbol
Conditions
Min
Typ
Max
Unit
tCYC
200
nS
tSCKH
60
TSCKL
60
TOD
50
TID
40
TIH
100
tCYC
tSCKL
tSCKH
SCK
0.8 VDD
0.2 VDD
tID
tIH
0.8 VDD
SI
Input Data
0.2 VDD
tOD
SO
Output Data
18-9
ELECTRICAL DATA
S3C8454/P8454
Clock Circuit
XIN
XOUT
C1
Ceramic
External clock
Test Condition
XIN
Min
Typ
Max
Unit
25
MHz
25
MHz
25
MHz
Min
Typ
Max
Unit
C2
XOUT
C1
C2
XIN
XOUT
Test Condition
Crystal
10
ms
Ceramic
ms
External clock
50
ns
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore
be held at low level until the tST1 time has elapsed.
18-10
S3C8454/P8454
ELECTRICAL DATA
1/fOSC1
tXL
tXH
XIN
VDD - 0.5 V
0.4 V
Symbol
Conditions
Min
Typ
Max
Unit
VDDVLD
2.7
5.5
Detect Voltage
VVLD
1.15
1.40
1.51
Current consumption
IVLD
VDD = 5.5 V
100
200
uA
18-11
ELECTRICAL DATA
S3C8454/P8454
fCPU
fOSC
B
25 MHz
6.25 MHz
18 MHz
16 MHz
14 MHz
4.5 MHz
4 MHz
3.5 MHz
3 MHz
12 MHz
1 MHz
4 MHz
1
3
2.7
4.5
18-12
S3C8454/P8454
MECHANICAL DATA
19
MECHANICAL DATA
OVERVIEW
The S3C8454 microcontroller is available in a 80-pin QFP package (80-QFP-1420C) and a 80-pin TQFP
package (80-TQFP-1212AN).
23.90 0.30
0-8
20.00 0.20
+ 0.10
14.00 0.20
0.10 MAX
80-QFP-1420C
0.80 0.20
17.90 0.30
0.15 - 0.05
#80
#1
0.80
0.35 + 0.10
0.05 MIN
0.15 MAX
(0.80)
2.65 0.10
3.00 MAX
0.80 0.20
19-1
MECHANICAL DATA
S3C8454/P8454
14.00 BSC
0-7
12.00 BSC
12.00 BSC
80-TQFP-1212
0.60 0.15
14.00 BSC
0.09-0.20
#80
#1
0.17-0.27
0.50
0.05-0.15
(1.25)
1.00 0.05
1.20 MAX
19-2
S3C8454/P8454
20
S3P8454 OTP
S3P8454 OTP
OVERVIEW
The S3P8454 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8454
microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data
format.
S3P8454 is fully compatible with S3C8454, both in function and in pin configuration. As it has simple
programming requirements, S3P8454 is ideal for use as an evaluation chip for the S3C8454.
20-1
S3P8454 OTP
S3C8454/P8454
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PM
DM
RD
WR
VLD
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
SDAT/CS1/P4.5
SCLK/CS0/P4.4
VDD1/VDD1
VSS1/VSS1
XOUT
XIN
VPP/EA
P4.3
P4.2
RESET/RESET
RESET
P4.1
P4.0
PWM1/P3.7
PWM0/P3.6
TDOUT/P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S3P8454
80-QFP
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P1.5/SI
P1.6/SO
P1.7/SCK
P2.0/INT0
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
P2.5/INT5
P2.6/INT6
P2.7/INT7
P3.0/TDCK
P3.1/TCCK
P3.2/TDCAP
P3.3/TCCAP
P3.4/TCOUT
NOTE:
20-2
D7
D6
D5
D4
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
S3C8454/P8454
S3P8454 OTP
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PM
DM
RD
WR
VLD
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
SDAT/CS1/P4.5
SCLK/CS0/P4.4
VDD1/VDD1
VSS1/VSS1
XOUT
XIN
VPP/EA
P4.3
P4.2
RESET/RESET
RESET
P4.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
S3P8454
80-TQFP
(Top View)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P1.5/SI
P1.6/SO
P1.7/SCK
P2.0/INT0
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
P2.5/INT5
P2.6/INT6
P2.7/INT7
P3.0/TDCK
P3.1/TCCK
P3.2/TDCAP
P3.3/TCCAP
P3.4/TCOUT
TDOUT/P3.5
PWM0/P3.6
PWM1/P3.7
P4.0
20-3
S3P8454 OTP
S3C8454/P8454
During Programming
Pin Name
Pin No.
I/O
Function
P4.5
SDAT
10
I/O
P4.4
SCLK
11
VPP
16
RESET
RESET
19
Chip Initialization
VDD1/VSS1
VDD/VSS
12/13
EA
S3P8454
S3C8454
Program Memory
4 Kbyte EPROM
2.7 V to 5.5 V
2.7 V to 5.5V
Pin Configuration
80 QFP, 80 TQFP
80 QFP, 80 TQFP
EPROM Programmability
VPP
(TEST)
REG
/MEM
Address
(A15A0)
R/W
5V
0000H
EPROM read
12.5 V
0000H
EPROM program
12.5 V
0000H
EPROM verify
12.5 V
0E3FH
20-4
Mode
S3C8454/P8454
S3P8454 OTP
Symbol
VDD
Conditions
Min
Typ
Max
Unit
f OSC = 25 MHz
(instruction clock = 6.25 MHz)
4.5
5.5
f OSC = 12 MHz
(instruction clock = 3 MHz)
2.7
5.5
VDD
0.2 VDD
VIH1
0.51 VDD
VIH2
XIN
VDD 0.5
VIH3
Test, RESET
VIL1
VIL2
XIN
VIL3
Test, RESET
0.2VDD
VOH
VDD= 5 V
IOH = 1 mA
VDD 1.0
IOH = 100 uA
VDD 0.5
0.8VDD
0.4
VOL1
VDD = 5 V, IOL = 2 mA
All output pins except port 2
0.4
VOL2
0.5
1.0
ILIH1
VIN = VDD
All input pins except XIN
ILIH2
ILIL1
VIN = 0 V
All input pins except XIN and
20
RESET
ILIL2
ILOH
VOUT = VDD
All I/O pins and output pins
ILOL
VOUT = 0 V
All I/O pins and output pins
RL1
30
46
80
120
240
320
20
Ports 0-5, TA = 25 C
RL2
TA = 25 C, RESET only
20-5
S3P8454 OTP
S3C8454/P8454
Symbol
ILOH
ILOL
RL1
Conditions
Min
Typ
Max
Unit
VOUT = VDD
All I/O pins and output pins
VOUT = 0 V
All I/O pins and output pins
VIN = 0 V; VDD = 5 V 10 %
30
46
80
VIN = 0 V; VDD = 5 V 10 %
120
240
320
20
40
VDD = 2.7 V
12 MHz oscillation
14
16
110
220
Ports 0-5, TA = 25 C
RL2
TA = 25 C, RESET only
Supply current (note)
IDD1
IDD2
IDD3
VDD = 5 V 10 %
20 MHz oscillation
mA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
20-6