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wht is dft?

wht is the diffrence between verification and dft?

difference between defect, fault and failure?
wht is observability and controlability?
wht is scan?
how can we perform scan operation?
wht is serial and parallel loading?
wht is the difference between sequential and combinational atpg?
wht is atpg?
wht is drc violation?
wht is fault model?
how many fault models are there?
wht is scan stiching?
wht is bist?
Compare LOC and LOS
What is setup time and hold time
Clock divider
What is compression
Fault coverage vs test coverage
In scan chains if some flip flops are +ve edge triggered and remaining flip flops are
-ve edge triggered
What you mean by scan chain reordering?
Diff b/w Named Capture Precedures and Clock Procedures
How much is your design count? Complexity? Clock freq
how do you debug simulation mismatches when you simulae the generated ATPG
how do you solve coverage issues?

lockup latches in the scan chains.

These are inserted in the chains where ever there is a change in the clock domain.
By clock domain we mean, two clocks or the same clock with phase difference.

Let us have a condition here to explain the things; we have a design with 2 clocks
CLK1 and CLK2. There is a single chain in the design, which means that the scan
chain have flops which can be clocked by either of the clock.
The tool by default will order the flops in the scan chain such that first we have one
clock domain's flop followed by the other domain flops. Let us consider that the
CLK2 flops follows CLK1 flops.
Now consider the flop which is at the boundary that is the one where the output of
the CLK1's flop is going to the CLK2's scan_in. Clock skew between these successive
scan-storage cells must be less than the propagation delay between the scan output
of the first storage cell and the scan input of the next storage cell. Otherwise, data
slippage may occur. Thus, data that latches into the last flop of CLK1 also latches
into the first flop of CLK2. This situation results in an error because the CLK2's flop
should latch the CLK1's "old" data rather than its "new" data.
To overcome this issue we add the lock up latch where ever there are clock domain
crossing. In our example we would add a lock-up latch which has an active high
enable and is being controlled by inverted of CLK1. Thus becomes transparent only
when CLKA goes low and effectively adds a half clock of hold time to the output of
the last flip-flop of clock domain CLK1.

1. In your design you have dual port memories each working at a different
frequency. What is the clock frequency you use for testing (MBIST)?
2. When a failure is detected in parallel testing of memories, how do you know
which memory is failing?
3. What are the extra pins needed for BIRA (Built In Repair Analysis)
4. What could be the possible reasons for scan chain failures during GLS (Gate level
Simulation)? Other than setup issues.
5. Did you got any issues during timing simulation of MBIST patterns?
6. What are typical frequencies for scan shift, MBIST tests?
7. How is it different implementing MBIST logic for ROMs, SRAM, DRAMS, and
register files? Can same controller handle all these? What are the typical issues
8. What are the differences between IJTAG and JTAG standard?
9. What are the differences between Boundary scan and IEEE1500 standards? Other
than Boundary scan is used for board level testing and the IEEE1500 for core based
10. What is the effect of LOS method for testing delay faults on the tester?
11. What are the typical issues you face during timing simulation of scan and MBIST

12. What are copy and shadow cell? How are they useful?
13. What are the typical clock skew issues you faced during post layout/ timing
14. How do you implement DFT for a design have lot of Analog blocks? How to
improve coverage?
15. How do you test at-speed faults for inter clock domains?
16. Are multi-cycle paths tested in the design?
17. Why do you need multiple-load patterns? What are its advantages over basic
scan patterns?
18. What are the typical steps to improve coverage when our coverage target is not
19. Steps to fix broken scan chain issues during ATPG? Step by step procedure to
find the issue?
20. What is sequential depth?
21. How to specify clocks for at-speed testing in encounter test or any other tool?
What is the syntax?
22. In SDF we have 3 values best, typical and worst case? Best is for good
processor, less temp , high vol and worst is reverse. What is typical?
23. What is split capture?
24. What Is the most challenging issue you faced? How you fixed it?