VHDL Data Types

VHDL Data Types
Suresh Balpande
www.sbalpande.webs.com
VHDL Data Types
VHDL Data Types

Scalar
Integer
Enumerated
Real (floating point)*
Physical*
Composite
Array
Record
Access (pointers)*
* Not supported by synthesis tools
Predefined Data Types
bit (0 or 1)
bit_vector (array of bits)
integer
real
time (physical data type)
Different data types

Enumeration:
Red, blue
standard
logic:
Resolved,
Unresolved
Boolean:
TRUE,
FALSE
Data
types
Float:
0.124
Integer:
13234,23
Bit:
0,1
Character
a,b
String:
text
Examples of some common types

Type BOOLEAN is (FALSE, TRUE)
type bit is (0 ,1);
type character is (-- ascii string)
type INTEGER is range of integer numbers
type REAL is range of real numbers
VHDL Data Objects

Constant
Variable
Signal
File*
* Not supported by synthesis tools

Identifiers
May contain A-Z, a-z, 0-9, _
Must start with letter
May not end with _
May not include two consecutive _
VHDL is case insensitive
Sel sel and SEL refer to same object
Identifier Examples
A2G
valid
8bit_counter
invalid -- starts with number
_NewValue
invalid -- starts with _
first#
invalid -- illegal character
Characters and Strings

Characters
A, 0, 1, $, x, *
Strings
string of characters
00101101
0X110ZZ1
Characters and Strings

Bit Strings
B011111010110
O3726
X7D6
Integer Data Type
Integer
Minimum range for any implementation as defined by
standard: - 2,147,483,647 to 2,147,483,647
Example assignments to a variable of type integer :
ARCHITECTURE test_int OF test IS
BEGIN
PROCESS (X)
VARIABLE a: INTEGER;
BEGIN
a := 1; -- OK
a := -1; -- OK
a := 1.0; -- illegal
END PROCESS;
END test_int;
Integer Data Type

Minimum range for any implementation: 2,147,483,647 to 2,147,483,647
Define range of integer
minimizes synthesized logic
type CountValue is range 0 to 15;

type Twenties is range 20 to 29;
type Thirties is range 39 downto 30;
Example of Integer Data Type

process(addr)
variable j: integer range 0 to 35;
variable addru: unsigned(7 downto 0);
begin
for i in 7 downto 0 loop
addru(i) := addr(i);
end loop;
j := conv_integer(addru);
M <= rom(j);
end process;
Enumeration types:
An enumeration type is defined by listing
(enumerating) all possible values
Examples:
type COLOR is (BLUE, GREEN,
YELLOW, RED);
type MY_LOGIC is (0, 1, U, Z);
-- then MY_LOGIC can be one of the 4
values
VHDL Data Types

Scalar Types (Cont.)
Enumerated
User specifies list of possible values
Example declaration and usage of enumerated data type :
TYPE binary IS ( ON, OFF );
... some statements ...
ARCHITECTURE test_enum OF test IS
BEGIN
PROCESS (X)
VARIABLE a: binary;
BEGIN
a := ON; -- OK
... more statements ...
a := OFF; -- OK
... more statements ...
END PROCESS;
END test_enum;
Exercises
Example of the enumeration type of the menu of a restaurant:
type food is (hotdog, tea, sandwich, cake, chick_wing);
(a) Declare the enumeration type of the traffic light.
Answer: _______________________________________
(b) Declare the enumeration type of the outcomes of rolling a
dice.
Answer: _______________________________________
(c) Declare the enumeration type of the 7 notes of music.
Answer: _______________________________________
Physical
Physical
Can be user defined range
Physical type example
Time units are the only predefined physical type in VHDL.
Physical
Physical
Can be user defined range
Physical type example
Current in Amp, mA.,
Predefined physical data type
VHDL Data Types

Real
Minimum range for any implementation as defined by
standard: -1.0E38 to 1.0E38
Example assignments to a variable of type real :
ARCHITECTURE test_real OF test IS
BEGIN
PROCESS (X)
VARIABLE a: REAL;
BEGIN
a := 1.3; -- OK
a := -7.5; -- OK
a := 1; -- illegal
a := 1.7E13; -- OK
a := 5.3 ns; -- illegal
END PROCESS;
END test_real;
VHDL Data Types

Physical
Require associated units
Range must be specified
Example of physical type declaration :
TYPE resistance IS RANGE 0 TO 10000000
UNITS
ohm; -- ohm
Kohm = 1000 ohm; -- i.e. 1 KW
Mohm = 1000 kohm; -- i.e. 1 MW
END UNITS;
Time is the only physical type predefined in

VHDL standard
Booleans
type boolean is (false, true);
variable A,B,C: boolean;
C := not A
C := A and B
C := A or B
C := A nand B
C := A nor B
C := A xor B
C := A xnor B
Bits
type bit is (0, 1);
signal x,y,z: bit;
x <= 0;
y <= 1;
z <= x and y;
Standard Logic
library IEEE;
use IEEE.std_logic_1164.all;
type std_ulogic is ( U, -- Uninitialized

X -- Forcing unknown
0 -- Forcing zero
1 -- Forcing one
Z -- High impedance
W -- Weak unknown
L -- Weak zero
H -- Weak one
-); -- Dont care
Standard Logic
type std_ulogic is unresolved.
Resolved signals provide a mechanism
for handling the problem of multiple
output signals connected to one signal.
subtype std_logic is resolved std_ulogic;
Resolved logic concept

(Multi-value Signal logic)
Can the outputs be connected together?
C1
??
C2
Resolved signal concept

Signal c1,c2, b1: bit;
b1<=c1;
c1
b1
Resolved signal concept

Signal c1,c2, b1: bit;
b1<=C1;
b1<=C2;
??
illegal
C1
b1
??
C2
Type Std_logic and std_ulogic
Std_logic is a type of resolved logic, that means a signal

can be driven by 2 inputs
std_ulogic: (the u: means unresolved) Std_ulogic type
is unresolved logic, that means a signal cannot be driven
by 2 inputs
VHDL Data Types

Composite Types
Array
Used to group elements of the same type into a single VHDL object
Range may be unconstrained in declaration
Range would then be constrained when array is used
Example declaration for one-dimensional array (vector) :
TYPE data_bus IS ARRAY(0 TO 31) OF BIT;
0 ...element indices... 31
0 ...array values...
1
VARIABLE X : data_bus;
VARIABLE Y : BIT;
Y := X(12);
-- Y gets value of element at index 12

VHDL Data Types

Composite Types (Cont.)
Example one-dimensional array using DOWNTO :
TYPE reg_type IS ARRAY(15 DOWNTO 0) OF BIT;
15 ...element indices... 0
0 ...array values...
1
VARIABLE X : reg_type;
VARIABLE Y : BIT;
Y := X(4);
-- Y gets value of element at index 4
DOWNTO keyword must be used if leftmost

index is greater than rightmost index
Big-endian bit ordering, for example
VHDL Data Types

Composite Types (Cont.)
Records
Used to group elements of possibly different types into a single
VHDL object
Elements are indexed via field names
Examples of record declaration and usage :
TYPE binary IS ( ON, OFF );
TYPE switch_info IS
RECORD
status : BINARY;
IDnumber : INTEGER;
END RECORD;
VARIABLE switch : switch_info;
switch.status := ON; -- status of the switch
switch.IDnumber := 30; -- e.g. number of the switch

VHDL Data Types

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VHDL Data Types

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VHDL Data Types

VHDL Data Types

VHDL Data Types

Predefined Data Types

Different data types

Examples of some common types

VHDL Data Objects

* Not supported by synthesis tools

Characters and Strings

Characters and Strings

Integer Data Type

Integer Data Type

type CountValue is range 0 to 15;

Example of Integer Data Type

VHDL Data Types

Time units are the only predefined physical type in VHDL.

Current in Amp, mA.,

Predefined physical data type

VHDL Data Types

VHDL Data Types

Time is the only physical type predefined in

type std_ulogic is ( U, -- Uninitialized

Resolved logic concept

Resolved signal concept

Resolved signal concept

Type Std_logic and std_ulogic

Std_logic is a type of resolved logic, that means a signal

VHDL Data Types

-- Y gets value of element at index 12

VHDL Data Types

-- Y gets value of element at index 4

DOWNTO keyword must be used if leftmost

VHDL Data Types

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