Reference:

The 8051 Microcontroller: Architecture, Programming & Applications

by
Kenneth J. Ayala

What is Microcontroller (C)

Microprocessor is CPU on chip.
Microcontroller is computer on chip.
Microcontroller functions as a complete system without the need of any external
components.
Due to advanced VLSI technology, it is currently possible to put CPU, memory, I/O ports,
oscillator, timers and counters on a single chip.
It is extensively used in millions of applications used in our daily life (where heavy
computation and memory consumption is not required) e.g. toys, cameras, video recorders,
CD players, washing machines etc.
Key features (must have)
i. CPU (8-bit)
ii. On chip oscillator (for clock and synchronization)
iii. On chip RAM
iv. On chip ROM
v. On chip I/O ports
vi. Serial port
vii. Timer-counter
viii. On chip BUS control

Architecture and organization of Microcontroller

External
Interrupts

Interrupt
control

ROM for
program
code

On-Chip
RAM

Timer/
counters

BUS
Control

I/O
Ports

Serial
Port

CPU

Oscillator

Block diagram of a Microcontroller

IC 8051 family (Atmel)

89XX

ROM
(byte)

RAM
(byte)

Timer/c
ounter

INT
Source

I/O
pins

pins

8951

4K

128

32

40

8952

8K

256

32

40

8953

12K

256

32

40

8955

20K

256

32

40

898252

8K

256

32

40

898051

1K

64

16

20

892051

2K

128

16

20

8051 Program memory (ROM)

ROM is a factory programmed memory for basic IC functioning.
Normal ROMs can not be reprogrammed.
Alternatives are EPROM (Electrically Programmable ROM).
EPROMs can be programmed offline (IC is not connected for any applications) by suitable
EPROM programmer.
Erasing can be done via UV light.

The 8051 architecture

8051 block diagram

The 8051 architecture

1.
2.
3.
4.
5.
6.

8 bit ALU with registers; Accumulator (A) and B

16 bit Program Counter (PC) and Data Pointer (DPTR) (DPL, DPH)
8 bit Program Status Word (PSW)
8 bit stack pointer (SP)
Internal ROM of 4K byte
Internal RAM of 128 byte

Four registers banks, each containing eight registers

[= 32 byte]

Sixteen bytes which can be addressed at bit level

[= 16 byte]

Eighty bytes of general purpose data memory

[= 80 byte]
7. 32 I/O pins arranged as four 8-bit ports: P0-P3
8. Two 16-bit time/counters (TL0, TL1, TH0, TH1)
9. Full duplex serial data receiver transmitter: SBUF
10. Control registers: TCON, TMOD, SCON, PCON, IP & IE
11. Two external and three internal interrupt sources
12. Oscillator and clock circuits
IP:
IE:
SBUF:
TCON:
TMOD:
SCON:
PCON:

Interrupt priority
Interrupt enable
Serial data buffer register
Timer/Counter control register
Timer mode control register
Serial port control register
Power control register

The 8051 architecture

8051 registers and memory

The 8051 pin diagram

The 8051 architecture

Pin diagram of 8051
Port 0: Port 0 is a dual purpose port. In general it is used as a general purpose I/O port, but
with an external memory, it becomes a multiplexed address and data bus.
Port 1: Port 1 is an 8-bit bidirectional I/O port. No alternate functions are assigned for Port
1 pins , thus they are used solely for interfacing to external devices.
Port 2: Port 2 is an 8-bit dual purpose port serving as general I/O port , or as the high byte
of the address bus for designs with external memories.
Port 3: Port 3 is an 8-bit bidirectional I/O port. It also serves the functions of various
special features of the 80C51 Family as follows:
P3.0
RXD
(Serial input port)
P3.1
TXD
(Serial output port)
P3.2
INT0
(External interrupt 0)
P3.3
INT1
(External interrupt 1)
P3.4
T0
(Timer/Counter 0 external input)
P3.5
T1
(Timer/Counter 1 external input)
P3.6
WR
(External data memory write strobe)
P3.7
RD
(External data memory read strobe)

The 8051 architecture

Pin diagram of 8051
ALE/PROG: Port 0 is used for both address and data. Address Latch Enable pin is used for
de-multiplexing the address and data. This pin is also the program pulse input (PROG)
during EPROM programming.
PSEN: Program Store Enable is the read strobe to external Program Memory. PSEN is not
activated when the device is executing out of internal Program Memory.
EA/VPP: When External Access Enable is held high the CPU executes out of internal
Program Memory. Holding EA low forces the CPU to execute out of external memory
regardless of the Program Counter value. In the EPROM devices, this pin also receives the
programming supply voltage (VPP) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
VCC: Supply voltage
VSS: Circuit ground potential

The 8051 architecture

8051 Memory organization

4K byte On-Chip ROM (to store all hardware programs).

If internal ROM is running out of memory then there is a facility to use external ROM.
There is a pin EA (External Access). If EA = 1 then internal ROM and if EA = 0 then external
ROM will be used.
0FFF
FFFF
Internal
External
ROM

ROM

EA = 1
0000
4K
On-Chip RAM: arranged in two parts;
128 byte internal data RAM
128 byte Special Function Register
FF
Special
Function
Register

7F
Internal
data
RAM

00

EA = 0
64K 1000

External
data
RAM

FFFF

80

00FF

The 8051 architecture

8051 Memory organization
8051 implements separate memory space for programs (code) and data.
The on-chip RAM contains a rich arrangement of general purpose storage, bit addressable
storage, register banks, and special function registers.
The internal memory space is divided between register banks (00H-1FH), bit-addressable
RAM (20H-2FH), general purpose RAM (30H-7FH) and special function registers (80HFFH).
FF
Special Function Registers
80 Direct addressing Only
7F
Direct and Indirect
Addressing
30
2F
Bit Addressable
20
1F
General Purpose Register
4 Register Banks
00

The 8051 architecture

Four register bank
Each bank has R0-R7
Selectable by PSW.3 & 4
Bit addressable memory 20H 2FH (16
locations X 8-bits = 128 bits )
1AH 23H.2

The 8051 architecture

8051 oscillator and clock
A quartz crystal and capacitors are employed to generate
clock pulses and the crystal frequency is the basic
internal clock frequency of the microcontroller.
Typical clock frequency are between 1MHz to 16MHz and
can be observed at XTAL2 pin.
The smallest interval of time to accomplish any simple
instruction, or part of complex instruction, is the
machine cycle which itself is made up of six states.
A state is the basic time interval for
discrete operations of the microcontroller.
Program instructions may require one, two
or four machine cycles to be executed,
depending on the type of instruction.
Time taken by an instruction to be executed can be
calculated by finding the number of cycles C and is given
by the following relation:
Machine cycle =

12
crystal frequency

Tinst =

C1

XTAL1
30pF
C2

Quartz crystal
oscillator
XTAL2

30pF

GND

no.of machine cycles 12

crystal frequency

The 8051 architecture

Accumulator (A) and B register
The accumulator (A) is the most versatile register and is used for many operations
including addition, subtraction, integer multiplication and division, and Boolean
bit manipulations.
The register A is also used for all data transfers between the 8051 and any external
memory.
The B register is used with the A register for multiplication and division operations
and has no other function than as a location where data may be saved.

The 8051 architecture

Program Counter
Program Counter (PC) indicates where the microcontroller is in its instruction
sequence.
Program instructions bytes are fetched from locations in the memory that are
addressed by the PC.
PC holds either the address of the instruction being executed or the address of the
next instruction to be executed.
The PC is automatically incremented after every instruction byte is fetched and may
also be altered by certain instructions.
The PC is the only register that does not have an internal address.

Data Pointer
The Data Pointer (DPTR), used to access external code or data memory, is a 16-bit
register at address 82h (DPL) and 83h (DPH).
The following three instructions write 55h into external RAM location 1000h:
MOV
MOV
MOVX

A, #55h
DPTR, #1000h
@DPTR, A

The 8051 architecture

Program Status Word (PSW) and Flags
The program status word (PSW) at address D0H contains status bits (flags) as shown below.
PSW has four math flags that respond automatically to the outcomes of math operations
and three general purpose user flags that can be set to 0 or 1 by the programmer.

Carry Flag: CF is dual purpose bit. It is set 1 if there is a carry out of bit 7 during an add or
if there is a borrow into bit 7 during a subtract. CF is also the Boolean Accumulator
serving as a 1-bit register for Boolean operation.
Auxiliary Carry: When adding binary-coded-decimal (BCD) values, the AC flag is set if a
carry was generated out of bit 3 into bit 4.

The 8051 architecture

Flag 0: F0 is a general purpose flag bit available for user applications.
Register bank select bits: RS0 and RS1 are register bank select bits. They are cleared after a
system reset and are changed by programmer.
Overflow flag: OV is set after an addition or subtraction operation if there was an arithmetic
overflow. When signed numbers are added or subtracted, software can examine this bit to
determine if the result is in proper range or not.
Parity bit: P is automatically set or cleared each machine cycle to establish even parity with
the accumulator. The number of 1-bits in the accumulator plus the P bit is always even. (if
no. of 1 bits is odd in A then P = 1, if no. of 1 bits in A is even then P = 0.)

The 8051 architecture

Stack Pointer
The SP is an 8-bit register at address 81H. It contains the address of the data item currently
on top of the stack. Stack operations include pushing data on the stack and popping data
off the stack.
When data is to be placed on the stack, the SP increments before storing data on the stack so
that the stack grows up as data is stored. As data is retrieved from the stack, the byte is read
from the stack and then the SP decrements to point to the next available byte of stored data.

The 8051 architecture

Interrupts
An interrupt is the occurrence of a condition an event that causes a temporary
suspension of a program while the condition is serviced by another program called
subroutine.
Interrupts may be generated by internal chip operations or provided by external sources. Any
interrupt can cause the 8051 to perform a hardware call to an interrupt handling subroutine
that is located at a predetermined address in program memory.
There are five interrupt sources on the 8051; two external interrupts (INT0 and INT1) at port
pins P3.2 and P3.3, two timer interrupts (Timer flag 0 and Timer flag 1) and one serial port
interrupt (RI or TI).
Programmer is able to alter control bits of Interrupt Enable register (IE), Interrupt Priority
register (IP) and the Timer Control register (TCON).
After the interrupt is handled by the interrupt subroutine, the interrupted program must
resume operation at the instruction where the interrupt took place.
Program resumption is done by storing the interrupted PC address on the stack in RAM
before changing the PC to the interrupt address in ROM. The PC address will be restored
from the stack after an RETI instruction is executed at the end of interrupt subroutine.

The 8051 architecture

Special Function Registers
The 8051 operations that do not use the internal 128-byte RAM address from 00H to 7FH are
done by a group of specific internal registers, each called a Special Function Registers (SFR),
which may be addressed much like internal RAM, using addresses 80H to FFH.
Note that most of the 128 addresses from 80H to FFH are not defined, only 21 SFR addresses
are defined.
Some SFRs are also bit addressable together with byte addressable. So programmer should
be careful when accessing bits versus bytes.
Note that any address used in a program must start with a number; thus address E0H for the
A SFR will begin with 0 and would be 0E0H. Failure to use this number convention will result
in an assembler error when program is assembled.

The 8051 architecture

Special Function Registers

The 8051 architecture

Interrupt Enable register (IE)

Interrupt Priority register (IP)

The 8051 architecture

Counters and Timers
The 8051 contains two 16-bit timer/counters for timing intervals or counting events. Timer 0
is at addresses 8AH (TL0, low-byte) and 8CH (TH0, high-byte), and Timer 1 is at addresses
8BH (TL1, low-byte) and 8DH (TH1, high-byte). Timer operation is set by the time/counter
control register (TCON) at address 88H and the time mode control register (TMOD) at
address 89H. Only TCON is bit addressable (TCON.0 to TCON.7).
Time/Counter control register (TCON)

Time mode control register (TMOD)

The 8051 architecture

Time/Counter control register (TCON)

The 8051 architecture

Serial data input/output
The 8051 contains an on-chip serial port for communicating with serial devices with a serial
interface (A/D converters, shift registers, nonvolatile RAMs, etc.).
One register, the serial data buffer (SBUF) at address 99H, holds both the transmit data and
receive data. Writing to SBUF loads data for transmission; reading SBUF accesses received
data.
Various modes of operation are programmable through the bit-addressable serial port
control register (SCON) at address 98H.
The power control register (PCON) at address 87H controls data rates and contains
miscellaneous control bits.
Pins RXD (P3.0) and TXD (P3.1) connect to the serial data network.