Mentor Graphics Tools Tutorial -1

1-Installing ModelSim
2- Using ModelSim

Design of half adder using dataflow modeling.

Syntax Check
Create test fixture using tools wizard
Simulation of half adder
Design of full adder using gate level modeling (instantiation of half adders).

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1. INSTALLING ModelSim

1.1. Download ModelSim PE Student edition:

Download latest ModelSim PE student edition from Mentor Graphics official website. Either by using the link
Or by manually visiting and searching the correct download location on the Mentor Graphics official website.
ModelSim PE student edition is a free version Simulator Environment and it has some limitations. To run the
simulations on this version the user needs a free license file which can be acquired from the Mentor Graphics
official website.
Acquiring the free license is a last step in the installation process and is mandatory. The license is for a limited
duration of 3 months (may vary) and once lapsed, the whole procedure of installation has to be followed again.

1.2. Installing ModelSim PE Student edition:

The installation is straightforward and self explanatory steps. Mostly, clicking Next button or Yes will do. Be
careful at the last step (please see caution). If somehow the license acquire step fails, the installation process has
to be carried out from the beginning.
Run the ModelSim installation executable file. It will first unpack the files and will bring a installation wizard as
shown below.

Click Next

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At the last step of the installation, make sure that before selecting FINISH the machine is
connected to the internet as the installation needs to aquire the license file from the Mentor
Graphics website and ModelSim wont run without the license file.
DONT change the name of the license file or the file contents!
If the license file isnt in the Inbox, it can be found in the Spam folder, check there.

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1. 3. Acquiring the License file:

After the installation is complete, the installation wizard will ask for FINISH. Before hitting the FINISH
button the machine should be connected to a live internet connection.
The installation will redirect to a license request form on the Mentor Graphics website. Fill the form and make

sure the email id entered is correct.

The license file is sent to the email id entered in the request form. Download the license file (this will most
probably be named as student_license.dat. Nothings wrong with the extension so use as it is)
Save/Copy the file in the directory Modeltech_pe_edu_10.0c (ModelSim Installation directory). See the
example in the following figure.

Installation part finishes here. Now the tool can be used! The license will last for 3
months.

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2. USING ModelSim

Run ModelSim PE Student Edition Simulation Environment

Double click the icon

Or Start Menu  All Programs  ModelSim PE Student Edition 10.0c  ModelSim.

2.1. Make New Project:

Click Create a Project. A new project is made once for a new design (the design may have many leaf cells in
the hierarchy these cells are created within the existing project).

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To open and work with existing design, use Open a Project. Though, mostly, ModelSim keeps last active
project on startup.
The project is named adders. It is located in the directory C:\Modeltech_pe_edu_10.0c\examples.

It is suggested that the designer always organize the directory structure and must know where
the design project has been created.

It is important how the project is organized. It is strongly recommended that the naming is done
sensibly. As a convention, name the Verilog file same as the module name and the variations of
similar module be name with a variation. For instance, if I am to design a 4 bit ripple carry
adder, I may name the adder as adder_4bit_ripl.v, its module name as adder_4bit_ripl.

Typically, a mixed approach is used in designing. In the first step the top design is broken down
to the leaf cells, this is called top down approach. Now the design is built/coded from the very
leaf/child cell (lowest level). Once all the lowest level leaf/child cells are created the upper level
cells are created using these lowest level leaf/child cells. In this way the top level design is
reached.

It is just like building a house. First an architecture is drafted on a paper. Then basic building
blocks like concrete and bricks etc are used to create rooms and bit by bit a house(top level) is

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2.2. Create New File:

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Take your time and make yourself familiar with the interface.

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2.3. Design Entry:

Now, double click the verilog file (in the project pan) half_adder.v.
Alternatively, right click the verilog file half_adder.v  Edit

Write the module (design of half adder using any modeling style)
The example uses dataflow modeling style.

2.4. Compilation & Syntax Check:

Left Click Compile selected icon
. Alternatively, either go to the Menu bar  Compile  Compile
selected or right click the verilog file  Compile  Compile selected.

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The window below shows the error (carefully analyze the error message):

Correct code:
module half_adder(sum, carry, a, b);
output
input

sum, carry;
a,b;

assign
assign

sum = a ^ b;
carry = a & b;

//correction

endmodule

Re-compile the code.

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2.5. Simulation:
Simulation is very important and appropriate test bench (one with complete coverage) is key to almost bug-free
design. The design is bound to fail if it is not simulated carefully. So, good time should be devoted in writing
the test bench and analyzing the simulation results.

Appendix

2.5. Simulation by forcing values:

Simulation is very important and appropriate test bench (one with complete coverage) is key to almost bug-free
design. The design is bound to fail if it is not simulated carefully. So, good time should be devoted in writing
the test bench and analyzing the simulation results.

2.5.1. Run Simulation:

Left Click Simulate icon

. Alternatively, on the Menu bar  Simulate  Start Simulation

Compilation step create some files in the work library. These are important for simulation step. The work
library will have compiled version of design module. The module will have same name as that of the design
module (not the file or project name). Select the module to be simulated and click OK.

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This will open the simulation environment which will look something like this:

2.5.1. Send objects to the waveform window:

Right Click instance  Add  To Wave  All items in design

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Waveform window looks something like this:

2.5.1. Forcing values on INPUTS:

Right Click the input (one by one)  Force

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For this example, for first run the signals are forced values a=1, b=0.

2.5.1. Run Simulation:

Click Run by clicking the button

is 100 ns.

. The simulation will run for 100 ns as by default, the run time selected

Check the simulated Results:

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Zoom in

and check.

Further force values and validate the design by using half adders truth table.

a
0
0
1
1

b
0
1
0
1

sum
0
1
1
0

carry
0
0
0
1

Simulation Results:

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SUMMARY
ISE WINDOW:
1.

Design Entry (Implementation mode):

a) New Project (only once every new project)
Project  New SourceVerilog Module  give name Next  Next Finish.
b) Design Entry using Verilog (Verilog module) DU (Design Unit)
Write the verilog code for the design and save.
c) Syntax Check:
SOURCE: Select correct file.
PROCESS: Synthesize XST Double Click Check Syntax.

2.

Simulation (Behavioral Simulation mode):

a) TB (Test bench) for the DU.
Project  New SourceVerilog Test Fixture  give name Next  Next Finish.
b) Edit the test fixture file by adding the appropriate stimulus.
SOURCE: Select correct file.
PROCESS: Xilinx ISE Simulator Double Click Simulate Behavioral Model .

3.

Assign FPGA component locations to the pins in DU(Implementation mode):

SOURCE: Select the top module.
PROCESS: User Constraints Double Click Floor Plan IO Pre-Synthesis

IMPACT WINDOW:
Assign appropriate locations to the pins in module and save. Go back to the ISE WINDOW.

ISE WINDOW:
4.

Synthesis (Implementation mode):

SOURCE: Select the top module.
PROCESS: Double Click Synthesize XST.

5.

Implementation-translate, map, place & route (Implementation mode):

PROCESS: Double Click Implement Design.

6.

Generate Program File (Implementation mode):

***Skip step 6. a) if programming on-board PROM.
a) Right Click Generate Programming File  Properties  Category=Startup Options 
FPGA Start-Up Clock = JTAG Clock  OK.
b) Double Click Generate Programming File.

7.

Programming the FPGA using Adept:

a) Connect the FPGA kit with the PC via an appropriate USB connector.
b) Switch the FPGA kit ON (Red(Power) LED will glow).
c) Windows Start Button  All Programs  Digilent  Adept  Adept.

ADEPT WINDOW:
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If the FPGA kit is powered ON, connected to the PC and the Digilents USB cable drivers are installed the Adept
programmer window will auto recognize the connected FPGA kit and will show digilents device name (such as
Nexsys2 or Basys2) under Connect:.
Also, the programming options will be available for: 1. FPGA. 2. PROM.
For FPGA: (make sure the jumper is at USB/PC )
(The programming information will be lost at power OFF and the FPGA has to be re-programmed at every
power ON and OFF so, it is a volatile programming. To retain the programming information so that it is autoloaded at every start-up, choose to program the on-board PROM)
a) Click Browse (the one next to FPGA tab)  locate the bit file generated by ISE (will have same
name as the top module and will be located in the project directory). If there is a .bit at the location
it will show.
b) Select the bit file  Click Open  Program (the one next to FPGA section).

c)

Adept will report Program Successful.

For PROM: (make sure the jumper is at PROM/ROM)

(The programming information is retained and is auto-loaded at every start-up)
a)

Click Browse (the one next to PROM tab)  locate the bit file generated by ISE (will have same
name as the top module and will be located in the project directory). If there is a .bit at the location
it will show.

b) Select the bit file  Click Open  Program (the one next to PROM section).

c)

Adept will report Program Successful.

FPGA KIT:
a)
b)

Check that a yellow LED on the FPGA kit, glows. This indicates the FPGA has been programmed.
Analyze/Observe the working of the design DU.

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