Cadence Allegro and OrCAD (Including ADW) RELEASE

17.0 README -- Windows Version

Installation Guide
You can find the Cadence Allegro and OrCAD (Including ADW) 17.0 Release Installation Guide
for Windows, Version 17.0 (pcbInstall.pdf) in the Disk 1 folder of the Cadence Product DVD.

Migration Information
Important migration information is contained in the Migration Guide for Allegro Platform
Products Release 17.0 document, which is available when you install Cadence Allegro and
OrCAD (Including ADW) products.

System Requirements
Information about minimum and recommended system requirements can be found in the Allegro
Platform System Requirements document, which is available when you install Cadence Allegro
and OrCAD (Including ADW) products.

Whats New
A product note for the release is available in the Disk 1 folder of the Cadence Product DVD.
Product notes for individual products are available when you install the Cadence Allegro and
OrCAD (Including ADW) products.

KPNS
The Known Problems and Solutions (KPNS) document is located at:
http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=landi
ng/spb170/kpnsList.html

Custom Environments
Customers using custom batch files or scripts to set up their environments must add the following
to their path. There is the potential that some Allegro products may not launch without this
setting.
<installation_directory>\OpenAccess\bin\x64\opt

Allegro /SigXplorer ABIML Libraries for Default Trace Models

with Surface Roughness Effect
The Allegro /SigXplorer ABIML Library includes ABIML libraries for SigXplorer default
trace models with surface roughness effect. It is designed to provide accurate trace models in
Allegro /SigXplorer without time consuming EMS2D solver runs. The Library is installed if you
select to install Allegro /SigXplorer.

Downloading and installing SPB Software

Cadence software can be downloaded from:
http://downloads.cadence.com
Log in with a valid user ID and password and click the Windows tab. In the Windows tab,
click the link SPB170.
Download CDs and then extract the zip files into a temporary directory such as cdnstemp.
This will leave you with a directory structure that is similar to:
Autoplay folder
Disk1 folder
autorun.inf
setup.exe
setup.ini
Complete the installation by running setup.exe from the temporary directory. You can
install the following using the download:
License Manager
Cadence Allegro and OrCAD (Including ADW) Products
Allegro Design Entry HDL Allegro AMS Library
Cadence Allegro and OrCAD (Including ADW) Client
Note: You can also download and install the Download Manager to manage installations.
Consult the installation guide for detailed information.

List of Fixed CCRs

Enhancement CCRs
Bug CCRs

Enhancement CCRs:
CCR ID
3234
5284
16835
19137
20171
20669
23153
23937
25885
26507
27528
27810
30099
31767
38127
38238
50171
60478
62636
73421
76692
128368
158021
206566
238386
264832
268892
274411
280874
323567
332099
344616
346568
347510
350730
359356
359910
367680
370008
373789
381828
406590
406748
424198
429472
436529
444498
446935

Description
Add multi shapes and allows drill offsets in Padstack Designer
Need the ability to connect a VIA only on one ground layer.
Constraint Manager export spreadsheet does not have headers
Option to use multiple shapes for pad applications
Maestro needs personalized user configuration settings
Need ability to define more than one pad geometries for the pastemask layer
Need a new rounded corner rectangular shape to support lead free pads
Want ability to add multiple shapes in a shape symbol
Want physical and spacing constraints in Constraint Manager to be editable
Want ability to create a shape/flash symbol with multiple voids
Enable selective connections to specific shape planes
Should be able to specify radius on corners of square pads in Allegro
Allow to define and assign physical and spacing constraints in Constraint Manager
Need to be able to launch shape editor from Pad Designer
Should be able to specify multiple shapes within padstack definition
Add void data for shape symbol in Allegro.
Allow padstack multi shapes and voids
Enable access to physical and spacing constraints from Constraint Manager
Pin/via with NO_SHAPE_CONNECT property should be connected to shape based on
layer restrictions
Allow complex shapes as pads in Allegro
Copy and paste operations in Pad Designer should be intuitive
Ability to add multiple shapes to a shape symbol
Allow Net Physical and Net Spacing values to be assigned to nets and net groups
Pin/via with NO_SHAPE_CONNECT property should be connected to shape based on
layer restrictions
Need a new rounded corner rectangular shape to support lead free pads
Want ability to create multiple shapes for shape symbols (.ssm)
Need a new rounded corner rectangular shape to support lead free pads
Allow layer, spacing, and physical rules in Constraint Manager
Enable extraction of library path and embedding of version in padstack
Want via/pin full contact thermal-relief option individually when generating artwork.
Shape enhancement to add void under BBvias
Need a quick way for creating pastemask with irregular patterns
Add ability to select shape within padstack and edit it
Allow split shapes in SSM symbol creation
Way to determine the PAD and SYMBOL library paths used
Should be able to create multiple shapes in a shape symbol
Ability to specify which ground layer a specific via may connect
Ability to replace all rectangular pads to rounded corner padstacks for ROHS
compliance
Allow multi shapes and void in padstacks
Allow control of connection by layer for No shape Connect
Voiding is needed per layer on elements such as pins, vias, and clines
Need to be able to have multiple solder pastemask shapes on a shape pad.
Ability to connect pins to specific dynamic plane layer shapes
Add multi shapes and allows drill offsets in Padstack Designer
Ability to create multiple shapes for shape symbols (.ssm)
Ability to have multi shape voids and to use flash symbol on the pastemask layer
Ability to specify to which ground layer a specific pin(s) and/or via(s) may connect
Ability to disconnect some via pad instances from shapes on specified layers only

449232
456289
473128
475594
506490
517552
519454
522870
526609
527962
528274
528661
531644
537717
548512
563376
581012
582800
584368
590975
592832
599820
608696
627491
630654
634543
636218
642884
653880
660780
664840
668830
679953
680526
680531
690596
709354
714361
716181
720210
720408
723886
729979
731567
734176
738568
740108
741262
743751
745485
749890
750158
750533
753110
755057
755852

Void dynamic shapes for all layers between the signal and the referenced plane layer
Need to void non-etch entities
Allow pad that contains multiple shape.
Need method of creating voids on one layer from elements on an adjacent layer
Need option to use multiple shapes for padstack applications
Pin to Shape clearance should measure real distance rather than perpendicular distance
Need option to create rectangular pads with rounded corners
Need ability to add multi-shapes in Padstack Designer
Need option to have individual antipads for each drill of a multi drill padstack
Ability to determine original library path of padstacks
Enhance the database to retain padstack paths to original libraries.
Provide support for square holes in the Allegro PCB editor and Padstack tools
New report to point out manufacturing acid trap on cline and clines to pad
Allow pastemask with multiple shapes
Allow pastemask with multiple shapes
Ability to define and edit thermal relief ties on a layer by layer basis
Support drill bit and finished drill size definition in pad_designer and drill legend
Need a spacing rule for shape that lies under the layer where the net is actually routed
Need ability to add a void inside a .ssm shape
Ability to create a shape/flash symbol with multiple voids
Need the ability to selectively connect pads to shapes on specific layers
Ability to define package ball parameters for 3D viewer
Enhancement to allow voids in pastemask
Voiding of rectangular shapes needs to be improved
Ability to control component pin plane connections
Need option for padstack library path report
Shape symbols need to support complex shapes with multiple geometries and voids
Ability to install additional products after hotfix is installed
Enhancement to change material in cross section form without changes in other fields
Draw J-Loop wire bond in SiP Digital Layout
Enable installation without Admin rights
Ability to connect pads to shapes on specific plane layers.
Need instance-level isolation for some pin/via from specific same-net plane layers
Ability to control DYN_THERMAL_CON_TYPE per layer
Need dynamic shapes voiding for square pads
Need option for padstack library path report
Need option to create rectangular pads with rounded corners
Pin/via with NO_SHAPE_CONNECT property should be connected to shape based on
layer restrictions
Pin/via with NO_SHAPE_CONNECT property should be connected to shape based on
layer restrictions
Ability to create round corners on rectangular pads
Allow voids inside Shape Symbol on Etch layer
Need padstack option to indicate drill hole-size or finish hole-size.
Request padstack library path report
The 'hole to hole' DRC check mode should be enabled by default
Set Hole to Metal DRC by default
Need option for padstack library path report
Ability to specify which ground layer a specific via may connect
Option requested to add DRC capability to enable Antipad as Keepout (ARK) to all
pin types.
Donut shaped antipad needed
Need a property to control the connection of a through pin
Enhance hole to hole spacing constraint to check suppressed and existing pads
Enable Hole to Hole check even when the hole is inside the pad
Enable Hole to Hole DRC regardless of pad size
Allow multiple shapes in the shape editor
Enable Hole to Hole check even when the holes are inside the pad.
Enhancement request for multi shape paste mask in Pad Designer

756208
765563
766605
766658
779683
784632
798725
803386
806190
810736
813261
814245
819768
820782
829145
829889
831667
832863
834802
835745
841191
849192
852890
853657
854163
859926
861864
862518
862776
864538
868219
868695
874433
877995
881050
881854
882846
883054
885048
885974
887684
890232
890237
893276
897917
898898
903184
923400
930189
933642
934779
937138
943830
944337

Enable Hole to Hole check even when the hole is inside the pad.
Allow ARK check for all pin types
Option to add DRC capability to enable Antipad as Keepout (ARK) to all pin types
Ability to define route keepout and shape keepout in Padstack Editor
Via Labels should not count named dielectric layers
Increase the material name size to allow more than 19 characters
Enhancements for dynamic shape parameters
Ability to specify which ground layer a specific via may connect
Need the ability to add two separate shapes in an SSM symbol
Enhancement to have Hole to Hole DRC checks available with existing pads
Via Labels display wrong layer count on the actual via when dielectric layers are
named
Via Labels should not count named dielectric layers.
Allow shape pads to contain voids.
Pin/via with NO_SHAPE_CONNECT property should be connected to shape based on
layer restrictions
Padstack with multiple shapes
NO_SHAPE_CONNECT should accept layer names
Ability to specify which ground layer a specific via may connect
Way to find the source of a pad
Need round corners on rectangular pads
Allow silent installation of base release without showing any GUI
Need a pin keepout area
Allow multiple solder paste mask
Need Hole to element check even when the hole is inside a pad
Option to add DRC capability to enable Antipad as Keepout (ARK) to all pin types
Add LIBRARY_PATH property to padstack and generate a padstack library report
Update ARK to allow support for all pad types
Ability to specify plating thickness and material for via padstack
Allow Hole to element check even when the hole is inside the pad
Allow Hole to Shape DRC for hole smaller than pad
Allow installation of base release products even if Hotfix is installed
All hole check needs to be enabled by default
Ability to disconnect some via pad instances from shapes on specified layer only
Need rounded corners on dynamic voids for rectangular elements
Allow adding more products over existing install
TCL: Request to make line width of a LINE and ARC/CIRCLE same
Use Cadence hierarchy to access shared DLL files
Allow shape symbols to contain voids
Enhance DAT file error message: No more memory for the traces
Allow installation of base release products even if Hotfix is installed
Allow installation of base release products even if Hotfix is installed
Allow drill size and Finished hole size in the padstack
Need a variable to control the voiding at the edges of a rectangular pad (round/
rectangle).
Need a variable to control the voiding at the edges of a rectangular pad (round/
rectangle).
Increase material name limit from existing 19 characters in BRD database
Option to select which ground layer a specific via may connect
Ability to add multiple shapes in a pad.
With measure command selected objects are not highlighted with temporary color
Allow multiple shapes inside a padstack
Ability to get the original PADPATH for each padstack
Thermal pads can be assigned a specific thermal pad per the power/ground net
assigned
Provide J-wire process profile in 2D and 3D views
Finger to finger wire in arc lock(J-wire) required
Allow multi shapes in padstack
Property name of link should be clickable in generated PDF using PDF Publisher

947202
953840
954340
954869
965807
967959
968438
968560
969384
973288
974187
975732
980881
982299
983073
984155
990910
995999
996287
1001113
1025814
1028081
1030721
1031528
1033602
1047320
1053407
1055024
1067825
1071396
1071833
1072368
1076900
1078501
1080131
1080322
1081140
1082542
1085045
1086521
1087248
1089690
1090560
1096723
1100772
1111932
1113966
1113974
1119687
1119689
1120238
1121015
1121021
1122016
1124172

Add a tiny switch model

Ability to add multiple paste areas to one large padstack
Need padstacks with rounded corners
Enable Antipad as Keepout (ARK) for all pin types
Mechanical Pin to Conductor Spacing is not getting checked for SMD pin
Need a property to connect a via to only one plane layer
Increase material field characters
Increase cross-section layer name stream length
Do not overwrite HOME variable during silent installation
Need padstack library path report
Include drill bit size information in the Drill Chart
Need round corners on rectangular pads
Allow void in shape for SSM symbol
Add new optocoupler models
Set the thermal contact width according to the layers
Enable all the Hole DRC checks in Spacing modes of Analysis mode by default
Ability to get via label information
Display complete FFT for all large data file options
Increase the material name character limit to more than 19
Ability to limit vertically (z-axis) the amount of copper interconnect to redundant
shapes
Include Line to Platted hole spacing DRC
Option to suppress DRCs in the 3D Viewer between objects on the same net
Include Hole to Hole DRC checks for existing pads
Pin/via with NO_SHAPE_CONNECT property should be connected to shape based on
layer restrictions
Allow drill size and finished hole size in Padstack Designer
Option to suppress DRCs in the 3D Viewer between objects on the same net
Include Hole to Hole DRC checks with pads present.
Include Hole to Hole DRC checks with pads present.
Add Mirror command icon to PCB Editor toolbar
Shape voiding is larger than the constraint for Shape to Pin Spacing
Ability to control DYN_THERMAL_CON_TYPE per layer
Need the via labels to coincide with the labeling of the layers in the visibility form
Text Block is always changed to Block No 2 when placing on Embedded Layers
Need the Pad Boundary function to allow continuous pad trimming without exiting
the command.
Request the ability to copy pad trimming edits to other layers
Hole to Hole Constraint need to work in presence of Regular Pad around hole
Need a general Acid Trap check that will flag Same Net violations.
Need a padstack that connects to only outer layers, top and bottom
Getting Out of Memory message if Display probe during simulation option is set
Allow Hole to element check even when the hole is inside the pad
Hotfix should be automatically installed to existing base location
Allow negative X offset for Intersheet references.
Need option to export Database Diary
Need an option to adjust height information in place bound shape globally
In Constraint Manager DRC Spacing the Show Element DRC totals are wrong.
Ensure that the hierarchy is not changed in OrbitIO
Allow padstack multi shapes and voids
Pad Designer to allow for voids in shape.
Add an option for donut shaped pad in Pad Designer
Ability to remove base and Hotfix in silent installation mode
Increase material name character limit to more than 19
IFF import with no variables should not create vardef.dat
When importing multiple IFF-Files to DE-HDL, check for existing vardef.dat in the
project
Allow multiple shapes in SSM
Ability to find out padstack library source

1125332
1131052
1131696
1134412
1136821
1144257
1148436
1151038
1170519
1172831
1173343
1174296
1175167
1177375
1177379
1181686
1182087
1185182
1185342
1192959
1196969
1197198
1198198
1198274
1200018
1202097
1207509
1208762
1208887
1221008
1225521
1228778
1229078
1230897
1234912
1237506
1237999
1239626
1241471
1242363
1245253
1246220
1246427
1251988
1252616
1254682
1260069
1269374
1269377
1271029
1284810
1287528

Installer should run even if Hotfix is installed

Ability to sort the errors in Constraint Manager
Ability to install new products even if Hotfix is installed
Ability to place replicate without redundant vias and shapes
Allow installing new products to Server/Client setup
All hole check needs to be enabled by default
Need option to set a constraint for via hole to via hole clearance
Pin/via with NO_SHAPE_CONNECT property should be connected to shape based on
layer restrictions
Include net name in DRC error messages shown in SiP 3D Viewer
In Pad Designer increase the mask layer limit to 32
Ability to add hole plating thickness information to padstack.
Problem with saving read only Capture design even after it is made writable
Support for TCL 8.5
Documentation needs to be updated for axlCNSCreate()
Documentation changes for axlCNS* functions
Ability to add net class and its members to Physical, Spacing, and SameNet
Add the Finished hole size field to Padstack Designer
Shape should create rounded corners to obey shape to pin spacing
Need an option to void a single via instance by layer
Delete all installed folders after removing OrCAD Lite
Enhance Cross Section: import comma separated values; character size more than 19;
columns to retain size
Allow option to add multiple paste areas to one large padstack
Increase limit of mask layers from 16 to 32 in Padstack Designer
3D Viewer: When a Net is highlighted and clicked to rotate the view, the highlight
turns off
Ability to add chamfer or round corners on square pads in Padstack Designer
Pin/via with NO_SHAPE_CONNECT property should be connected to shape based on
layer restrictions
Capture must not create folder with name starting with space while creating new
project
Environment variable for controlling the Allegro font size from the site level itself
Hole to Metal DRC should always be on
Out of memory error for simulation of large data file
Need a pin keepout area
Link Database Part crashes if Excel file is open
Need support of Control File for silent installation
Documentation and example of axlDBGetPropDict skill function is missing in Skill
documentation.
Alternate Constraint Manager rows should have different colors
Enhance PublishPDF on command line for black and white printing
Display wire bond angle in the Wire Bond Status window (HUD)
Need DRC for Acid Traps created by cline with another cline or pad
Ability to add via plating thickness in the padstack
Slide to behave with testpoints the way regular vias behave
Option to find placed via's original padstack library path, not the current via padstack
library path
Enable STEP export to convert mixed unit into one single unit
Script to remove Cadence paths after removal of Cadence installation
Rename the installer configuration utility to suggest it is preparing the tool for removal
Option to use a control file for silent installation
Allow voiding for rectangular or square pads
Shapes incorrectly pour around rectangular pads
Support drag and drop of objects to classes in Constraint Manager
Cannot deselect from multiple selection in Constraint Manager
Add property to suppress soldermask DRCs
Add xsection icon to Allegro Physical Viewer Plus tool bar
Mismatch in width of line and polyline in Part Editor

1287942
1294318
1296697
1301158
1302062
1302218
1303096
1303243
1305598
1305977
1307429
1310564
1311135
1311778
1313599
1314763
1317664
1320104
1321349
1325376
1326944
1327668
1329452
1330053
1331719
1333124
1333935
1338067
1338485
1339810
1340240
1340712
1340737
1343636
1343714
1346925
1348177
1351067
1353105
1354085
1355542
1357085
1362790
1377229
1377689
1378611

Ability to connect pin on a specific layer

Ability to split a shape by drawing a line or rectangle
When the Extend selection is on, Slide cline should not change the Arc radius.
Option to suppress DRCs in the 3D Viewer between objects on the same net
Add zoom to object function in the 3D Viewer
Enhance reduce_padstack command for vias and BBvias
Convert mixed units to single unit in STEP file
Add help for the items in the Analysis Modes Design Options dialog
Requesting the Height text to be changed to Length in the Show Element form
Extend cut by window feature to support shapes
Cannot save MCM database on Linux
Enable via connections to specific shape planes
Ability to run skill encryption in Windows
Ability to specify different tolerances in slot for length vs width
Add property to symbol to suppress pin to route keepout DRC
Generate hierarchical ports in new column in Capture even if design not using default
units
Layer Priority does not work for custom colors while plotting the layer using plot
Add Void Adjacent Layer Shapes feature of SiP to the PCB tool set
Page number overlaps with signals in Intersheet Reference
Ability to control bonding of dummy net pins in non-standard wire bond
Improve handling of fixed clines having tapered traces.
Ability to waive single pin net DRCs in Constraint Manager
Display size setting for RDC environment
Need detailed documentation for cmfeedback
Ability to generate Metal Usage Report for selected area
Change the error message to a warning when the wire bond settings form is opened.
Options to control ic-nets becoming pkg-nets when refreshing a co-design die
Amend PADS import doc to specify that a new board file will be created in the Output
Directory path
Show Add button in cache mode in Component Browser
Allow a zero or blank in the Dielectric Constant field of Cross Section
Use default values and specify input error for VCO model application in PSpice
NET_SHORT property should not be copied when Retain net on vias is not set
NET_SHORT property should not be copied when Retain net on vias is not set
Perform silent installation without showing any GUI
Need an option to generate board shape density per layer
Ability to have same class/subclass mapped to more than one stream layer
Displaying incorrect value in Film Area Short Report
Adding a very large die in Logic Edit Parts List takes extremely long.
Include description of Regular Expression (RegEx) in Checkplus documents
File Export Worksheet File is not using the current board file location as last
used directory
Display of holes and pads inconsistent in Allegro 3D Viewer
Ability to split a shape by drawing a line or rectangle
Enhance acute angle check for PCB editor
Ability to view cross section in Physical Viewer
Spacing between a rectangular pin and shape gives a wrong voiding
Enable STEP export to convert mixed units into one single unit

Bug CCRs:
CCR ID
26896
772810
806180
811320
863260
867110
903475
925935
934052
935427
937203
937498
962851
968365
981217
1010620
1014710
1082381
1083164
1083826
1083967
1084460
1095316
1095613
1095722
1097767
1103665
1114371
1115306
1119787
1120107
1121100
1130204
1130235
1134649
1134861
1141757
1158873
1163921
1164301
1167832
1173237
1173683
1174296
1179099
1191854
1196866
1198819
1216954
1224422

Description
Unable to cut and paste in the max parallel fields in Constraint Manager
Capture crashes when running derive database part
Simsrvr crashes while running simulation
Error when running EDIF300 in Windows 7
Relational table is not refreshed when a new property is added to it in database
PSpice out of memory error followed by crash on Windows 7
Height property does not show up in the netlist file
Wrong pin is returned on searching pin number in design on doing backannotation
after pin swap.
FPGA System Planner is unable to access shared DLL
Error when running EDIF 300 writer on Windows 7 and Vista
Deleting a pin and then placing another pin on the same location results in error
Control file not accepted in silent installation
Search should not show all floating nets
User DSN not available in CIS Setup with non-admin privileges
Display problem for drop-down menus in Capture when using multiple monitors
Out of memory error while running simulation with marching option on
Net alias for some parts in PSpice library are not correct
Error when running EDIF 300 on Windows 7
Cannot deselect multiple selected pins after opening edit properties for pins
Void area is different between solid shape and hatch shape
EDIF 300 Schematic Writer does not run on Windows 7
DRC check in Capture for package with two part instances shows ERROR(ORCAP1621) but design annotates
Silent mode client installation sets CDS_LIC_FILE to NULL
Structure destruction for Stacked Via when executing slide command with Dynamic
Fillets.
Net name does not increment correctly when copied using CTRL key in Capture
CIS BOM Template not refreshed in first run
Part goes off-grid in Capture even when snap to grid is set
Net name does not increment correctly when copied using CTRL key in Capture
EDIF import OLB file pin does not move along the part boundary
Behavior of select net and copy net names commands of Constraint Manager
different in 16.6 and 16.5
Cursor shows different pointers in Constraint Manager on Windows 7
Modifying column headers of a relational table gives error in CIS Explorer
Display problem for drop-down menus in Capture when using multiple monitors
Return value from axlUIViewFileScrollTo is incorrect when allegro_html is set
PSpice does not run from CIS and shows ORCAP - 1028 error
Changed value of a property is not showing in board text
Cursor with infinite pointer does not follow mouse movement
Display DRC is not highlighting the DRC in Constraint Manager
axlDesignType does not specify partition
Dynamic Shape Update during Update Symbol wrongly merges static shape with
dynamic shape
Entering special characters in variant name causes variant information loss
Problem with saving read only design in Capture even after it is made writable
TCL utility causes Capture to crash
Problem with saving read only design in Capture even after it is made writable
EDIF 300 reader and writer crash
User DSN not available in CIS Setup with non-admin privileges
Free Viewer displays "E- No match for subclass command, BOTTOM" when board
is loaded.
New property column is not updated in the Constraint Manager spreadsheet
Out of memory error for large files in PSpice
DE-HDL cannot export EDIF file

1225371
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1250860
1259880
1260454
1271061
1275776
1277093
1278545
1282049
1285816
1286252
1289499
1290136
1292577
1293544
1298906
1300124
1302131
1302949
1309217
1310226
1313392
1313691
1313882
1315640
1316949
1318454
1319017
1319663
1319852
1319866
1319968
1321527
1322164
1324182
1324387
1324912
1326723
1327190
1328377
1328452
1328884
1329092
1329583
1330982
1331463
1333082

Audit ECSets progress window is always on top

Drill hole to hole constraint not working correctly and does not display DRC error
Cannot slide diffpairs as a group in 16.6
Place Replicate Create removes reuse module from MDD file
Audit ECSets progress window is always on top
The checkContextBit SKILL function is not available
Stackup incorrect after importing techfile that has dielectric above TOP and bellow
BOTTOM
Spacing options check holes within pads option not workingnot adding board
property
Renaming column header in relational database gives error in CIS Explorer
CREFER Numbers are printed with white spaces with Publish PDF
Dot sizes are different between plot output and Publish PDF.
Show error message when a replicate model MDD file is used in the reuse flow
Add connect does not connect to same net via when unused pad suppression is
enabled
Net class object list is not sorted in correct order
Allegro Text Setup fails to retain original text block name during Text Block
Compaction
Unable to connect IC pin to ground on board
Unable to generate EDIF 300 schematic or netlist
Unable to edit the pads in DRA
Renaming using default grid gives error of no grid found
AiDT fails with error message E- (SPGRE-22): GRE execute command failed
Disband group not allowing via to move
SPECCTRA: Mirrored pad does not seem to be recognized correctly
Via list order is not followed by add connect
Pad Designer does not have scroll bars when forms are resized
Irregular void in dynamic shape
Allegro not following Same Net Spacing value for shapes.
Unable to import STEP files exported from PCB Editor
Capture symbol library part has incorrect pin name
Could not add the CDS_LIC_FILE variable for silent mode client installation
EDIF 300 netlist crashes on Windows 7
Capture library file locked if a title block from the library is used
con2con always reports the first Part Name when problems are reported on second or
third Part Name from the same primitive
Super Smooth is incorrectly listed in the Design Parameters description fields for the
slide command
Super Smooth is not available for Add Connect in the Design Parameters or rightclick option in add connect
Dynamic Phase DRC marker displayed at drawing origin
Need Hole to Hole spacing checks active when pad exists
Component Browser displays incorrect search results for values greater than or equal
to 300K
Autorouting using comp_order not following the topology
Shape does not void properly
Capture Lite gets into login loop while setting CIS for a SQL database
EDIF 300 from Project Manager tools menu crashes
Allegro hangs on importing SPECCTRA Session file
Sliding Via without Pad does not shove the Cline to clear DRC
When attempting to change shape types, after the first one is changed the right-click
Next selection does not work
Create Module with Group is checked, missing some components in MDD file
EDIF 200 translator scaling is not correct
Dynamic shapes fail to void causing DRCs
Use the Via Priority as defined in the Via list
Edit pad Boundary Line Lock not followed
Skill code for making a tabular column using grid

1333930
1334302
1339158
1343625
1349418
1349803
1353460
1355198
1355635
1358511
1358978
1359438
1361608
1364831
1367312
1371230
1371978
1379230

Reference Designator pointer marker should be shown when moving text as a group
Import Logic - Import Changes Only or Overwrite Current constraints fails to update
signal models.
Backannotation does not consider allegro.cfg when selected manually.
Place Replicate removes vias, clines, and shapes
Typo in error message
Display option changes to Both if Value Exists when setting it to Value if Value
Exists for multiple parts
Inconsistent behavior of Constraint Manager when selecting net or net groups with
net filter on
Incorrect representation of via in Allegro 3D Viewer when rotated
QuickView in Place Manual do not show Module Instance MDD
Replace padstack error message unclear
Hug issue with shapes in add connect cannot route across void
File - Save Project As in Capture is not adding project to the most recently used list
Need to import techfile a second time to correctly update the assembly constraints
PCB Editor exits when the numOpenFiles() command is run
Hotfix installation does not progress when backup or rollback option is selected
'Apply Allegro Character Limits on All Projects' option shows different settings for
forward and backward netlist
Test Probe allowed in No_Probe shape
PDF Publisher does not follow file permissions in Linux