Académique Documents
Professionnel Documents
Culture Documents
Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
Preface
DANGER!
It means that death, severe personal injury, or considerable equipment damage will occur if safety
precautions are disregarded.
WARNING!
It means that death, severe personal, or considerable equipment damage could occur if safety
precautions are disregarded.
CAUTION!
It means that light personal injury or equipment damage may occur if safety precautions are
disregarded. This particularly applies to damage to the device and to resulting damage of the
protected equipment.
WARNING!
The firmware may be upgraded to add new features or enhance/modify existing features, please
make sure that the version of this manual is compatible with the product in your hand.
WARNING!
During operation of electrical equipment, certain parts of these devices are under high voltage.
Severe personal injury or significant equipment damage could result from improper behavior.
Only qualified personnel should work on this equipment or in the vicinity of this equipment. These
personnel must be familiar with all warnings and service procedures described in this manual, as
well as safety regulations.
In particular, the general facility and safety regulations for work with high-voltage equipment must
be observed. Noncompliance may result in death, injury, or significant equipment damage.
DANGER!
Never allow the current transformer (CT) secondary circuit connected to this equipment to be
opened while the primary system is live. Opening the CT circuit will produce a dangerously high
voltage.
WARNING!
Exposed terminals
Do not touch the exposed terminals of this equipment while the power is on, as the high voltage
generated is dangerous
ii
Preface
Residual voltage
Hazardous voltage can be present in the DC circuit just after switching off the DC power supply. It
takes a few seconds for the voltage to discharge.
CAUTION!
Earth
Operating environment
The equipment must only be used within the range of ambient environment detailed in the
specification and in an environment free of abnormal vibration.
Ratings
Before applying AC voltage and current or the DC power supply to the equipment, check that they
conform to the equipment ratings.
Do not attach and remove printed circuit boards when DC power to the equipment is on, as this
may cause the equipment to malfunction.
External circuit
When connecting the output contacts of the equipment to an external circuit, carefully check the
supply voltage used in order to prevent the connected circuit from overheating.
Connection cable
Tel: +86-25-87178185,
Fax: +86-25-87178208
Version: R1.07
iii
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relays use and application.
All contents provided by this manual are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this relay.
2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this relay.
5 Management
Introduce the management function (measurement, recording and remote control) of this relay.
6 Hardware
Introduce the main function carried out by each plug-in module of this relay and providing the
definition of pins of each plug-in module.
7 Settings
List settings including system settings, communication settings, label settings, logic links and etc.,
and some notes about the setting application.
9 Configurable Function
Introduce configurable function of the device and all configurable signals are listed.
10 Communication
Introduce the communication port and protocol which this relay can support, IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
11 Installation
iv
Preface
Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations. A typical wiring connection to this relay is indicated.
12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.
13 Maintenance
A general maintenance policy for this relay is outlined.
&
AND gate
1
OR gate
Comparator
BI
SET
EN
Preface
SIG
XXX
Output signal
Timer
t
t
0ms
0ms
[XXX]
[XXX]
Example
A, B, C
L1, L2, L3
AN, BN, CN
Ua, Ub, Uc
ABC
L123
U (voltage)
U0, U1, U2
VN, V1, V2
vi
1 Introduction
1 Introduction
Table of Contents
1 Introduction ...................................................................................... 1-a
1.1 Application....................................................................................................... 1-1
1.2 Function ........................................................................................................... 1-3
1.3 Features ........................................................................................................... 1-6
List of Figures
Figure 1.1-1 Typical application of PCS-902 ............................................................................1-1
Figure 1.1-2 Functional diagram of PCS-902...........................................................................1-2
1-a
Date: 2013-09-05
1 Introduction
1-b
Date: 2013-09-05
1 Introduction
1.1 Application
PCS-902 is a digital line distance protection with the main and back-up protection functions, which
is designed for overhead line or cables and hybrid transmission lines of various voltage levels.
52
52
PCS-902
PCS-902
Main protection of PCS-902 comprises of pilot distance protection (PUTT, POTT, blocking and
unblocking) and pilot directional earth-fault protection (selectable for independent communication
channel or sharing channel with POTT), which can clear any internal fault instantaneously for the
whole line with the aid of protection signal. DPFC distance protection can perform extremely high
speed operation for close-up faults. There is direct transfer trip (DTT) feature incorporated in the
relay.
PCS-902 also includes distance protection (3 forward zones and 1 reverse zone distance
protection with selectable mho or quadrilateral characteristic), 4 stages directional earth fault
protection, 4 stages directional phase overcurrent protection, 2 stages voltage protection
(under/over voltage protection), 4 stages frequency protection (under/over frequency protection),
broken conductor protection, pole discrepancy protection, breaker failure protection, thermal
overload protection, and dead zone protection etc. Morever, a backup overcurrent and earth fault
protection will be automatically enabled when VT circuit fails. In addition, stub overcurrent
protection is provided for one and a half breakers arrangement when transmission line is put into
maintenance.
PCS-902 has selectable mode of single-phase tripping or three-phase tripping and configurable
auto-reclosing mode for 1-pole, 3-poles and 1/3-pole operation.
PCS-902 with appropriate selection of integrated protection functions can be applied for various
voltage levels and primary equipment such as cables, overhead lines, interconnectors and
transformer feeder, etc. It also supports configurable binary inputs, binary outputs, LEDs and IEC
61850 protocol.
1-1
Date: 2013-09-05
1 Introduction
BUS
52
81
85
21
21D
67G
67P
50G
50P
50GVT
50PVT
50BF
49
46BC
62PD
FR
59
FL
Data Transmitt/Receive
51G
50DZ
51P
27
25
79
LINE
Function
ANSI
Pilot protection
85
21D
Distance protection
21
67G
50G
51G
67P
50P
10
51P
11
Overvoltage protection
59
12
Undervoltage protection
27
13
Frequency protection
81
14
46BC
15
50BF
16
49
17
50STB
18
50DZ
19
62PD
20
SOTF
21
50PVT
22
50GVT
23
Synchronism check
25
24
Automatic reclosure
79
25
Fault recorder
FR
1-2
Date: 2013-09-05
1 Introduction
26
Fault location
FL
1.2 Function
1.
Protection Function
Distance protection
Power swing blocking releasing, selectable for each of above mentioned zones
Current protection
Four stages directional earth fault protection, selectable time characteristic (definite-time
or inverse-time) and directionality (forward direction, reverse direction or non-directional)
1-3
Date: 2013-09-05
1 Introduction
Voltage protection
Frequency protection
Control function
Synchro-checking
Automatic reclosure (single shot or multi-shot (max. 4) for 1-pole AR and 3-pole AR)
Dual-channels redundancy
2.
Synchronism check for remote and manual closing (only for one circuit breaker)
Energy metering (active and reactive energy are calculated in import respectively export
direction)
3.
Logic
1-4
Date: 2013-09-05
1 Introduction
4.
Additional function
Fault location
VT circuit supervision
CT circuit supervision
Self diagnostic
Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.
Disturbance recorder including 32 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)
Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via the optical coupler
PPS (DIN): Pulse per second (PPS) via the optical coupler
SAS
Advanced
PPS (Fiber) PPS: Pulse per second (PPS) via optical-fibre interface
NoTimeSync
5.
Monitoring
Channel status
1-5
Date: 2013-09-05
1 Introduction
Frequency
6.
Communication
Optional 2 or 4 Ethernet ports (depend on the chosen type of MON plug-in module) conform
to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP
Optional 2 Ethernet ports via optic fiber (ST interface) conform to IEC 61850 protocol, DNP3.0
protocol or IEC 60870-5-103 protocol over TCP/IP
7.
User Interface
Friendly HMI interface with LCD and 9-button keypad on the front panel.
Auxiliary softwarePCS-Explorer
1.3 Features
The intelligent device integrated with protection, control and monitor provides powerful
protection function, flexible protection configuration, user programmable logic and
configurable binary input and binary output, which can meet with various application
requirements.
Fast fault clearance for faults within the protected line, the operating time is less than 10 ms
for close-up faults, less than 15ms for faults in the middle portion of protected line and less
than 25ms for remote end faults.
The unique DPFC distance element integrated in the protective device provides extremely
high speed operation and insensitive to power swing.
Self-adaptive floating threshold which only reflects deviation of power frequency component
improves the protection sensitivity and stability under the condition of load fluctuation and
system disturbance.
1-6
Date: 2013-09-05
1 Introduction
Advanced and reliable power swing blocking releasing feature which ensure distance
protection operate correctly for internal fault during power swing and prevent distance
protection from maloperation during power swing
Flexible automatic reclosure supports various initiation modes and check modes
Multiple setting groups with password protection and setting value saved permanently before
modification
Powerful PC tool software can fulfill protection function configuration, modify setting and
waveform analysis.
1-7
Date: 2013-09-05
1 Introduction
1-8
Date: 2013-09-05
2 Technical Data
2 Technical Data
Table of Contents
2 Technical Data .................................................................................. 2-a
2.1 Electrical Specifications ................................................................................. 2-1
2.1.1 AC Current Input ................................................................................................................ 2-1
2.1.2 AC Voltage Input ................................................................................................................ 2-1
2.1.3 Power Supply ..................................................................................................................... 2-1
2.1.4 Binary Input ........................................................................................................................ 2-1
2.1.5 Binary Output ..................................................................................................................... 2-2
2-a
Date: 2013-09-05
2 Technical Data
2-b
Date: 2013-09-05
2 Technical Data
ABC
50Hz, 60Hz
1A
Linear to
5A
4In
-for 10s
30In
-for 1s
100In
250In
Burden
Number
ABC
50Hz, 60Hz
100V~130V
Linear to
1V~170V
Thermal withstand
-continuously
200V
-10s
260V
-1s
300V
Burden at rated
Number
IEC 60255-11:2008
Rated voltage
110Vdc/125Vdc/220Vdc/250Vdc
88~300Vdc
Burden
Quiescent condition
<30W
Operating condition
<35W
24Vdc
48Vdc
1.2mA
2.4mA
Pickup voltage
16.8-28.8Vdc
33.6-57.6Vdc
Dropoff voltage
<12Vdc
<24Vdc
2-1
Date: 2013-09-05
2 Technical Data
Maximum permissible voltage
100Vdc
Withstand voltage
1ms
Number
Rated voltage
110Vdc
125Vdc
220Vdc
250Vdc
1.1mA
1.25mA
2.2mA
2.5mA
Pickup voltage
77-132Vdc
87.5-150Vdc
154-264Vdc
175-300Vdc
Dropoff voltage
<55Vdc
<62.5Vdc
<110Vdc
<125Vdc
300Vdc
Withstand voltage
1ms
Number
Tripping/signaling contact
Output mode
Continuous carry
8A@250Vdc
8A@125Vdc
<8ms (3ms)
Dropoff time
<5ms
0.65A@48Vdc
0.25A@110Vdc
0.25A@125Vdc
0.15A@220Vdc
0.15A@250Vdc
Burden
Maximal system voltage
Test voltage across open contact
300mW
380Vac
250Vdc
1000V RMS for 1min
10A@3s
15A@1s
20A@0.5s
30A@0.2s
10000 operations
Number
2.
Output mode
Continuous carry
Pickup time
2-2
Date: 2013-09-05
2 Technical Data
Dropoff time
<5ms
1.0A@48Vdc
0.9A@110Vdc
0.4A@220Vdc
380Vac
250Vdc
1000V RMS for 1min
Flush mounted
Chassis color
Silver grey
Approx. 15kg
Chassis material
Aluminum alloy
Location of terminal
Device structure
Protection class
Standard
IEC 60255-1:2009
Front side
IP40
Other sides
IP30
IP20
IEC 60255-1:2009
Operating temperature
-40C to +70C
Permissible humidity
Pollution degree
Altitude
<3000m
Protocol
IEC 60870-5-103:1997
Maximal capacity
32
Transmission distance
<500m
Safety level
Twisted pair
RJ-45
ST (Multi mode)
2-3
Date: 2013-09-05
2 Technical Data
Transmission rate
100Mbits/s
Transmission standard
100Base-TX
100Base-FX
Transmission distance
<100m
<2km (1310nm)
Protocol
Safety level
Connector type
ST
Fibre type
Multi mode
Transmission distance
<2km
Wave length
1310nm
Transmission power
Min. -20.0dBm
Min. -30.0dBm
Margin
Min +3.0dB
Connector type
LC
Fibre type
Multi mode
Transmission distance
<2km
Wave length
1310nm
Transmission power
Min. -20.0dBm
Min. -30.0dBm
Margin
Min +3.0dB
Connector type
FC
ST
Fibre type
Single mode
Multi mode
Wave length
1310nm
1550nm
850nm
Transmission distance
Max.40km
Max.100km
Max.2km
Transmission power
-13.03.0 dBm
-12dBm~-20 dBm
Min.-37 dBm
Min.-36 dBm
Min. -30.0dBm
Min.-3 dBm
Min.-3 dBm
Min.-8 dBm
Connector type
ST
Fibre type
Multi mode
Wave length
820nm
2-4
Date: 2013-09-05
2 Technical Data
Minimum receiving power
Min. -25.0dBm
Margin
Min +3.0dB
RS-232
Baud Rate
Printer type
Safety level
RS-485
Transmission distance
<500m
Maximal capacity
32
Timing standard
PPS, IRIG-B
Safety level
IEC60068-2-1:2007
IEC60068-2-2:2007
IEC60068-2-30:2005
IEC 60255-27:2005
Dielectric tests
Standard
IEC 60255-5:2000
Overvoltage category
Insulation
resistance
measurements
2-5
Date: 2013-09-05
2 Technical Data
IEC 60255-22-3:2007 class
Frequency sweep
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz
Radio frequency interference tests
Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-22-4:2008
Conducted
RF
Electromagnetic
Disturbance
IEC 60255-22-6:2001
Power supply, AC, I/O, Comm. Terminal: Class , 10Vrms, 150
kHz~80MHz
IEC 61000-4-8:2001
Immunity
IEC 61000-4-9:2001
class , 6.4/16s, 1000A/m for 3s
IEC 61000-4-10:2001
immunity
IEC60255-11: 2008
- Voltage dips
2.6 Certifications
ISO9001:2008
ISO14001:2004
OHSAS18001:2007
ISO10012:2003
CMMI L4
2-6
Date: 2013-09-05
2 Technical Data
2.7 Terminals
Connection Type
Wire Size
2
AC current
can be adopted.
AC voltage
Power supply
Contact I/O
Range
Accuracy
Phase range
0~ 360
Frequency
fn3 Hz
0.02Hz
0.05~5.00In
Voltage
0.05~1.50Un
Energy (Wh)
Energy (VAh)
0.05~1.50Un
0.05~5.00In
0.05~1.50Un
0.05~5.00In
0.05~1.50Un
0.05~5.00In
0.05~1.50Un
0.05~5.00In
0.05~1.50Un
0.05~5.00In
Local or remote
1s
3s
3s/day
1ms
2-7
Date: 2013-09-05
2 Technical Data
Recording position
1ms
Potential-free contact
Resolution of SOE
2ms
0.050In~30.000In (A)
Accuracy
0.050In~30.000In (A)
Accuracy
Un~2Unn (V)
Accuracy
(0.000~4Unn)/In (ohm)
Accuracy
Resetting ratio
105%
Time delay
0.000~10.000 (s)
Accuracy
1%Setting+30ms
0.050In~30.000In (A)
Accuracy
Resetting ratio
95%
Time delay
0.000~20.000 (s)
0.050In~30.000In (A)
2-8
Date: 2013-09-05
2 Technical Data
Accuracy
Resetting ratio
95%
Time delay
0.000~20.000 (s)
Un~2Unn (V)
Accuracy
Resetting ratio
95%
Time delay
0.000~30.000 (s)
0~Unn (V)
Accuracy
Resetting ratio
105%
Time delay
0.000~30.000 (s)
50.00~65.00 (Hz)
Accuracy
0.02Hz
Resetting ratio
95%
Time delay
0.000~100.000 (s)
Accuracy
Accuracy
0.02Hz
Resetting ratio
105%
Time delay
Accuracy
0.200~20.000 (Hz/s)
Accuracy
0.02Hz/s
<20ms
2-9
Date: 2013-09-05
2 Technical Data
Drop-off time
<20ms
0.050In~30.000In (A)
0.050In~30.000In (A)
0.050In~30.000In (A)
Accuracy
0.000~10.000 (s)
0.000~10.000 (s)
0.050In~30.000In (A)
Accuracy
0.100~100.000 (min)
1.000~3.000
1.000~3.000
Resetting ratio
95%
Drop-off time
<30ms
2.5% operating time or 30ms, whichever is greater
Time accuracy
0.050In~30.000In (A)
Accuracy
Resetting ratio
95%
Time delay
0.000~10.000 (s)
Accuracy
0.050In~30.000In
Accuracy
Time delay
0.000~10.000s
Accuracy
1%Setting+30ms
0.050In~30.000In (A)
0.050In~30.000In (A)
Accuracy
Resetting ratio
95%
Time delay
0.000~600.000 (s)
Accuracy
0.20~1.00
Accuracy
2.5% of setting
PCS-902 Line Distance Relay
2-10
Date: 2013-09-05
2 Technical Data
Resetting ratio
95%
Time delay
0.000~600.000 (s)
Accuracy
1% of Setting+30ms
2.10.15 Auto-reclosing
Phase difference setting range
0~89 (Deg)
Accuracy
2.0Deg
0.02Un~0.8Un (V)
Accuracy
Max(0.01Un, 2.5%)
0.02~1 (Hz)
Accuracy
0.01Hz
1%Setting+20ms
1%Setting+20ms
1%Setting+20ms
< 2.5%
Tolerance will be higher in case of single-phase fault with high ground resistance.
2-11
Date: 2013-09-05
2 Technical Data
2-12
Date: 2013-09-05
3 Operation Theory
3 Operation Theory
Table of Contents
3 Operation Theory ............................................................................. 3-a
3.1 System Parameters ......................................................................................... 3-1
3.1.1 General Application ............................................................................................................ 3-1
3.1.2 Function Description .......................................................................................................... 3-1
3.1.3 Settings .............................................................................................................................. 3-1
3-a
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
List of Figures
Figure 3.3-1 Logic diagram of CB position supervision.........................................................3-4
Figure 3.3-2 Logic diagram of trip&closing circuit supervision ............................................3-5
Figure 3.4-1 Flow chart of protection program .......................................................................3-8
Figure 3.4-2 Logic diagram of fault detector ...........................................................................3-9
Figure 3.5-1 Logic diagram of auxiliary element ...................................................................3-19
3-g
3 Operation Theory
Figure 3.6-1 Protected reach of distance protection for each zone ....................................3-22
Figure 3.6-2 Operating time of single-phase fault (50Hz, SIR=1) .........................................3-23
Figure 3.6-3 Operating time of single-phase fault (60Hz, SIR=1) .........................................3-24
Figure 3.6-4 Operating time of two-phase fault (50Hz, SIR=1) .............................................3-24
Figure 3.6-5 Operating time of two-phase fault (60Hz, SIR=1) .............................................3-25
Figure 3.6-6 Operating time of three-phase fault (50Hz, SIR=1) ..........................................3-25
Figure 3.6-7 Operating time of three-phase fault (60Hz, SIR=1) ..........................................3-26
Figure 3.6-8 Operating time of single-phase fault (50Hz, SIR=30) .......................................3-26
Figure 3.6-9 Operating time of single-phase fault (60Hz, SIR=30) .......................................3-27
Figure 3.6-10 Operating time of two-phase fault (50Hz, SIR=30) .........................................3-27
Figure 3.6-11 Operating time of two-phase fault (60Hz, SIR=30) .........................................3-28
Figure 3.6-12 Operating time of three-phase fault (50Hz, SIR=30) ......................................3-28
Figure 3.6-13 Operating time of three-phase fault (60Hz, SIR=30) ......................................3-29
Figure 3.6-14 Operation characteristic for forward fault ......................................................3-30
Figure 3.6-15 Operation characteristic for reverse fault ......................................................3-31
Figure 3.6-16 Logic diagram of DPFC distance protection ..................................................3-32
Figure 3.6-17 Distance element with load trapezoid .............................................................3-33
Figure 3.6-18 Phase-to-ground operation characteristic for forward fault .........................3-35
Figure 3.6-19 Phase-to-phase operation characteristic for forward fault ...........................3-36
Figure 3.6-20 Operation characteristic for reverse fault ......................................................3-38
Figure 3.6-21 Steady-state characteristic of three-phase short-circuit fault ......................3-38
Figure 3.6-22 Operation characteristic of three-phase close up short-circuit fault ...........3-39
Figure 3.6-23 Shift impedance characteristic of zone 1 and zone 2 ....................................3-40
Figure 3.6-24 Operation characteristic of reverse Z4 distance protection .........................3-41
Figure 3.6-25 Logic diagram of enabling distance protection (Mho) ..................................3-43
Figure 3.6-26 Logic diagram of distance protection (Mho zone 1) ......................................3-43
Figure 3.6-27 Logic diagram of distance protection (Mho zone 2) ......................................3-44
Figure 3.6-28 Logic diagram of distance protection (Mho zone 3) ......................................3-45
Figure 3.6-29 Logic diagram of distance protection (Mho zone 4) ......................................3-46
Figure 3.6-30 Quadrilateral forward distance element characteristics ...............................3-50
3-h
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
List of Tables
Table 3.1-1 System parameters ................................................................................................3-1
Table 3.2-1 Line parameters ......................................................................................................3-2
Table 3.3-1 I/O signals of CB position supervision .................................................................3-4
Table 3.3-2 Internal settings of CB position supervision .......................................................3-5
Table 3.4-1 I/O signals of fault detector ...................................................................................3-9
Table 3.4-2 Settings of fault detector .....................................................................................3-10
Table 3.5-1 I/O signals of auxiliary element ...........................................................................3-14
Table 3.5-2 Settings of auxiliary element ...............................................................................3-19
3-l
3 Operation Theory
3 Operation Theory
3 Operation Theory
3-o
3 Operation Theory
3-p
3 Operation Theory
3.1.3 Settings
Table 3.1-1 System parameters
No.
Name
Range
Step
Unit
Remark
Active_Grp
1~10
Opt_SysFreq
50 or 60
PrimaryEquip_Name
U1n
33.00~65500.00
0.01
kV
U2n
80.00~220.00
0.01
I1n
100~65500
I2n
1 or 5
Hz
System frequency
The name of primary equipment
Primary rated value of VT (phase to
phase)
Secondary rated value of VT (phase to
phase)
f_High_FreqAlm
50~65
Hz
The
device
will
issue
an
alarm
f_Low_FreqAlm
45~60
Hz
The
device
will
issue
an
alarm
3-1
3 Operation Theory
3.2.3 Settings
Table 3.2-1 Line parameters
No.
Name
Range
Step
Unit
Remark
Positive-sequence reactance of the whole
line (secondary value)
Positive-sequence resistance of the whole
line (secondary value)
Zero-sequence reactance of the whole line
(secondary value)
Zero-sequence resistance of the whole line
(secondary value)
Zero-sequence
mutual
reactance
(secondary value)
Zero-sequence mutual resistance of the
whole line (secondary value)
X1L
(0.000~4Unn)/In
0.001
ohm
R1L
(0.000~4Unn)/In
0.001
ohm
X0L
(0.000~4Unn)/In
0.001
ohm
R0L
(0.000~4Unn)/In
0.010
ohm
X0M
(0.000~4Unn)/In
0.001
ohm
R0M
(0.000~4Unn)/In
0.01
ohm
LineLength
0.00~655.35
0.01
km
phi1_Reach
30.00~89.00
0.01
Deg
Real_K0
-4.000~4.000
0.001
10
Imag_K0
-4.000~4.000
0.001
Real
component
of
zero-sequence
compensation coefficient
Imaginary component of zero-sequence
compensation coefficient
3 Operation Theory
appropriate monitor method is used to check the rationality of the binary input. When the binary
input of CB open position is detected, the status of CB position will be thought as incorrect and an
alarm [Alm_52b] will be issued if there is current detected in the line.
Together with the status of circuit breaker and the information of external circuit, this function can
be used to supervise control circuit of circuit breaker.
External manual closing binary input (ManCls) is only used for SOTF logic application, the control
of circuit breaker (CB) closing or opening should refer to section 3.29 (Control and Synchrocheck
for Manual Closing).
Alm_52b
52b_PhB
52b_PhC
ManCls
2.
Alm_52b
ManCls
3.
TCCS.Alm
52b
TCCS.Input
ManCls
TCCS will be disabled automatically when it is used for phase-segregated circuit breaker.
3-3
3 Operation Theory
Input Signal
Description
52b_PhA
52b_PhB
52b_PhC
ManCls
52b
52a
TCCS.Input
Control circuit failure (normally closed contact and normally open contact of
three-phase circuit breaker are all de-energized due to DC power loss of control
circuit)
No.
Output Signal
Description
Alm_52b
CB position is abnormal
TCCS.Alm
Note!
The signal [52a] only take effect in the tripping/closing circuit supervision and not affect
any protection function. Only if tripping/closing circuit supervision is configured, this signal
needs to be connected to the device.
3.3.5 Logic
BI
[52b_PhA]
>=1
&
&
BI
[52b_PhB]
>=1
&
BI
[52b_PhC]
>=1
&
>=1
&
BI
[52b]
&
SIG
Ia>I_Line
>=1
&
SIG
10s
>=1
10s
Alm_52b
Ib>I_Line
&
SIG
Ic>I_Line
3-4
3 Operation Theory
>=1
BI
[52a]
BI
[52b]
BI
[TCCS.Input]
>=1
[TCCS.t_DPU]
[TCCS.t_DDO]
TCCS.Alm
I_Line is threshold value used to determine whether line is on-load or no-load. Default value
0.06In.
3.3.6 Settings
Table 3.3-2 Internal settings of CB position supervision
No.
Name
Default Value
Unit
Remark
TCCS.t_DPU
0.5
TCCS.t_DDO
0.5
2.
3.
Pickup condition 3: Phase voltage or phase-to-phase voltage is greater than the voltage
setting of overvoltage protection
4.
3-5
3 Operation Theory
Pickup condition 3 and 4 are only available when respective protection elements are enabled.
If any of the above conditions is complied, the FD will operate to activate the output circuit
providing DC power supply to the output relays.
DPFC current fault detector element (pickup condition 1) and residual current fault detector
element (pickup condition 2) are always enabled, and all protection functions are permitted to
operate when they operate.
3.4.2.1 Fault Detector Based on DPFC Current (pickup condition 1)
DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from that of a
cycle before.
20
40
60
Original Current
80
100
120
20
40
60
DPFC current
80
100
120
100
50
0
-50
-100
From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection.
It is used to determine whether this pickup condition is met according to Equation 3.4-1.
For multi-phase short-circuit fault, the DPFC phase-to-phase current has high sensitivity to ensure
the pickup of protection device. For usual single phase to earth fault, it also has sufficient
sensitivity to pick up except the earth fault with very large fault resistance. Under this condition the
DPFC current is relative small, however, residual current is also used to judge pickup condition
(pickup condition 2).
This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steadily under normal or power swing
3-6
3 Operation Theory
condition, the adaptive floating threshold with the ISet is higher than the change of current under
these conditions and hence maintains the element stability.
The criterion is:
IMAX>1.25ITh+ISet
Equation 3.4-1
Where:
IMAX: The maximum half-wave integration value of phase-to-phase current (=AB, BC, CA)
ISet: The fixed threshold value (i.e. the setting [FD.DPFC.I_Set])
ITh: The floating threshold value
The coefficient, 1.25, is an empirical value which ensures the threshold always higher than the
unbalance output value of the system.
If operating condition is met, DPFC current element will pickup and trigger FD to provide DC power
supply for output relays, the FD operation signal will maintain 7 seconds after DPFC current
element drops off.
3.4.2.2 Fault Detector Based on Residual Current (pickup condition 2)
This pickup condition will be met when 3I0 is greater than the setting [FD.ROC.3I0_Set].
Where:
3I0: residual current calculates from the vector sum of Ia, Ib and Ic
When residual current FD element operates and lasts for longer than 10 seconds, an alarm
[Alm_PersistI0] will be issued.
If operating condition is met, the residual current FD element will pickup and trigger FD to provide
DC power supply for output relay, and pickup signal will be kept for 7 seconds after the residual
current FD element drops off.
3.4.2.3 Fault Detector Based on Overvoltage (pickup condition 3)
Overvoltage fault detector will be automatically effective when overvoltage protection is enabled.
If the logic setting [59Px.Opt_1P/3P] is set as 1 (x=1 or 2), i.e. the protective device adopts
1-out-of-3 mode, when any phase voltage is greater than the setting [59Px.U_Set] (x=1 or 2), the
overvoltage fault detector element will pickup and trigger FD to provide DC power supply for
output relays, the FD operation signal will maintain 7 seconds after overvoltage fault detector
element drops off.
If the logic setting [59Px.Opt_1P/3P] is set as 0 (x=1 or 2), i.e. the protective device adopts
3-out-of-3 mode, when all three phase voltages are greater than the setting [59Px.U_Set] (x=1 or
2), the overvoltage fault detector element will pickup and trigger FD to provide DC power supply
for output relays, the FD operation signal will maintain 7 seconds after overvoltage fault detector
element drops off.
3-7
3 Operation Theory
3.4.2.4 Fault Detector Based on Circuit Breaker Position Discrepancy (pickup condition 4)
When pole discrepancy protection is enabled, i.e. the logic setting [62PD.En] is set as 1, and if
three phases of circuit breaker are not in the same status, pole discrepancy FD element will
operate to provide DC power supply for output relays, and pickup signal will maintain 7 seconds
after pole discrepancy FD element drops out.
2.
3.
Hardware self-check
4.
5.
6.
Channel supervision
Once the protection fault detector element in protection calculation DSP picks up, the protection
device will switch to fault calculation program, for example the calculation of distance protection,
and to determine logic. If the fault is within the protected zone, the protection device will send
tripping command.
The protection program flow chart is shown as Figure 3.4-1.
Main program
Sampling program
No
Regular program
Yes
Pickup?
The protection FD pickup conditions are the same as the FD in fault detector DSP as shown below.
The operation criteria for the conditions are also the same as that in fault detector DSP. Please
3-8
3 Operation Theory
2.
3.
Pickup condition 3: Phase voltage or phase-to-phase voltage is greater than the setting value
4.
When any pickup condition mentioned above is met, the protection device will go to fault
calculation state.
Pickup condition 3 and 4 are not common fault detector elements, only used for respective
protection element. Please refer to section 3.15.1 and section 3.20 for details.
Output Signal
Description
FD.Pkp
FD.DPFC.Pkp
FD.ROC.Pkp
3.4.6 Logic
SIG
Ia
SIG
Ib
SIG
Ic
Iab=(Ia-Ib)
Ibc=(Ib-Ic)
Ica=(Ic-Ia)
Iab>[FD.DPFC.I_Set]
>=1
Ibc>[FD.DPFC.I_Set]
Ica>[FD.DPFC.I_Set]
FD.DPFC.Pkp
>=1
0s
7s
FD.Pkp
3I0=Ia+Ib+Ic
3I0>[FD.ROC.3I0_Set]
FD.ROC.Pkp
3-9
3 Operation Theory
3.4.7 Settings
Table 3.4-2 Settings of fault detector
No.
Name
Range
Step
Unit
FD.DPFC.I_Set
(0.050~30.000)In
0.001
FD.ROC.3I0_Set
(0.050~30.000)In
0.001
Remark
Current setting of DPFC current fault
detector element
Current setting of residual current fault
detector element
It shares DPFC current element of DPFC fault detector. If DPFC fault detector operates
(FD.DPFC.Pkp=1) and current change auxiliary element is enabled, current change auxiliary
element operates.
2.
There are 3 stages for residual current auxiliary element (AuxE.ROC1, AuxE.ROC2 and
AuxE.ROC3). Each residual current auxiliary element will operate instantly if calculated residual
current amplitude is larger than corresponding current setting
The criteria are:
AuxE.ROC1: 3I0>[AuxE.ROC1.3I0_Set]
AuxE.ROC2: 3I0>[AuxE.ROC2.3I0_Set]
AuxE.ROC3: 3I0>[AuxE.ROC3.3I0_Set]
Where:
3I0: The calculated residual current
3.
3-10
3 Operation Theory
There are 3 stages for phase current auxiliary element (AuxE.OC1, AuxE.OC2 and AuxE.OC3).
Each phase current auxiliary element will operate instantly if phase current amplitude is larger than
corresponding current setting.
The criteria are:
AuxE.OC1: IMAX>[AuxE.OC1.I_Set]
AuxE.OC2: IMAX>[AuxE.OC2.I_Set]
AuxE.OC3: IMAX>[AuxE.OC3.I_Set]
Where:
IMAX: The maximum phase current among three phases
4.
AuxE.UVG will operate instantly if any phase-to-ground voltage is lower than corresponding
voltage setting.
The criterion is:
UMIN<[ AuxE.UVG.U_Set]
Where:
UMIN: The minimum value among three phase-to-ground voltages
6.
AuxE.UVS will operate instantly if any phase-to-phase voltage is lower than corresponding voltage
setting.
The criterion is:
UMIN<[ AuxE.UVS.U_Set]
Where:
UMIN: The minimum value among three phase-to-phase voltages
7.
AuxE.ROV will operate instantly if calculated residual voltage is larger than corresponding voltage
3-11
3 Operation Theory
setting.
The criterion is:
3U0>[ AuxE.ROV.3U0_Set]
Where:
3U0: The calculated residual voltage
3-12
3 Operation Theory
AuxE.St
AuxE.OCD.Blk
AuxE.OCD.St_Ext
AuxE.ROCx.En
AuxE.OCD.On
AuxE.ROCx.Blk
AuxE.ROCx.St
AuxE.OCx.En
AuxE.ROCx.On
AuxE.OCx.Blk
AuxE.OCx.St
AuxE.UVD.En
AuxE.OCx.StA
AuxE.UVD.Blk
AuxE.OCx.StB
AuxE.UVG.En
AuxE.OCx.StC
AuxE.UVG.Blk
AuxE.OCx.On
AuxE.UVS.En
AuxE.UVD.St
AuxE.UVS.Blk
AuxE.UVD.St_Ext
AuxE.ROV.En
AuxE.UVD.On
AuxE.ROV.Blk
AuxE.UVG.St
AuxE.UVG.StA
AuxE.UVG.StB
AuxE.UVG.StC
AuxE.UVG.On
AuxE.UVS.St
AuxE.UVS.StAB
AuxE.UVS.StBC
AuxE.UVS.StCA
AuxE.UVS.On
AuxE.ROV.St
AuxE.ROV.On
Where:
x can be 1, 2 or 3
3-13
3 Operation Theory
Input Signal
AuxE.OCD.En
AuxE.OCD.Blk
AuxE.ROC1.En
AuxE.ROC1.Blk
AuxE.ROC2.En
AuxE.ROC2.Blk
AuxE.ROC3.En
AuxE.ROC3.Blk
AuxE.OC1.En
10
AuxE.OC1.Blk
11
AuxE.OC2.En
12
AuxE.OC2.Blk
13
AuxE.OC3.En
14
AuxE.OC3.Blk
15
AuxE.UVD.En
16
AuxE.UVD.Blk
17
AuxE.UVG.En
18
AuxE.UVG.Blk
19
AuxE.UVS.En
20
AuxE.UVS.Blk
Description
Current change auxiliary element enabling input, it is triggered from binary input or
programmable logic etc.
Current change auxiliary element blocking input, it is triggered from binary input or
programmable logic etc.
Stage 1 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 1 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 2 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 3 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 1 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 1 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 2 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 3 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Voltage change auxiliary element enabling input, it is triggered from binary input or
programmable logic etc.
Voltage change auxiliary element blocking input, it is triggered from binary input or
programmable logic etc.
Phase-to-ground under voltage auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element blocking input, it is triggered from
3-14
3 Operation Theory
binary input or programmable logic etc.
21
AuxE.ROV.En
22
AuxE.ROV.Blk
No.
Residual voltage auxiliary element enabling input, it is triggered from binary input
or programmable logic etc.
Residual voltage auxiliary element blocking input, it is triggered from binary input
or programmable logic etc.
Output Signal
Description
AuxE.St
AuxE.OCD.St_Ext
AuxE.OCD.On
AuxE.ROC1.St
AuxE.ROC1.On
AuxE.ROC2.St
AuxE.ROC2.On
AuxE.ROC3.St
AuxE.ROC3.On
10
AuxE.OC1.St
11
AuxE.OC1.StA
12
AuxE.OC1.StB
13
AuxE.OC1.StC
14
AuxE.OC1.On
15
AuxE.OC2.St
16
AuxE.OC2.StA
17
AuxE.OC2.StB
18
AuxE.OC2.StC
19
AuxE.OC2.On
20
AuxE.OC3.St
21
AuxE.OC3.StA
22
AuxE.OC3.StB
23
AuxE.OC3.StC
24
AuxE.OC3.On
25
AuxE.UVD.St
26
AuxE.UVD.St_Ext
27
AuxE.UVD.On
28
AuxE.UVG.St
29
AuxE.UVG.StA
30
AuxE.UVG.StB
31
AuxE.UVG.StC
32
AuxE.UVG.On
33
AuxE.UVS.St
34
AuxE.UVS.StAB
35
AuxE.UVS.StBC
36
AuxE.UVS.StCA
37
AuxE.UVS.On
3-15
3 Operation Theory
38
AuxE.ROV.St
39
AuxE.ROV.On
3.5.5 Logic
SIG
FD.DPFC.Pkp
SIG
AuxE.OCD.En
SIG
AuxE.OCD.Blk
En
AuxE.OCD.En
SIG
Ia
SIG
Ib
SIG
Ic
SIG
&
&
0s
[AuxE.OCD.t_DDO]
AuxE.OCD.St_Ext
AuxE.OCD.On
Calculate residual
current:
3I0=Ia+Ib+Ic
3I0>[AuxE.ROC1.3I0_Set]
AuxE.ROC1.En
&
AuxE.ROC1.St
&
SIG
AuxE.ROC1.Blk
En
AuxE.ROC1.En
SIG
AuxE.ROC2.En
AuxE.ROC1.On
3I0>[AuxE.ROC2.3I0_Set]
&
AuxE.ROC2.St
&
SIG
AuxE.ROC2.Blk
En
AuxE.ROC2.En
SIG
AuxE.ROC3.En
AuxE.ROC2.On
3I0>[AuxE.ROC3.3I0_Set]
SIG
AuxE.ROC3.Blk
En
AuxE.ROC3.En
&
AuxE.ROC3.St
&
AuxE.ROC3.On
3-16
3 Operation Theory
SIG
Ia
Ia>[AuxE.OC1.I_Set]
&
AuxE.OC1.StA
SIG
Ib
Ib>[AuxE.OC1.I_Set]
&
AuxE.OC1.StB
SIG
Ic
Ic>[AuxE.OC1.I_Set]
&
AuxE.OC1.StC
>=1
SIG
&
AuxE.OC1.En
AuxE.OC1.St
&
SIG
AuxE.OC1.Blk
En
AuxE.OC1.En
SIG
Ia
AuxE.OC1.On
Ia>[AuxE.OC2.I_Set]
&
AuxE.OC2.StA
SIG
Ib
Ib>[AuxE.OC2.I_Set]
&
AuxE.OC2.StB
SIG
Ic
Ic>[AuxE.OC2.I_Set]
&
AuxE.OC2.StC
>=1
SIG
&
AuxE.OC2.En
AuxE.OC2.St
&
SIG
AuxE.OC2.Blk
En
AuxE.OC2.En
SIG
Ia
AuxE.OC2.On
Ia>[AuxE.OC3.I_Set]
&
AuxE.OC3.StA
SIG
Ib
Ib>[AuxE.OC3.I_Set]
&
AuxE.OC3.StB
SIG
Ic
Ic>[AuxE.OC3.I_Set]
&
AuxE.OC3.StC
>=1
SIG
&
AuxE.OC3.En
AuxE.OC3.St
&
SIG
AuxE.OC3.Blk
En
AuxE.OC4.En
AuxE.OC3.On
3-17
3 Operation Theory
SIG
Ua
SIG
Ub
SIG
Uc
Ua>[AuxE.UVD.U_Set]
>=1
Ub>[AuxE.UVD.U_Set]
&
AuxE.UVD.St
Uc>[AuxE.UVD.U_Set]
0s
SIG
[AuxE.UVD.t_Ext]
AuxE.UVD.En
AuxE.UVD.St_Ext
&
SIG
AuxE.UVD.Blk
En
AuxE.UVD.En
SET
AuxE.UVD.On
UA<[AuxE.UVG.U_Set]
&
AuxE.UVG.StA
SET
UB<[AuxE.UVG.U_Set]
&
AuxE.UVG.StB
SET
UC<[AuxE.UVG.U_Set]
&
AuxE.UVG.StC
>=1
SIG
&
AuxE.UVG.En
AuxE.UVG.St
&
SIG
AuxE.UVG.Blk
En
AuxE.UVG.En
AuxE.UVG.On
SET
UAB<[AuxE.UVS.U_Set]
&
AuxE.UVS.StAB
SET
UBC<[AuxE.UVS.U_Set]
&
AuxE.UVS.StBC
SET
UCA<[AuxE.UVS.U_Set]
&
AuxE.UVS.StCA
>=1
SIG
&
AuxE.UVS.En
AuxE.UVS.St
&
SIG
AuxE.UVS.Blk
En
AuxE.UVS.En
AuxE.UVS.On
SIG
Ua
SIG
Ub
SIG
Uc
SIG
AuxE.ROV.En
SIG
AuxE.ROV.Blk
En
AuxE.ROV.En
3U0>[AuxE.ROV.3U0_Set]
&
AuxE.ROV.St
&
AuxE.ROV.On
3-18
3 Operation Theory
SIG
AuxE.OCD.St_Ext
SIG
AuxE.ROC1.St
SIG
AuxE.ROC2.St
SIG
AuxE.ROC3.St
SIG
AuxE.OC1.St
>=1
>=1
AuxE.St
>=1
SIG
AuxE.OC2.St
SIG
AuxE.OC3.St
SIG
AuxE.UVD.St_Ext
SIG
AuxE.UVG.St
SIG
AuxE.UVS.St
SIG
AuxE.ROV.St
>=1
>=1
>=1
3.5.6 Settings
Table 3.5-2 Settings of auxiliary element
No.
1
Name
AuxE.OCD.t_DDO
Range
0.000~10.000
Step
0.001
Unit
s
Remark
Extended time delay of current change
auxiliary element
Enabling/disabling current change
AuxE.OCD.En
auxiliary element
0 or 1
0: disable
1: enable
AuxE.ROC1.3I0_Set
(0.050~30.000)In
0.001
AuxE.ROC1.En
0 or 1
0: disable
1: enable
AuxE.ROC2.3I0_Set
(0.050~30.000)In
0.001
AuxE.ROC2.En
0 or 1
0: disable
1: enable
AuxE.ROC3.3I0_Set
(0.050~30.000)In
0.001
AuxE.ROC3.En
0 or 1
0: disable
1: enable
AuxE.OC1.I_Set
(0.050~30.000)In
3 Operation Theory
auxiliary element
Enabling/disabling stage 1 phase
10
AuxE.OC1.En
0 or 1
0: disable
1: enable
11
AuxE.OC2.I_Set
(0.050~30.000)In
auxiliary element
Enabling/disabling stage 2 phase
12
AuxE.OC2.En
0 or 1
0: disable
1: enable
13
AuxE.OC3.I_Set
(0.050~30.000)In
auxiliary element
Enabling/disabling stage 3 phase
14
AuxE.OC3.En
0 or 1
0: disable
1: enable
15
AuxE.UVD.U_Set
0~Un
0.001
16
AuxE.UVD.t_Ext
0.000~10.000
0.001
17
AuxE.UVD.En
auxiliary element
0 or 1
0: disable
1: enable
18
AuxE.UVG.U_Set
0~Un
0.001
19
AuxE.UVG.En
0 or 1
0: disable
1: enable
20
AuxE.UVS.U_Set
0~Unn
0.001
21
AuxE.UVS.En
0 or 1
0: disable
1: enable
22
AuxE.ROV.3U0_Set
0~Un
0.001
23
AuxE.ROV.En
auxiliary element
0 or 1
0: disable
1: enable
3-20
3 Operation Theory
2.
3.
4.
5.
6.
7.
Load encroachment
3-21
3 Operation Theory
It is used to prevent all distance elements from undesired trip due to load encroachment
under heavy load condition especially for long lines.
8.
9.
Z4
EM
EN
Z1DZ
Z2
Z3
Where:
Z1: forward direction zone 1
Z2: forward direction zone 2
Z3: forward direction zone 3
Z4: reverse direction zone 4
DZ: DPFC distance protection
The choice of impedance reach is as follow. (only for reference)
The zone 1 impedance reach setting should be set to cover as much the protected line as possible
but not to respond faults beyond the protected line. The accuracy of the relay distance elements is
3-22
3 Operation Theory
2.5% in general applications, however, the error could be much larger due to errors of current
transformer, voltage transformer and inaccuracies of line parameter from which the relay settings
are calculated. It is recommended the zone 1 reach is set to 80%~85% of the protected line in
consideration the aforesaid errors and safety margin to prevent instantaneously tripping for faults
on adjacent lines. The remaining 20% of the protected line relies on the zone 2 distance elements.
With the pilot scheme distance protection, fast fault clearance could also be achieved for end zone
faults at both ends of the protected line.
The general rule for zone 2 impedance reach setting is set to cover the protected line plus 20% of
the adjacent line. However, the coverage of adjacent line should be extended in the presence of
additional infeed at the remote end of the protected line to ensure 20% coverage of adjacent line.
This assures the fast operation of zone 2 distance element for faults at the remote end of the
protected line since the fault is well within zone 2 reach. This is important for pilot protection as the
impedance reach of pilot zone is the same as that of zone 2 distance element. In a parallel line
situation, a fault cleared sequentially on a line may cause current reversal in the healthy line. If the
pilot zone settings are set to cover 50% of adjacent line and the POTT or Blocking scheme is used,
the current reversal in the healthy line could cause relay mal-operation. Therefore, current reversal
logic is required and explained in section 3.8.2.6.
The Z3 distance element acts as backup protection for protected line and adjacent line but not to
over the zone 2 setting of adjacent line. The zone 3 impedance reach is generally 2 times zone 1
reach, i.e. 160% of protected line.
For different system impedance ratio (SIR), the operating time of distance protection for different
fault location are shown as the following figures.
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-23
3 Operation Theory
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-24
3 Operation Theory
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-25
3 Operation Theory
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
33
32.5
32
Operating Time (ms)
31.5
31
30.5
30
29.5
29
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
3-26
3 Operation Theory
27.5
27
Operating Time (ms)
26.5
26
25.5
25
24.5
24
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
45
40
35
Operating Time (ms)
30
25
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-27
3 Operation Theory
35
30
Operating Time (ms)
25
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
33
32
Operating Time (ms)
31
30
29
28
27
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-28
3 Operation Theory
27.5
27
Operating Time (ms)
26.5
26
25.5
25
24.5
24
23.5
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
3-29
3 Operation Theory
EM
EN
I
ZS
ZK
jX
Zzd
Zk
Zs+Zk
-Zs
Where:
ZZD: the setting of DPFC distance protection
ZS: total impedance between local system and device location
ZK: measurement impedance
: positive-sequence sensitive angle, i.e. [phi1_Reach]
Figure 3.6-14 shows the operation characteristic of DPFC distance protection on R-X plane when
a fault occurs in forward direction, which is the circle with the Zs as the center and theZs+Zzd as
the radius. When measured impedance Zk is in the circle, DPFC distance protection will operate.
DPFC distance protection has a larger capability of enduring fault resistance than distance
protection using positive-sequence as polarized voltage.
3-30
3 Operation Theory
ZZD
F
EM
EN
I
ZK
ZS
jX
Z's
Zzd
-Zk
21D
21D.En
21D.Op
21D.Blk
21D.On
3-31
3 Operation Theory
Input Signal
21D.En
21D.Blk
No.
Description
DPFC distance protection enabling input, it is triggered from binary input or
programmable logic etc.
DPFC distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
21D.Op
21D.On
3.6.3.4 Logic
EN
[21D.En]
21D.On
&
SIG
21D.En
SIG
21D.Blk
SIG
FD.Pkp
EN
[VTS.En_Out_VT]
SIG
SIG
SET
[21D.Z_Set]<0.05/In
SET
Z<[21D.Z_Set]
SIG
UP<0.85Un
SET
Z<[21D.Z_Set]
SIG
UPP<0.85Unn
SIG
PD signal
&
>=1
&
>=1
&
21D.Op
&
&
Note!
PD signal only blocks DPFC distance element of corresponding phase (i.e. broken phase),
and healthy phases (operation phases) are not affected.
3.6.3.5 Settings
Table 3.6-2 Settings of DPFC distance protection
No.
1
Name
21D.Z_Set
Range
Step
Unit
Remark
(0.000~4Unn)/In
0.001
ohm
3-32
3 Operation Theory
protection
Enabling/disabling
2
21D.En
DPFC
distance
protection
0 or 1
0: disable
1: enable
jX
Load
Load
Load Area
Load Area
R
RLoad
RLoad
Two settings are equipped to exclude the encroachment of the load impedance:
RLoad: the minimum load resistance
Load: the load area angle
These values are common for all zones.
3-33
3 Operation Theory
LoadEnch
LoadEnch.En
LoadEnch.St
LoadEnch.Blk
LoadEnch.On
Input Signal
LoadEnch.En
LoadEnch.Blk
No.
Description
Load trapezoid characteristic enabling input, it is triggered from binary input or
programmable logic etc.
Load trapezoid characteristic blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
Measured impedance into the load area.
If load trapezoid characteristic is enabled and measured impedance into the load
LoadEnch.St
are, LoadEnch.St=1,
If measured impedance is out of the load are or load trapezoid characteristic is
disabled, LoadEnch.St=0
LoadEnch.On
3.6.4.4 Settings
Table 3.6-4 Settings of load encroachment
No.
Name
Range
Step
Unit
Remark
Angle
setting
characteristic,
1
LoadEnch.phi_Blinder
0~45
Deg
of
it
load
should
trapezoid
be
set
(Load_Max),
Load_Max+5 is
recommended.
Resistance setting of load trapezoid
LoadEnch.R_Blinder
(0.05~200)/In
0.01
ohm
characteristic,
it
according
the
to
should
be
minimum
set
load
LoadEnch.En
load
trapezoid
characteristic
0,1
0: disable
1: enable
3-34
3 Operation Theory
EM
IN
EN
I
ZS
ZK
jX
ZZD
ZK
-2ZS/3
Where:
ZZD: the setting of distance protection
ZS: total impedance between local system and protective device location
ZK: measurement impedance
: positive-sequence sensitive angle, i.e. [phi1_Reach]
Phase-to-neutral positive sequence voltage is used as polarized signal for phase-to-ground
distance protection.
For zone 1 and zone 2:
Operation voltage:
Polarized voltage:
3-35
3 Operation Theory
In short line, phase shift 1 could be applied to the polarized voltage to improve the performance
against high resistance fault. The device provides an angle-shift setting, [ZG.phi_Shift], to set
value of 1 among 0, 15and 30. Their impedance shift characteristics towards quadrant 1 are
respectively shown as the impedance circle A, B and C in Figure 3.6-23.
For zone 3:
Operation voltage:
Polarized voltage:
UP uses phase positive-sequence voltage as polarized voltage. For earth fault, positive-sequence
voltage is mainly formed from healthy phases, basically retaining the phase of the
positive-sequence voltage before fault.
Phase comparison equation is:
The operation characteristic is shown in Figure 3.6-18. Operation characteristic of ZK on R-X plane
is a circle with line connecting ends of ZZD and -2ZS/3 as the diameter. The origin is enclosed in the
circle.
2.
ZZD
ZK
-ZS/2
3 Operation Theory
Operation voltage:
Polarized voltage:
Phase shift 2 could be applied to polarized voltage of zones 1 and 2 just like 1 in
phase-to-ground distance element. It is also used for improving performance against high
resistance fault in short line. The device provides an angle-shift setting, [21M.ZP.phi_Shift], to set
value of 2 among 0, 15and 30. Their impedance shift characteristics towards quadrant 1 are
respectively shown as the impedance circle A, B and C in Figure 3.6-23.
For zone 3:
Operation voltage:
Polarized voltage:
Phase-to-phase positive-sequence voltage is applied as the polarized voltage of this element.
Phase comparison equation is:
EN
I
ZK
ZS
3-37
3 Operation Theory
jX
Z'S
ZZD
R
-ZK
Z'S: total impedance between remote system and protective device location
jX
ZZD
ZK
Phase-to-phase distance protection is also used for three-phase short-circuit fault. The operation
characteristic is shown in Figure 3.6-21. Operation characteristic of ZK on R-X plane is a circle with
setting impedance ZZD as the diameter.
3-38
3 Operation Theory
jX
ZZD
ZK
R
Circle C
-ZS
Circle B
Circle A
Where:
ZZD: the setting of distance protection (zone x)
ZS: total impedance between local system and protective device location
ZK: measured impedance
: positive-sequence characteristic angle, i.e. [phi1_Reach]
Circle A: transient characteristic
Circle B: steady-state characteristic shifting towards quadrant
Circle C: steady-state characteristic shifting towards quadrant
As shown in Figure 3.6-22, the characteristic of the distance protection for a three-phase fault on a
system is an impedance circle cross the origin, and there is a voltage dead zone around the origin.
In order to eliminate the dead zone of the distance protection for a close up three-phase fault
memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below.
The transient (during process of memory) operation characteristic is shown as the impedance
circle A in the above figure. The circle takes ZZD and -ZZS as diameter and thus the origin is within
the impedance circle. When three-phase fault happens in reverse direction, its transient
characteristic is shown in Figure 3.6-20, i.e. the distance protection has a clearly defined
directionality and no dead zone during the process of memory.
For zone 1, zone 2 and zone 3 of the phase-to-phase distance protection, if distance protection
operates with memorized polarizing voltage, this means a close up forward fault. When the
memory fades out, the operation characteristic will be reverse offset a little to enclose the origin as
impedance circle B shown in Figure 3.6-22 to ensure keeping operating of distance protection until
the fault being cleared. If distance protection does not operate with memorized polarizing voltage,
3-39
3 Operation Theory
it will be a close up reverse fault. When the memory fades out, the operation characteristic will be
forward offset not to enclose the origin as impedance circle C shown in Figure 3.6-22, and the
distance protection will not mal-operate even if voltage is zero.
The distance protection with such design thoroughly eliminates the dead zone when three-phase
close up fault occurs. It also has favorable directivity and will not operate for a reverse three-phase
fault at busbar.
When receiving manual closing signal or 3-pole reclosing signal, the operation characteristic of
phase to phase distance protection will always enclose the origin of impedance, with no dead zone,
i.e. the reverse offset impedance circle B shown in Figure 3.6-22.
jX
B: 15 C: 30
ZZD
A: 0
D
-ZS
The impedance characteristic of phase-to-ground distance protection is the circle with line
connecting ends of ZZD and -2ZS/3 as the diameter and that of phase-to-phase distance is the
circle with line connecting ends of ZZD and -ZS/2 as the diameter.
In order to prevent the transient overreach caused by the infeed power supply from the remote
end, the zero-sequence reactance line D is added. These measures have enhanced the capacity
against fault resistance when using distance protection in short lines.
3.
Zone 4
ZZDR
F
ZZDF
M
EM
EN
ZK
3-40
3 Operation Theory
jX
ZZDF
ZK
ZZDR
Where:
ZZDF: impedance setting of zone 4 in forward direction, i.e. [21M.Z4.Z_Fwd]
ZZDR: impedance setting of zone 4 in reverse direction, i.e. [21M.Z4.Z_Rev]
: positive-sequence characteristic angle, i.e. [phi1_Reach]
ZK: measurement impedance
When a fault occurs on the rear busbar, reverse distance element is provided to clear it with
definite time delay and is taken as backup protection for reverse busbar fault. Its operation
characteristic is shown in Figure 3.6-24.
3-41
3 Operation Theory
21M.Z1.On
21M.Blk
21M.Z2.On
21M.ZGx.En
21M.Z3.On
21M.ZPx.En
21M.Z4.On
21M.ZGx.Blk
21M.Z1.Op
21M.ZPx.Blk
21M.Z2.Op
21M.Zx.En_ShortDly
21M.Z3.Op
21M.Zx.Blk_ShortDly
21M.Z4.Op
21M.Z1.En_Instant
Input Signal
Description
Distance protection enabling input, it is triggered from binary input or
21M.En
21M.Blk
21M.ZGx.En
21M.ZGx.Blk
21M.ZPx.En
21M.ZPx.Blk
21M.Zx.En_ShortDly
21M.Zx.Blk_ShortDly
21M.Z1.En_Instant
No.
Output Signal
Description
21M.Z1.On
21M.Z2.On
21M.Z3.On
21M.Z4.On
21M.Z1.Op
21M.Z2.Op
3-42
3 Operation Theory
7
21M.Z3.Op
21M.Z4.Op
3.6.5.4 Logic
SIG
21M.En
SIG
VTS.Alm
SIG
21M.Blk
EN
[VTS.En_Out_VT]
&
21M.Enable
>=1
SIG
21M.Enable
SIG
21M.ZG1.En
EN
[21M.ZG1.En]
SIG
21M.ZG1.Blk
SIG
21M.ZP1.En
&
21M.ZG1.Enable
&
&
21M.ZP1.Enable
&
EN
[21M.ZP1.En]
SIG
21M.ZP1.Blk
SIG
21M.Z1.Rls_PSBR
SIG
FD.Pkp
SIG
21M.ZG1.Enable
SIG
Flag.21M.ZG1
SIG
LoadEnch.St (PG)
SET
3I0>[FD.ROC.3I0_Set]
SIG
Flag.21M.ZP1
SIG
LoadEnch.St (PP)
SIG
21M.ZP1.Enable
SIG
FD.Pkp
SIG
21M.Z1.En_Instant
SIG
21M.ZG1.Op
SIG
21M.ZP1.Op
>=1
21M.Z1.On
&
&
[21M.ZG1.t_Op]
&
>=1
21M.ZG1.Op
&
&
>=1
21M.Z1.Flg_PSBR
&
&
[21M.ZP1.t_Op]
&
&
>=1
21M.ZP1.Op
>=1
21M.Z1.Op
3-43
3 Operation Theory
Where:
21M.Z1.Rls_PSBR: Please refer to Figure 3.6-42.
Flag.21M.ZG1 means that measured impedance by zone 1 of phase-to-ground distance
protection is within the range determined by the setting [21M.ZG1.Z_Set].
Flag.21M.ZP1 means that measured impedance by zone 1 of phase-to-phase distance protection
is within the range determined by the setting [21M.ZP1.Z_Set].
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
SIG
21M.Enable
SIG
21M.ZG2.En
EN
[21M.ZG2.En]
SIG
21M.ZG2.Blk
SIG
21M.ZP2.En
&
21M.ZG2.Enable
&
&
21M.ZP2.Enable
&
EN
[21M.ZP2.En]
SIG
21M.ZP2.Blk
SIG
21M.Z2.En_ShortDly
SIG
21M.Z2.Blk_ShortDly
EN
[21M.Z2.En_ShortDly]
SIG
21M.Z2.Enable_ShortDly
SIG
21M.Z2.Rls_PSBR
SIG
FD.Pkp
>=1
21M.Z2.On
&
&
21M.Z2.Enable_ShortDly
&
[21M.ZG2.t_ShortDly]
&
>=1
21M.ZG2.Op
&
SIG
21M.ZG2.Enable
SIG
Flag.21M.ZG2
SIG
LoadEnch.St (PG)
[21M.ZG2.t_Op]
&
>=1
&
SET
3I0>[FD.ROC.3I0_Set]
SIG
Flag.21M.ZP2
SIG
LoadEnch.St (PP)
SIG
21M.ZP2.Enable
21M.Z2.Flg_PSBR
&
&
[21M.ZP2.t_Op]
>=1
&
21M.ZP2.Op
&
[21M.ZP2.t_ShortDly]
SIG
FD.Pkp
SIG
21M.Z2.Enable_ShortDly
SIG
21M.ZG2.Op
SIG
21M.ZP2.Op
>=1
21M.Z2.Op
3 Operation Theory
Where:
21M.Z2.Rls_PSBR: Please refer to Figure 3.6-42.
Flag.21M.ZG2 means that measured impedance by zone 2 of phase-to-ground distance
protection is within the range determined by the setting [21M.ZG2.Z_Set].
Flag.21M.ZP2 means that measured impedance by zone 2 of phase-to-phase distance protection
is within the range determined by the setting [21M.ZP2.Z_Set].
SIG
21M.Enable
SIG
21M.ZG3.En
EN
[21M.ZG3.En]
SIG
21M.ZG3.Blk
SIG
21M.ZP3.En
&
21M.ZG3.Enable
&
&
21M.ZP3.Enable
&
EN
[21M.ZP3.En]
SIG
21M.ZP3.Blk
SIG
21M.Z3.En_ShortDly
SIG
21M.Z3.Blk_ShortDly
EN
[21M.Z3.En_ShortDly]
SIG
21M.Z3.Enable_ShortDly
SIG
21M.Z3.Rls_PSBR
SIG
FD.Pkp
SIG
21M.ZG3.Enable
SIG
Flag.21M.ZG3
SET
3I0>[FD.ROC.3I0_Set]
SIG
LoadEnch.St (PG)
SIG
Flag.21M.ZP3
SIG
LoadEnch.St (PP)
SIG
21M.ZP3.Enable
>=1
21M.Z3.On
&
&
21M.Z3.Enable_ShortDly
&
[21M.ZG3.t_ShortDly]
>=1
21M.ZG3.Op
&
&
[21M.ZG3.t_Op]
&
>=1
21M.Z3.Flg_PSBR
&
&
[21M.ZP3.t_Op]
>=1
&
21M.ZP3.Op
&
[21M.ZP3.t_ShortDly] 0
SIG
FD.Pkp
SIG
21M.Z3.Enable_ShortDly
SIG
21M.ZG3.Op
SIG
21M.ZP3.Op
>=1
21M.Z3.Op
Where:
21M.Z3.Rls_PSBR: Please refer to Figure 3.6-42.
3-45
3 Operation Theory
21M.Enable
SIG
21M.ZG4.En
EN
[21M.ZG4.En]
SIG
21M.Zp4.Blk
SIG
21M.ZP4.En
EN
[21M.ZP4.En]
SIG
21M.ZP4.Blk
SIG
FD.Pkp
SIG
21M.ZG4.Enable
SET
3I0>[FD.ROC.3I0_Set]
SIG
LoadEnch.St (PG)
SIG
Flag.21M.ZG4
SIG
Flag.21M.ZP4
SIG
LoadEnch.St (PP)
SIG
21M.ZP4.Enable
SIG
FD.Pkp
SIG
21M.ZG4.Op
SIG
21M.ZP4.Op
&
21M.ZG4.Enable
&
&
21M.ZP4.Enable
&
>=1
21M.Z4.On
&
&
[21M.ZG4.t_Op]
21M.ZG4.Op
&
>=1
21M.Z4.Flg_PSBR
&
&
[21M.ZP4.t_Op]
21M.ZP4.Op
&
>=1
21M.Z4.Op
Where:
Flag.21M.ZG4 means that measured impedance by zone 4 of phase-to-ground distance
protection is within the range determined by the settings [21M.Z4.Z_Fwd] and [21M.Z4.Z_Rev].
Flag.21M.ZP4 means that measured impedance by zone 4 of phase-to-phase distance protection
is within the range determined by the settings [21M.Z4.Z_Fwd] and [21M.Z4.Z_Rev].
3-46
3 Operation Theory
3.6.5.5 Settings
Table 3.6-6 Settings of distance protection (Mho)
No.
Name
Range
Step
Unit
21M.ZG.phi_Shift
0, 15 or 30
Deg
21M.ZP.phi_Shift
0, 15 or 30
Deg
21M.ZG1.Z_Set
(0.000~4Unn)/In
0.001
ohm
21M.ZG1.t_Op
0.000~10.000
0.001
Remark
Phase
shift
of
21M.ZG1.En
1,
of
shift
of
zone
1,
of
delay
of
zone
of
zone
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-ground
21M.ZG1.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
21M.ZP1.Z_Set
(0.000~4Unn)/In
0.001
ohm
21M.ZP1.t_Op
0.000~10.000
0.001
delay
of
21M.ZP1.En
of
zone
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-phase
21M.ZP1.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
11
21M.ZG2.Z_Set
(0.000~4Unn)/In
0.001
ohm
12
21M.ZG2.t_Op
0.000~10.000
0.001
13
21M.ZG2.t_ShortDly
0.000~10.000
0.001
delay
of
21M.ZG2.En
of
time
delay
of
zone
of
14
zone
zone
of
0 or 1
0: disable
1: enable
3-47
3 Operation Theory
Enabling/disabling
phase-to-ground
21M.ZG2.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
16
21M.ZP2.Z_Set
(0.000~4Unn)/In
0.001
ohm
17
21M.ZP2.t_Op
0.000~10.000
0.001
18
21M.ZP2.t_ShortDly
0.000~10.000
0.001
delay
of
21M.ZP2.En
of
time
delay
of
zone
of
19
zone
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-phase
21M.ZP2.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
Fixed accelerate zone 2 of distance
21
21M.Z2.En_ShortDly
protection
0 or 1
0: disable
1: enable
22
21M.ZG3.Z_Set
(0.000~4Unn)/In
0.001
ohm
23
21M.ZG3.t_Op
0.000~10.000
0.001
24
21M.ZG3.t_ShortDly
0.000~10.000
0.001
delay
of
21M.ZG3.En
of
time
delay
of
zone
of
25
zone
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-ground
21M.ZG3.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
27
21M.ZP3.Z_Set
(0.000~4Unn)/In
0.001
ohm
28
21M.ZP3.t_Op
0.000~10.000
0.001
29
21M.ZP3.t_ShortDly
0.000~10.000
0.001
3-48
delay
of
zone
of
time
delay
of
zone
of
3 Operation Theory
phase-to-phase distance protection
Enabling/disabling
30
21M.ZP3.En
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-phase
21M.ZP3.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
Fixed accelerate zone 3 of distance
32
21M.Z3.En_ShortDly
protection
0 or 1
0: disable
1: enable
33
21M.Z4.Z_Fwd
(0.000~4Unn)/In
0.001
ohm
34
21M.Z4.Z_Rev
(0.000~4Unn)/In
0.001
ohm
35
21M.Z4.t_Op
0.000~10.000
0.001
36
21M.ZG4.En
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-ground
21M.ZG4.En_BlkAR
0 or 1
value is 1)
0: disable
1: enable
Enabling/disabling
38
21M.ZP4.En
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-phase
21M.ZP4.En_BlkAR
0 or 1
value is 1)
0: disable
1: enable
3-49
3 Operation Theory
Zone 1, 2 and 3
Quadrilateral forward distance element characteristic for zone 1, 2 and 3 is shown as follows:
jX
A
ZZD
RZD
C
Where:
ZZD: impedance setting in forward direction
RZD: resistance setting in forward direction
: line positive-sequence characteristic angle
: the angle of directional line in the second quadrant, fixed at 15
: the angle of directional line in the fourth quadrant, fixed at 15
: downward offset angle of the reactance line AB
2.
Zone 4
When a fault occurs on the busbar at the back, reverse distance element zone 4 is provided to
clear it with definite time delay and is used as backup protection for reverse busbar fault.
3-50
3 Operation Theory
jX
C
RZD
ZZD
Where:
ZZD: impedance setting in reverse direction
RZD: resistance setting in reverse direction
: positive-sequence characteristic angle,
: the angle of directional line, fixed at 15
: the angle of directional line, fixed at 15
: downward offset angle of the reactance line AB
For quadrilateral distance protection, the reactance line should consider downward offset angle
as shown in Figure 3.6-30 and Figure 3.6-31. According to system status, the downward offset
angle can be independently set for phase-to-ground distance element and phase-to-phase
distance element. The downward offset angle of all zones can be settable by the corresponding
settings [21Q.ZGx.RCA] and [21Q.ZPx.RCA]. (x=1, 2, 3, 4)
3-51
3 Operation Theory
21Q.Z1.On
21Q.Blk
21Q.Z2.On
21Q.ZGx.En
21Q.Z3.On
21Q.ZPx.En
21Q.Z4.On
21Q.ZGx.Blk
21Q.Z1.Op
21Q.ZPx.Blk
21Q.Z2.Op
21Q.Zx.En_ShortDly
21Q.Z3.Op
21Q.Zx.Blk_ShortDly
21Q.Z4.Op
21Q.Z1.En_Instant
Input Signal
Description
Distance protection enabling input, it is triggered from binary input or
21Q.En
21Q.Blk
21Q.ZGx.En
21Q.ZGx.Blk
21Q.ZPx.En
21Q.ZPx.Blk
21Q.Zx.En_ShortDly
21Q.Zx.Blk_ShortDly
21Q.Z1.En_Instant
No.
Output Signal
Description
21Q.Z1.On
21Q.Z2.On
21Q.Z3.On
21Q.Z4.On
21Q.Z1.Op
21Q.Z2.Op
3-52
3 Operation Theory
7
21Q.Z3.Op
21Q.Z4.Op
3.6.6.4 Logic
SIG
21Q.En
SIG
21Q.Blk
SIG
VTS.Alm
EN
[VTS.En_Out_VT]
&
21Q.Enable
>=1
21Q.Enable
EN
[21Q.ZG1.En]
SIG
21Q.ZG1.En
SIG
21Q.ZG1.Blk
EN
[21Q.ZP1.En]
&
>=1
21Q.ZG1.Enable
&
21Q.Z1.On
&
21Q.ZP1.Enable
&
SIG
21Q.ZP1.En
SIG
21Q.ZP1.Blk
SIG
FD.Pkp
SIG
21Q.ZG1.Enable
SIG
LoadEnch.St (PG)
SET
3I0>[FD.ROC.3I0_Set]
SIG
Flag.21Q.ZG1
SIG
21Q.Z1.Rls_PSBR
SIG
FD.Pkp
&
&
&
&
[21Q.ZG1.t_Op]
>=1
21Q.ZG1.Op
&
>=1
&
SIG
21Q.ZP1.Enable
SIG
LoadEnch.St (PP)
SIG
Flag.21Q.ZP1
21Q.Z1.Flg_PSBR
&
&
[21Q.ZP1.t_Op]
>=1
&
SIG
21Q.Z1.En_Instant
SIG
21Q.ZG1.Op
SIG
21Q.ZP1.Op
21Q.ZP1.Op
>=1
21Q.Z1.Op
Where:
21Q.Z1.Rls_PSBR: Please refer to Figure 3.6-42.
3-53
3 Operation Theory
21Q.Enable
EN
[21Q.ZG2.En]
SIG
21Q.ZG2.En
SIG
21Q.ZG2.Blk
EN
[21Q.ZP2.En]
&
>=1
21Q.ZG2.Enable
&
21Q.Z2.On
&
21Q.ZP2.Enable
&
SIG
21Q.ZP2.En
SIG
21Q.ZP2.Blk
SIG
21Q.Z2.En_ShortDly
SIG
21Q.Z2.Blk_ShortDly
EN
[21Q.Z2.En_ShortDly]
SIG
21Q.Z2.Enable_ShortDly
SIG
FD.Pkp
SIG
21Q.ZG2.Enable
&
&
21Q.Z2.Enable_ShortDly
&
&
SET
&
3I0>[FD.ROC.3I0_Set]
SIG
LoadEnch.St (PG)
SIG
Flag.21Q.ZG2
SIG
21Q.Z2.Rls_PSBR
SIG
21Q.ZP2.Enable
SIG
LoadEnch.St (PP)
SIG
Flag.21Q.ZP2
SIG
21Q.ZG2.Op
SIG
21Q.ZP2.Op
[21Q.ZG2.t_ShortDly] 0
&
>=1
21Q.ZG2.Op
&
[21Q.ZG2.t_Op]
>=1
21Q.Z2.Flg_PSBR
&
&
[21Q.ZP2.t_ShortDly] 0
&
>=1
21Q.ZP2.Op
[21Q.ZP2.t_Op]
>=1
21Q.Z2.Op
Where:
21Q.Z2.Rls_PSBR: Please refer to Figure 3.6-42.
Flag.21Q.ZG2 means that measured impedance by zone 2 of phase-to-ground distance protection
is within the range determined by the settings [21Q.ZG2.Z_Set] and [21Q.ZG2.R_Set].
3-54
3 Operation Theory
21Q.Enable
EN
[21Q.ZG3.En]
SIG
21Q.ZG3.En
SIG
21Q.ZG3.Blk
EN
[21Q.ZP3.En]
&
>=1
21Q.ZG3.Enable
&
21Q.Z3.On
&
21Q.ZP3.Enable
&
SIG
21Q.ZP3.En
SIG
21Q.ZP3.Blk
SIG
21Q.Z3.En_ShortDly
SIG
21Q.Z3.Blk_ShortDly
EN
[21Q.Z3.En_ShortDly]
SIG
21Q.Z3.Enable_ShortDly
SIG
FD.Pkp
SIG
21Q.ZG3.Enable
SET
3I0>[FD.ROC.3I0_Set]
SIG
LoadEnch.St (PG)
SIG
Flag.21Q.ZG3
SIG
21Q.Z3.Rls_PSBR
SIG
FD.Pkp
&
&
21Q.Z3.Enable_ShortDly
&
&
&
&
[21Q.ZG3.t_ShortDly] 0
&
>=1
21Q.ZG3.Op
[21Q.ZG3.t_Op]
SIG
21Q.ZP3.Enable
SIG
LoadEnch.St (PP)
SIG
Flag.21Q.ZP3
SIG
21Q.ZG3.Op
SIG
21Q.ZP3.Op
>=1
&
21Q.Z3.Flg_PSBR
&
&
[21Q.ZP3.t_ShortDly] 0
&
>=1
21Q.ZP3.Op
[21Q.ZP3.t_Op]
>=1
21Q.Z3.Op
Where:
21Q.Z3.Rls_PSBR: Please refer to Figure 3.6-42.
Flag.21Q.ZG3 means that measured impedance by zone 3 of phase-to-ground distance protection
is within the range determined by the settings [21Q.ZG3.Z_Set] and [21Q.ZG3.R_Set].
Flag.21Q.ZP3 means that measured impedance by zone 3 of phase-to-phase distance protection
is within the range determined by the settings [21Q.ZP3.Z_Set] and [21Q.ZP3.R_Set].
3-55
3 Operation Theory
SIG
21Q.Enable
EN
[21Q.ZG4.En]
SIG
21Q.ZG4.En
SIG
21Q.ZG4.Blk
EN
[21Q.ZP4.En]
&
>=1
21Q.ZG4.Enable
&
21Q.Z4.On
&
21Q.ZP4.Enable
&
SIG
21Q.ZP4.En
SIG
21Q.ZP4.Blk
SIG
FD.Pkp
SIG
21Q.ZG4.Enable
SET
3I0>[FD.ROC.3I0_Set]
SIG
LoadEnch.St (PG)
SIG
Flag.21Q.ZG4
SIG
FD.Pkp
SIG
21Q.ZP4.Enable
SIG
LoadEnch.St (PP)
SIG
Flag.21Q.ZP4
SIG
21Q.ZG4.Op
SIG
21Q.ZP4.Op
&
&
[21Q.ZG4.t_Op]
21Q.ZG4.Op
&
>=1
21Q.Z4.Flg_PSBR
&
[21Q.ZP4.t_Op]
21Q.ZP4.Op
&
>=1
21Q.Z4.Op
Where:
Flag.21Q.ZG4 means that measured impedance by zone 4 of phase-to-ground distance protection
is within the range determined by the settings [21Q.ZG4.Z_Set] and [21Q.ZG4.R_Set].
Flag.21Q.ZP4 means that measured impedance by zone 4 of phase-to-phase distance protection
is within the range determined by the settings [21Q.ZP4.Z_Set] and [21Q.ZP4.R_Set].
3.6.6.5 Settings
Table 3.6-8 Settings of distance protection (Quad)
No.
Name
Range
Step
Unit
Remark
Downward
21Q.ZG1.RCA
0~45
Deg
reactance
offset
line
angle
for
zone
of
the
1
of
21Q.ZG1.Z_Set
(0.000~4Unn)/In
0.001
ohm
3-56
3 Operation Theory
3
21Q.ZG1.R_Set
(0.000~4Unn)/In
0.001
ohm
21Q.ZG1.t_Op
0.000~10.000
0.001
delay
of
21Q.ZG1.En
zone
of
of
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-ground
21Q.ZG1.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
Downward
21Q.ZP1. RCA
0~45
Deg
reactance
offset
line
angle
for
of
zone
the
1
of
21Q.ZP1.Z_Set
(0.000~4Unn)/In
0.001
ohm
21Q.ZP1.R_Set
(0.000~4Unn)/In
0.001
ohm
21Q.ZP1.t_Op
0.000~10.000
0.001
10
delay
of
21Q.ZP1.En
zone
of
11
of
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-phase
21Q.ZP1.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
Downward
13
21Q.ZG2.RCA
0~45
Deg
reactance
offset
line
angle
for
of
zone
the
2
of
21Q.ZG2.Z_Set
(0.000~4Unn)/In
0.001
ohm
15
21Q.ZG2.R_Set
(0.000~4Unn)/In
0.001
ohm
16
21Q.ZG2.t_Op
0.000~10.000
0.001
17
21Q.ZG2.t_ShortDly
0.000~10.000
0.001
18
21Q.ZG2.En
0 or 1
of
of
delay
of
zone
of
time
delay
of
zone
of
zone
of
3 Operation Theory
0: disable
1: enable
Enabling/disabling
phase-to-ground
21Q.ZG2.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
Downward
20
21Q.ZP2. RCA
0~45
Deg
reactance
offset
line
angle
for
of
zone
the
2
of
21Q.ZP2.Z_Set
(0.000~4Unn)/In
0.001
ohm
22
21Q.ZP2.R_Set
(0.000~4Unn)/In
0.001
ohm
23
21Q.ZP2.t_Op
0.000~10.000
0.001
24
21Q.ZP2.t_ShortDly
0.000~10.000
0.001
delay
of
21Q.ZP2.En
zone
of
25
of
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-phase
21Q.ZP2.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
Fixed accelerate zone 2 of distance
27
21Q.Z2. En_ShortDly
protection
0 or 1
0: disable
1: enable
Downward
28
21Q.ZG3.RCA
0~45
Deg
reactance
offset
line
angle
for
of
zone
the
3
of
21Q.ZG3.Z_Set
(0.000~4Unn)/In
0.001
ohm
30
21Q.ZG3.R_Set
(0.000~4Unn)/In
0.001
ohm
31
21Q.ZG3.t_Op
0.000~10.000
0.001
32
21Q.ZG3.t_ShortDly
0.000~10.000
0.001
33
21Q.ZG3.En
0 or 1
of
delay
of
zone
of
time
delay
of
zone
of
zone
of
3-58
3 Operation Theory
0: disable
1: enable
Enabling/disabling
phase-to-ground
21Q.ZG3.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
Downward
35
21Q.ZP3. RCA
0~45
Deg
reactance
offset
line
angle
for
of
zone
the
3
of
21Q.ZP3.Z_Set
(0.000~4Unn)/In
0.001
ohm
37
21Q.ZP3.R_Set
(0.000~4Unn)/In
0.001
ohm
38
21Q.ZP3.t_Op
0.000~10.000
0.001
39
21Q.ZP3.t_ShortDly
0.000~10.000
0.001
delay
of
21Q.ZP3.En
zone
of
time
delay
of
zone
of
40
of
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-phase
21Q.ZP3.En_BlkAR
0 or 1
to block AR
0: disable
1: enable
Fixed accelerate zone 3 of distance
42
21Q.Z3. En_ShortDly
protection
0 or 1
0: disable
1: enable
Downward
43
21Q.ZG4.RCA
0~45
Deg
reactance
offset
line
angle
for
zone
of
the
4
of
21Q.ZG4.Z_Set
(0.000~4Unn)/In
0.001
ohm
45
21Q.ZG4.R_Set
(0.000~4Unn)/In
0.001
ohm
46
21Q.ZG4.t_Op
0.000~10.000
0.001
delay
of
21Q.ZG4.En
zone
of
47
of
zone
of
0 or 1
0: disable
1: enable
3-59
3 Operation Theory
Enabling/disabling
phase-to-ground
21Q.ZG4.En_BlkAR
0 or 1
value is 1)
0: disable
1: enable
Downward
49
21Q.ZP4. RCA
0~45
Deg
reactance
offset
line
angle
for
of
zone
the
4
of
21Q.ZP4.Z_Set
(0.000~4Unn)/In
0.001
ohm
51
21Q.ZP4.R_Set
(0.000~4Unn)/In
0.001
ohm
52
21Q.ZP4.t_Op
0.000~10.000
0.001
delay
of
21Q.ZP4.En
zone
of
53
of
zone
of
0 or 1
0: disable
1: enable
Enabling/disabling
phase-to-phase
21Q.ZP4.En_BlkAR
0 or 1
value is 1)
0: disable
1: enable
Pilot.Z_Set_B
M
EM
Pilot.Z_Rev_A
Pilot.Z_Set_A
The operation characteristic of pilot zone is same as that of zone 2, including mho and
quadrilateral characteristic.
3-60
3 Operation Theory
When an internal fault occurs, distance protection at weak source end may not operate due to
small fault current. Thus, a reverse distance element is provided to coordinate with the
independent pilot distance protection to implement weak infeed logic, ensure pilot distance
protection can operate to send signal or trip in the weak end. The operation characteristic is shown
in Figure 3.6-38. The reverse weak infeed distance element is forward offset with 1/4 of the
reverse setting to enclose the origin.
Operation characteristics of pilot reverse weak infeed element distance are shown as below.
jX
jX
21Q.Z_Rev/4
21M.Z_Rev/4
21Q.R_Rev
21M.Z_Rev
21Q.Z_Rev
Where:
: positive-sequence characteristic angle, i.e. [phi1_Reach]
: the angle of directional line, fixed at 15
: the angle of directional line, fixed at 15
: tilted angle of the reactance line AC, fixed at 12
3.6.7.2 Logic
SIG
FD.Pkp
SIG
21M.Enable
SIG
21M.Pilot.Rls_PSBR
SET
Flag.21M.Pilot.Z (PG)
SIG
LoadEnch.St (PG)
SET
Flag.21M.Pilot.Z (PP)
SIG
LoadEnch.St (PP)
&
&
&
ZPilotP
&
>=1
21M.Zpilot.Flag_PSBR
&
3 Operation Theory
SIG
FD.Pkp
SIG
21Q.Enable
SIG
21Q.Pilot.Rls_PSBR
SET
Flag.21Q.Pilot.Z (PG)
SIG
LoadEnch.St (PG)
SET
Flag.21Q.Pilot.Z (PP)
SIG
LoadEnch.St (PP)
&
&
&
ZPilotP
&
>=1
21Q.Zpilot.Flag_PSBR
&
Where:
21M.Pilot.Rls_PSBR, 21Q.Pilot.Rls_PSBR: Please refer to Figure 3.6-42.
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
Flag.21Q.Pilot.Z (PG) means that measured impedance by phase-to-ground distance element is
within the range determined by the setting [21Q.Pilot.Z_Set]. (Quad characteristic)
Flag.21Q.Pilot.Z (PP) means that measured impedance by phase-to-phase distance element is
within the range determined by the setting [21Q.Pilot.Z_Set]. (Quad characteristic)
Flag.21M.Pilot.Z (PG) means that measured impedance by phase-to-ground distance element is
within the range determined by the setting [21M.Pilot.Z_Set]. (Mho characteristic)
Flag.21M.Pilot.Z (PP) means that measured impedance by phase-to-phase distance element is
within the range determined by the setting [21M.Pilot.Z_Set]. (Mho characteristic)
3.6.7.3 Settings
Table 3.6-9 Settings of pilot distance zone
No.
Name
Range
Step
Unit
21M.Pilot.Z_Set
(0.000~4Unn)/In
0.001
ohm
21Q.Pilot.Z_Set
(0.000~4Unn)/In
0.001
ohm
Remark
Impedance
21M.Pilot.Z_Rev
(0.000~4Unn)/In
0.001
ohm
of
pilot
distance
setting
of
pilot
distance
setting
protection
setting
in
of
reverse
pilot
distance
direction
(Mho
characteristic)
4
21Q.Pilot.Z_Rev
(0.000~4Unn)/In
0.001
ohm
3-62
Impedance
setting
of
pilot
distance
3 Operation Theory
characteristic)
5
21Q.Pilot.R_Set
(0.000~4Unn)/In
0.001
ohm
Impedance
21Q.Pilot.R_Rev
(0.000~4Unn)/In
0.001
ohm
of
pilot
distance
setting
setting
of
pilot
distance
68.St
68.Blk
Input Signal
Description
Power swing detection enabling input, it is triggered from binary input or
68.En
68.Blk
21.St
FD.ROC.Pkp
52b
52a
No.
1
Output Signal
68.St
Description
Power swing detection takes into effect.
3-63
3 Operation Theory
3.6.8.3 Logic
EN
[68.En]
SIG
68.En
SIG
68.Blk
SIG
I1>[Y.I_PSBR]
SIG
21.St
SIG
FD.ROC.Pkp
SIG
3 CB Closed
SIG
3 CB open
SIG
Unblocking for SF
SIG
Unblocking for UF
&
&
&
&
&
t1
t2
&
68.St
&
>=1
>=1
Y: 21M or 21Q
3.6.8.4 Settings
Table 3.6-11 Settings of power swing detection
No.
Name
Range
Step
Unit
Remark
Enabling/disabling power swing detection
68.En
0 or 1
0: disable
1: enable
3-64
3 Operation Theory
1.
If any of the following condition is matched, FD PSBR will operate for 160ms.
1)
Positive sequence current is lower than the setting [I_PSBR] before general fault detector
element operates.
2)
Positive sequence current is higher than the setting [I_PSBR] before general fault detector
element operates, but the duration is less than 10ms.
As shown in figure below, assume normal load impedance locates at position 1, and the
impedance under current I_PSBR locates at position 2, if the condition for FD PSBR mentioned
above operates, it means FD operates between point 1, point 2 and point 3 as example, then FD
PSBR will operate for 160ms.
[I_PSBR]
FD
Normal load
impedance
Point 1
Point 3
Point 2
2.
3 Operation Theory
If a three-phase fault occurs and FD PSBR is invalid (160ms after FD operates), neither FD PSBR
nor UF PSBR will be able to release the distance protection. Thus, SF PSBR is provided for this
case specially. This detection is based on measuring the voltage at power swing center, during
power swing, U1cos will constantly change periodically.
UOS=U1COS
Where:
: the angle between positive sequence voltage and current
U1: the positive sequence voltage
As shown in the figure below, assume system connection impedance angle of 90, current vector
will be perpendicular to the line connecting EM and EN, and have the same phase as power swing
center voltage. During normal operation of system or power swing, U1cos just reflects
positive-sequence voltage of power swing center. In case of 3-phase short circuit, U1cos is
voltage drop on arc resistor, transition resistance is arc resistance, and voltage drop on arc resistor
is less than 5%UN. In actual system, line impedance angle is not 90. Through compensation of
angle , power swing center voltage can be measured accurately. After compensation, power
swing center voltage is U1cos(90oL), where L is line impedance angle.
EM
EN
UOS
During power swing, power swing center voltage U1cos has the following characteristics: When
3-66
3 Operation Theory
electric potential phase angle difference between power supplies at two sides is 180o, U1cos0
and change rate dU1cos/dt is the maximum. When this phase angle difference is near 0o, power
swing center voltage change rate dU1cos/dt is the minimum. During short circuit, U1cos
remains unchanged and dU1cos/dt0. However, in early stage of short circuit when normal state
enters short circuit state, dU1cos/dt is very large. Therefore, use of dU1cos/dt solely to
differentiate power swing and short circuit is not complete.
For these reasons, the method to release distance protection on condition that power swing center
voltage U1cos is less than a setting and after a short delay can be used as symmetric fault
discriminating element. This element can accurately differentiate power swing and 3-phase short
circuit fault, and constitute a complete power swing blocking scheme with other elements. The
element to open distance protection if U1cos is less than a certain setting and after a delay is
easy to realize and has short delay, and can trip fault more quickly and accurately trip 3-phase
short circuit fault during power swing.
The criterion of SF PSBR element comprises the following two parts:
The second criterion is a backup of the first criterion allowing longer monitoring period of voltage
variation.
To reduce the time delay for SF PSBR element during power swing, the change rate of voltage at
power swing center is also used which can release SF PSBR element quickly for the fault occurred
during power swing. The typical release time is less than 60ms.
3.6.9.1 Function Block Diagram
21M
21M.En_PSBR
21M.Z1.Rls_PSBR
21M.Blk_PSBR
21M.Z2.Rls_PSBR
21M.Z3.Rls_PSBR
21M.Pilot.Rls_PSBR
21Q
21Q.En_PSBR
21Q.Z1.Rls_PSBR
21Q.Blk_PSBR
21Q.Z2.Rls_PSBR
21Q.Z3.Rls_PSBR
21Q.Pilot.Rls_PSBR
3-67
3 Operation Theory
Input Signal
Description
21M.En_PSBR
21Q.En_PSBR
21M.Blk_PSBR
21Q.Blk_PSBR
No.
Output Signal
Description
21M.Z1.Rls_PSBR
21Q.Z1.Rls_PSBR
21M.Z2.Rls_PSBR
21Q.Z2.Rls_PSBR
21M.Z3.Rls_PSBR
21Q.Z3.Rls_PSBR
21M.Pilot.Rls_PSBR
21Q.Pilot.Rls_PSBR
3.6.9.3 Logic
SIG
Y.En_PSBR
SIG
Y.Blk_PSBR
SIG
FD.Pkp
SIG
Y.Enable_PSBR
EN
[Y.Zx .En_PSBR]
SIG
symmetrical |U1cos|<
&
Y.Enable_PSBR
&
>=1
t
0ms
>=1
Unblocking for SF
&
Y.Zx.Rls_PSBR
Unblocking for UF
>=1
SIG
Unsymmetrical |I0|+|I2|>
SIG
Y.Zx.Flg_PSBR
SET
I1>[Y.I_PSBR]
&
10ms
0ms
&
&
0
SIG
FD.Pkp
SIG
Y.Zx.Flg_PSBR
160ms
>=1
Y: 21M or 21Q
x: 1, 2, 3 or pilot
3-68
3 Operation Theory
Y.Zx.Flg_PSBR: Please refer to Figure 3.6-26~Figure 3.6-29, Figure 3.6-33~Figure 3.6-36, Figure
3.6-40 and Figure 3.6-39.
3.6.9.4 Settings
Table 3.6-13 Settings of PSBR
No.
Name
Range
Step
Unit
Remark
Enabling/disabling zone 1 of distance
protection controlled by PSBR (Mho
21M.Z1.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
Enabling/disabling zone 1 of distance
protection controlled by PSBR (Quad
21Q.Z1.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
Enabling/disabling zone 2 of distance
protection controlled by PSBR (Mho
21M.Z2.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
Enabling/disabling zone 2 of distance
protection controlled by PSBR (Quad
21Q.Z2.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
Enabling/disabling zone 3 of distance
protection controlled by PSBR (Mho
21M.Z3.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
Enabling/disabling zone 3 of distance
protection controlled by PSBR (Quad
21Q.Z3.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
Enabling/disabling
pilot
distance
21M.Pilot.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
21Q.Pilot.En_PSBR
Enabling/disabling
0 or 1
pilot
distance
3 Operation Theory
characteristic)
0: disable
1: enable
9
21M.I_PSBR
(0.050~30.000)In
0.001
10
21Q.I_PSBR
(0.050~30.000)In
0.001
21SOTF.On
21SOTF.Blk
21SOTF.Op
21SOTF.Op_PDF
Input Signal
21SOTF.En
21SOTF.Blk
No.
Description
Distance SOTF protection enabling input, it is triggered from binary input or
programmable logic etc.
Distance SOTF protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
21SOTF.Op
21SOTF.Op_PDF
21SOTF.On
Description
Accelerate distance protection to trip when manual closing or auto-reclosing to
fault
Accelerate distance protection to trip when another fault happened under pole
discrepancy conditions
Accelerate distance protection is enabled.
3-70
3 Operation Theory
3.6.10.3 Logic
SIG
21SOTF.En
SIG
21SOTF.Blk
EN
[21SOTF.En]
&
&
21SOTF.On
Distance SOTF protection can be enabled or disabled, and can be initiated by several cases,
including manual closing signal, 3-pole reclosing, 1-pole reclosing and pole discrepancy
conditions.
BI
[52b_PhA]
BI
[52b_PhB]
BI
[52b_PhC]
>=1
&
SIG
FD.Pkp
EN
[SOTF.Opt_Mode_ManCls]=1 or 2
EN
[SOTF.Opt_Mode_ManCls]=0 or 2
BI
ManCls
EN
[21SOTF.En_ManCls]
EN
[21SOTF.Z2.En_ManCls]
SIG
Y.Z2.Flg_PSBR
EN
[21SOTF.Z3.En_ManCls]
SIG
Y.Z3.Flg_PSBR
EN
[21SOTF.Z4.En_ManCls]
SIG
Y.Z4.Flg_PSBR
SIG
21SOTF.On
SIG
FD.Pkp
>=1
0
400ms
&
&
&
[21SOTF.t_ManCls] 0
&
&
21SOTF.Op
>=1
&
&
Figure 3.6-44 Logic diagram of distance SOTF protection by manual closing signal
When the circuit breaker is in open position while the device does not pick up, or external manual
closing binary input is energized, then manual closing signal will be kept for 400ms, which will
enable SOTF logic only for 400ms.
3-71
3 Operation Theory
SIG
FD.Pkp
SIG
21SOTF.On
EN
[21SOTF.En_3PAR]
SIG
EN
[21SOTF.Z2.En_3PAR]
SIG
Y.Z2.Flg_PSBR
EN
[21SOTF.Z2.En_PSBR]
SIG
Y.Z2.Rls_PSBR
EN
[21SOTF.Z3.En_3PAR]
&
SIG
Y.Z3.Flg_PSBR
EN
[21SOTF.Z3.En_PSBR]
SIG
Y.Z3.Rls_PSBR
EN
[21SOTF.Z4.En_3PAR]
SIG
Y.Z4.Flg_PSBR
EN
[21SOTF.Z4.En_PSBR]
SIG
Y.Z4.Rls_PSBR
EN
[21SOTF.En_1PAR]
SIG
PD signal
SIG
Y.Z2.Rls_PSBR
&
&
>=1
&
&
&
[21SOTF.t_3PAR]
&
>=1
>=1
21SOTF.Op
>=1
&
&
>=1
&
&
[21SOTF.t_1PAR]
&
For single-phase permanent fault, distance SOTF protection for 1-pole reclosing onto the faulty
phase will trip three-phase circuit breaker.
3-72
3 Operation Theory
SIG
21SOTF.On
SIG
FD.Pkp
EN
[21SOTF.En_PDF]
SIG
Y.Z2.Rls_PSBR (Phase A)
SIG
PD signal (Phase A
SIG
PD signal (Phase B or C
SIG
Y.Z2.Rls_PSBR (Phase B)
SIG
PD signal (Phase B
SIG
PD signal (Phase A or C
SIG
Y.Z2.Rls_PSBR (Phase C)
SIG
PD signal (Phase C
SIG
PD signal (Phase A or B
&
&
[21SOTF.t_PDF]
21SOTF.Op_PDF
&
&
>=1
&
Under pole discrepancy condition after single-phase tripping, distance SOTF protection will
accelerate to operate if another fault happens to the healthy phase.
Y: 21M or 21Q
3.6.10.4 Settings
Table 3.6-15 Settings of distance SOTF protection
No.
Name
Range
Step
Unit
Remark
Enabling/disabling distance SOTF
21SOTF.En
protection
0 or 1
0: disable
1: enable
Enabling/disabling
distance
21SOTF.Z2.En_ManCls
0 or 1
SOTF
zone
of
protection
for
manual closing
1: enable
0: disable
Enabling/disabling
distance
21SOTF.Z3.En_ManCls
0 or 1
SOTF
zone
of
protection
for
manual closing
1: enable
0: disable
Enabling/disabling
21SOTF.Z4.En_ManCls
0 or 1
distance
SOTF
zone
of
protection
for
manual closing
3-73
3 Operation Theory
1: enable
0: disable
Enabling/disabling
distance
5
21SOTF.Z2.En_3PAR
0 or 1
SOTF
zone
of
protection
for
3-pole reclosing
1: enable
0: disable
Enabling/disabling
distance
21SOTF.Z3.En_3PAR
0 or 1
SOTF
zone
of
protection
for
3-pole reclosing
1: enable
0: disable
Enabling/disabling
distance
21SOTF.Z4.En_3PAR
0 or 1
SOTF
of
protection
zone
for
3-pole reclosing
1: enable
0: disable
Enabling/disabling
zone
21SOTF.Z2.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing
1: enable
0: disable
Enabling/disabling
zone
21SOTF.Z3.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing
1: enable
0: disable
Enabling/disabling
zone
21SOTF.Z4.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing
1: enable
0: disable
Enabling/disabling distance SOTF
protection under pole discrepancy
11
21SOTF.En_PDF
0 or 1
conditions
1: enable
0: disable
Time delay of distance protection
12
21SOTF.t_PDF
0.000~10.000
0.001
13
SOTF.Opt_Mode_ManCls
0, 1 or 2
3-74
3 Operation Theory
0: initiated by input signal of
manual closing
1: initiated by CB position
2: initiated by either input signal of
manual closing or CB position
Table 3.6-16 Internal settings of distance SOTF protection
No.
Name
Default Value
Unit
Remark
Enabling/disabling distance SOTF protection for
21SOTF.En_ManCls
manual closing
0: disable
1: enable
21SOTF.t_ManCls
0.025
21SOTF.En_3PAR
3-pole reclosing
0: disable
1: enable
21SOTF.t_3PAR
0.025
21SOTF.En_1PAR
1-pole reclosing
0: disable
1: enable
21SOTF.t_1PAR
0.025
3 Operation Theory
PCS-902
TX
RX
RX
TX
PCS-902
ST connectors
ST connectors
PCS-902
TX
RX
RX
TX
FC connectors
PCS-902
FC connectors
Figure 3.7-2 Direct optical link up to 40km with 1310nm or up to 100km with 1550nm
Channel of 64kbits/s or 2048kbits/s via multiplexer is shown in Figure 3.7-3, Figure 3.7-4 and
Figure 3.7-5.
C37.94 (N*64kbits/s)
Multi-mode FO
Communication convertor
TX
RX
RX
TX
PCS-902
ST connectors
Interface
Link to
communicate
device
ST connectors
3 Operation Theory
G.703 (64kbits/s)
MUX-64
Single-mode FO
TX
RX
RX
TX
Interface
Link to
communicate
device
PCS-902
FC connectors
FC connectors
G.703-E1 (2048kbits/s)
MUX-2M
Single-mode FO
TX
RX
RX
TX
Interface
PCS-902
FC connectors
Link to
communicate
device
FC connectors
Master-master mode
Slave-slave mode
Master-slave mode
3-77
3 Operation Theory
One of them uses internal clock, the other uses external clock
The logic setting [FOx.En_IntClock] is used in pilot scheme protection to select the communication
clock. The internal clock is enabled automatically when the logic setting [FOx.En_IntClock] is set
as 1. Contrarily, the external clock is enabled automatically when the logic setting
[FOx.En_IntClock] is set to 0.
If the device uses multiplex PCM channel, logic setting [FOx.En_IntClock] at both ends should be
set as 0 (Mode 2). If the device uses dedicated optical fibre channel, clock Mode 1 and Mode 3
can be used. Mode 1 is recommended in considering simplification to user, i.e. logic setting
[FOx.En_IntClock] at both ends should be set as 1.
3.7.2.3 Identity Code
In order to ensure reliability of the device when digital communication channel is applied, settings
[FO.LocID] and [FO.RmtID] are provided as identity code to distinguish uniquely the device at
remote end using same channel.
Under normal conditions, the identity code of the device at local end should be different with that at
remote end. In addition, it is recommended that the identity code of all devices, i.e., the setting
[FO.LocID], should be unique in the power grid. The setting range is from 0 to 65535. Only for loop
test, they are set as the same.
The setting [FO.LocID] of the device at an end should be the same as the setting [FO.RmtID] of
the device at opposite end and the greater [FO.LocID] between the two ends is chosen as a
master end for sampling synchronism, the smaller [FO.LocID] is slave end. If the setting [FO.LocID]
is set the same as [FO.RmtID], that implies the device in loopback testing state.
The setting [FO.LocID] is packaged in the message frame and transmitted to the remote end.
When the [FO.LocID] of the device at remote end is received by local device is same to the setting
[FO.RmtID] of local device, the message received from the remote end is valid, and protection
information involved in message is read. When these settings are not matched, the message is
considered as invalid and protection information involved in message is ignored, corresponding
alarms will be issued.
3.7.2.4 Channel Statistics
The device has the function of on-line channel monitoring and channel statistics. It can produce
channel statistic report automatically at 9:00 every day and the report can be printed for operator
to check the channel quality. The monitoring contents of channel status are shown as follows, and
they can be viewed by the menu Main MenuTestProt Ch CountChx Counter.
1.
It shows the starting time of the channel status statistics of the device at local end.
2.
3-78
3 Operation Theory
It shows the calculated communication channel time delay of the device at local end now (unit: us).
The calculation is based on the assumption of same channel path for to and from remote end. The
device measures propagation delay of communication channel based on the below principle.
Side S transmits a frame of message to side M, and meanwhile records the transmitting time tss
on the basis of clock on side S. When side M receives the message, it will record receiving time
tmr of the message with its own clock, and return a frame of message to side S at next fixed
transmitting time, meanwhile data of tms-tmr is included in the frame of message. Side S will
receive the message from side M at the time tsr and obtain the data of tms-tmr.
Therefore, the propagation delay of the channel Td is obtained through calculation:
Td
(t sr t ss ) (t ms t mr )
2
By using the above calculated Td, the device automatically compensate time synchronization of
sampling data at each end and transimission time lag.
T1
tss
tsr
tmr
Td
tms
"S"
"M"
T2
4.
It shows the total number of the error frames of the device at local end from starting time of
channel statistics until now. Error frame means that this frame fails in CRC check.
5.
It shows the total number of abnormal messages of the device at local end from starting time of
channel statistics until now.
6.
It shows the total number of the lost frames of the device at local end from starting time of channel
statistics until now.
7.
FOx.N_RmtAbnor (total number of abnormal messages from the remote end of channel x)
3-79
3 Operation Theory
It shows the total number of abnormal messages received from the remote end from starting time
of channel statistics until now.
8.
It shows the total number of serious error frame seconds of the device at local end from starting
time of the channel statistics until now.
9.
It shows the total number of loss synchronous of the device at local end from starting time of the
channel statistics until now.
FOx.On
FOx.Send1
FOx.Recv1
FOx.Send2
FOx.Recv2
FOx.Send3
FOx.Recv3
FOx.Send4
FOx.Recv4
FOx.Send5
FOx.Recv5
FOx.Send6
FOx.Recv6
FOx.Send7
FOx.Recv7
FOx.Send8
FOx.Recv8
FOx.Alm
FOx.Alm_ID
Input Signal
Description
FOx.En
Enabling channel x
FOx.Send1
FOx.Send2
FOx.Send3
FOx.Send4
FOx.Send5
FOx.Send6
FOx.Send7
FOx.Send8
3-80
3 Operation Theory
Sending signal 9 of channel x (it is configured fixedly as sending permissive
10
FOx.Send9
11
FOx.Send10
12
FOx.Send11
13
FOx.Send12
signal 1 when pilot directional earth-fault protection sharing pilot channel 1 with
pilot distance protection, or sending permissive signal 2 only for pilot directional
earth-fault protection adopting independent pilot channel 2)
No.
Output Signal
Description
FOx.On
Channel x is enabled.
FOx.Recv1
FOx.Recv2
FOx.Recv3
FOx.Recv4
FOx.Recv5
FOx.Recv6
FOx.Recv7
FOx.Recv8
10
FOx.Recv9
signal via channel No.1, or receiving permissive signal of A-phase via channel
No.1 (only for phase-segregated command scheme))
Receiving signal 10 of channel x (it is configured fixedly as receiving permissive
11
FOx.Recv10
12
FOx.Recv11
13
FOx.Recv12
signal 1 when pilot directional earth-fault protection sharing pilot channel 1 with
pilot distance protection, or receiving permissive signal 2 only for pilot
directional earth-fault protection adopting independent pilot channel 2)
14
FOx.Alm
15
FOx.Alm_ID
Channel x is abnormal
Received ID from the remote end is not as same as the setting [FO.RmtID] of
the device in local end
3-81
3 Operation Theory
3.7.5 Logic
SIG
SIG
FOx.Alm
SIG
FOx.Alm_ID
SIG
FOx.En
EN
FOx.En
&
FOx.Recvn
>=1
&
FOx.On
Where:
n can be 1~12
3.7.6 Settings
Table 3.7-2 Settings of pilot channel
No.
Name
Range
Step
Unit
Remark
FO.LocID
0-65535
FO.RmtID
0-65535
FO.Protocol
FOx.BaudRate
G.703
C37.94
C37.94
64 or 2048
kbps
FOx.En_IntClock
0 or 1
0: external clock
1: internal clock
Enabling/disabling channel x
FOx.En
0 or 1
0: disable
1: enable
3 Operation Theory
85.Z.En1
SIG
85.Z.En2
EN
[85.Z.En]
SIG
&
&
85.Z.On
85.Z.Blk
Pilot distance protection receives and sends signals via pilot channel, and the logic of receiving
signal is shown in Figure 3.8-2.
SET
85.Blocking
&
>=1
Valid_Recv1
SIG
85.Recv1
SIG
85.Abnor_Ch1
SIG
Unblocking1 Valid
EN
[85.PUTT]
EN
[85.POTT]
&
>=1
&
>=1
3-83
3 Operation Theory
FD.Pkp
SIG
85.ZX.En1
SIG
85.ZX.En2
EN
[85.ZX.En]
SIG
85.ZX.Blk1
SIG
85.ZX.Blk2
SIG
79.Ready
SIG
Zpilot
&
&
&
85.ZX.On
>=1
&
[85.t_DPU_ZX]
&
0ms
85.Op_ZX
Zone extension uses the setting of pilot zone (ZPilot), and its operation characteristic can be Mho
or Quad.
3.8.2.2 Permissive Underreaching Transfer Trip (PUTT)
Distance elements zone 1 (Z1) with underreaching setting and pilot zone (ZPilot) with
overreaching setting are used for this scheme. Z1 element will send permissive signal to the
remote end and release tripping after Z1 time delay expired. After receiving permissive signal with
ZPilot element pickup, a tripping signal will be released.
The signal transmission element for PUTT is set according to underreaching mode, so current
reversal need not be considered.
For PUTT, there may be a dead zone under weak power source condition. If the fault occurs
outside Z1 zone at strong power source side, Z1 at weak power supply side may not operate to trip
and transmit permissive signal, and pilot distance protection will not operate. Therefore, the
3-84
3 Operation Theory
system fault can only be removed by Z2 at strong power source side with time delay.
ZPilot
Z2
Z1
M
EM
Fault
Z1
EN
Z2
ZPilot
Relay A
Relay B
Z1
Z1
&
&
85.Op_Z
85.Op_Z
ZPilot
ZPilot
Pilot distance protection always adopts pilot channel 1, and the logic of PUTT is shown in Figure
3.8-5.
SIG
21M/21Q.Z1.Op
0ms
100ms
SIG
85.ExTrp
0ms
150ms
SET
85.PUTT
&
SIG
85.Z.On
SIG
FD.Pkp
SIG
Valid_Recv1
SIG
ZPilot
>=1
&
Send1
&
&
8ms
0ms
85.Op_Z
3-85
3 Operation Theory
Under weak power source condition, the problem of dead zone at weak power source end is
eliminated by the weak infeed logic, please refers to section 3.8.2.7 for details.
ZPilot
Z2
EM
Zpilot_Rev
A
Fault
EN
N
Zpilot_Rev
Z2
ZPilot
Relay A
ZPilot
&
85.Op_Z
>=1
Relay B
&
85.Op_Z
>=1
WI
ZPilot
WI
Zpilot
SIG
85.ExTrp
SIG
CB open position
SIG
Valid_Recv1
0ms
150ms
>=1
&
&
200ms
0ms
&
Send1
SIG
ZPilot
SIG
85.Z.On
SIG
WI
&
&
>=1
&
t1
t2
&
85.Op_Z
&
SIG
FD.Pkp
SET
[85.POTT]
8ms
0ms
Where:
t1: pickup time delay of current reversal, the setting [85.t_DPU_CR1]
t2: dropoff time delay of current reversal, the setting [85.t_DDO_CR1]
3-86
3 Operation Theory
3.8.2.4 Blocking
Permissive scheme has high security, but it relies on pilot channel seriously. Pilot distance
protection will not operate when there is an internal fault with abnormal channel. Blocking scheme
could be considered as an alternative.
Blocking scheme takes use of pilot distance element Zpilot operation to terminate sending of
blocking signal. Blocking signal will be sent once fault detector picks up without pilot zone Zpilot
operation. Pilot distance protection will operate with a short time delay if pilot distance element
operates and not receiving blocking signal after timer expired.
The setting of pilot zone element Zpilot in Blocking scheme is overreaching, so current reversal
condition should be considered. However, the short time delay of pilot distance protection has an
enough margin for current reversal, that this problem has been resolved.
The short time delay must consider channel delay and with a certain margin to set. As shown in
Figure 3.8-8, an external fault happens to line MN. The fault is behind the device at M side, for
blocking scheme, the device at M side will send blocking signal to the device at N side. If channel
delay is too long, the device at side N has operated before receiving blocking signal. Hence, the
time delay of pilot distance protection adopted in blocking scheme should be set according to
channel delay.
Blocking signal
EM
Fault
EN
For blocking scheme, pilot distance protection will operate when there is an internal fault with
abnormal channel, however, it is possible that pilot distance protection issue an undesired trip
when there is an external fault with abnormal channel.
ZPilot
EM
Zpilot_Rev
A
Fault
EN
Zpilot_Rev
ZPilot
3-87
3 Operation Theory
Relay A
Relay B
FD.Pkp
&
Zpilot
&
[85.t_DPU_Blocking1]
85.Op_Z
85.Op_Z
&
FD.Pkp
&
Zpilot
[85.t_DPU_Blocking1]
SIG
Zpilot
SIG
85.ExTrp
0ms
150ms
&
SIG
CB open position
&
200ms
SIG
>=1
0ms
&
Valid_Recv1
Send1
&
SIG
FwdDir_ZPilot
SIG
WI
SIG
FD.Pkp
SET
85.Blocking
SIG
85.Z.On
>=1
&
[85.t_DPU_Blocking1]
85.Op_Z
&
Current reversal logic is only used for permissive scheme. For blocking scheme, the time delay of
pilot distance protection has enough margin for current reversal, so current reversal need not be
considered.
3.8.2.5 Unblocking
Permissive scheme will trip only when it receives permissive signal from the remote end. However,
it may not receive permissive signal from the remote end when pilot channel fails. For this case,
pilot distance protection can adopt unblocking scheme. Under normal conditions, the signaling
equipment works in the pilot frequency, and when the device operates to send permissive signal,
the signaling equipment will be switched to high frequency. While pilot channel is blocked, the
signaling equipment will receive neither pilot frequency signal nor high frequency signal. The
signaling equipment will provide a contact to the device as unblocking signal. When the device
receives unblocking signal from the signaling equipment, it will recognize channel failure, and
unblocking signal will be taken as permissive signal temporarily.
The unblocking function can only be used together with PUTT and POTT.
3-88
3 Operation Theory
SIG
[85.En_Unblocking1]
SIG
85.Unblocking1
&
&
[85.t_Unblocking1] 0ms
SIG
EN
[85.Opt_PilotCh1]
SIG
>=1
&
Unblocking1 Valid
N
A
M
Weak
source
EN
N
A
B
EN
EM
As shown above, the device A judges a forward fault while the device B judges a reverse fault
before break D is tripped. However, the device A judges a reverse fault while the device B judges a
forward fault after breaker D is tripped. There is a competition between pickup and drop off of pilot
zones in the device A and the device B when the fault measured by the device A changes from
forward direction into reverse direction and vice versa for the device B. There may be
maloperation for the device in line A-B if the forward direction of the device B has operated but the
forward direction of the device A drops off slightly slower or the forward direction of the device B
has operated but the forward direction information of the device A is still received due to the
channel delay (the permissive signal is received).
In general, the following two methods shall be adopted to solve the problem of current reversal:
1.
The fault shall be measured by means of the reverse element of the device B. Once the
reverse element of the device B operates, the send signals and the tripping circuit will be
blocked for a period of time after a short time delay. This method can effectively solve the
problem of competition between the device A and the device B, but there shall be a
precondition. The reverse element of the device B must be in cooperation with the forward
element of the device A, i.e. in case of a fault in adjacent lines, if the forward element of the
3-89
3 Operation Theory
device A operates, and the reverse element of the device B must also operate. Once the
bilateral cooperation fails, the anticipated function cannot be achieved. In addition, the
blocking time for sending signals and the tripping circuit after the reverse element of the
device B operates shall be set in combination with the channel time delay.
2.
Considering the pickup and drop off time difference of distance elements and the channel time
delay between the device A and the device B, the maloperation due to current reversal shall
be eliminated by setting the time delay. The reverse direction element of the device is not
required for this method, the channel time delay and the tripping time of adjacent breaker
shall be taken into account comprehensively.
This protection device adopts the second method to eliminate the maloperation due to current
reversal.
SIG
SIG
&
t1
t2
t1: [85.t_DPU_CR1]
t2: [85.t_DDO_CR1]
Referring to above figure, when signal from the remote end is received without pilot forward zone
pickup, the current reversal blocking logic is enabled after t1 delay.
The time delay of t1 [85.t_DPU_CR1] shall be set the shortest possible but allowing sufficient time
for pilot forward zone pickup, generally set as 25ms.
Once the current reversal logic is enabled, the healthy line device B transfer tripping is blocked.
The logic will be disabled by either the dropoff of signal or the pickup of pilot forward zone. A time
delay t2 [85.t_DDO_CR1] is required to avoid maloperation for the case that the pilot forward zone
(or forward element of pilot directional earth-fault protection) of device B picks up before the signal
from device A drops off. Considering the channel propagation delay and the pickup and drop-off
time difference of pilot forward zone (or pilot directional earth-fault element) with margin, t2 is
generally set between 25ms~40ms.
Because the time delay of pilot distance protection has an enough margin to current reversal,
current reversal blocking only used for permissive scheme not blocking scheme.
3.8.2.7 Weak Infeed
In case of a fault in line at one end of which there is a weak power source, the fault current
supplied to the fault point from the weak power source is very small or even nil, and the
conventional distance element could not operate. The weak infeed logic combines the protection
information from the strong power source end and the electric feature of the local end to cope with
the case.
The weak infeed logic can be only applied for BOTT and POTT. The weak infeed logic has options
for echo or both echo and tripping.
3-90
3 Operation Theory
ZPilot
Z1
M
EM
Fault
Zpilot_Rev
B
Z1
Zpilot_Rev
EN
ZPilot
Load
When the weak infeed logic is enabled, distance forward and reverse element and direction
element of directional earth-fault protection do not operate with the voltage lower than the setting
[85.U_UV_WI] after the device picks up, upon receiving signal from remote end, the weak infeed
logic will echo the signal back to remote end for 200ms if the weak infeed echo is enabled, the
weak infeed end will echo signal and release tripping according to the logic.
ZPilot_Rev at weak source end must coordinate with ZPilot_Set of the remote end. The coverage
of ZPilot_Rev must exceed that of ZPilot_Set of the remote end. ZPilot_Rev only activates in the
protection calculation when the weak infeed logic is enabled. In case of the weak infeed logic not
enabled, the setting coordination is not required.
If the device does not pick up, and the weak infeed logic is enabled, upon receiving signal from
remote end with the voltage lower than the setting [85.U_UV_WI], the weak infeed logic will echo
back to remote end for 200ms. When either weak infeed echo or weak infeed tripping is enabled,
then the weak infeed logic is deemed to be enabled. During the device picking up, the weak infeed
logic is shown in Figure 3.8-15.
SIG
FD.Pkp
SIG
Valid_Recv1
SIG
SIG
SIG
SIG
EN
[85.En_WI]
SET
Up<[85.U_UV_WI]
SET
Upp<[85.U_UV_WI]
>=1
&
&
Forward direction (WI)
>=1
>=1
200ms
0ms
&
3-91
3 Operation Theory
If the device does not pick up, the weak infeed logic is shown as the following figure:
SIG
EN
[85.En_WI]
SET
Up<[85.U_UV_WI]
&
&
WI echo
>=1
200ms
SET
0ms
&
Upp<[85.U_UV_WI]
For permissive scheme, the signal receive condition means that the permissive signal is received
or the unblocking signal is valid.
3.8.2.8 CB Echo
A feature is also provided which enables fast tripping to be maintained along the whole length of
the protected line, even when one terminal is open. The device will initiate sending a pulse of
200ms permissive signal when signal receive condition is met during CB is in open position.
SIG
FD.Pkp
SIG
CB open position
SIG
Valid_Recv1
EN
85.POTT
&
&
200ms
0ms
&
Send permissive signal
&
CB Echo logic is only applied to permissive overreach mode not underreach mode, and it is
processed without the device pickup. This logic will be terminated immediately once the device
picks up.
3-92
3 Operation Theory
85.Z.On
85.Z.En2
85.ZX.On
85.Z.Blk
85.Op_Z
85.Abnor_Ch1
85.Send1
85.Rcv1
85.SendB
85.RcvB
85.SendC
85.RcvC
85.Op_ZX
85.ExTrp
85.ZX_St
85.Unblocking1
85.ZX.En1
85.ZX.En2
85.ZX.Blk1
85.ZX.Blk2
79.Ready
Input Signal
85.Z.En1
85.Z.En2
85.Z.Blk
85.Abnor_Ch1
Description
Pilot distance protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Pilot distance protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Pilot distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Input signal of indicating that pilot channel 1 is abnormal
Input signal of receiving permissive signal via channel No.1, or input signal of
85.Recv1
receiving
permissive
signal
of
A-phase
via
channel
No.1
(only
for
85.RecvB
85.RecvC
85.ExTrp
Input signal of receiving permissive signal of B-phase via channel No.1 (only for
phase-segregated command scheme)
Input signal of receiving permissive signal of C-phase via channel No.1 (only for
phase-segregated command scheme)
Input signal of initiating sending permissive signal from external tripping signal
3-93
3 Operation Theory
9
85.Unblocking1
10
85.ZX.En1
11
85.ZX.En2
12
85.ZX.Blk1
13
85.ZX.Blk2
14
79.Ready
No.
Unblocking signal 1
Zone Extension enabling input 1, it is triggered from binary input or programmable
logic etc.
Zone Extension enabling input 2, it is triggered from binary input or programmable
logic etc.
Zone Extension blocking input 1, it is triggered from binary input or programmable
logic etc.
Zone Extension blocking input 2, it is triggered from binary input or programmable
logic etc.
AR has been ready for reclosing cycle.
Output Signal
Description
85.Z.On
85.ZX.On
85.Op_Z
85.Send1
85.SendB
85.SendC
85.Op_ZX
85.ZX_St
3.8.5 Settings
Table 3.8-2 Settings of pilot distance protection
No.
Name
Range
Step
Unit
Remark
Option of pilot scheme
85.Opt_PilotMode
0~2
0: POTT
1: PUTT
2: Blocking
Option
of
phase-segregated
85.Opt_Ch_PhSeg
signal scheme
0 or 1
phase-segregated
signal
scheme
Enabling/disabling weak infeed
3
85.En_WI
scheme
0 or 1
0: disable
1: enable
85.U_UV_WI
0~Unn
85.Z.En
0 or 1
0.001
3-94
pilot
3 Operation Theory
distance protection
0: disable
1: enable
Enabling/disabling unblocking
6
85.En_Unblocking1
scheme
0 or 1
0: disable
1: enable
Time
85.t_DPU_Blocking1
0.000~1.000
0.001
delay
scheme
of
for
blocking
pilot
distance
protection operation
8
85.t_DDO_CR1
0.000~1.000
0.001
85.t_DPU_CR1
0.000~1.000
0.001
10
85.ZX.En
zone
extension protection
0 or 1
0: disable
1: enable
11
85.t_DPU_ZX
0.000~10.000
0.001
Name
85.t_Unblocking1
Default Value
0.1
Unit
s
Remark
Pickup time delay of unblocking scheme for pilot
channel 1
Option of PLC channel for pilot channel 1
85.Opt_PilotCh1
0: phase-to-phase channel
1: phase-to-ground channel
3 Operation Theory
85.DEF.En1
SIG
85.DEF.En2
EN
[85.DEF.En]
SIG
85.DEF.Blk
&
&
85.DEF.On
Pilot directional earth-fault protection comprises permissive scheme and blocking scheme. It can
share pilot channel 1 ([85.DEF.En_IndepCh]=0) with pilot distance protection, or uses independent
pilot channel 2 ([85.DEF.En_IndepCh]=1) by setting logic setting [85.DEF.En_IndepCh]. For
underreach mode, pilot directional earth-fault always adopts independent pilot channel 2. The
logic of receiving signal is shown in Figure 3.9-2.
SET
85.Blocking
SIG
85.Recv1
&
>=1
&
SIG
85.Abnor_Ch1
SIG
Unblocking1 Valid
SET
85.PUTT
&
>=1
>=1
Valid_Recv_DEF
EN
[85.DEF.En_IndepCh]
SET
85.Blocking
&
&
>=1
SIG
85.Recv2
SIG
85.Abnor_Ch2
SIG
Unblocking2 Valid
&
3-96
3 Operation Theory
SIG
FwdDir_ROC
&
85.FwdDir_DEF_Pilot
SIG
3I0>[85.DEF.3I0_Set]
SIG
RevDir_ROC
&
85.RevDir_DEF_Pilot
SIG
FD.ROC.Pkp
EM
Rev_DEF_Pilot
A
Fault
EN
Rev_DEF_Pilot
FWD_DEF_Pilot
Relay A
FWD_DEF_Pilot
&
&
85.DEF.t_DPU
85.Op_DEF
85.Op_DEF
85.DEF.t_DPU
FWD_DEF_Pilot
Relay B
For blocking scheme, pilot directional earth-fault protection will operate when there is an internal
fault with abnormal channel, however, it is possible that pilot directional earth-fault protection issue
an undesired trip when there is an external fault with abnormal channel.
3-97
3 Operation Theory
SIG
[85.ExTrp]
SIG
CB open position
SIG
Valid_Recv_DEF
SIG
FD.Pkp
SIG
85.FwdDir_DEF_Pilot
SIG
85.RevDir_DEF_Pilot
SIG
Valid_Recv_DEF
SIG
FD.Pkp
SET
85.PUTT
SET
85.POTT
SIG
85.DEF.On
0ms
150ms
&
>=1
&
200ms
0ms
&
85.Send_DEF
&
&
&
t1
t2
&
>=1
&
&
&
[85.DEF.t_DPU]
>=1
85.Op_DEF
&
EN
85.DEF.En_IndepCh
[85.t_DPU_CR2] and t2
When sharing pilot channel 1 with pilot distance protection, t1 and t2 are the settings
[85.t_DPU_CR1] and [85.t_DDO_CR1] respectively.
3.9.2.2 Blocking
Permissive scheme has high security, but it relies on pilot channel seriously. Pilot directional
earth-fault protection will not operate when there is an internal fault with abnormal channel.
Blocking scheme could be considered as an alternative.
Blocking scheme sends blocking signal when fault detector picks up if and zero-sequence forward
element does not operate or both zero-sequence forward element and zero-sequence reverse
element do not operate. Pilot directional earth-fault protection will operate if forward directional
zero-sequence overcurrent element operates and not receiving blocking signal.
3-98
3 Operation Theory
FWD_DEF_Pilot
Rev_DEF_Pilot
EM
Fault
EN
Rev_DEF_Pilot
FWD_DEF_Pilot
Relay B
Relay A
Pkp_FD_Prot
Pkp_FD_Prot
&
REV_DEF_Pilot
&
&
REV_DEF_Pilot
&
FWD_DEF_Pilot
FWD_DEF_Pilot
&
&
85.Op_DEF
&
85.Op_DEF
&
[t_DEF_PilotP]
[t_DEF_PilotP]
Trp
SIG
85.ExTrp
SIG
CB open position
SIG
Valid_Recv_DEF
SIG
85.FwdDir_DEF_Pilot
SIG
85.RevDir_DEF_Pilot
SIG
FD.Pkp
SET
85.Blocking
SIG
85.DEF.On
>=1
0ms
150ms
>=1
&
Send_DEF
&
&
&
[85.DEF.t_DPU]
85.Op_DEF
&
When DEF shares pilot channel 1 with pilot distance protection, time delay of pilot directional
earth-fault protection will change from the setting [85.DEF.t_DPU] to the setting
[85.t_DPU_Blocking1].
Because the time delay of pilot directional earth-fault protection has enough margin for current
reversal, so blocking scheme should not consider the current reversal condition.
3-99
3 Operation Theory
3.9.2.3 Unblocking
Permissive scheme will operate only when it receives permissive signal from the remote end.
However, it may not receive permissive signal from the remote end when pilot channel fails. For
this case, pilot directional earth-fault protection can adopt unblocking scheme. Under normal
conditions, the signaling equipment works in the pilot frequency, and when the device operates to
send permissive signal, the signaling equipment will be switched to high frequency. While the
channel is blocked, the signaling equipment will receive neither pilot frequency signal nor high
frequency signal. The signaling equipment will provide a contact to the device as unblocking signal.
When the device receives unblocking signal from the signaling equipment, it will recognize
channel failure, and unblocking signal will be taken as permissive signal temporarily.
The unblocking scheme can only be used together with permissive scheme.
EN
[85.En_Unblocking2]
BI
85.Unblocking2
&
&
&
[85.t_Unblocking2]
SIG
Selection of multi-phase
EN
[85.Opt_PilotCh2]
SIG
Unblocking2 Valid
0ms
>=1
3-100
3 Operation Theory
85.DEF.On
85.DEF.En2
85.Op_DEF
85.DEF.Blk
85.DEF_BlkAR
85.Abnor_Ch1
85.Send1
85.Abnor_Ch2
85.Send2
85.Rcv1
85.Rcv2
85.ExTrp
85.Unblocking1
85.Unblocking2
Input Signal
Description
Pilot directional earth-fault protection enabling input 1, it is triggered from binary
85.DEF.En1
85.DEF.En2
85.DEF.Blk
85.Abnor_Ch1
85.Abnor_Ch2
85.Recv1
85.Recv2
85.ExTrp
Input signal of initiating sending permissive signal from external tripping signal
85.Unblocking1
Unblocking signal 1
10
85.Unblocking2
Unblocking signal 2
No.
Output Signal
Description
85.DEF.On
85.Op_DEF
85.DEF_BlkAR
85.Send1
85.Send2
3-101
3 Operation Theory
3.9.5 Settings
Table 3.9-2 Settings of pilot directional earth-fault protection
No.
Name
Range
Step
Unit
Remark
Enabling/disabling pilot directional
85.DEF.En
earth-fault protection
0 or 1
0: disable
1: enable
Enabling/disabling pilot directional
earth-fault protection operate to
block AR
85.DEF.En_BlkAR
0 or 1
for
independent
pilot
directional
earth-fault protection
3
85.DEF_En_IndepCh
0:
0 or 1
pilot
directional
earth-fault
pilot
directional
earth-fault
unblocking
85.En_Unblocking2
0 or 1
channel 2
0: disable
1: enable
85.DEF.3I0_Set
(0.050~30.000)In
0.001
85.DEF.t_DPU
0.001~10.000
0.001
85.t_DPU_CR2
0.000~1.000
0.001
of
pilot
directional
earth-fault protection
Time
delay
delay
pickup
for
current
protection
adopts
85.t_DDO_CR2
0.000~1.000
0.001
protection
adopts
Name
85.t_Unblocking2
Default Value
0.2
Unit
Remark
3-102
3 Operation Theory
channel 2
Option of PLC channel for pilot channel 2
2
85.Opt_PilotCh2
0: phase-to-phase channel
1: phase-to-ground channel
M
C
Fault
N
A
EN
When line LM has an earth fault, the fault currents flowing through the relay A and the relay D are
of similar magnitude in most cases. It is desirable that the fault is isolated from the power system
by tripping the circuit breaker C and circuit breaker D. Hence, the overcurrent protection of relay A
and relay D require to associate with current direction to fulfill selective tripping.
Directional earth fault protection has a time delay due to coordinate with that of downstream so it
cannot clear the fault quickly. Pilot directional earth-fault protection, which is fulfilled by directional
earth fault element on both ends, it can maintain fast operation and achieve high sensitivity to
detect high resistance fault.
3 Operation Theory
Forward direction
Reverse direction
Where:
is the setting [RCA_OC]
is the phase angle between polarized voltage and current
The power value is calculated as below:
P=U[ICOS(-)]
1.
2.
From above diagram can be seen, when =, P reaches to the maximum value. It is considered
as the most sensitive forward direction. Hence, is called as sensitivity angle of phase
overcurrent protection.
1.
In the event of asymmetrical fault, because phase or phase-to-phase voltage may decrease to
very low voltage whereas positive-sequence voltage does not, the polarized voltage of phase or
phase-to-phase current direction uses positive-sequence voltage to avoid wrong direction due to
too low polarized voltage. Therefore, using positive-sequence voltage as polarized voltage can
ensure that the direction determination has no dead zone for asymmetrical fault. For symmetric
fault, if positive-sequence voltage decreases to 15%Un, the device uses memorized
positive-sequence voltage as polarized voltage, the memorized positive-sequence voltage is 1.5
3-104
3 Operation Theory
When using normal polarized voltage to calculate phase and phase-to-phase current direction,
there are total twelve direction determination algorithm including forward direction and reverse
direction.
Table 3.10-1 Direction description
Direction
Phase A
Phase B
Phase C
Phase AB
Phase BC
Phase CA
3.
Polarized Voltage
Current
Forward direction
U1a
Ia
Reverse direction
U1a
Ia
Forward direction
U1b
Ib
Reverse direction
U1b
Ib
Forward direction
U1c
Ic
Reverse direction
U1c
Ic
Forward direction
U1ab
Iab
Reverse direction
U1ab
Iab
Forward direction
U1bc
Ibc
Reverse direction
U1bc
Ibc
Forward direction
U1ca
Ica
Reverse direction
U1ca
Ica
When the symmetrical fault occurs on a power system, positive-sequence voltage may reduce to
less than 0.15Un, the device will switch to phase or phase-to-phase current direction for
under-voltage condition. The 1.5 cycle pre-fault positive-sequence voltage is used as polarized
voltage with reverse threshold to ensure stable direction decision when three-phase voltage goes
to approximately zero due to close up fault.
At first, the threshold is forward offset before direction is determined, and the threshold will be
reversed offset after direction is determined.
3.10.2.2 Zero-sequence/Negative-sequence Current Direction
By setting the characteristic angle [RCA_ROC] and [RCA_NegOC] to determine the most
sensitive forward angle of zero-sequence current and negative-sequence current, power value is
calculated using zero-sequence current with zero-sequence voltage or negative-sequence current
with negative-sequence voltage to determine the direction of zero-sequence current and
negative-sequence current respectively in forward direction or reverse direction.
When the power value is between 0 and -0.1In, neither forward direction nor reverse direction is
considered.
3-105
3 Operation Theory
jX
3U0
-180
-3I0
R
O
3I0
Reverse direction
Forward direction
1.
Calculating the power value using zero-sequence current (3I0) and zero-sequence voltage (3U0)
to determine the direction of zero-sequence current
According to the equation:
The zero-sequence current and the zero-sequence voltage can be gained by calculation
3-106
3 Operation Theory
Calculating the power value using negative-sequence current (3I2) and negative-sequence
voltage (3U2) to determine the direction of negative-sequence current
According to the equation:
The negative-sequence current and the negative-sequence voltage can be gained by calculation
Negative-sequence power is: P=3U2[3I2COS(-)]
3.
is the setting [Z0_Comp], which cannot exceed the total zero-sequence impedance of
the protected line
is the setting [Z2_Comp], which cannot exceed the total negative-sequence impedance
of the protected line
3-107
3 Operation Theory
Output Signal
Description
FwdDir_ROC
RevDir_ROC
FwdDir_NegOC
RevDir_NegOC
FwdDir_A
FwdDir_B
FwdDir_C
RevDir_A
RevDir_B
10
RevDir_C
11
FwdDir_AB
12
FwdDir_BC
13
FwdDir_CA
3-108
3 Operation Theory
14
RevDir_AB
15
RevDir_BC
16
RevDir_CA
3.10.5 Settings
Table 3.10-3 Settings of current direction
No.
Name
Range
Step
Unit
RCA_OC
30.00~89.00
0.01
Deg
RCA_ROC
30.00~89.00
0.01
Deg
RCA_NegOC
30.00~89.00
0.01
Deg
Z0_Comp
(0.000~4Unn)/In
0.001
ohm
Z2_Comp
(0.000~4Unn)/In
0.001
ohm
Remark
The characteristic angle of directional
phase overcurrent element
The characteristic angle of directional earth
fault element
The characteristic angle of directional
negative-sequence overcurrent element
The
compensated
zero-sequence
impedance
The
compensated
negative-sequence
impedance
Four-stage phase overcurrent protection with independent logic, current and time delay
settings.
2.
3.
Direction control element can be selected to control each stage phase overcurrent protection
with three options: no direction, forward direction and reverse direction.
4.
Second harmonic can be selected to block each stage of phase overcurrent protection.
3.11.2.1 Overview
Phase overcurrent protection consists of following three elements:
3-109
3 Operation Theory
1.
2.
Direction control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.
3.
Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each phase overcurrent element can individually enable the output signal from
harmonic element as a blocking input.
Equation 3.11-1
Where:
Ip is measured phase current.
[50/51Px.I_Set] is the current setting of stage x (x=1, 2, 3, or 4) of overcurrent element.
3.11.2.3 Direction Control Element
Please refer to section 3.10 for details.
3.11.2.4 Harmonic Blocking Element
When phase overcurrent protection is used to protect feeder transformer circuits harmonic
blocking function can be selected for each stage of phase overcurrent element by configuring logic
setting [50/51Px.En_Hm2_Blk] (x=1, 2, 3 or 4) to prevent maloperation due to inrush current.
When the percentage of second harmonic component to fundamental component of any phase
current is greater than the setting [50/51P.K_Hm2], harmonic blocking element operates to block
stage x overcurrent element if corresponding logic setting [50/51Px.En_Hm2_Blk] enabled.
Operation criterion:
Equation 3.11-2
Where:
is second harmonic of phase current
3-110
3 Operation Theory
Where:
Iset is current setting [50/51Px.I_Set].
Tp is time multiplier setting [50/51Px.TMS].
is a constant.
K is a constant.
C is a constant.
I is measured phase current from line CT
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Px.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.11-1 Inverse-time curve parameters
50/51Px.Opt_Curve
Time Characteristic
Definite time
0.14
0.02
13.5
1.0
80.0
2.0
0.05
0.04
120.0
1.0
28.2
2.0
0.1217
19.61
2.0
0.491
ANSI Inverse
0.0086
0.02
0.0185
0.0515
0.02
0.114
10
64.07
2.0
0.25
11
28.55
2.0
0.712
12
0.086
0.02
0.185
13
Programmable user-defined
If all available curves do not comply with user application, user may set [50/51Px.Opt_Curve] as
13 to customize the inverse-time curve characteristic with constants , K and C. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Px.tmin], then the operating time of the protection changes to the value of setting
3-111
3 Operation Theory
[50/51Px.tmin] automatically.
Define-time or inverse-time phase overcurrent protection drops off instantaneously after fault
current disappears.
50/51Px.On
50/51Px.En2
50/51Px.StA
50/51Px.Blk
50/51Px.StB
50/51Px.StC
50/51Px.St
50/51Px.Op
Input Signal
50/51Px.En1
50/51Px.En2
50/51Px.Blk
No.
Output Signal
Description
Stage x of phase overcurrent protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Stage x of phase overcurrent protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of phase overcurrent protection blocking input, it is triggered from binary
input or programmable logic etc.
Description
50/51Px.On
50/51Px.Op
50/51Px.St
50/51Px.StA
50/51Px.StB
50/51Px.StC
3-112
3 Operation Theory
3.11.5 Logic
SET
Ia>[50/51Px.I_Set]
SET
Ib>[50/51Px.I_Set]
SET
Ic>[50/51Px.I_Set]
SET
[50/51Px.Opt_Dir]=1
SIG
Forward DIR
SET
[50/51Px.Opt_Dir]=2
&
50/51Px.StA
&
&
50/51Px.StB
&
&
50/51Px.StC
>=1
SIG
Reverse DIR
SET
[50/51Px.Opt_Dir]=0
SIG
I3P
SET
[50/51Px.En_Hm2_Blk]
EN
[50/51Px.En]
SIG
50/51Px.En1
SIG
50/51Px.En2
SIG
50/51Px.Blk
SIG
FD.Pkp
&
>=1
2nd Hm Detect
50/51Px.St
&
Timer
t
50/51Px.Op
t
&
&
50/51Px.On
&
Where:
x=1, 2, 3, 4
3.11.6 Settings
Table 3.11-3 Settings of phase overcurrent protection
No.
Name
Range
Step
Unit
Remark
Setting
50/51P.K_Hm2
0.000~1.000
0.001
of
component
second
for
harmonic
blocking
phase
overcurrent elements
2
50/51P1.I_Set
(0.050~30.000)In
0.001
50/51P1.t_Op
0.000~20.000
0.001
50/51P1.En
overcurrent protection
0 or 1
0: disable
1: enable
50/51P1.En_BlkAR
Enabling/Disabling
0 or 1
auto-reclosing
3-113
3 Operation Theory
overcurrent protection operates
0: disable
1: enable
Direction option for stage 1 of phase
overcurrent protection
6
50/51P1.Opt_Dir
0, 1 or 2
0: no direction
1: forward direction
2: reverse direction
Enabling/disabling second harmonic
blocking for stage 1 of phase
50/51P1.En_Hm2_Blk
0 or 1
overcurrent protection
0: disable
1: enable
Option of characteristic curve for
50/51P1.Opt_Curve
0~13
stage
of
phase
overcurrent
protection
Time multiplier setting for stage 1 of
9
50/51P1.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection
Minimum operating time for stage 1
10
50/51P1.tmin
0.000~20.000
0.001
11
50/51P1.Alpha
0.010~5.000
for
stage
customized
0.001
of
inverse-time
characteristic
phase
overcurrent
protection
Constant
12
50/51P1.C
0.000~20.000
for
stage
customized
0.001
of
inverse-time
characteristic
phase
overcurrent
protection
Constant
13
50/51P1.K
0.050~20.000
for
stage
customized
0.001
characteristic
of
inverse-time
phase
overcurrent
protection
14
50/51P2.I_Set
(0.050~30.000)In
0.001
15
50/51P2.t_Op
0.000~20.000
0.001
16
50/51P2.En
overcurrent protection
0 or 1
0: disable
1: enable
17
50/51P2.En_BlkAR
Enabling/Disabling
0 or 1
auto-reclosing
3-114
3 Operation Theory
overcurrent protection operates
0: disable
1: enable
Direction option for stage 2 of phase
overcurrent protection
18
50/51P2.Opt_Dir
0, 1 or 2
0: no direction
1: forward direction
2: reverse direction
Enabling/disabling second harmonic
blocking for stage 2 of phase
19
50/51P2.En_Hm2_Blk
0 or 1
overcurrent protection
0: disable
1: enable
Option of characteristic curve for
20
50/51P2.Opt_Curve
0~12
stage
of
phase
overcurrent
protection
Time multiplier setting for stage 2 of
21
50/51P2.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection.
Minimum operating time for stage 2
22
50/51P2.tmin
0.000~20.000
0.001
23
50/51P3.I_Set
(0.050~30.000)In
0.001
24
50/51P3.t_Op
0.000~20.000
0.001
25
50/51P3.En
overcurrent protection
0 or 1
0: disable
1: enable
Enabling/Disabling
auto-reclosing
50/51P3.En_BlkAR
0 or 1
27
50/51P3.Opt_Dir
0, 1 or 2
0: no direction
1: forward direction
2: reverse direction
Enabling/disabling second harmonic
28
50/51P3.En_Hm2_Blk
0 or 1
overcurrent protection
0: disable
3-115
3 Operation Theory
1: enable
Option of characteristic curve for
29
50/51P3.Opt_Curve
0~12
stage
of
phase
overcurrent
protection
Time multiplier setting for stage 3 of
30
50/51P3.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection.
Minimum operating time for stage 3
31
50/51P3.tmin
0.000~20.000
0.001
32
50/51P4.I_Set
(0.050~30.000)In
0.001
33
50/51P4.t_Op
0.000~20.000
0.001
34
50/51P4.En
overcurrent protection
0 or 1
0: disable
1: enable
Enabling/Disabling
auto-reclosing
50/51P4.En_BlkAR
0 or 1
36
50/51P4.Opt_Dir
0, 1 or 2
0: no direction
1: forward direction
2: reverse direction
Enabling/disabling second harmonic
blocking for stage 4 of phase
37
50/51P4.En_Hm2_Blk
0 or 1
overcurrent protection
0: disable
1: enable
Option of characteristic curve for
38
50/51P4.Opt_Curve
0~12
stage
of
phase
overcurrent
protection
Time multiplier setting for stage 4 of
39
50/51P4.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection.
Minimum operating time for stage 4
40
50/51P4.tmin
0.010~20.000
0.001
3-116
3 Operation Theory
Four-stage earth fault protection with independent logic, current and time delay settings.
2.
3.
Directional element can be selected to control each stage of earth fault protection with three
options: no direction, forward direction and reverse direction.
4.
Second harmonic can be selected to block each stage of earth fault protection.
3.12.2.1 Overview
Earth fault protection consists of following three elements:
1.
Overcurrent element: each stage equipped with one independent overcurrent element.
2.
Directional control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.
3.
Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each overcurrent element can individually enable the output signal of harmonic
blocking element as a blocking input.
Equation 3.12-1
Where:
3I0 is the calculated residual current.
[50/51Gx.3I0_Set] is the current setting of stage x (x=1, 2, 3, or 4) of earth fault protection.
3-117
3 Operation Theory
Where:
is second harmonic of residual current
Equation 3.12-3
Where:
Iset
3 Operation Theory
Time Characteristic
Definite time
0.14
0.02
13.5
1.0
80.0
2.0
0.05
0.04
120.0
1.0
28.2
2.0
0.1217
19.61
2.0
0.491
ANSI Inverse
0.0086
0.02
0.0185
0.0515
0.02
0.114
10
64.07
2.0
0.25
11
28.55
2.0
0.712
12
0.086
0.02
0.185
13
Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Gx.Opt_Curve] as
13 to customize the inverse-time curve characteristic, and constants K, and C with
configuration tool software. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Gx.tmin], then the operating time of the protection changes to the value of setting
[50/51Gx.tmin] automatically.
Define-time or inverse-time directional earth-fault protection drops off instantaneously after fault
current disappears.
50/51Gx.On
50/51Gx.En2
50/51Gx.St
50/51Gx.Blk
50/51Gx.Op
3-119
3 Operation Theory
Input Signal
50/51Gx.En1
50/51Gx.En2
50/51Gx.Blk
No.
Description
Stage x of earth fault protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Stage x of earth fault protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Stage x of earth fault protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
50/51Gx.On
50/51Gx.St
50/51Gx.Op
3.12.5 Logic
SIG
FD.Pkp
EN
[50/51Gx.En]
SIG
50/51Gx.En1
SIG
50/51Gx.En2
SIG
50/51Gx.Blk
SET
3I0>[50/51Gx.3I0_Set]
EN
[50/51Gx.En_Abnor_Blk]
&
&
&
50/51Gx.On
>=1
&
&
50/51Gx.St
&
SIG
No abnormal conditions
>=1
Timer
t
&
50/51Gx.Op
SET
[50/51Gx.Opt_Dir]=1
SIG
Forward DIR
SET
[50/51Gx.Opt_Dir]=2
SIG
Reverse DIR
SET
[50/51Gx.Opt_Dir]=0
SIG
CTS.Alm
EN
[50/51Gx.En_CTS_Blk]
SIG
I3P
SET
[50/51Gx.En_Hm2_Blk]
&
&
>=1
&
>=1
2nd Hm Detect
&
3-120
3 Operation Theory
Where:
x=1, 2, 3, 4
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR, earth
fault protection will operate. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 1, the stage x of
earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 0,
earth fault protection is not controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting
[50/51Gx.En_Abnor_Blk] is set as 1, the stage x of earth fault protection will be blocked. If the
logic setting [50/51Gx.En_Abnor_Blk] is set as 0, earth fault protection is not controlled by
direction element.
Abnormal condition 3: VT circuit failure. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 1,
the stage x of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is
set as 0, earth fault protection is not controlled by direction element.
3.12.6 Settings
Table 3.12-3 Settings of earth fault protection
No.
Name
Range
Step
Unit
Remark
Setting
50/51G.K_Hm2
0.000~1.000
0.001
of
second
harmonic
50/51G1.3I0_Set
(0.050~30.000)In
0.001
50/51G1.t_Op
0.000~20.000
0.001
50/51G1.En
0 or 1
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 1 of earth
50/51G1.En_BlkAR
0 or 1
50/51G1.Opt_Dir
0, 1 or 2
0: no direction
1: forward direction
2: reverse direction
50/51G1.En_Hm2_Blk
Enabling/disabling
0 or 1
second
3-121
3 Operation Theory
earth fault protection
0: disable
1: enable
Enabling/disabling blocking for
stage 1 of earth fault protection
8
50/51G1.En_Abnor_Blk
0 or 1
50/51G1.En_CTS_Blk
0 or 1
10
50/51G1.Opt_Curve
0~13
11
50/51G1.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection
Minimum operating time for stage
12
50/51G1.tmin
0.050~20.000
0.001
13
50/51G1.Alpha
0.010~5.000
customized
0.001
characteristic
inverse-time
earth
fault
protection
Constant C for stage 1 of
14
50/51G1.C
0.000~20.000
customized
0.001
characteristic
inverse-time
earth
fault
protection
Constant K for stage 1 of
15
50/51G1.K
0.050~20.000
customized
0.001
characteristic
inverse-time
earth
fault
protection
16
50/51G2.3I0_Set
(0.050~30.000)In
0.001
17
50/51G2.t_Op
0.000~20.000
0.001
18
50/51G2.En
0 or 1
0: disable
1: enable
Enabling/Disabling auto-reclosing
19
50/51G2.En_BlkAR
0 or 1
3-122
3 Operation Theory
0: disable
1: enable
Direction option for stage 2 of
earth fault protection
20
50/51G2.Opt_Dir
0, 1 or 2
0: no direction
1: forward direction
2: reverse direction
Enabling/disabling
second
50/51G2.En_Hm2_Blk
0 or 1
22
50/51G2.En_Abnor_Blk
0 or 1
23
50/51G2.En_CTS_Blk
0 or 1
24
50/51G2.Opt_Curve
0~12
25
50/51G2.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection
Minimum operating time for stage
26
50/51G2.tmin
0.050~20.000
0.001
27
50/51G3.3I0_Set
(0.050~30.000)In
0.001
28
50/51G3.t_Op
0.000~20.000
0.001
29
50/51G3.En
0, 1 or 2
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 3 of earth
30
50/51G3.En_BlkAR
0 or 1
31
50/51G3.Opt_Dir
0 or 1
3 Operation Theory
earth fault protection
0: no direction
1: forward direction
2: reverse direction
Enabling/disabling
second
50/51G3.En_Hm2_Blk
0 or 1
33
50/51G3.En_Abnor_Blk
0 or 1
34
50/51G3.En_CTS_Blk
0 or 1
35
50/51G3.Opt_Curve
0~12
36
50/51G3.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection
Minimum operating time for stage
37
50/51G3.tmin
0.050~20.000
0.001
38
50/51G4.3I0_Set
(0.050~30.000)In
0.001
39
50/51G4.t_Op
0.000~20.000
0.001
40
50/51G4.En
0, 1 or 2
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 4 of earth
41
50/51G4.En_BlkAR
0 or 1
42
50/51G4.Opt_Dir
0 or 1
0: no direction
1: forward direction
3-124
3 Operation Theory
2: reverse direction
Enabling/disabling
second
50/51G4.En_Hm2_Blk
0 or 1
44
50/51G4.En_Abnor_Blk
0 or 1
45
50/51G4.En_CTS_Blk
0 or 1
46
50/51G4.Opt_Curve
0~12
47
50/51G4.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection
Minimum operating time for stage
48
50/51G4.tmin
0.050~20.000
0.001
3-125
3 Operation Theory
50PVT.On
50PVT.En2
50PVT.Op
50PVT.Blk
50PVT.St
50GVT.En1
50PVT.StA
50GVT.En2
50PVT.StB
50GVT.Blk
50PVT.StC
50GVT.On
50GVT.Op
50GVT.St
Input Signal
50PVT.En1
50PVT.En2
50PVT.Blk
50GVT.En1
50GVT.En2
50GVT.Blk
No.
Output Signal
Description
Phase overcurrent protection for VT circuit failure enabling input 1, it is triggered
from binary input or programmable logic etc.
Phase overcurrent protection for VT circuit failure enabling input 2, it is triggered
from binary input or programmable logic etc.
Phase overcurrent protection for VT circuit failure blocking input, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure enabling input 1, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure enabling input 2, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure blocking input, it is triggered
from binary input or programmable logic etc.
Description
50PVT.On
50PVT.Op
50PVT.St
50PVT.StA
50PVT.StB
50PVT.StC
50GVT.On
50GVT.Op
50GVT.St
3-126
3 Operation Theory
3.13.4 Logic
SIG
50GVT.En1
SIG
50GVT.En2
EN
[50GVT.En]
SIG
50GVT.Blk]
SIG
FD.Pkp
&
&
50GVT.On
&
50GVT.St
&
SET
3I0>[50GVT.3I0_Set]
SIG
FD.ROC.Pkp
SIG
VTS.Alm
SIG
50PVT.En1
SIG
50PVT.En2
EN
50PVT.En]
SIG
50PVT.Blk]
[50GVT.t_Op]
0ms
50GVT.Op
&
&
&
50PVT.On
>=1
&
[50PVT.t_Op]
&
SIG
FD.Pkp
SIG
VTS.Alm
SET
Ia>[50PVT.I_Set]
0ms
50PVT.Op
50PVT.St
&
50PVT.StA
&
50PVT.StB
SET
Ib>[50PVT.I_Set]
&
50PVT.StC
SET
Ic>[50PVT.I_Set]
3.13.5 Settings
Table 3.13-2 Settings of overcurrent protection for VT circuit failure
No.
Name
Range
Step
Unit
50PVT.I_Set
(0.050~30.000)In
0.001
50PVT.t_Op
0.000~10.000
0.001
Remark
Current setting of phase overcurrent
protection when VT circuit failure
Time delay of phase overcurrent
protection when VT circuit failure
Enabling/disabling phase overcurrent
50PVT.En
0 or 1
0: disable
1: enable
50GVT.3I0_Set
(0.050~30.000)In
0.001
50GVT.t_Op
0.000~10.000
0.001
50GVT.En
0 or 1
ground
3-127
3 Operation Theory
overcurrent protection when VT circuit
failure
0: disable
1: enable
50GSOTF.On
50GSOTF.En2
50GSOTF.Op
50GSOTF.Blk
50GSOTF.St
Input Signal
50GSOTF.En1
50GSOTF.En2
50GSOTF.Blk
Description
Residual current SOTF protection enabling input 1, it is triggered from binary input
or programmable logic etc.
Residual current SOTF protection enabling input 2, it is triggered from binary input
or programmable logic etc.
Residual current SOTF protection blocking input, it is triggered from binary input
3-128
3 Operation Theory
or programmable logic etc.
No.
Output Signal
Description
50GSOTF.On
50GSOTF.Op
50GSOTF.St
3.14.5 Logic
SIG
3-pole AR signal
SIG
SET
3I0>[50GSOTF.3I0_Set]
>=1
&
SIG
FD.ROC.Pkp
SIG
1-pole AR signal
SIG
50GSOTF.En1
SIG
50GSOTF.En2
SIG
50GSOTF.Blk
EN
[50GSOTF.En_3I0]
100ms
0ms
&
>=1
50GSOTF.Op
&
60ms
0ms
>=1
50GSOTF.St
&
&
50GSOTF.On
3.14.6 Settings
Table 3.14-2 Settings of residual current SOTF protection
No.
Name
Range
Step
Unit
50GSOTF.3I0_Set
(0.050~30.000)In
0.001
Remark
Current setting of residual current
SOTF protection
Enabling/disabling residual current
50GSOTF.En_3I0
SOTF protection
0 or 1
0: disable
1: enable
3-129
3 Operation Theory
Two-stage phase overvoltage protection with independent logic, voltage and time delay
settings.
2.
3.
4.
1-out-of-3 or 3-out-of-3 logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)
1.
Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[59Px.Opt_Up/Upp] is set to 0, phase voltage criterion is selected and if [59Px.Opt_Up/Upp] is
set to 1, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is greater than any enabled stage voltage setting,
the stage protection picks up and operates after delay, which will drop off instantaneously when
fault voltage disappears.
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Px.Opt_1P/3P].
U_max>[ 59Px.U_Set]
Equation 3.15-1
or
Ua>[59Px.U_Set] & Ub>[59Px.U_Set] & Uc>[59Px.U_Set]
3-130
Equation 3.15-2
PCS-902 Line Distance Relay
Date: 2013-12-25
3 Operation Theory
Where:
U_max is the maximum value among three phase-voltage.
Ua, Ub, Uc are three phase voltages.
[59Px.U_Set] is the setting of stage x (x=1 or 2) overvoltage protection.
When [59Px.Opt_1P/3P] is set as 0, 1-out-of-3 logic (Equation 3.15-1) is selected as operation
criterion, and when set as 1, 3-out-of-3 logic (Equation 3.15-2) is selected.
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Px.Opt_1P/3P].
U_max>[ 59Px.U_Set]
Equation 3.15-3
or
Uab>[59Px.U_Set] & Ubc>[59Px.U_Set] & Uca>[59Px.U_Set]
Equation 3.15-4
Characteristic Curve
Phase overvoltage protection stage 1 and stage 2 can be selected as definite-time or inverse-time
characteristic, and inverse-time operating time curve is as follows.
Where:
Uset is the voltage setting [59Px.U_Set] (x=1 or 2).
Tp is time multiplier setting [59Px.TMS].
K is a constant.
C is a constant.
is a constant.
U is the measured voltage
For stage 1 and stage 2 of overvoltage protection, operating characteristic can be chosen from
definite-time characteristic and 12 inverse-time characteristics by setting the logic setting
[59Px.Opt_Curve]. The parameters of each characteristic are listed in the following table.
3-131
3 Operation Theory
Table 3.15-1 Inverse-time curve parameters
59Px.Opt_Curve
Time Characteristic
Definite time
0.14
0.02
13.5
1.0
80.0
2.0
0.05
0.04
120.0
1.0
28.2
2.0
0.1217
19.61
2.0
0.491
ANSI Inverse
0.0086
0.02
0.0185
0.0515
0.02
0.114
10
64.07
2.0
0.25
11
28.55
2.0
0.712
12
0.086
0.02
0.185
When inverse-time characteristic is selected, if calculated operating time is less than setting
[59Px.tmin], then the operating time changes to the value of setting [59Px.tmin] automatically.
Define-time or inverse-time phase overvoltage protection drops off instantaneously when
measured voltage is lower than reset voltage.
3.15.1.3 Function Block Diagram
59Px
59Px.En1
59Px.On
59Px.En2
59Px.St
59Px.Blk
59Px.St1
59Px.St2
59Px.St3
59Px.Op
59Px.Alm
59Px.Op_InitTT
3-132
3 Operation Theory
Input Signal
59Px.En1
59Px.En2
59Px.Blk
No.
Description
Stage x of overvoltage protection enabling input 1, it is triggered from binary input
or programmable logic etc.
Stage x of overvoltage protection enabling input 2, it is triggered from binary input
or programmable logic etc.
Stage x of overvoltage protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
59Px.On
59Px.Op
59Px.St
59Px.St1
59Px.St2
59Px.St3
59Px.Op_InitTT
59Px.Alm
3-133
3 Operation Theory
3.15.1.5 Logic
EN
[59Px.En]
SIG
59Px.En1
SIG
59Px.En2
SIG
59Px.Blk
&
&
59Px.On
BI
[52b_PhA]
BI
[52b_PhB]
BI
[52b_PhC]
EN
[59Px.En_52b_TT]
EN
[59Px.En_TT]
EN
[59Px.En_Alm]
SIG
&
&
&
>=1
59Px.Op_InitTT
&
FD.Pkp
&
SIG
59Px.On
EN
[59Px.Opt_Up/Upp]
&
&
>=1
SET
Timer
t
&
UA>[59Px.U_Set]
&
&
SET
UAB>[59Px.U_Set]
&
&
>=1
SET
Timer
t
&
UB>[59Px.U_Set]
59Px.Op
&
SET
&
UBC>[59Px.U_Set]
>=1
&
&
>=1
SET
>=1
Timer
t
t
UC>[59Px.U_Set]
&
SET
59Px.Alm
&
>=1
59Px.St
UCA>[59Px.U_Set]
59Px.St1
59Px.St2
EN
[59Px.Opt_1P/3P]
59Px.St3
x=1, 2
3.15.1.6 Settings
Table 3.15-3 Settings of overvoltage protection
No.
Name
Range
Step
Unit
59P1.U_Set
Un~2Unn
0.001
59P1.t_Op
0.000~30.000
0.001
Remark
Voltage setting for stage 1 of overvoltage
protection
Time delay for stage 1 of overvoltage
protection
Enabling/disabling stage 1 of overvoltage
59P1.En
protection
0 or 1
0: disable
1: enable
3-134
3 Operation Theory
Option of 1-out-of-3 mode or 3-out-of-3
4
59P1.Opt_1P/3P
mode
0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option of phase-to-phase voltage or phase
59P1.Opt_Up/Upp
voltage
0 or 1
0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage 1 of overvoltage
59P1.En_Alm
0 or 1
0: disable
1: enable
Enabling/disabling transfer trip controlled
by CB open position for stage 1 of
59P1.En_52b_TT
0 or 1
overvoltage protection
0: disable
1: enable
Enabling/disabling stage 1 of overvoltage
59P1.En_TT
0 or 1
0: disable
1: enable
59P1.Opt_Curve
0~13
10
59P1.TMS
0.010~200.000
0.001
11
59P1.tmin
0.050~20.000
0.001
12
59P2.U_Set
Un~2Unn
0.001
13
59P2.t_Op
0.000~30.000
0.001
overvoltage protection
Time multiplier setting for stage 1 of
inverse-time overvoltage protection
Minimum delay for stage 1 of inverse-time
overvoltage protection
Voltage setting for stage 2 of overvoltage
protection
Time delay for stage 2 of overvoltage
protection
Enabling/disabling stage 2 of overvoltage
14
59P2.En
protection
0 or 1
0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3
15
59P2.Opt_1P/3P
mode
0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option of phase-to-phase voltage or phase
16
59P2.Opt_Up/Upp
voltage
0 or 1
0: phase voltage
1: phase-to-phase voltage
17
59P2.En_Alm
0 or 1
3 Operation Theory
protection for alarm purpose
0: disable
1: enable
Enabling/disabling transfer trip controlled
by CB open position for stage 2 of
18
59P2.En_52b_TT
0 or 1
overvoltage protection
0: disable
1: enable
Enabling/disabling stage 2 of overvoltage
19
59P2.En_TT
0 or 1
0: disable
1: enable
Option of characteristic curve for stage 2 of
20
59P2.Opt_Curve
0~12
21
59P2.TMS
0.010~200.000
0.001
22
59P2.tmin
0.050~20.000
0.001
overvoltage protection
Time multiplier setting for stage 2 of
inverse-time overvoltage protection
s
Two-stage phase undervoltage protection with independent logic, voltage and time delay
settings.
2.
3.
4.
1-out-of-3 or 3-out-of-3 logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)
1.
Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[27Px.Opt_Up/Upp] is set to 0, phase voltage criterion is selected and if [27Px.Opt_Up/Upp] is
3-136
3 Operation Theory
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Px.Opt_1P/3P].
U_min<[ 27Px.U_Set]
Equation 3.15-5
or
Ua<[ 27Px.U_Set] & Ub<[27Px.U_Set] & Uc<[27Px.U_Set]
Equation 3.15-6
Where:
U_min is the minimum value among three phase voltages.
Ua, Ub and Uc are three phase voltages.
[27Px.U_Set] is the setting of stage x (x=1 or 2) undervoltage protection.
When [27Px.Opt_1P/3P] is set as 0, 1-out-of-3 logic (Equation 3.15-5) is selected as operation
criterion, and when set as 1, 3-out-of-3 logic (Equation 3.15-6) is selected.
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Px.Opt_Up/Upp].
U_min<[ 27Px.U_Set]
Equation 3.15-7
or
Uab<[27Px.U_Set] & Ubc<[27Px.U_Set] & Uca<[27Px.U_Set]
Equation 3.15-8
Where:
U_min is the minimum value among three phase-to-phase voltages.
Uab, Ubc and Uca are three phase-to-phase voltages.
[27Px.U_Set] is the setting of stage x (x =1 or 2) undervoltage protection.
When the setting [27Px.Opt_1P/3P] is set as 0, 1-out-of-3 logic (Equation 3.15-7) is selected as
operation criterion, and when it is set as 1, 3-out-of-3 logic (Equation 3.15-8) is selected.
2.
Characteristic Curve
3-137
3 Operation Theory
Where:
Uset is the setting [27Px.U_Set] (x=1 or 2).
Tp is time multiplier setting [27Px.TMS].
K is a constant.
C is a constant.
is a constant.
U is the measured voltage
For stage 1 and stage 2 of undervoltage protection, operating characteristic can be chosen from
definite-time characteristic and twelve inverse-time characteristics by setting the logic setting
[27Px.Opt_Curve]. The parameters of each characteristic are listed in the following table.
Table 3.15-4 Inverse-time curve parameters of phase undervoltage protection
27Px.Opt_Curve
Time Characteristic
Definite time
0.14
0.02
13.5
1.0
80.0
2.0
0.05
0.04
120.0
1.0
28.2
2.0
0.1217
19.61
2.0
0.491
ANSI Inverse
0.0086
0.02
0.0185
0.0515
0.02
0.114
10
64.07
2.0
0.25
11
28.55
2.0
0.712
12
0.086
0.02
0.185
When inverse-time characteristic is selected, if calculated operating time is less than setting
[27Px.tmin], then the operating time changes to the value of setting [27Px.tmin] automatically.
3-138
3 Operation Theory
Define-time or inverse-time phase under voltage protection drops off instantaneously when
measured voltage is higher than reset voltage.
3.15.2.3 Function Block Diagram
27Px
27Px.En1
27Px.On
27Px.En2
27Px.Alm
27Px.Blk
27Px.Op
27Px.St
27Px.St1
27Px.St2
27Px.St3
Input Signal
27Px.En1
27Px.En2
27Px.Blk
No.
Description
Stage x of undervoltage protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Stage x of undervoltage protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of undervoltage protection blocking input, it is triggered from binary input
or programmable logic etc.
Output Signal
Description
27Px.On
27Px.Op
27Px.Alm
27Px.St
27Px.St1
27Px.St2
27Px.St3
3.15.2.5 Logic
When FD element reflecting current operates, including DPFC current element and residual
current element, the undervoltage protection is released for operation.
When any of the following conditions is fulfilled, the undervoltage protection will be blocked.
1.
VT signal failsif the voltage comes from busbar VT, the voltage will restore to the normal
immediately after the fault being cleared away. However, if the voltage comes from line VT,
the voltage will drop to zero immediately after the fault is cleared. The undervoltage protection
3-139
3 Operation Theory
will be continuously in operation, thus an auxiliary current criterion is provided to solve it.
2.
3.
Any phase of circuit breaker is open (binary input of normal close contact of breaker is
energized) and the corresponding phase current is smaller than 0.06In.
SIG
20ms
Pole dead
100ms
>=1
SIG
VTS.Alm
Block UV
SIG
CB open position
[27Px.En]
SIG
27Px.En1
SIG
27Px.En2
SIG
27Px.Blk
EN
[27Px.En_Alm]
SET
[27P1.Opt_1P/3P]
SIG
FD.Pkp
SIG
27Px.On
SIG
Block UV
SET
[27Px.Opt_Up/Upp]
&
&
27Px.On
&
&
&
>=1
SET
Timer
t
&
&
UA<[27Px.U_Set]
&
SET
UAB<[27Px.U_Set]
&
&
>=1
SET
&
Timer
t
27Px.Op
UB<[27Px.U_Set]
&
&
SET
>=1
27Px.Alm
&
UBC<[27Px.U_Set]
>=1
&
&
>=1
SET
UC<[27Px.U_Set]
&
Timer
t
t
>=1
27Px.St
SET
UCA<[27Px.U_Set]
27Px.St1
27Px.St2
27Px.St3
x=1, 2
3-140
3 Operation Theory
3.15.2.6 Settings
Table 3.15-6 Settings of undervoltage protection
No.
Name
Range
Step
Unit
27P1.U_Set
0~Unn
0.001
27P1.t_Op
0.000~30.000
0.001
Remark
Voltage setting for stage 1 of undervoltage
protection
Time delay for stage 1 of undervoltage
protection
Enabling/disabling stage 1 of undervoltage
27P1.En
protection
0 or 1
0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3
27P1.Opt_1P/3P
mode
0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option
27P1.Opt_Up/Upp
of
voltage
criterion
adopting
0 or 1
0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage 1 of undervoltage
27P1.En_Alm
0 or 1
0: disable
1: enable
Option of characteristic curve for stage 1
27P1.Opt_Curve
0~13
27P1.TMS
0.010~200.000
0.001
27P1.tmin
0.050~20.000
0.001
10
27P2.U_Set
0~Unn
0.001
11
27P2.t_Op
0.000~30.000
0.001
of undervoltage protection
Time multiplier setting for stage 1 of
inverse-time undervoltage protection
Minimum delay for stage 1 of inverse-time
undervoltage protection
Voltage setting for stage 2 of undervoltage
protection
Time delay for stage 2 of undervoltage
protection
Enabling/disabling stage 2 of undervoltage
12
27P2.En
protection
0 or 1
0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3
13
27P2.Opt_1P/3P
mode
0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode
14
27P2.Opt_Up/Upp
Option
0 or 1
of
voltage
criterion
adopting
3 Operation Theory
0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage 2 of undervoltage
15
27P2.En_Alm
0 or 1
0: disable
1: enable
Option of characteristic curve for stage 2
16
27P2.Opt_Curve
0~12
17
27P2.TMS
0.010~200.000
0.001
18
27P2.tmin
0.050~20.000
0.001
of undervoltage protection
Time multiplier setting for stage 2 of
inverse-time undervoltage protection
s
If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2.
Equation 3.16-1
Where:
f is system frequency.
[81O.OFx.f_Set] is the frequency setting of stage x (x=1, 2, 3, or 4) of overfrequency protection.
3-142
3 Operation Theory
81O.OFx.On
81O.En2
81O.St
81O.Blk
81O.OFx.Op
Input Signal
81O.En1
81O.En2
81O.Blk
No.
Description
Overfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Overfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Overfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
81O.OFx.On
81O.OFx.Op
81O.St
3.16.1.5 Logic
SIG
81O.En1
SIG
81O.En2
EN
[81O.OF1.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f40 or f65
OTH
f>[81O.f_Pkp]
&
&
81O.OF1.On
&
1
&
50ms
0ms
81O.St1
&
SET
f>[81O.OF1.f_Set]
EN
[81O.OF1.En]
[81O.OF1.t_Op]
&
0ms
81O.OF1.Op
3-143
3 Operation Theory
SIG
81O.En1
SIG
81O.En2
EN
[81O.OF2.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f40 or f65
OTH
f>[81O.f_Pkp]
&
&
81O.OF2.On
&
1
&
50ms
0ms
81O.St2
&
SET
f>[81O.OF2.f_Set]
EN
[81O.OF2.En]
[81O.OF2.t_Op]
&
0ms
81O.OF2.Op
81O.En1
SIG
81O.En2
EN
[81O.OF3.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f40 or f65
OTH
f>[81O.f_Pkp]
&
&
81O.OF3.On
&
1
&
50ms
0ms
81O.St3
&
SET
f>[81O.OF3.f_Set]
EN
[81O.OF3.En]
[81O.OF3.t_Op]
&
0ms
81O.OF3.Op
81O.En1
SIG
81O.En2
EN
[81O.OF4.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f40 or f65
OTH
f>[81O.f_Pkp]
&
&
81O.OF4.On
&
1
&
50ms
0ms
81O.St4
&
SET
f>[81O.OF4.f_Set]
EN
[81O.OF4.En]
[81O.OF4.t_Op]
&
0ms
81O.OF4.Op
3-144
3 Operation Theory
SIG
81O.St1
SIG
81O.St2
SIG
81O.St3
SIG
81O.St4
1
81O.St
3.16.1.6 Settings
Table 3.16-2 Settings of overfrequency protection
No.
Name
Range
Step
Unit
81O.f_Pkp
50.000~65.000 (Hz)
0.001
Hz
81O.OF1.f_Set
50.000~65.000 (Hz)
0.001
Hz
81O.OF1.t_Op
0.050~20.000 (s)
0.001
Remark
Frequency
pickup
81O.OF1.En
for
overfrequency protection
Frequency setting for stage 1 of
overfrequency protection
Time
delay
for
stage
of
of
overfrequency protection
Enabling/disabling
setting
stage
overfrequency protection
0 or 1
0: disable
1: enable
81O.OF2.f_Set
50.000~65.000 (Hz)
0.001
Hz
81O.OF2.t_Op
0.050~20.000 (s)
0.001
delay
for
81O.OF2.En
of
of
overfrequency protection
Enabling/disabling
stage
stage
overfrequency protection
0 or 1
0: disable
1: enable
81O.OF3.f_Set
50.000~65.000 (Hz)
0.001
Hz
81O.OF3.t_Op
0.050~20.000 (s)
0.001
delay
for
81O.OF3.En
of
of
overfrequency protection
Enabling/disabling
10
stage
stage
overfrequency protection
0 or 1
0: disable
1: enable
11
81O.OF4.f_Set
50.000~65.000 (Hz)
0.001
Hz
12
81O.OF4.t_Op
0.050~20.000 (s)
0.001
13
81O.OF4.En
0 or 1
delay
for
stage
of
of
overfrequency protection
Enabling/disabling
stage
3-145
3 Operation Theory
overfrequency protection
0: disable
1: enable
If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2.
If df/dt[81U.df/dt_Blk], the calculation of protection is not carried out and the output relay will
be blocked. The blocking element will not be released automatically until the system frequency
recovers to be less than the setting [81U.f_Pkp].
3.
Equation 3.16-2
Where:
f is system frequency.
[81U.UFx.f_Set] is the frequency settings of stage x (x=1, 2, 3 or 4) of underfrequency protection.
The equation of df/dt blocking function is as follows.
df/dt[81U.df/dt_Blk]
Equation 3.16-3
Where:
df/dt is the frequency slip speed and the time step (i.e. dt) for the calucation is equal to 5 cycle.
[81U.df/dt_Blk] is the setting of df/dt blocking underfrequency protection.
Underfrequency protection can be blocked by the frequency slip speed (df/dt). If the logic setting
3-146
3 Operation Theory
81U.UFx.On
81U.En2
81U.St
81U.Blk
81U.UFx.Op
Input Signal
81U.En1
81U.En2
81U.Blk
No.
Description
Underfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Underfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Underfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
81U.UFx.On
81U.UFx.Op
81U.St
3-147
3 Operation Theory
3.16.2.5 Logic
SIG
81U.En1
SIG
81U.En2
EN
[81U.UF1.En]
SIG
81U.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f<40 or f>65
OTH
f<[81U.f_Pkp]
50ms
SET
-df/dt>[81U.df/dt_Blk]
>=1
&
&
81U.UF1.On
&
&
1
0ms
81U.St1
&
[81U.UF1.t_Op]
EN
81U.UF1.En_df/dt_Blk
SET
f<[81U.UF1.f_Set]
EN
[81U.UF1.En]
0ms
81U.UF1.Op
&
81U.En1
SIG
81U.En2
EN
[81U.UF2.En]
SIG
81U.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f<40 or f>65
OTH
f<[81U.f_Pkp]
50ms
SET
-df/dt>[81U.df/dt_Blk]
>=1
&
&
81U.UF2.On
&
&
1
0ms
81U.St2
&
[81U.UF2.t_Op]
EN
81U.UF2.En_df/dt_Blk
SET
f<[81U.UF2.f_Set]
EN
[81U.UF2.En]
0ms
81U.UF2.Op
&
3-148
3 Operation Theory
SIG
81U.En1
SIG
81U.En2
EN
[81U.UF3.En]
SIG
81U.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f<40 or f>65
OTH
f<[81U.f_Pkp]
50ms
SET
-df/dt>[81U.df/dt_Blk]
>=1
&
&
81U.UF3.On
&
&
1
0ms
81U.St3
&
[81U.UF3.t_Op]
EN
81U.UF3.En_df/dt_Blk
SET
f<[81U.UF3.f_Set]
EN
[81U.UF3.En]
0ms
81U.UF3.Op
&
81U.En1
SIG
81U.En2
EN
[81U.UF4.En]
SIG
81U.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f<40 or f>65
OTH
f<[81U.f_Pkp]
50ms
SET
-df/dt>[81U.df/dt_Blk]
>=1
&
&
81U.UF4.On
&
&
1
0ms
81U.St4
&
[81U.UF4.t_Op]
EN
81U.UF4.En_df/dt_Blk
SET
f<[81U.UF4.f_Set]
EN
[81U.UF4.En]
0ms
81U.UF4.Op
&
3-149
3 Operation Theory
SIG
81U.St1
SIG
81U.St2
SIG
81U.St3
SIG
81U.St4
>=1
>=1
81U.St
>=1
3.16.2.6 Settings
Table 3.16-4 Settings of underfrequency protection
No.
Name
Range
Step
Unit
81U.f_Pkp
45.000~60.000
0.01
Hz
81U.df/dt_Blk
0.200~20.000
0.01
Hz/s
81U.UF1.f_Set
45.000~60.000
0.001
Hz
81U.UF1.t_Op
0.050~30.000
0.01
Remark
Frequency
pickup
81U.UF1.En
for
underfrequency protection
Rate
of
frequency
change
for
delay
for
stage
of
of
underfrequency protection
Enabling/disabling
setting
stage
underfrequency protection
0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
change
81U.UF1.En_df/dt_Blk
0 or 1
to
block
stage
of
underfrequency protection
0: disable
1: enable
81U.UF2.f_Set
45.000~60.000
0.001
Hz
81U.UF2.t_Op
0.050~30.000
0.01
delay
for
81U.UF2.En
of
of
underfrequency protection
Enabling/disabling
stage
stage
underfrequency protection
0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
change
10
81U.UF2.En_df/dt_Blk
0 or 1
to
block
stage
of
underfrequency protection
0: disable
1: enable
11
81U.UF3.f_Set
45.000~60.000
0.001
3-150
Hz
Date: 2013-12-25
3 Operation Theory
underfrequency protection
12
81U.UF3.t_Op
0.050~30.000
0.01
Time
delay
for
81U.UF3.En
of
of
underfrequency protection
Enabling/disabling
13
stage
stage
underfrequency protection
0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
change
14
81U.UF3.En_df/dt_Blk
0 or 1
to
block
stage
of
underfrequency protection
0: disable
1: enable
15
81U.UF4.f_Set
45.000~60.000
0.001
Hz
16
81U.UF4.t_Op
0.050~30.000
0.01
delay
for
81U.UF4.En
of
of
underfrequency protection
Enabling/disabling
17
stage
stage
underfrequency protection
0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
change
18
81U.UF4.En_df/dt_Blk
0 or 1
to
block
stage
of
underfrequency protection
0: disable
1: enable
3 Operation Theory
binary output contact, which can ensure the circuit breaker is still tripped in case the secondary
circuit between the device and the circuit breaker is abnormal, to avoid undesired tripping of
breaker failure protection and the expansion of the affected area. Instantaneous re-tripping
function does not block AR.
When both the phase-segregated tripping contact from line protection and the corresponding
phase overcurrent element operate, or both the three-phase tripping contact and any phase
overcurrent element operate, breaker failure protection will send three-phase tripping command to
trip local circuit breaker after time delay of [50BF.t1_Op] and trip all adjacent circuit breakers after
time delay of [50BF.t2_Op].
When the protection element except undervoltage element within this device operates and issues
tripping signal, breaker failure protection will also be initiated.
Taking into account that the faulty current is too small for generator or transformer fault, the
sensitivity of phase current element may not meet the requirements, zero-sequence current
criterion and negative-sequence current criterion are provided in addition to the phase overcurrent
element for breaker failure protection initiated by input signal [50BF.ExTrp3P_GT] from generator
and transformer protection. They can be enabled or disabled by logic settings [50BF.En_3I0_3P]
and [50BF.En_I2_3P] respectively.
For some special fault (for example, mechanical protection or overvoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
order to make breaker failure protection can also operate under the above situation, an input
signal [50BF.ExTrp_WOI] is equipped to initiate breaker failure protection, once the input signal is
energized, normally closed auxiliary contact of circuit breaker is chosen in addition to breaker
failure current check to trigger breaker failure timer. The device takes current as priority with CB
auxiliary contact (52b) as an option criterion for breaker failure check.
50BF.On
50BF.ExTrp3P_GT
50BF.Op_ReTrpA
50BF.ExTrp_WOI
50BF.Op_ReTrpB
50BF.ExTrpA
50BF.Op_ReTrpC
50BF.ExTrpB
50BF.Op_ReTrp3P
50BF.ExTrpC
50BF.Op_t1
50BF.En
50BF.Op_t2
50BF.Blk
3-152
3 Operation Theory
Input Signal
Description
50BF.ExTrp3P_L
50BF.ExTrp3P_GT
50BF.ExTrpA
50BF.ExTrpB
50BF.ExTrpC
50BF.ExTrp_WOI
50BF.En
50BF.Blk
No.
Output Signal
50BF.On
50BF.Op_ReTrpA
50BF.Op_ReTrpB
50BF.Op_ReTrpC
50BF.Op_ReTrp3P
50BF.Op_t1
50BF.Op_t2
3-153
3 Operation Theory
3.17.5 Logic
SIG
50BF.En
EN
[50BF.En]
SIG
50BF.Blk
SIG
50BF.On
SIG
FD.Pkp
EN
[50BF.En_ReTrp]
EN
[50BF.En_3I0_1P]
SET
3I0>[50BF.3I0_Set]
SIG
BFI_A
&
50BF.On
&
>=1
>=1
&
&
>=1
BI
[50BF.ExTrpA]
SET
IA>[50BF.I_Set]
SIG
BFI_B
>=1
&
[50BF.ExTrpB]
SET
IB>[50BF.I_Set]
SIG
BFI_C
>=1
&
[50BF.ExTrpC]
SET
IC>[50BF.I_Set]
SIG
BFI_3P
BI
[50BF.ExTrp3P_L]
[50BF.t_ReTrp] 0ms
[50BF.Op_ReTrpB]
[50BF.t_ReTrp] 0ms
[50BF.Op_ReTrpC]
&
>=1
BI
[50BF.Op_ReTrpA]
&
>=1
BI
[50BF.t_ReTrp] 0ms
>=1
>=1
>=1
&
>=1
BI
[50BF.ExTrp3P_GT]
BI
[50BF.ExTrp_WOI]
EN
[50BF.En_3I0_3P]
[50BF.Op_ReTrp3P]
&
>=1
&
SET
3I0>[50BF.3I0_Set]
EN
[50BF.En_I2_3P]
SET
I2>[50BF.I2_Set]
EN
[50BF.En_CB_Ctrl]
BI
[52b_PhA]
&
>=1
>=1
&
&
&
[50BF.t1_Op]
0ms
[50BF.Op_t1]
[50BF.t2_Op]
0ms
[50BF.Op_t2]
&
&
BI
[52b_PhB]
BI
[52b_PhC]
SIG
50BF.On
SIG
FD.Pkp
&
3-154
3 Operation Theory
3.17.6 Settings
Table 3.17-2 Settings of breaker failure protection
No.
Name
Range
Step
Unit
Remark
Current setting of phase current
criterion for BFP
Current setting of zero-sequence
current criterion for BFP
Current
setting
of
negative-sequence
current
criterion for BFP
50BF.I_Set
(0.050~30.000 )In
0.001
50BF.3I0_Set
(0.050~30.000 )In
0.001
50BF.I2_Set
(0.050~30.000 )In
0.001
50BF.t_ReTrp
0.000~10.000
0.001
50BF.t1_Op
0.000~10.000
0.001
50BF.t2_Op
0.000~10.000
0.001
50BF.En
0 or 1
50BF.En_ReTrp
0 or 1
50BF.En_3I0_1P
0 or 1
10
50BF.En_3I0_3P
0 or 1
11
50BF.En_I2_3P
0 or 1
12
50BF.En_CB_Ctrl
0 or 1
3 Operation Theory
greater heat to lead temperature increase and if the temperature reaches too high values the
equipment might be damaged.
Thermal overload protection estimates the internal heat content (temperature) continuously. This
estimation is made by using a thermal model with two time constants, which is based on current
measurement.
When the temperature increases to the alarm value, the protection issues alarm signals to remind
the operator for attention, and if the temperature continues to increase to the trip value, the
protection sends trip command to disconnect the protected line.
Two stages for alarm purpose and two stages for trip purpose
The device provides a thermal overload model which is based on the IEC60255-8 standard. The
thermal overload formulas are shown as below.
1.
I2
T ln 2
I (k I B ) 2
2.
T ln
I 2 I p2
I 2 (k I B ) 2
Where:
T = Time to operate (in seconds)
3-156
3 Operation Theory
Refer to IEC60255-8
Ip
P=
IB
P = 0.0
P = 0.6
P = 0.8
P = 0.9
kIB
The hot start characteristic is adopted in the device. The calculation is carried out at zero of Ip, so
users need not to set the value of Ip.
Tripping outputs of the protection is controlled by current, even if the thermal accumulation value is
greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclosure, will operate.
49.On
49.En
49.St
49.Blk
49-1.Alm
49-1.Op
49-2.Alm
49-2.Op
Input Signal
49.Clr_Cmd
49.En
49.Blk
Description
Input signal of clear thermal accumulation value
Thermal overload protection enabling input, it is triggered from binary input or
programmable logic etc.
Thermal overload protection blocking input, it is triggered from binary input or
3-157
3 Operation Theory
programmable logic etc.
No.
Output Signal
Description
49.On
49.St
49-1.Op
49-2.Op
49-1.Alm
49-2.Alm
3.18.5 Logic
SIG
49.En
SIG
49.Blk
EN
[49-1.En_Trp]
EN
[49-1.En_Alm]
SIG
FD.Pkp
&
&
49.On
>=1
&
49.St
&
Timer
t
49-1.Op
t
SIG
I3P
Timer
t
&
SET
[49.Ib_Set]
BI
[49.Clr_Cmd]
49-1.Alm
SIG
49.En
SIG
49.Blk
EN
[49-2.En_Trp]
EN
[49-2.En_Alm]
SIG
FD.Pkp
&
&
49.On
>=1
&
49.St
&
Timer
t
49-2.Op
t
SIG
I3P
&
SET
[49.Ib_Set]
BI
[49.Clr_Cmd]
Timer
t
49-2.Alm
3-158
3 Operation Theory
3.18.6 Settings
Table 3.18-2 Settings of thermal overload protection
No.
Name
Range
Step
Unit
49-1.K
1.000~3.000
0.001
49-2.K
1.000~3.000
0.001
49.Ib_Set
(0.050~30.000 )In
0.001
49.Tau
0.100~100.000
0.001
min
49-1.En_Alm
0 or 1
49-1.En_Trp
0 or 1
49-2.En_Alm
0 or 1
49-2.En_Trp
0 or 1
Remark
The factor setting for stage 1 of
thermal overload protection which
is associated to the thermal state
formula
The factor setting for stage 2 of
thermal overload protection which
is associated to the thermal state
formula
The reference current setting of the
thermal overload protection
The time constant setting of the
IDMT overload protection
Enabling/disabling stage 1 of
thermal overload protection for
alarm purpose
0: disable
1: enable
Enabling/disabling stage 1 of
thermal overload protection for trip
purpose
0: disable
1: enable
Enabling/disabling stage 2 of
thermal overload protection for
alarm purpose
0: disable
1: enable
Enabling/disabling stage 2 of
thermal overload protection for trip
purpose
0: disable
1: enable
3-159
3 Operation Theory
CT1
CT2
Bus
Bus
To the device
Line
Line
50STB.On
50STB.En2
50STB.Op
50STB.Blk
50STB.St
50STB.89b_DS
50STB.StA
50STB.StB
50STB.StC
Input Signal
50STB.En1
50STB.En2
50STB.Blk
50STB.89b_DS
No.
Output Signal
Description
Stub overcurrent protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Stub overcurrent protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Stub overcurrent protection blocking input, it is triggered from binary input or
programmable logic etc.
Normally closed auxiliary contact of line disconnector
Description
50STB.On
50STB.Op
3-160
3 Operation Theory
3
50STB.St
50STB.StA
50STB.StB
50STB.StC
3.19.4 Logic
Only one stage is available to stub overcurrent protection. Based on calculating summation
current from dual CTs, the logic scheme of stub overcurrent protection is shown as Figure 3.19-2.
SIG
50STB.En1
SIG
50STB.En2
SIG
50STB.Blk
EN
[50STB.En]
SIG
FD.Pkp
SIG
50STB.89b_DS
&
&
50STB.On
&
>=1
[50STB.t_Op]
50STB.Op
50STB.St
&
50STB.StA
SET
Ia>[50STB.I_Set]
&
50STB.StB
SET
Ib>[50STB.I_Set]
&
50STB.StC
SET
Ic>[50STB.I_Set]
3.19.5 Settings
Table 3.19-2 Settings of stub overcurrent protection
No.
Name
Range
Step
Unit
50STB.I_Set
(0.050~30.000)In
0.001
50STB.t_Op
0.000~10.000
0.001
Remark
Current setting of stub overcurrent
protection
Time delay of stub overcurrent
protection
Enabling/disabling stub overcurrent
50STB.En
protection
0 or 1
1: enable
0: disable
3-161
3 Operation Theory
50DZ.On
50DZ.En2
50DZ.Op
50DZ.Blk
50DZ.St
50DZ.Init
Input Signal
Description
50DZ.En1
Dead zone protection enabling input 1, it can be binary inputs or logic link.
50DZ.En2
Dead zone protection enabling input 2, it can be binary inputs or logic link.
50DZ.Blk
50DZ.Init
No.
Dead zone protection blocking input, such as function blocking binary input. When
the input is 1, dead zone protection is reset and time delay is cleared.
Initiation signal input of the dead zone protection.
Output Signal
Description
50DZ.On
50DZ.St
3-162
3 Operation Theory
3
50DZ.Op
3.20.5 Logic
EN
[50DZ.En]
SIG
50DZ.En1
SIG
50DZ.En2
SIG
50DZ.Blk
SIG
FD.Pkp
BI
[52b_PhA]
BI
[52b_PhB]
BI
[52b_PhC]
SET
Ia > [50DZ.I_Set]
SET
Ib > [50DZ.I_Set]
SET
Ic > [50DZ.I_Set]
SIG
&
&
50DZ.On
&
&
50DZ.St
&
>=1
[50DZ.t_Op]
&
0ms
50DZ.Op
50DZ.Init
3.20.6 Settings
Table 3.20-2 Settings of dead zone protection
No.
Name
Range
Step
Unit
Remark
Current
50DZ.I_Set
(0.050~30.000)In
0.001
setting
for
dead
zone
50DZ.t_Op
0.000~10.000
0.001
50DZ.En
0 or 1
dead
zone
protection.
1: enable
0: disable
3-163
3 Operation Theory
system, which will result in overheat of the generator or the motor. With the load current increasing,
overcurrent elements based on zero-sequence current or negative-sequence current may operate.
Pole discrepancy protection is required to operate before the operation of these overcurrent
elements.
62PD.On
62PD.En2
62PD.Op
62PD.Blk
62PD.St
Input Signal
62PD.En1
62PD.En2
62PD.Blk
No.
Description
Pole discrepancy protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Pole discrepancy protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Pole discrepancy protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
62PD.On
62PD.Op
62PD.St
3.21.5 Logic
Phase-segregated circuit breaker auxiliary contacts are connected to the device. When the state
of three phase-segregated circuit breaker auxiliary contacts are inconsistent, pole discrepancy
protection will be started and initiate output after a time delay [62PD.t_Op].
Pole discrepancy protection can be blocked by external input signal [62PD.Blk]. In general, this
input signal is usually from the output of 1-pole AR initiation, so as to prevent pole discrepancy
protection from operation during 1-pole AR initiation.
3-164
3 Operation Theory
SIG
62PD.En1
SIG
62PD.En2
EN
[62PD.En]
BI
[62PD.Blk]
SIG
BI
&
&
62PD.On
&
FD.Pkp
62PD.St
&
[62PD.t_Op]
[62PD.In_PD]
EN
[62PD.En_3I0/I2_Ctrl]
SET
3I0>[62PD.3I0_Set]
SET
I2>[62PD.I2_Set]
0ms
62PD.Op
>=1
>=1
The signal 62PD.In_PD is input signal of pole discrepancy status, which is always from PD signal
of circuit breaker position supervison module. When the states of three auxiliary contacts of
phase-segregate circuit breaker are inconsistent, the signal is energized.
3.21.6 Settings
Table 3.21-2 Settings of pole discrepancy protection
No.
Name
Range
Step
Unit
62PD.3I0_Set
(0.050~30.000 )In
0.001
62PD.I2_Set
(0.050~30.000 )In
0.001
62PD.t_Op
0.000~600.000
0.001
62PD.En
0 or 1
62PD.En_3I0/I2_Ctrl
0 or 1
Remark
Current setting of residual current
criterion for pole discrepancy
protection
Current
setting
of
negative-sequence current criterion
for pole discrepancy protection
Time delay of pole discrepancy
protection
Enabling/disabling
pole
discrepancy protection
0: disable
1: enable
Enabling/disabling
residual
current
criterion
and
negative-sequence current criterion
for pole discrepancy protection
0: disable
1: enable
3 Operation Theory
46BC.On
46BC.En2
46BC.St
46BC.Blk
46BC.Op
46BC.Alm
Input Signal
46BC.En1
46BC.En2
Description
Enable broken conductor protection input 1, it is triggered from binary input or
programmable logic etc.
Enable broken conductor protection input 2, it is triggered from binary input or
programmable logic etc.
3-166
3 Operation Theory
3
46BC.Blk
No.
Output Signal
Description
46BC.On
46BC.St
46BC.Op
46BC.Alm
3.22.5 Logic
SIG
[46BC.En1]
&
&
SIG
[46BC.En2]
SIG
[46BC.Blk]
SET
Ia>[46BC.I_Min]
46BC.On
46BC.St
&
[46BC.t_Op] 0ms
>=1
SET
Ib>[46BC.I_Min]
SET
Ic>[46BC.I_Min]
SET
SET
&
I2/I1>[46BC.I2/I1_Set]
46BC.Op
[46BC.En_Trp]
&
46BC.Alm
SET
[46BC.En_Alm]
3.22.6 Settings
Table 3.22-2 Settings of broken conductor protection
No.
Name
Range
Step
Unit
46BC.I2/I1_Set
0.20~1.00
0.001
46BC.t_Op
0.000~600.000
0.001
46BC.I_Min
(0.050~30.000)In
0.001
46BC.En_Trp
0 or 1
46BC.En_Alm
0 or 1
Remark
negative-sequence
current
to
positive-sequence current of broken
conductor protection
Time delay of broken conductor
protection
Minimum operation current of broken
conductor protection
Enabling/disabling broken conductor
protection to operate to trip
0: disable
1: enable
Enabling/disabling broken conductor
protection to operate to alarm
0: disable
1: enable
3-167
3 Operation Theory
3.23 Synchrocheck
3.23.1 General Application
The purpose of synchrocheck is to ensure two systems are synchronism before they are going to
be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus auto-reclosing and
manual closing are applied with the synchrocheck to avoid this situation and maintain the system
stability. The synchrocheck includes synchronism check and dead charge check.
UB
Figure 3.23-1 shows the characteristics of synchronism check element used for the auto-reclosing
if both line and busbar are live. The synchronism check element operates if voltage difference,
phase angle difference and frequency difference are all within their setting values.
1.
UB[25.U_Lv]
3-168
3 Operation Theory
UL[25.U_Lv]
|UB-UL|[25.U_Diff]
2.
UBULcos0
UBULsin([25.phi_Diff])UBULsin([25.phi_Diff])
Where,
is phase difference between UB and UL
3.
|f(UB)-f(UL)|[25.f_Diff]
If frequency check is disabled (i.e. [25.En_fDiffChk] is set as 0), a detected maximum slip cycle
can also be determined by the following equation based on phase difference setting and the
synchronism check time setting:
f =[25.phi_Diff]/(180[25.t_SynChk])
Where:
f is slip cycle
If frequency check is enabled (i.e. [25.En_fDiffChk] is set as 1), then [25.t_SynChk] can be set to
be a very small value (default value is 50ms).
3.23.2.1 Synchronism Voltage Circuit Failure Supervision
If synchronism voltage from line VT or busbar VT is used for auto-reclosing with synchronism or
dead line or busbar check, the synchronism voltage is monitored.
If the circuit breaker is in closed state (52b of three phases are de-energized), but the synchronism
voltage is lower than the setting [25.U_Lv], it means that synchronism voltage circuit fails and an
alarm [25.Alm_VTS_UB] or [25.Alm_VTS_UL] will be issued with a time delay of 10s.
If auto-reclosing is disabled, or the logic setting [25.En_NoChk] is set as 1, synchronism voltage
is not required and synchronism voltage circuit failure supervision will be disabled.
When synchronism voltage circuit failure is detected, function of synchronism check and dead
check in auto-reclosing logic will be disabled.
After synchronism voltage reverted to normal condition, the alarm will be reset automatically with a
time delay of 10s.
3-169
3 Operation Theory
SIG
FD.Pkp
SIG
79.Inprog
SIG
UL<[25.U_Lv]
BI
>=1
&
10s
10s
>=1
&
25.MCB_VT_UL
EN
25.En_SynChk
SIG
25.En_DdL_DdB
SIG
25.En_DdL_LvB
SIG
25.En_LvL_DdB
SIG
25.Blk_VTS_UL
25.Alm_VTS_UL
>=1
&
SIG
FD.Pkp
SIG
79.Inprog
SIG
UB<[25.U_Lv]
BI
>=1
&
10s
10s
>=1
&
25.Alm_VTS_UB
25.MCB_VT_UB
EN
25.En_SynChk
SIG
25.En_DdL_DdB
SIG
25.En_DdL_LvB
SIG
25.En_LvL_DdB
SIG
25.Blk_VTS_UB
>=1
&
3-170
3 Operation Theory
25.Ok_fDiffChk
25.Blk_SynChk
25.Ok_UDiffChk
25.Blk_DdChk
25.Ok_phiDiffChk
25.Start_Chk
25.Ok_DdL_DdB
25.Blk_VTS_UB
25.Ok_DdL_LvB
25.Blk_VTS_UL
25.Ok_LvL_DdB
25.MCB_VT_UB
25.Chk_LvL
25.MCB_VT_UL
25.Chk_DdL
25.Chk_LvB
25.Chk_DdB
25.Ok_DdChk
25.Ok_SynChk
25.Ok_Chk
25.Alm_VTS_UL
25.Alm_VTS_UB
f_Prot
f_Syn
U_Diff
f_Diff
Phi_Diff
Input Signal
Description
25.Blk_Chk
25.Blk_SynChk
25.Blk_DdChk
25.Start_Chk
25.Blk_VTS_UB
25.Blk_VTS_UL
Input signal of blocking synchronism check for AR. If the value is 1, the output of
synchronism check is 0.
Input signal of blocking dead charge check for AR.
Input signal of starting synchronism check, usually it was starting signal of AR
from auto-reclosing module.
3-171
3 Operation Theory
7
25.MCB_VT_UB
25.MCB_VT_UL
No.
Output Signal
Description
To indicate that frequency difference condition for synchronism check of AR is
25.Ok_fDiffChk
25.Ok_UDiffChk
25.Ok_phiDiffChk
25.Ok_DdL_DdB
25.Ok_DdL_LvB
25.Ok_LvL_DdB
25.Chk_LvL
25.Chk_DdL
25.Chk_LvB
10
25.Chk_DdB
11
25.Ok_DdChk
12
25.Ok_SynChk
13
25.Ok_Chk
14
25.Alm_VTS_UB
15
25.Alm_VTS_UL
16
f_Prot
17
f_Syn
18
U_Diff
19
f_Diff
20
phi_Diff
3.23.5 Logic
These logic diagrams give the introduction to the working principles of the synchronism check and
dead charge check.
3.23.5.1 Synchronism Check Logic
The frequency difference, voltage difference, and phase difference of voltages from both sides of
the circuit breaker are calculated in the device, they are used as input conditions of the
synchronism check.
When the synchronism check function is enabled and the voltages of both ends meets the
requirements of the voltage difference, phase difference, and frequency difference, and there is no
synchronism check blocking signal, it is regarded that the synchronism check conditions are met.
3-172
3 Operation Theory
SIG
25.Blk_Chk
SIG
25.Blk_SynChk
EN
[25.En_SynChk]
SIG
25.Start_Chk
SIG
UB>[25.U_Lv]
SIG
UL>[25.U_Lv]
SIG
25.Ok_UDiff
SIG
25.Ok_phiDiff
SIG
25.Ok_fDiff
>=1
&
&
&
50ms
0ms
[25.t_SynChk]
&
0ms
25.Ok_SynChk
25.Blk_Chk
SIG
25.Blk_DdChk
SIG
25.Start_Chk
EN
[25.En_DdL_DdB]
SIG
Uref<[25.U_Dd]
SIG
Usyn>[25.U_Lv]
EN
[25.En_DdL_LvB]
SIG
Uref<[25.U_Dd]
SIG
Usyn>[25.U_Lv]
EN
[25.En_LvL_DdB]
SIG
Uref>[25.U_Lv]
SIG
Usyn<[25.U_Dd]
SIG
25.Alm_VTS_UB
SIG
25.Alm_VTS_UL
>=1
&
&
[25.t_DdChk]
>=1
0ms
25.Ok_DdChk
&
25.Ok_DdL_DdB
&
&
25.Ok_DdL_LvB
&
&
25.Ok_LvL_DdB
&
>=1
3 Operation Theory
25.Ok_SynChk
EN
25.En_NoChk
SIG
25.Ok_DdChk
>=1
25.Ok_Chk
This device comprises two synchrocheck modules, correspond to circuit breaker 1 and circuit
breaker 2 respectively.
3.23.6 Settings
Table 3.23-2 Settings of synchrocheck
No.
Name
Range
Step
Unit
Remark
Voltage selecting mode of line.
0: A-phase voltage
1: B-phase voltage
25.Opt_Source_UL
0~5
2: C-phase voltage
3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage
Voltage selecting mode of bus.
0: A-phase voltage
1: B-phase voltage
25.Opt_Source_UB
0~5
2: C-phase voltage
3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage
25.U_Dd
0.05Un~0.8Un
0.001
25.U_Lv
0.5Un~Un
0.001
25.K_Usyn
0.20-5.00
25.phi_Diff
0~ 89
Compensation
Deg
25.phi_Comp
0~359
for
Phase
difference
Deg
limit
of
coefficient
synchronism voltage
difference
for
phase
between
two
synchronism voltages
8
25.f_Diff
0.02~1.00
0.01
25.U_Diff
0.02Un~0.8Un
10
25.t_DdChk
0.010~25.000
3-174
Hz
Frequency
difference
limit
of
difference
limit
of
3 Operation Theory
condition
11
25.t_SynChk
0.010~25.000
Time
delay
to
confirm
12
25.En_fDiffChk
frequency
difference check
0 or 1
0: disable
1: enable
Enabling/disabling
13
25.En_SynChk
synchronism
check
0 or 1
0: disable
1: enable
Enabling/disabling dead line and
14
25.En_DdL_DdB
0 or 1
0: disable
1: enable
Enabling/disabling dead line and
15
25.En_DdL_LvB
0 or 1
0: disable
1: enable
Enabling/disabling live line and
16
25.En_LvL_DdB
0 or 1
0: disable
1: enable
Enabling/disabling AR without any
17
25.En_NoChk
check
0 or 1
0: disable
1: enable
3-175
3 Operation Theory
3-176
3 Operation Theory
79.On
79.Blk
79.Off
79.Sel_1PAR
79.Close
79.Sel_3PAR
79.Ready
79.Sel_1P/3PAR
79.AR_Blkd
79.Trp
79.Active
79.Trp3P
79.Inprog
79.TrpA
79.Inprog_1P
79.TrpB
79.Inprog_3P
79.TrpC
79.Inprog_3PS1
79.LockOut
79.Inprog_3PS2
79.PLC_Lost
79.Inprog_3PS3
79.WaitMaster
79.Inprog_3PS4
79.CB_Healthy
79.WaitToSlave
79.Clr_Counter
79.Perm_Trp1P
79.Ok_Chk
79.Perm_Trp3P
79.Rcls_Status
79.Fail_Rcls
79.Succ_Rcls
79.Fail_Chk
79.Mode_1PAR
79.Mode_3PAR
79.Mode_1/3PAR
Input Signal
79.En
79.Blk
Description
Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1,
enabling AR will be controlled by the external signal via binary input
Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1,
disabling AR will be controlled by the external input
3-177
3 Operation Theory
Input signal for selecting 1-pole AR mode of corresponding circuit
79.Sel_1PAR
79.Sel_3PAR
79.Sel_1P/3PAR
79.Trp
79.Trp3P
79.TrpA
79.TrpB
10
79.TrpC
breaker
Input signal for selecting 3-pole AR mode of corresponding circuit
breaker
Input signal for selecting 1/3-pole AR mode of corresponding circuit
breaker
79.LockOut
12
79.PLC_Lost
13
79.WaitMaster
14
79.CB_Healthy
15
79.Clr_Counter
16
79.Ok_Chk
No.
Input signal of indicating the alarm signal that signal channel is lost
Input signal of waiting for reclosing permissive signal from master
AR (when reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
perform the close function
Output Signal
Description
79.On
79.Off
79.Close
79.Ready
79.AR_Blkd
79.Active
79.Inprog
79.Inprog_1P
79.Inprog_3P
10
79.Inprog_3PS1
11
79.Inprog_3PS2
12
79.Inprog_3PS3
13
79.Inprog_3PS4
14
79.WaitToSlave
15
79.Perm_Trp1P
16
79.Perm_Trp3P
17
79.Rcls_Status
3-178
3 Operation Theory
1: AR is in progress.
2: AR is successful.
18
79.Fail_Rcls
Auto-reclosing fails
19
79.Succ_Rcls
Auto-reclosing is successful
20
79.Fail_Chk
21
79.Mode_1PAR
22
79.Mode_3PAR
23
79.Mode_1/3PAR
24
79.N_Total_Rcls
25
79.N_1PS1
26
79.N_3PS1
27
79.N_3PS2
28
79.N_3PS3
29
79.N_3PS4
3.24.5 Logic
3.24.5.1 AR Ready
For the first reclosing of multi-shot AR, AR mode can be 1-pole AR or 3-pole AR, however, the
selection is valid only to the first reclosing, after that it can only be 3-pole AR.
When logic setting [79.SetOpt] is set as 1, AR mode is determined by logic settings. When logic
setting [79.SetOpt] is set as 0, AR mode is determined by external signal via binary inputs.
An auto-reclosure must be ready to operate before performing reclosing. The output signal
[79.Ready] means that the auto-reclosure can perform at least one time of reclosing function, i.e.,
breaker open-close-open.
When the device is energized or after the settings are modified, the following conditions must be
met before the reclaim time begins:
1.
AR function is enabled.
2.
The circuit breaker is ready, such as, normal storage energy and no low pressure signal.
3.
The duration of the circuit breaker in closed position before fault occurrence is not less than
the setting [79.t_CBClsd].
4.
After the auto-reclosure operates, the auto-reclosure must reset, i.e., [79.Active]=0, in addition to
the above conditions for reclosing again.
The logic of AR ready is shown in Figure 3.24-2.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After fault is cleared, the tripping command will drop off immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
3-179
3 Operation Theory
SIG
79.LockOut
SIG
1-pole AR Initiation
SIG
En
[79.En_PDF_Blk]
SIG
79.Sel_1PAR
[79.t_PersistTrp] 0ms
>=1
0ms [79.t_DDO_BlkAR]
[79.t_SecFault] 0ms
&
&
>=1
&
En
[79.N_Rcls]=1
SIG
SIG
Phase A open
SIG
Phase B open
79.AR_Blkd
>=1
&
&
>=1
&
SIG
Phase C open
The input signal [79.CB_Healthy] must be energized before auto-reclosure gets ready. Because
most circuit breakers can finish one complete process: open-closed-open, it is necessary that
circuit breaker has enough energy before reclosing. When the time delay of AR is exhausted, AR
will be blocked if the input signal [79.CB_Healthy] is still not energized within time delay
[79.t_CBReady]. If this function is not required, the input signal [79.CB_Healthy] can be not to
configure, and its state will be thought as 1 by default.
In orde to block AR reliably even if the signal of manually open circuit breaker not connected to the
input of blocking AR, when the circuit breaker is open by manually and there is CB position input
under normal conditions, AR will be blocked with the time delay of 100ms if AR is not initated and
no any trip signal.
When auto-reclosure is blocked, auto-reclosing failure, synchrocheck failure or last shot is
reached, or when the internal blocking condition of AR is met (such as, zone 3 of distance
protection operates, the device operates for multi-phase fault, three-phase fault and so on. These
flags of blocking AR have been configured in the device, additional configuration is not required.),
auto-reclosure will be discharged immediately and next auto-reclosing will be disabled.
When the input signal [79.LockOut] is energized, auto-reclosure will be blocked immediately. The
blocking flag of AR will be also controlled by the internal blocking condition of AR. When the
blocking flag of AR is valid, auto-reclosure will be blocked immediately.
3-180
3 Operation Theory
SIG
3 CB closed
[79.t_CBClsd]
SIG
79.Active
>=1
SIG
100ms
&
>=1
&
&
100ms
SIG
79.Ready
79.Inprog
[79.CB_Healthy]
0ms
SIG
79.AR_Blkd
>=1
SIG
BlockAR
SIG
79.Fail_Rcls
SIG
79.Fail_Chk
SIG
EN
[79.En]
EN
[79.En_ExtCtrl]
BI
[79.t_CBReady]
&
>=1
&
>=1
&
>=1
79.On
&
SIG
79.En
SIG
79.Blk
&
When a fault occurs under pole disagreement condition, blocking AR can be enabled or disabled.
The time delay [79.t_SecFault] is used to discriminate another fault which begins after 1-pole AR
initiated. AR will be blocked if another fault happens after this time delay if the logic setting
[79.En_PDF_Blk] is set as 1, and 3-pole AR will be initiated if [79.En_PDF_Blk] is set as 1.
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop off with a time delay [79.t_DDO_BlkAR] after blocking signal disappears.
When one-shot and 1-pole AR is enabled, auto-reclosure will be blocked immediately if there are
binary inputs of multi-phase CB position is energized.
When any protection element operates to trip, the device will output a signal [79.Active] until AR
drop off (Reset Command). Any tripping signal can be from external protection device or internal
protection element.
AR function can be enabled by internal logic settings of AR mode or external signal via binary
inputs in addition to internal logic setting [79.En]. When logic setting [79.En_ExtCtrl] is set as 1,
AR enable are determined by external signal via binary inputs and logic settings. When logic
setting [79.En_ExtCtrl] set as 0, AR enable are determined only by logic settings.
For one-shot reclosing, if 1-pole AR mode is selected, auto-reclosure will reset when there is
three-phase tripping signal or input signal of multi-phase open position.
3-181
3 Operation Theory
SIG
79.On
SIG
79.Mode_3PAR
SIG
79.Ready
SIG
79.Trp
SIG
79.Trp3P
SIG
79.TrpA
SIG
79.TrpB
SIG
79.TrpC
SIG
Phase A open
SIG
Phase B open
SIG
Phase C open
Logic
79.Perm_Trp3P
79.Perm_Trp1P
When AR is enabled, the device will output the signal [79.Perm_Trp3P] if AR is not ready, or AR
mode is set as 3-Pole AR, or another fault occurs after the circuit breaker is open.
3.24.5.2 AR Initiation
AR mode can be selected by external signal via binary inputs or internal logic settings. If the logic
setting [79.SetOpt] set as 1, AR mode is determined by the internal logic settings. If the logic
settings [79.SetOpt] set as 0, AR mode is determined by the external inputs.
1.
AR can be initiated by tripping signal of line protection, and the tripping signal may be from internal
trip signal or external trip signal.
When selecting 1-pole AR or 1/3-pole AR, line single-phase fault will trigger 1-pole AR. When AR
is ready to reclosing (79.Ready=1) and the single-phase tripping command is received, this
single-phase tripping command will be kept in the device, and 1-pole AR will be initiated after the
single-phase tripping command drops off. The single-phase tripping command kept in the device
will be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is
shown in Figure 3.24-4.
3-182
3 Operation Theory
SIG
Reset Command
&
>=1
SIG
Single-phase Trip
&
SIG
&
79.Ready
SIG
79.Sel_1PAR
SIG
79.Sel_1P/3PAR
1-pole AR Initiation
>=1
When selecting 3-pole AR or 1/3-pole AR, three-phase tripping will trigger 3-pole AR. When AR is
ready to reclosing (79.Ready=1) and the three-phase tripping command is received, this
three-phase tripping command will be kept in the device, and 3-pole AR will be initiated after the
three-phase tripping command drops off. The three-phase tripping command kept in the device will
be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is shown
in Figure 3.24-5.
SIG
Reset Command
&
>=1
SIG
Three-phase Trip
&
SIG
&
79.Ready
SIG
79.Sel_3PAR
SIG
79.Sel_1P/3PAR
3-pole AR Initiation
>=1
2.
AR initiated by CB state
A logic setting [79.En_CBInit] is available for selection that AR is initiated by CB state. Under
normal conditions, when AR is ready to reclosing (79.Ready=1), AR will be initiated if circuit
breaker is open and corresponding phase current is nil. AR initiated by CB state can be divided
into initiating 1-pole AR and 3-pole AR, their logics are shown in Figure 3.24-6 and Figure 3.24-7
respectively. Usually normally closed contact of circuit breaker is used to reflect CB state.
3-183
3 Operation Theory
SIG
Phase A open
SIG
Phase B open
>=1
&
&
&
&
SIG
Phase C open
EN
[79.En_CBInit]
SIG
79.Ready
SIG
79.Sel_1PAR
SIG
79.Sel_1P/3PAR
1-pole AR Initiation
>=1
SIG
Phase A open
SIG
Phase B open
SIG
Phase C open
EN
[79.En_CBInit]
SIG
79.Ready
EN
[79.Sel_3PAR]
EN
[79.Sel_1P/3PAR]
&
&
&
3-pole AR Initiation
>=1
3.24.5.3 AR Reclosing
After AR is initiated, the device will output the initiating contact of AR. For 1-pole AR, in order to
prevent pole discrepancy protection from maloperation under pole discrepancy conditions, the
contact of 1-pole AR initiation can be used to block pole discrepancy protection.
When the dead time delay of AR expires after AR is initiated, as for 1-pole AR, the result of
synchronism check will not be judged, and reclosing command will be output directly. As far as the
3-pole AR, if the synchronism check is enabled, the release of reclosing command shall be subject
to the result of synchronism check. After the dead time delay of AR expires, if the synchronism
check is still unsuccessful within the time delay [79.t_wait_Chk], the signal of synchronism check
failure (79.Fail_Syn) will be output and the AR will be blocked. If 3-pole AR with no-check is
enabled, the condition of synchronism check success (25.Ok_Chk) will always be established.
And the signal of synchronism check success (25.Ok_Chk) from the synchronism check logic can
be applied by auto-reclosing function inside the device or external auto-reclosure device.
3-184
3 Operation Theory
79.Inprog_1P
>=1
79.Inprog
79.Inprog_3P
SIG
1-pole AR Initiation
[79.t_Dd_1PS1]
0ms
SIG
3-pole AR Initiation
[79.t_Dd_3PS1]
0ms
>=1
AR Pulse
&
&
[79.t_Wait_Chk] 0ms
SIG
79.Fail_Chk
79.Ok_Chk
In the process of channel abnormality, an internal fault occurs on the transmission line, backup
protection at both ends of line will operate to trip the circuit breaker of each end. The operation
time of backup protection at both ends of the line is possibly non-accordant, whilst the time delay
of AR needs to consider the arc-extinguishing and insulation recovery ability for transient fault, so
the time delay of AR shall be considered comprehensively according to the operation time of the
device at both ends. When the communication channel of main protection is abnormal (input
signal [79.PLC_Lost] is energized), and the logic setting [79.En_AddDly] is set as 1, then the
dead time delay of AR shall be equal to the original dead time delay of AR plus the extra time
delay [79.t_AddDly], so as to ensure the recovery of insulation intensity of fault point when
reclosing after transient fault. This extra time delay [79.t_AddDly] is only valid for the first shot AR.
>=1
SIG
BI
&
&
[79.PLC_Lost]
SIG
79.Active
EN
[79.En_AddDly]
&
Extend AR time
Reclosing pulse length may be set through the setting [79.t_PW_AR]. For the circuit breaker
without anti-pump interlock, a logic setting [79.En_CutPulse] is available to control the reclosing
pulse. When this function is enabled, if the device operates to trip during reclosing, the reclosing
pulse will drop off immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing
command is issued, AR will drop off with time delay [79.t_Reclaim], and can carry out next
reclosing.
3-185
3 Operation Theory
SIG
SIG
WaitMasterValid
&
0ms
50ms
0ms
[79.t_PW_AR]
>=1
AR Pulse
SIG
Single-phase Trip
SIG
Three-phase Trip
EN
[79.En_CutPulse]
79.AR_Out
>=1
&
&
>=1
&
SIG
[79.t_Reclaim]
79.AR_Out
0ms
Reset Command
The reclaim timer defines a time from the issue of the reclosing command, after which the
reclosing function resets. Should a new trip occur during this time, it is treated as a continuation of
the first fault. The reclaim timer is started when the CB closing command is given.
SIG
1-pole AR Initiation
>=1
0ms
SIG
3-pole AR Initiation
SIG
79.Fail_Rcls
SET
[79.Opt_Priority]=High
[79.t_Fail]
>=1
&
79.WaitToSlave
The output signal 79.WaitToSlave is usually configured to the signal 79.WaitMaster of slave AR.
Slave AR is permissible to reclosing only if master AR is reclosed successfully.
3.24.5.4 Reclosing Failure and Success
For transient fault, the fault will be cleared after the device operates to trip. After the reclosing
command is issued, AR will drop off after time delay [79.t_Reclaim], and can carry out next
reclosing. When the reclosing is unsuccessful or the reclosing condition is not met after AR
initiated, the reclosing will be considered as unsuccessful, including the following cases.
1.
If any protection element operates to trip when AR is enabled ([79.On]=1) and AR is not ready
([79.Ready]=0), the device will output the signal (79.Fail_Rcls).
2.
For one-shot AR, if the tripping command is received again within reclaim time after the
reclosing pulse is issued, the reclosing shall be considered as unsuccessful.
3.
For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
3-186
3 Operation Theory
tripping command is received again after the last reclosing pulse is issued, the reclosing shall
be considered as unsuccessful.
4.
The logic setting [79.En_FailCheck] is available to judge whether the reclosing is successful
by CB state, when it is set as 1. If CB is still in open position with a time delay [79.t_Fail] after
the reclosing pulse is issued, the reclosing shall be considered as unsuccessful. For this case,
the device will issue a signal (79.Fail_Rcls) to indicate that the reclosing is unsuccessful, and
this signal will drop off after (Reset Command). AR will be blocked if the reclosing shall be
considered as unsuccessful.
SET
[79.Opt_Priority]=Low
SIG
79.WaitMaster
SIG
79.On
SIG
79.Ready
SIG
&
WaitMaster Valid
&
&
>=1
0ms
SIG
SIG
79.Inprog
SIG
79.AR_Blkd
SIG
WaitMasterValid
200ms
>=1
79.Fail_Rcls
&
&
[79.t_WaitMaster]
0ms
>=1
SIG
AR Pulse
SIG
3 CB closed
EN
[79.En_FailCheck]
&
[79.t_Fail]
0ms
&
&
&
79.Succ_Rcls
[79.t_Fail]
After unsuccessful AR is confirmed, AR will be blocked. AR will not enter into the ready state
unless the circuit breaker position drops off , and can only begin to enter into the ready state again
after the circuit breaker is closed.
3.24.5.5 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [79.N_Rcls], the
maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is
selected. Some corresponding settings may be hidden if one-shot AR is selected.
1.
1-pole AR
3-187
3 Operation Theory
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 1-pole AR mode, 1-pole AR will be initiated
only for single-phase fault and respective faulty phase selected, otherwise, AR will be blocked. For
single-phase transient fault on the line, line protection device will operate to trip and 1-pole AR is
initiated. After the dead time delay for 1-pole AR is expired, the device will send reclosing pulse,
and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and the device will output the signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1-pole AR mode, the first
reclosing is 1-pole AR, and the subsequent reclosing can only be 3-pole AR. For single-phase
transient fault on the line, line protection device will operate to trip and then 1-pole AR is initiated.
After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and
then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and then 3-pole AR is initiated. At this time, the time delay applies the setting [79.t_Dd_3PS2].
After the time delay is expired, if the reclosing condition is met, the device will send reclosing pulse.
The sequence is repeated until the reclosing is successful or the maximum permit reclosing
number [79.N_Rcls] is reached. If the first fault is multi-phase fault, the device operates to trip
three-phase and initiate 3-pole AR. At this time, the time delay applies the setting [79.t_Dd_3PS1].
For the possible reclosing times of 3-pole AR in 1-pole AR mode, please refer to Table 3.24-2.
2.
3-pole AR
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 3-pole AR mode, line protection device will
operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated. After the
dead time delay for 3-pole AR is expired, the device will send reclosing pulse, and then the
auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next reclosing. For
permanent fault, the device will operate to trip again after the reclosing is performed, and the
device will output the signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and 3-pole AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the
next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [79.N_Rcls] is reached.
3.
1/3-pole AR
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 1/3-pole AR mode, line protection device
will operate to trip when a transient fault occurs on the line and 1-pole AR will be initiated for
single-phase fault and 3-pole AR will be initiated for multi-phase fault. After respective dead time
delay for AR is expired, the device will send reclosing pulse, and then the auto-reclosure will drop
off after the time delay [79.t_Reclaim] to ready for the next reclosing. For permanent fault, the
device will operate to trip again after the reclosing is performed, and the device will output the
3-188
3 Operation Theory
Setting Value
1-pole AR
3-pole AR
1/3-pole AR
N-1AR
N-3AR
N-1AR
N-3AR
N-1AR
N-3AR
Duplicated protection configurations are normally applied for UHV lines. If reclosing function is
integrated within line protections, the auto-reclosing function can be enabled in any or both of the
line protections without coordination.
If both sets of reclosing functions are enabled, when one of them first recloses onto a permanent
fault, the other will block the reclosing pulse according to the latest condition of the faulty phase.
For one-shot AR mode, if the current is detected in the faulty phase, AR will be blocked
immediately to prevent the circuit breaker from repetitive reclosing. For multi-shot AR mode, if the
current is detected in the faulty phase, the current reclosing pulse will be blocked and go into the
next reclosing pulse logic automatically. If the maximum permitted reclosing number [79.N_Rcls] is
reached, the auto-reclosure will drop off after the time delay [79.t_Reclaim].
For one-shot or multi-shot AR, there is a corresponding reclosing counter at each stage. After
reclosing pulse is sent, the corresponding reclosing counter will plus 1 and the reclosing counter
may be cleared by the submenu Clear Counter. If the circuit breaker is reclosed by other
devices during AR initiation, the auto-reclosure will go into the next reclosing pulse logic.
3.24.5.6 AR Time Sequence Diagram
The following two examples indicate typical time sequence of AR process for transient fault and
permanent fault respectively.
3-189
3 Operation Theory
Signal
Fault
Trip
CB 52b
Open
[79.t_Reclaim]
79.t_Reclaim
79.Active
79.Inprog
[79.t_Dd_1PS1]
79.Inprog_1P
[79.t_Dd_1PS1]
79.Ok_Chk
AR Out
[79.t_PW_AR]
79.Perm_Trp3P
79.Fail_Rcls
Time
Fault
Trip
52b
Open
Open
[79.t_Reclaim]
79.t_Reclaim
79.Active
79.Inprog
79.Inprog_1P
79.Inprog_3PS2
[79.t_Dd_1PS1]
[79.t_Dd_3PS2]
79.Ok_Chk
AR Out
[79.t_PW_AR]
[79.t_PW_AR]
79.Perm_Trp3P
79.Fail_Rcls
200ms
Time
3-190
3 Operation Theory
3.24.6 Settings
Table 3.24-3 Settings of auto-reclosing
No.
Name
Range
Step
Unit
Remark
79.N_Rcls
1~4
79.t_Dd_1PS1
0.000~600.000
0.001
79.t_Dd_3PS1
0.000~600.000
0.001
79.t_Dd_3PS2
0.000~600.000
0.001
79.t_Dd_3PS3
0.000~600.000
0.001
79.t_Dd_3PS4
0.000~600.000
0.001
79.t_CBClsd
0.000~600.000
0.001
time
of
fourth
shot
3-pole
reclosing
Time delay of circuit breaker in closed
position before reclosing
Time delay to wait for CB healthy, and
begin to timing when the input signal
79.t_CBReady
0.000~600.000
0.001
79.t_Wait_Chk
0.000~600.000
0.001
10
79.t_Fail
0.000~600.000
0.001
11
79.t_PW_AR
0.000~600.000
0.001
12
79.t_Reclaim
0.000~600.000
0.001
Reclaim time of AR
13
79.t_PersistTrp
0.000~600.000
0.001
check
Time delay allow for CB status change
to conform reclosing successful
14
79.t_DDO_BlkAR
0.000~600.000
0.001
when
blocking
disappears,
signal
AR
blocking
for
AR
condition
79.t_AddDly
0.000~600.000
0.001
16
79.t_WaitMaster
0.000~600.000
0.001
wait
time
for
reclosing
17
79.t_SecFault
0.000~600.000
0.001
18
79.En_PDF_Blk
0 or 1
Enabling/disabling
auto-reclosing
3-191
3 Operation Theory
blocked when a fault occurs under pole
disagreement condition
0: disable
1: enable
Enabling/disabling auto-reclosing with
19
79.En_AddDly
0 or 1
0: disable
1: enable
Enabling/disabling adjust the length of
20
79.En_CutPulse
reclosing pulse
0 or 1
0: disable
1: enable
Enabling/disabling confirm whether AR
21
79.En_FailCheck
0 or 1
0: disable
1: enable
Enabling/disabling auto-reclosing
22
79.En
0 or 1
0: disable
1: enable
Enabling/disabling AR by external input
23
79.En_ExtCtrl
0 or 1
24
79.En_CBInit
0 or 1
0: disable
1: enable
Option of AR priority
None: single-breaker arrangement
25
79.Opt_Priority
None, High or
High:
Low
arrangement
Low:
master
slave
AR
AR
of
multi-breaker
of
multi-breaker
arrangement
Control option of AR mode
1: select AR mode by internal logic
26
79.SetOpt
0 or 1
settings
0: select AR mode by external input
signals
Enabling/disabling 1-pole AR mode
27
79.En_1PAR
0 or 1
0: disable
1: enable
Enabling/disabling 3-pole AR mode
28
79.En_3PAR
0 or 1
0: disable
1: enable
3-192
3 Operation Theory
Enabling/disabling 1/3-pole AR mode
29
79.En_1P/3PAR
0 or 1
0: disable
1: enable
TT.Alm
TT.En
TT.Op
TT.Blk
TT.On
Input Signal
TT.Init
TT.En
TT.Blk
No.
Description
Input signal of initiating transfer trip after receiving transfer trip
Transfer trip enabling input, it is triggered from binary input or programmable logic
etc.
Transfer trip blocking input, it is triggered from binary input or programmable logic
etc.
Output Signal
Description
TT.Alm
TT.Op
TT.On
3-193
3 Operation Theory
3.25.5 Logic
SIG
TT.En
&
TT.On
SIG
TT.Blk
4s
BI
[TT.Init]
SIG
TT.Alm
EN
[TT.En_FD_Ctrl]
SIG
FD.Pkp
BI
[TT.Init]
10s
TT.Alm
&
TT.Op
>=1
3.25.6 Settings
Table 3.25-2 Settings of Transfer trip
No.
1
Name
TT.t_Op
TT.En_FD_Ctrl
Range
Step
Unit
0.000~600.000
0.001
Remark
Time delay of transfer trip
Transfer trip controlled by local fault detector
element
0: not controlled by local fault detector
element
1: controlled by local fault detector element
0 or 1
3-194
3 Operation Theory
TrpA
Blk
TrpB
TrpC
PrepTrp3P
Trp
Trp3P
BFI_A
BFI_B
BFI_C
BFI
Trp3P_PSFail
BlkAR
On
Input Signal
Description
Trip enabling input, it is triggered from binary input or programmable
En
logic etc.
Trip blocking input, it is triggered from binary input or programmable
Blk
logic etc.
A, phase B, phase C)
PrepTrp3P
When this signal is valid, three-phase tripping will be adopted for any
kind of faults.
No.
Output Signal
Description
On
TrpA
3-195
3 Operation Theory
3
TrpB
TrpC
Trp
Trp3P
BFI_A
BFI_B
BFI_ C
10
BFI
11
Trp3P_PSFail
12
BlockAR
Blocking auto-reclosing
3.26.5 Logic
After tripping signal is issued, the tripping pulse will be kept as same as the setting [t_Dwell_Trp] at
least. When the time delay is expired, for phase-segregated tripping, the tripping signal will drop
off immediately if the faulty current of corresponding phase is less than 0.06In (In is secondary
rated current), otherwise the tripping signal will be always kept until the faulty current of
corresponding phase is less than 0.06In. For three-phase tripping, the tripping signal will drop off
immediately if three-phase currents are all less than 0.06In, otherwise the tripping signal will be
always kept until three-phase currents are all less than 0.06In.
3-196
3 Operation Theory
SIG
FPS (phase A)
&
SIG
FPS (phase B)
&
SIG
FPS (phase C)
&
SIG
SIG
En
SIG
Blk
SIG
SIG
PrepTrp3P
&
>=1
&
>=1
&
>=1
&
&
>=1
>=1
&
EN
SIG
[En_Trp3P]
Trp
SIG
SIG
FPS (phase A)
&
SIG
FPS (phase B)
&
SIG
FPS (phase C)
&
&
>=1
>=1
>=1
&
200ms
SIG
0ms
Trp3P_PSFail
&
SIG
SIG
SIG
SIG
SIG
SIG
TrpA
[t_Dwell_Trp]
&
[t_Dwell_Trp]
&
[t_Dwell_Trp]
&
TrpA
Ia<0.06In
TrpB
&
TrpB
Ib<0.06In
TrpC
&
TrpC
Ib<0.06In
SIG
TrpA
SIG
TrpB
SIG
TrpC
>=1
Trp
3-197
3 Operation Theory
SIG
TrpA
SIG
TrpB
SIG
TrpC
&
Trp3P
>=1
&
BFI
SIG
&
BFI_A
SIG
TrpA
&
BFI_B
SIG
TrpB
&
BFI_C
SIG
TrpC
3-198
3 Operation Theory
SIG
Y.ZPx.Op
EN
[Y.ZPx.En_BlkAR]
SIG
Y.ZGx.Op
EN
[Y.ZGx.En_BlkAR]
SIG
50/51Px.Op
EN
[50/51Px.En_BlkAR]
SIG
50/51Gx.Op
EN
50/51Gx.En_BlkAR
SIG
51PVT.Op
SIG
51GVT.Op
SIG
59Pz.Op
SIG
27Pz.Op
SIG
81U.UFx.Op
SIG
81O.OFx.Op
SIG
50BF.Op_t1
SIG
50BF.Op_t2
SIG
49-1.Op
SIG
49-2.Op
SIG
50STB.Op
SIG
62PD.Op
SIG
46BC.Op
SIG
TT.Op
EN
En_MPF_Blk_AR
SIG
Multi-phase fault
EN
En_3PF_Blk_AR
SIG
Three-phase fault
EN
En_PhSF_Blk_AR
SIG
SIG
21SOTF.Op
SIG
50GSOTF.Op
SIG
&
>=1
>=1
&
&
>=1
&
>=1
>=1
>=1
>=1
>=1
BlockAR
>=1
>=1
>=1
>=1
>=1
&
&
>=1
>=1
&
>=1
&
3 Operation Theory
Where:
Y can be 21M or 21Q
x can be 1, 2, 3 or 4
z can be 1 or 2
3.26.6 Settings
Table 3.26-2 Settings of trip logic
No.
Name
Range
Step
Unit
Remark
Enabling/disabling
En_MPF_Blk_AR
auto-reclosing
blocked
0 or 1
0: disable
1: enable
Enabling/disabling
En_3PF_Blk_AR
auto-reclosing
blocked
0 or 1
0: disable
1: enable
Enabling/disabling
3
En_PhSF_Blk_AR
auto-reclosing
blocked
0 or 1
0: disable
1: enable
Enabling/disabling three-phase tripping mode
4
En_Trp3P
0 or 1
0: disable
1: enable
The dwell time of tripping command, empirical
value is 0.04
t_Dwell_Trp
0.000~10.000
0.001
3-200
3 Operation Theory
2.
Only current protection functions are enabled and VT is not connected to the device.
VTS.En
VTNS
VTNS.En
VTS.Alm
VTS.Blk
VTNS.Alm
VTNS.Blk
VTS.MCB_VT
Input Signal
VTS.En
VTS.Blk
Description
VT supervision enabling input, it is triggered from binary input or programmable
logic etc.
VT supervision blocking input, it is triggered from binary input or programmable
3-201
3 Operation Theory
logic etc.
VT neutral point supervision enabling input, it is triggered from binary input or
VTNS.En
VTNS.Blk
VTS.MCB_VT
No.
Output Signal
Description
VTS.Alm
VTNS.Alm
3.27.5 Logic
&
SIG
FD.Pkp
SIG
79.Inprog
SIG
3U0>0.08Unn
SIG
3U1<Unn
EN
[VTS.En_LineVT]
SIG
52b_3P
EN
[VTS.En_Out_VT]
>=1
>=1
&
>=1
BI
1: open
0: closed
&
[VTS.t_DPU] [VTS.t_DDO]
&
>=1
>=1
&
VTS.Alm
[VTS.MCB_VT]
EN
[VTS.En]
SIG
[VTS.En]
SIG
[VTS.Blk]
&
&
SIG
FD.Pkp
SIG
79.Inprog
OTH
U03>0.2Unn
>=1
&
1: open
0: closed
>=1
[VTS.t_DPU]
EN
[VTS.En_Out_VT]
EN
[VTS.En]
SIG
[VTNS.En]
SIG
[VTNS.Blk]
[VTS.t_DDO]
&
VTNS.Alm
&
3 Operation Theory
If there is already a VTS alarm before FD operated, VTS will continue to block distance protection,
that is VTS will be latched when FD operates.
3.27.6 Settings
Table 3.27-2 VTS Settings
No.
Name
Range
Step
Unit
Remark
VTS.t_DPU
0.200~100.000
0.001
VTS.t_DDO
0.200~100.000
0.001
VTS.En_Out_VT
0: disable
0 or 1
VTS.En_LineVT
0 or 1
1: line VT
0: busbar VT
Alarm function of VT circuit supervision
VTS.En
0 or 1
1: enable
0: disable
CTS.Alm
CTS.Blk
3-203
3 Operation Theory
Input Signal
CTS.En
CTS.Blk
No.
1
Description
CT circuit supervision enabling input, it is triggered from binary input or
programmable logic etc.
CT circuit supervision blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
CTS.Alm
Description
Alarm signal to indicate CT circuit fails
3.28.5 Logic
SIG
CTS.En
SIG
CTS.Blk
SIG
3I0>0.1In
SIG
3U0<3V
SIG
IA<0.06In
SIG
IB<0.06In
SIG
IC<0.06In
&
&
10s
10s
CTS.Alm
&
>=1
3-204
3 Operation Theory
3-205
3 Operation Theory
SIG
CSWI01.CILO.Disable
SIG
BIinput.CILO.Disable
EN
[CSWI01.En_Cls_Blk]
SIG
CSWI01.CILO.EnCls
SIG
CSWI01.RmtCtrl
SIG
BIinput.RmtCtrl
SIG
CSWI01.Cmd_RmtCtrl
SIG
CSWI01.LocCtrl
SIG
BIinput.LocCtrl
SIG
CSWI01.ManSynCls
SIG
CSWI01.Cmd_LocCtrl
SET
MCBrd.25.En_SynChk
SIG
Sig_Ok_Chk
SET
MCBrd.25.En_LvL_DdB
SET
MCBrd.25.En_DdL_LvB
SET
MCBrd.25.En_DdL_DdB
SIG
Sig_Ok_Chk
SET
MCBrd.25.En_NoChk
SIG
CSWIxx.CILO.Disable
SIG
BIinput.CILO.Disable
EN
[CSWIxx.En_Cls_Blk]
SIG
CSWIxx.CILO.EnCls
SIG
CSWIxx.RmtCtrl
SIG
BIinput.RmtCtrl
SIG
CSWIxx.Cmd_RmtCtrl
SIG
CSWIxx.LocCtrl
SIG
BIinput.LocCtrl
SIG
CSWIxx.Cmd_LocCtrl
>=1
>=1
>=1
&
&
>=1
[CSWI01.t_PW_Cls]
0ms
[CSWI01.Op_Cls]
>=1
&
>=1
>=1
>=1
>=1
>=1
>=1
>=1
&
[CSWIxx.t_PW_Cls]
0ms
[CSWIxx.Op_Cls]
>=1
&
>=1
>=1
&
Where:
xx=02~10
Only the first closing command CSWI01.Op_Cls controlled by synchrocheck logic can be used
3-206
3 Operation Theory
for CB closing.
After receiving a closing command, this device will continuously check whether the 2 voltages
(Incoming voltage and reference voltage) involved in synchronism check (or dead check) can meet
the criteria. Within the duration of [MCBrd.25.t_Wait_Chk], if the synchronism check (or dead
check) criteria are not met, the signal Sig_Ok_Chk will be set as 0; if the synchronism check (or
dead check) criteria are met, the signal Sig_Ok_Chk will be set as 1.
Access the menu Local CmdControl to issue control command locally, and this signal
CSWIxx.md_LocCtrl will be set as 1.
Remote control commands from SCADA/CC can be transmitted via IEC 60870-5-103 protocol or
IEC 61850 protocol, and this signal CSWIxx.Cmd_RmtCtrl will be set as 1.
SIG
CSWI01.CILO.Disable
SIG
BIinput.CILO.Disable
EN
[CSWI01.En_Opn_Blk]
SIG
CSWI01.CILO.EnOpn
SIG
CSWI01.RmtCtrl
SIG
BIinput.RmtCtrl
SIG
CSWI.Cmd_RmtCtrl
SIG
CSWI01.LocCtrl
SIG
BIinput.LocCtrl
SIG
CSWI01.ManOpn
SIG
CSWI01.Cmd_LocCtrl
SIG
CSWIxx.CILO.Disable
SIG
BIinput.CILO.Disable
EN
[CSWIxx.En_Opn_Blk]
SIG
CSWIxx.CILO.EnOpn
SIG
CSWIxx.RmtCtrl
SIG
BIinput.RmtCtrl
SIG
CSWIxx.Cmd_RmtCtrl
SIG
CSWIxx.LocCtrl
SIG
BIinput.LocCtrl
SIG
CSWIxx.Cmd_LocCtrl
>=1
>=1
&
[CSWI01.t_PW_Opn]
0ms
[CSWI01.Op_Opn]
[CSWIxx.t_PW_Opn]
0ms
[CSWIxx.Op_Opn]
>=1
&
>=1
>=1
&
>=1
>=1
>=1
&
>=1
&
>=1
>=1
&
3-207
3 Operation Theory
Where:
xx=01~10
The control output fulfills signal output circuit, and opens or closes circuit breaker, disconnector
and earth switch according to the control command. Object manipulation strictly performs three
steps: selection, check and excute, and perform output relay check, to ensure that the remote
control can be excuted safely and reliably.
When logic interlock is enabled, the device can receive the programmable interlock logic. The
device can automatically initiate the interlock logic to determine whether to allow control
operations. The device provides corresponding settings ([En_Opnxx_Blk] and [En_Clsxx_Blk]) for
each control object. When they are set as 1, the interlock function of the corresponding control
object is enabled. The interlock logic can be configured by using PCS-Explorer, and downloaded
to the device via the Ethernet port. If the interlock function is enabled, but it is not configured the
interlock logic, the result of the logic output is 0.
The control record is a file which is used to store remote control command records of this device
circularly. If the record number is to 256, the storage area of the control record will be full. If this
device has received a new remote command, this device will delete the oldest remote control
record, and then store the latest remote control record.
There are 10 configuration page corresponding to 10 control outputs in totall respectively. Each
configuration page can finish some signals configuration, including remote control, local control,
disable interlock blocking, and so on.
In order to conveniently configure control output, the same output signals, including
BIinput.RmtCtrl, BIinput.LocCtrl and BIinput.CILO.Disable, are available after processing
binary signals internally, as shown in figure below.
3-208
3 Operation Theory
Local
CSWIxx.
BIinput.
CSWIxx.
BIinput.
RmtCtrl
RmtCtrl
LocCtrl
LocCtrl
Control Mode
3-209
3 Operation Theory
1
For remote control or local control, they can be configured by either of CSWIxx.RmtCtrl and
BIinput.RmtCtrl, or either of CSWIxx.LocCtrl and BIinput.LocCtrl. X means that it is not
configured.
2. Synchrocheck
Three synchrocheck modes are designed for CB closing: no check mode, dead check mode and
synchronism check mode, if any one of the condition of three synchrocheck modes satisfied, then
synchrocheck signal Sig_Ok_Chk will be asserted.
The synchronism check function measures the conditions across the circuit breaker and compares
them with the corresponding settings. The output is only given if all measured quantities are
simultaneously within their set limits. Compared to the synchronism check for auto-reclosing, an
additional criterion is applied to check the rate of frequency change (df/dt) between both sides of
the CB.
When the following four conditions are all met, the synchronism check is successful.
1) Phase angle difference between incoming voltage and reference voltage is less than the
setting [MCBrd.25.phi_Diff]
2) Frequency difference between incoming voltage and reference voltage is less than
[MCBrd.25.f_Diff]
3) Voltage difference between between incoming voltage and reference voltage is less than
[MCBrd.25.U_Diff]
4) Rate of frequency change between incoming voltage and reference voltage is less than
[MCBrd.25.df/dt]
The dead check function measures the amplitude of line voltage and bus voltage at both sides of
the circuit breaker, and then compare them with the live check setting [MCBrd.25.U_Lv] and the
dead check setting [MCBrd.25.U_Dd]. The dead check is successful when the measured
quantities comply with the criteria.
When this device is set to work in no check mode and receives a closing command, CB will be
closed without synchronism check and dead check.
3-210
3 Operation Theory
Op_Opn
CILO.EnCls
Op_Cls
RmtCtrl
LocCtrl
CILO.Disable
ManSynCls
ManOpn
CSWIxx
CILO.EnOpn
Op_Opn
CILO.EnCls
Op_Cls
RmtCtrl
LocCtrl
CILO.Disable
BIinput
RmtCtrl
RmtCtrl
LocCtrl
LocCtrl
CILO.Disable
CILO.Disable
xx can be from 02 to 10
Input Signal
Description
From receiving a closing command, this device will continuously check
Sig_Ok_Chk
3-211
3 Operation Theory
check(or dead check) criteria are not met, [Sig_Ok_Chk] will be set as 0;
if the synchronism check(or dead check) criteria are met, [Sig_Ok_Chk]
will be set as 1.
2
CSWIxx.CILO.EnOpn
CSWIxx.CILO.EnCls
CSWIxx.Cmd_LocCtrl
CSWIxx.Cmd_RmtCtrl
(CB/DS/ES). When the remote control is active, No.xx binary outputs can
only be remotely controlled by SCADA or control centers. (xx=01~10)
It is used to disable the interlock blocking function for control output. If the
CSWIxx.CILO.Disable
BIinput.RmtCtrl
(CB/DS/ES). When the remote control is active, all binary outputs can only
be remotely controlled by SCADA or control centers.
It is used to select the local control to No.xx controlled object (CB/DS/ES).
BIinput.LocCtrl
When the local control is active, all binary outputs can only be locally
controlled.
It is used to disable the interlock blocking function for control output. If the
BIinput.CILO.Disable
10
CSWI01.ManSynCls
the
condition
of
local
control
is
met
and
the
signal
11
CSWI01.ManOpn
the
condition
of
local
control
is
met
and
the
signal
No.
Output Signal
Description
CSWIxx.Op_Opn
CSWIxx.Op_Cls
BIinput.RmtCtrl
BIinput.LocCtrl
output signals with input signals are available. The relationship with 10
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can be
BIinput.CILO.Disable
3-212
3 Operation Theory
3.29.5 Settings
Table 3.29-2 Control Settings
No.
Name
Range
Step
Unit
Remark
No.xx holding time of a normal open contact
CSWIxx.t_PW_Opn
0~65535
ms
CSWIxx.t_PW_Cls
0~65535
ms
CSWIxx.t_DPU_DPS
0~60000
ms
CSWIxx.En_Opn_Blk
logic
0 or 1
0: disable
1: enable
(xx=01, 02.10)
Enabling/disabling No.xx closing output of the
BO module be controlled by the interlocking
5
CSWIxx.En_Cls_Blk
logic
0 or 1
0: disable
1: enable
(xx=01, 02.10)
Table 3.29-3 Synchrocheck Settings
No.
Name
Range
Step
Unit
Remark
Voltage selecting mode of line
0: A-phase voltage
1: B-phase voltage
MCBrd.25.Opt_Source_UL
0~5
2: C-phase voltage
3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage
Voltage selecting mode of bus
0: A-phase voltage
1: B-phase voltage
MCBrd.25.Opt_Source_UB
0~5
2: C-phase voltage
3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage
3-213
3 Operation Theory
3
MCBrd.25.U_Dd
0.05Un~0.8Un
0.001
MCBrd.25.U_Lv
0.5Un~Un
0.001
MCBrd.25.K_Usyn
0.20-5.00
MCBrd.25.phi_Diff
0~ 89
MCBrd.25.phi_Comp
0~359
MCBrd.25.f_Diff
0.02~1.00
0.01
Hz
MCBrd.25.U_Diff
0.02Un~0.8Un
0.01
10
MCBrd.25.En_SynChk
0 or 1
11
MCBrd.25.En_DdL_DdB
0 or 1
12
MCBrd.25.En_DdL_LvB
0 or 1
13
MCBrd.25.En_LvL_DdB
0 or 1
14
MCBrd.25.En_NoChk
0 or 1
Compensation
coefficient
for
synchronism voltage
Deg
Phase
difference
limit
of
difference
limit
of
difference
limit
of
15
MCBrd.25.df/dt
0.00~3.00
0.01
Hz/s
16
MCBrd.25.t_Close_CB
20~1000
ms
time
from
receiving
closing
17
MCBrd.25.t_Wait_Chk
5~30
0.001
can
meet
the
criteria.
If
the
synchronism-check
(or
dead
3-214
3 Operation Theory
1.
2.
The logic makes the device ideal for single-phase tripping applications.
1)
Phase A: UOPA
2)
Phase B: UOPB
3)
Phase C: UOPC
2.
1)
2)
3)
Fault phase
UOPA
Phase A
UOPB
Phase B
UOPC
Phase C
UOPAB
Phase AB
UOPBC
Phase BC
UOPCA
Phase CA
3-215
3 Operation Theory
Region A
60
-60
Region B
Region C
180
Depended on the phase relation between I0 and I2A, the faulty phase can be determined.
1.
2.
3.
For single-phase earth fault, I0 and I2 of faulty phase are in-phase and its distance element
operates.
For phase to phase to earth fault, I0 and I2 of non-faulty phase are in-phase but its distance
element does not operate.
Output Signal
Description
PhSA
PhSB
3-216
3 Operation Theory
3
PhSC
GndFlt
Earth fault
[km]
Where:
Dist: The distance of fault location according to the Zcalc (km)
Zcalc: The impedance value calculated from the location of protection device to fault point
Zl: The impedance value of the whole line + mutual impedance
Length: The input length of transmission line (km)
3.31.2.2 Mutual Compensation
When an earth fault occurred on a line of parallel lines arrangement, a distance relay at one end of
the faulty line will tend to underreach whilst the distance relay at the other end will tend to
overreach. Usually the degree of underreach or overreach is acceptable, however, for cases
where precise fault location is required for long lines with high mutual coupling, mutual
compensation is then required to improve the distance measurement. Practically, the mutual effect
between the parallel lines is insignificant to positive and negative sequence and thus the mutual
compensation is only for zero sequence
3-217
3 Operation Theory
A
Ia
ZM
k
C
Ic
ZS
D
(1-k)ZL
kZL
ZL
The principle in the application of mutual compensation is shown as follows with the aid of
following sequence network diagram figure. The diagram indicates a parallel lines arrangement
with an earth fault at location k on line CD.
The equivalent sequence network for an earth fault on a parallel lines arrangement with single
source is shown as below.
Ia1
ZL1
ZS1
kZL1
(1-k)ZL1
Ic1
Ia2
ZL2
ZS2
kZL2
(1-k)ZL2
Ic2
Ia0
ZL0
ZS0
Z0M
kZL0
(1-k)ZL0
Ic0
The device at location C without mutual compensation will have voltage URC and current IRC
measured as shown in the expression
URC is the voltage of the device at location C.
3-218
3 Operation Theory
3-219
3 Operation Theory
A
B
C
P2
S2
P2
S2
P1
S1
P1
S1
02
01
02
01
04
03
04
03
06
05
06
05
08
07
08
07
FPS_Fault
Fault_Phase
FD.Pkp
Fault_Phase_Curr
Fault_Resid_Curr
Input Signal
Description
FPS_Fault
FD.Pkp
No.
1
Output Signal
Fault_Location
Description
The result of fault location
3-220
3 Operation Theory
2
Faulty_Phase
Fault_Phase_Curr
Fault_Resid_Curr
3-221
3 Operation Theory
3-222
4 Supervision
4 Supervision
Table of Contents
4 Supervision ...................................................................................... 4-a
4.1 Overview .......................................................................................................... 4-1
4.2 Supervision Alarms ......................................................................................... 4-1
4.3 Relay Self-supervision.................................................................................... 4-7
4.3.1 Relay Hardware Monitoring................................................................................................ 4-7
4.3.2 Fault Detector Monitoring ................................................................................................... 4-7
4.3.3 Check Setting..................................................................................................................... 4-7
List of Tables
Table 4.2-1 Alarm description ...................................................................................................4-1
Table 4.2-2 Troubleshooting .....................................................................................................4-5
4-a
Date: 2013-09-07
4 Supervision
4-b
4 Supervision
4.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before the
LED HEALTHY is on, the device need to be checked to ensure no abnormality. Therefore, the
automatic supervision function, which checks the health of the protection system when startup and
during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.
Item
Description
Blocking Device
Fail Signals
The device fails.
1
Fail_Device
Blocked
Fail_Setting_OvRange
Blocked
4-1
Date: 2013-09-07
4 Supervision
This signal will pick up instantaneously and will be
latched unless the recommended handling suggestion is
adopted.
3
Fail_BoardConfig
Blocked
Fail_SettingItem_Chgd
Blocked
Fail_Memory
Blocked
adopted.
Error is found during checking settings.
6
Fail_Settings
Blocked
adopted.
DSP chip is damaged.
7
Fail_DSP
Blocked
adopted.
Communication between two DSP chips is abnormal
8
Fail_DSP_Comm
Blocked
instantaneously.
Software configuation is incorrect.
9
Fail_Config
Blocked
adopted.
AC current and voltage samplings are abnormal.
10
Fail_Sample
Blocked
suggestion is adopted.
11
MCBrd.Fail_Sample
12
MCBrd.Fail_Settings
Blocked
Blocked
Alarm Signals
The device is abnormal.
13
Alm_Device
Unblocked
and it will drop off when all alarm signals drop off.
14
Alm_Insuf_Memory
15
Alm_CommTest
4-2
Unblocked
Unblocked
4 Supervision
instantaneously.
The error is found during MON module checking
16
Alm_Settings_MON
settings of device.
This signal will pick up with a time delay of 10s and will
Unblocked
Alm_Version
Unblocked
instantaneously.
The active group set by settings in device and that set
18
Alm_BI_SettingGrp
Unblocked
instantaneously.
Data frame is abnormal between two DSP modules.
19
Alm_DSP_Frame
Unblocked
instantaneously.
The power supply of BI plug-in module in slot xx is
20
Bxx.Alm_OptoDC
abnormal.
This signal will pick up with a time delay of 10s and will
Unblocked
Alm_Pkp_FD
This signal will pick up with a time delay of 50s and will
Unblocked
Alm_Pkp_I0
Unblocked
VTS.Alm
Unblocked
VTNS.Alm
Unblocked
CTS.Alm
This signal will pick up with a time delay of 10s and will
Unblocked
Alm_52b
auxiliary
normally
closed
contact
(52b)
of
Unblocked
BI_Maintenance
Unblocked
4-3
Date: 2013-09-07
4 Supervision
28
Alm_TimeSyn
Unblocked
Alm_Freq
than 45Hz.
This signal will pick up with a time delay of 100ms and
Unblocked
30
Alm_Sparexx
(xx=01~08)
Unblocked
31
FOx.Alm
Unblocked
FOx.Alm_ID
Unblocked
FOx.Alm_NoValFram
Unblocked
FOx.Alm_CRC
Unblocked
FOx.Alm_Off
Unblocked
instantaneously.
Optical fibre of channel x is connected wrongly.
36
FOx.Alm_Connect
Unblocked
27P1.Alm
Unblocked
38
27P2.Alm
Unblocked
39
59P1.Alm
Unblocked
40
59P2.Alm
Unblocked
41
49-1.Alm
42
49-2.Alm
43
46BC.Alm
44
25.Alm_VTS_UB
Unblocked
Unblocked
Unblocked
Unblocked
25.Alm_VTS_UL
4-4
Unblocked
PCS-902 Line Distance Relay
Date: 2013-09-07
4 Supervision
This signal will pick up with a time delay of 1.25s and will
drop off with a time delay of 10s.
46
79.Fail_Rcls
Auto-reclosing fails.
Unblocked
47
79.Fail_Chk
Unblocked
TT.Alm
Unblocked
10s.
Table 4.2-2 Troubleshooting
No.
Item
Handling suggestion
Fail Signals
Fail_Device
The signal is issued with other specific fail signals, and please refer to the
handling suggestion other specific alarm signals.
Please reset setting values according to the range described in the instruction
Fail_Setting_OvRange
manual, then re-power or reboot the device and the device will restore to
normal operation state.
1. Go to the menu InformationBorad Info, check the abnormality
information.
Fail_BoardConfig
2. For the abnormality board, if the board is not used, then remove, and if the
board is used, then check whether the board is installed properly and work
normally.
Please check the settings mentioned in the prompt message on the LCD, and
Fail_SettingItem_Chgd
Fail_Memory
Fail_Settings
Fail_DSP
Fail_DSP_Comm
Fail_Config
Chips are damaged and please inform the manufacture or the agent replacing
the module.
Please inform the manufacture or the agent for repair.
Please inform configuration engineers to check and confirm visualization
functions of the device
1. Please make the device out of service.
10
Fail_Sample
2. Then check if the analog input modules and wiring connectors connected to
those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.
1. Please make the device out of service.
11
MCBrd.Fail_Sample
12
MCBrd.Fail_Settings
13
Alm_Device
14
Alm_Insuf_Memory
The signal is issued with other specific alarm signals, and please refer to the
handling suggestion other specific alarm signals.
Please replace MON plug-in module.
4-5
Date: 2013-09-07
4 Supervision
15
Alm_CommTest
16
Alm_Settings_MON
17
Alm_Version
version checksum file) provided by R&D engineer to make the alarm signal
disappear. Then users get the correct software version. It is not allowed that
the alarm signal is issued on the device already has been put into service. the
devices having being put into service so that the alarm signal disappears.
Please check the value of setting [Active_Grp] and binary input of indiating
18
Alm_BI_SettingGrp
active group, and make them matched. Then the ALARM LED will be
extinguished and the corresponding alarm message will disappear and the
device will restore to normal operation state.
19
Alm_DSP_Frame
20
Bxx.Alm_OptoDC
3. After the voltage for binary input module restores to normal range, the
ALARM LED will be extinguished and the corresponding alarm message will
disappear and the device will restore to normal operation state.
Please check secondary values and protection settings. If settings are not set
21
Alm_Pkp_FD
reasonable to make fault detectors pick up, please reset settings, and then
the alarm message will disappear and the device will restore to normal
operation state.
Please check secondary values and protection settings. If settings are not set
22
Alm_Pkp_I0
reasonable to make fault detectors pick up, please reset settings, and then
the alarm message will disappear and the device will restore to normal
operation state.
23
VTS.Alm
24
VTNS.Alm
25
CTS.Alm
26
Alm_52b
27
BI_Maintenance
[BI_Maintenance] and then the alarm will disappear and the device restore to
normal operation state.
1. check whether the selected clock synchronization mode matches the clock
synchronization source;
28
Alm_TimeSyn
2. check whether the wiring connection between the device and the clock
synchronization source is correct
4-6
4 Supervision
3. check whether the setting for selecting clock synchronization (i.e.
[Opt_TimeSync]) is set correctly. If there is no clock synchronization, please
set the setting [Opt_TimeSync] as No TimeSync.
4. After the abnormality is removed, the ALARM LED will be extinguished
and the corresponding alarm message will disappear and the device will
restore to normal operation state.
29
30
Alm_Freq
Alm_Sparexx
(xx=01~08)
user-defined.)
Operation Alarm Signals
31
FOx.Alm
32
FOx.Alm_ID
33
FOx.Alm_NoValFram
34
FOx.Alm_CRC
35
FOx.Alm_Off
36
FOx.Alm_Connect
Please check the conncetion of optical fibre channel. (For example, receiving
and sending are inconsistent, or channel 1 and channel 2 are inconsistent)
Please check the corresponding binary input secondary circuit. After the
37
TT.Alm
4-7
Date: 2013-09-07
4 Supervision
Output Signal
Description
GOOSE alarm signal indicating that there is a network storm occurring on the
GAlm_AStorm_SL
GAlm_BStorm_SL
GAlm_CfgFile_SL
Namexx.GAlm_ADisc_SL_xx
Namexx.GAlm_BDisc_SL_xx
Namexx.GAlm_Cfg_SL_xx
network A.
GOOSE alarm signal indicating that there is a network storm occurring on the
network B.
GOOSE alarm signal indicating that there is an error in the GOOSE
configuration file
These are GOOSE alarm reports. When any alarm message is issued, the LED ALARM is lit without
the device being blocked. After the abnormality is removed, the device will return to normal with the
LED ALARM being distinguished automatically.
4-8
4 Supervision
No.
Output Signal
Handling suggestion
GAlm_AStorm_SL
GAlm_BStorm_SL
GAlm_CfgFile_SL
Namexx.GAlm_ADisc_SL_xx
Namexx.GAlm_BDisc_SL_xx
Namexx.GAlm_Cfg_SL_xx
Namexx is the name defined by the setting [Linkxx], xx=01, 02, 03, , 64
4-9
Date: 2013-09-07
4 Supervision
4-10
5 Management
5 Management
Table of Contents
5 Management ..................................................................................... 5-a
5.1 Measurement ................................................................................................... 5-1
5.1.1 Root-Mean-Square Values ................................................................................................. 5-1
5.1.2 Phase Angle ....................................................................................................................... 5-2
5.1.3 Primary Value ..................................................................................................................... 5-2
5-a
Date: 2013-09-07
5 Management
5-b
5 Management
5.1 Measurement
PCS-902 performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The relay samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.
Symbol
Definition
Resolution
Unit
Ia
0.000
Ib
0.000
Ic
0.000
I1
0.000
I2
0.000
3I0
0.000
3I0Adj
0.000
Ua
0.000
Ub
0.000
10
Uc
0.000
11
Uab
0.000
12
Ubc
0.000
13
Uca
0.000
14
Usyn
0.000
15
U1
0.000
16
U2
0.000
17
3U0
0.000
18
0.000
Hz
5-1
Date: 2013-09-07
5 Management
19
25.f_Syn
20
25.f_Diff
21
25.phi_Diff
22
25.U_Diff
0.000
Hz
0.000
Hz
0.000
Symbol
Ang (Ua-Ub)
Ang (Ub-Uc)
Ang (Uc-Ua)
Ang (Ua-Ia)
Ang (Ub-Ib)
Ang (Uc-Ic)
Ang (Ia-Ib)
Ang (Ib-Ic)
Ang (Ic-Ia)
Definition
Phase angle between phase-A voltage and
phase-B voltage
Phase angle between phase-B voltage and
phase-C voltage
Phase angle between phase-C voltage and
phase-A voltage
Phase angle between phase-A voltage and
phase-A current
Phase angle between phase-B voltage and
phase-B current
Phase angle between phase-C voltage and
phase-C current
Phase angle between phase-A current and
phase-B current
Phase angle between phase-B current and
phase-C current
Phase angle between phase-C current and
phase-A current
Resolution
Unit
Deg
Deg
Deg
Deg
Deg
Deg
Deg
Deg
Deg
5-2
5 Management
Symbol
Definition
Resolution
Unit
Ia
0.000
Ib
0.000
Ic
0.000
I1
0.000
I2
0.000
3I0
0.000
3I0Adj
0.000
Ua
0.000
kV
Ub
0.000
kV
10
Uc
0.000
kV
11
Uab
0.000
kV
12
Ubc
0.000
kV
13
Uca
0.000
kV
14
U1
0.000
kV
15
U2
0.000
kV
16
3U0
0.000
kV
17
U_Syn
0.000
kV
18
0.000
Hz
19
f_Syn
0.000
Hz
20
0.000
MW
21
0.000
MVar
22
0.000
MVA
23
Cos
0.000
24
Pa
0.000
MW
25
Pb
0.000
MW
26
Pc
0.000
MW
27
Qa
0.000
MVar
28
Qb
0.000
MVar
29
Qc
0.000
MVar
30
Cosa
0.000
31
Cosb
0.000
32
Cosc
0.000
5-3
Date: 2013-09-07
5 Management
33
f_Diff
34
df/dt
35
phi_Diff
36
U_Diff
37
PHr+_Pri
38
0.000
Hz
0.000
Hz/s
0.00
Deg
0.000
kV
0.000
MWh
PHr-_Pri
0.000
MWh
39
QHr+_Pri
0.000
MVAh
40
QHr-_Pri
0.000
MVAh
5.2 Recording
5.2.1 Overview
PCS-902 provides the following recording functions:
1.
Event recording
2.
Disturbance recording
3.
Present recording
All the recording information except waveform can be viewed on local LCD or by printing.
Waveform could only be printed or extracted with PCS-Explorer software tool and a waveform
analysis software.
5-4
5 Management
Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2.
The time resolution is 1ms using the relay internal clock synchronized via clock synchronized
device if connected. The date and time is recorded when a system fault is detected.
3.
An operating time (not including the operating time of output relays) is recorded in the record.
4.
Faulty phase
5-5
Date: 2013-09-07
5 Management
5.
Fault location
To get accurate result of fault location, the following settings shall be set correctly:
1)
2)
3)
4)
5)
6)
7)
8)
9)
6.
Protection elements
5-6
6 Hardware
6 Hardware
Table of Contents
6 Hardware .......................................................................................... 6-a
6.1 Overview .......................................................................................................... 6-1
6.2 Typical Wiring .................................................................................................. 6-4
6.2.1 Conventional CT/VT (For reference only) .......................................................................... 6-4
6.2.2 ECT/EVT (For reference only) ........................................................................................... 6-6
6.2.3 CT Requirement ................................................................................................................. 6-8
List of Figures
Figure 6.1-1 Rear view of fixed module position ....................................................................6-1
Figure 6.1-2 Hardware diagram ................................................................................................6-2
Figure 6.1-3 Front view of PCS-902 ..........................................................................................6-3
Figure 6.1-4 Typical rear view of PCS-902 ...............................................................................6-4
Figure 6.2-1 Typical wiring of PCS-902 (conventional CT/VT) ...............................................6-5
Figure 6.2-2 Typical wiring of PCS-902 (ECT/EVT) .................................................................6-7
Figure 6.3-1 View of PWR plug-in module .............................................................................6-10
Figure 6.3-2 Output contacts of PWR plug-in module ..........................................................6-10
PCS-902 Line Distance Relay
6-a
Date: 2013-09-07
6 Hardware
List of Tables
Table 6.3-1 Terminal definition and description of PWR plug-in module ............................6-10
Table 6.3-2 Terminal definition of AI module .........................................................................6-17
Table 6.3-3 Terminal definition of AI module .........................................................................6-20
Table 6.3-4 Terminal definition of AI module .........................................................................6-22
6-b
6 Hardware
6.1 Overview
PCS-902 adopts 32-bit microchip processor CPU produced by FREESCALE as control core for
management and monitoring function, meanwhile, adopts high-speed digital signal processor DSP
for all the protection calculation. 24 points are sampled in every cycle and parallel processing of
sampled data can be realized in each sampling interval to ensure ultrahigh reliability and safety of
the device.
12
13
PWR module
11
BO module
09
BO module
08
BO module
06
BO module
DSP module
05
BI module
CH Module
04
BI module
DSP module
AI module
MON module
PCS-902 is comprised of intelligent plug-in modules, except that few particular plug-in modules
position cannot be changed in the whole device (gray plug-in modules as shown in Figure 6.1-1),
other plug-in modules like AI (analog input) and IO (binary input and binary output) can be flexibly
configured in the remaining slot positions.
15
P1
Slot No.
01
02
03
07
10
14
PCS-902 has 16 slots, PWR plug-in module, MON plug-in module, DSP plug-in module and CH
plug-in module are assigned at fixed slots.
Besides 5 fixed modules are shown in above figure, there are 12 slots can be flexibly configured.
AI plug-in module, BI plug-in module and BO plug-in module can be configured at position
between slot 02, 03 and 06~15. It should be pay attention that AI plug-in module will occupy two
slots.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 6.1-2 for hardware diagram.
6-1
Date: 2013-09-07
A/D
Protection
Calculation
DSP
A/D
Fault
Detector
DSP
Output Relay
Conventional CT/VT
External
Binary Input
6 Hardware
ECVT
Pickup
Relay
ECVT
ETHERNET
LCD
Power
Supply
Uaux
+E
Clock SYN
LED
CPU
RJ45
Keypad
PRINT
The working process of the device is as shown in above figure: current and voltage from
conventional CT/VT are converted into small voltage signal and sent to DSP module after filtered
and A/D conversion for protection calculation and fault detector respectively (ECVT signal is sent
to the device without small signal and A/D convertion). When DSP module completes all the
protection calculation, the result will be recorded in 32-bit CPU on MON module. DSP module
carries out fault detector, protection logic calculation, tripping output, and MON module perfomes
SOE (sequence of event) record, waveform recording, printing, communication between the
device and SAS and communication between HMI and CPU. When fault detector detects a fault
and picks up, positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS-900 series based on microcomputer
are classified into standard and optional modules.
Table 6.1-1 PCS-902 module configuration
No.
ID
Module description
NR1101/NR1102
standard
NR1401
standard
NR1161
standard
NR1213
option
NR1503/NR1504
standard
NR1521
standard
NR1301
standard
6-2
Remark
6 Hardware
No.
ID
NR1136
Module description
Remark
option
standard
MON module provides functions like communication with SAS, event record, setting
management etc.
AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.
DSP module performs filtering, sampling, protection calculation and fault detector calculation.
CH module performs information exchange with the remote device through a dedicated
optical fibre channel, multiplex optical fibre channel or PLC channel.
BI module provides binary inputs via opto-couplers with rating voltage among
24V/110V/125V/220V/250V (configurable).
BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
PWR module converts DC 250/220/125/110V into various DC voltage levels for modules of
the device.
HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
NET-DSP module receives and sends GOOSE messages, sampled values (SV) from
merging unit by IEC61850-9-2 protocol.
PCS-902 series is made of a 4U height 19 chassis for flush mounting. Components mounted on
its front include a 320240 dot matrix LCD, a 9 button keypad, 20 LED indicators and a multiplex
RJ45 port. A monolithic micro controller is installed in the equipment for these functions.
Following figures show front and rear views of PCS-902 respectively.
ALARM
11
PCS-902
12
13
14
15
16
17
18
19
10
20
GRP
HEALTHY
ESC
1
2
ENT
6-3
Date: 2013-09-07
6 Hardware
20 LED indicators are, from top to bottom, operation (HEALTHY), self-supervision (ALARM),
others are configurable.
For the 9-button keypad, ENT is enter, GRP is group number and ESC is escape.
NR1102
NR1401
NR1161
NR1161
NR1213
NR1504
NR1504
NR1521
NR1521
NR1521
NR1521
NR1301
5V OK
ALM
TX
BO_ALM BO_FAIL
RX
ON
TX
OFF
RX
DANGER
1 BO_COM1
2
BO_FAIL
BO_ALM
BO_COM2
BO_FAIL
BO_ALM
OPTO+
OPTO-
9
10
PWR+
11
PWR-
12
GND
12
13
PWR module
11
NR1521F NR1301
BO module
BO module
06
BO module
05
BO module
04
NR1504
BI module
NR1161
DSP module
NR1213
CH Module
AI module
NR1161
DSP module
NR1401
MON module
NR1102
15
P1
Slot No.
01
02
03
07
08
09
10
14
6-4
6 Hardware
0801
CH-TX
CH-RX
BI_01
or
CH-TX
CH-RX
Fibre Optic
0203
Ib
0204
0205
To parallel line
Ic
0206
0207
IM0
0208
0215
Ub
0216
0217
0221
UL2
0222
0223
P110
PWR-
P111
OPTO+
P107
OPTO-
P108
BO_ALM
P101
COM
P105
BO_FAIL
P106
BO_ALM
P104
COM
Not used
0815
0816
0821
0822
1101
BO_01
1102
1103
BO_02
1104
BO_11
1121
1122
1201
BO_01
1202
1203
BO_02
1204
BO_11
1221
1222
1301
BO_01
1302
1303
BO_02
1304
BO_FAIL
P103
0814
Power
Supply
P102
BI_13
PWR+
0809
External DC power
supply
BI_12
UB2
0224
0808
UB1
0220
Not used
BI_18
Synchronism Voltage
0219
0807
BI_07
Controlled by fault
detector element
Uc
0218
BI_06
Ua
0214
Protection Voltage
0213
0802
0202
Dedicated Channel
Or
Telecom Equipment
BO_11
1321
1322
1501
B
0102
SGND
0103
BO_CtrlOpn1
0104
0101
SYN-
0102
SGND
0103
0104
Clock SYN
SYN+
1502
1503
BO_CtrlCls1
1504
0101
COM
1517
BO_CtrlOpn5
1518
1519
BO_CtrlCls5
1520
1521
0105
TXD
0106
SGND
0107
PRINTER
RTS
BO_Ctrl
Multiplex
RJ45 (Front)
1522
P112
0225
Grounding
Bus
6-5
Date: 2013-09-07
6 Hardware
PCS-902 (conventional CT/VT and conventional binary input and binary output)
Slot No.
01
04
05
08
09
11
12
13
15
P1
Module ID
NR1102
02
NR1401
03
NR1161
NR1213
06
07
NR1504
NR1504
10
NR1521
NR1521
NR1521
14
NR1521
NR1301
MON
AI
DSP
CH
BI
BI
BO
BO
BO
BO
PWR
08
09
11
12
13
PCS-902 (conventional CT/VT and GOOSE binary input and binary output)
Slot No.
01
04
05
06
Module ID
NR1102
02
NR1401
03
NR1161
NR1213
NR1136
07
NR1504
10
14
15
NR1301
P1
MON
AI
DSP
CH
NETDSP
BI
PWR
06
07
08
11
12
NR1301
PWR module
05
BO module
04
NR1521A NR1521C
BO module
BI module
NR1503
NET-DSP Module
NR1136
DSP module
NR1161
CH Module
NR1213
DSP module
NR1161
MON module
NR1102
Slot No.
01
02
03
09
10
13
14
15
P1
6-6
6 Hardware
CH-RX
Dedicated Channel
Or
Telecom Equipment
or
CH-TX
CH-RX
Fibre Optic
MU
Phase B
RX
TX
P111
OPTO+
P107
OPTO-
P108
Power
Supply
BO_FAIL
P103
BO_ALM
P101
COM
P105
BO_FAIL
P106
BO_ALM
P104
COM
0102
SGND
0103
0104
0101
SYN-
0102
SGND
0103
0104
0105
TXD
0106
SGND
0107
0804
0805
0806
0821
0822
1101
1102
1103
BO_02
1104
BO_11
1121
1122
1201
BO_01
1202
1203
BO_02
1204
BO_11
1221
1222
1502
1503
BO_CtrlCls1
1504
1517
BO_CtrlOpn5
1518
1519
BO_CtrlCls5
1520
1521
BO_Ctrl
1522
IRIG-B
PRINTER
RTS
BO_01
Clock SYN
SYN+
0803
0101
1501
COM
0802
BO_CtrlOpn1
P102
PWR-
0801
P110
BI_11
External DC power
supply
PWR+
BI_03
Controlled by fault
detector element
Phase C
BI_02
Phase A
SV from
ECT/EVT
BI_01
CH-TX
P112
Multiplex
RJ45 (Front)
0225
Grounding
Bus
Slot No.
01
04
05
06
Module ID
NR1102
02
03
NR1161
NR1213
NR1136
07
NR1504
08
09
10
11
12
13
14
15
NR1301
P1
MON
DSP
CH
NETDSP
BI
PWR
Slot No.
01
Module ID
02
03
04
05
06
NR1102
NR1161
NR1213
MON
DSP
CH
07
08
09
NR1136
NR1504
NETDSP
BI
11
12
13
NR1504
NR1521
NR1521
BI
BO
BO
10
14
15
P1
NR1521
NR1521
NR1301
BO
BO
PWR
6-7
Date: 2013-09-07
6 Hardware
In the protection system adopting electronic current and voltage transformer (ECT/EVT), the
merging unit will merge the sample data from ECT/EVT, and then send it to the device through
multi-mode optical fibre. DSP module receives the data from merging unit through the optical-fibre
interface to complete the protection calculation and fault detector.
The difference between the hardware platform based on ECT/EVT and the hardware platform
based on conventional CT/VT lies in the receiving module of sampled values only, and the device
receives the sampled value from merging unit through multi-mode optical fibre.
6.2.3 CT Requirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current.
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current.
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn
Icth
Ith
Idyn
Isn
Kalf
IPal
Performance verification
Esl > Esl
Esl
Kalf
IPal
Ipn
Isn
Rct
Rbn
Sbn
Esl
6-8
6 Hardware
Esl = kIpcf Isn(Rct+Rb)/Ipn
k
Ipcf
stability factor = 2
Protective checking factor current (amps)
Same as the maximum prospective fault current
Isn
Rct
Rb
Rc
RL
Rr
Ipn
For example:
1.
Esl = 2IpcfIsn(Rct+Rb)/Ipn
= 2Ipcf Isn(Rct+(Rr+2RL+Rc))/Ipn
= 2400005(1+(0.1+20.5+0.1))/2000=440V
Thus, Esl > Esl
6-9
Date: 2013-09-07
6 Hardware
as below.
NR1301
5V OK
ALM
BO_ALM BO_FAIL
ON
OFF
BO_COM1
BO_FAIL
BO_ALM
BO_COM2
BO_FAIL
BO_ALM
OPTO+
OPTO-
9
10 PWR+
11 PWR12 GND
The power switch in the dotted box of above figure maybe is not existed.
01
BO_FAIL
02
BO_ALM
03
04
BO_FAIL
05
BO_ALM
06
Symbol
Description
01
BO_COM1
Common terminal 1
02
BO_FAIL
03
BO_ALM
04
BO_COM2
Common terminal 2
05
BO_FAIL
6-10
6 Hardware
Terminal No.
Symbol
Description
06
BO_ALM
07
OPTO+
08
OPTO-
09
Blank
Not used
10
PWR+
11
PWR-
12
GND
Note!
The standard rated voltage of PWR module is self-adaptive to 88~300 Vdc. If input voltage
is out of range, an alarm signal (Fail_Device) will be issued. For non-standard rated
voltage power supply module please specify when place order, and check if the rated
voltage of power supply module is the same as the voltage of power source before the
device being put into service.
PWR module provides terminal 12 and grounding screw for device grounding. Terminal 12
shall be connected to grounding screw and then connected to the earth copper bar of
panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent EMI, so effective
grounding must be ensured before the device is put into service.
PCS-902, like almost all electronic relays, contains electrolytic capacitors. These
capacitors are well known to be subject to deterioration over time if voltage is not applied
periodically. Deterioration can be avoided by powering the relays up once a year.
6-11
Date: 2013-09-07
6 Hardware
NR1102D
NR1102I
NR1101E
TX
ETHERNET
ETHERNET
RX
TX
RX
ETHERNET
Memory
Interface
Terminal No.
4 RJ45 Ethernet
RS-485
NR1102D
128M DDR
128M DDR
Physical Layer
To SCADA
01
SYN+
02
SYN-
To
03
SGND
synchronization
clock
04
RS-232
NR1102I
Usage
05
RTS
06
TXD
07
SGND
To printer
Cable
2 RJ45 Ethernet
To SCADA
2 FO Ethernet
To SCADA
Optical fibre ST
RS-485
01
SYN+
02
SYN-
To
03
SGND
synchronization
clock
04
RS-232
05
RTS
06
TXD
07
SGND
2 RJ45 Ethernet
NR1101E
128M DDR
RS-485
To printer
Cable
To SCADA
01
02
03
SGND
6-12
To SCADA
6 Hardware
04
RS-485
05
06
07
SGND
To SCADA
08
RS-485
09
SYN+
10
SYN-
To
SGND
synchronization
11
clock
12
RS-232
13
RTS
14
TXD
15
SGND
To printer
Cable
16
The correct connection is shown in Figure 6.3-4. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the + and terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.
Twisted pair wire
01
02
SGND
03
COM
01
SYN-
02
SGND
03
Clock SYN
04
04
Cable
05
TXD
06
SGND
07
RTS
6-13
Date: 2013-09-07
6 Hardware
Socket
Plug
In
Out
In
Out
There are two types of AI module with rating 5 A or 1 A. Please declare which kind of AI module is
needed before ordering. Maximum linear range of the current converter is 40In.
1.
For one CT group input, three phase currents (Ia, Ib and Ic) and residual current from parallel line
(for mutual compensation) are input to AI module separately. Terminal 01, 03, 05 and 07 are
polarity marks. It is assumed that polarity mark of CT installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
6-14
6 Hardware
A
B
C
P2
S2
P2
S2
P1
S1
P1
S1
02
01
02
01
04
03
04
03
06
05
06
05
08
07
08
07
In order to accurately locate the fault for parallel lines arrangement, residual current from parallel
line is required to be connected to the device to eliminate the mutual effect between the parallel
lines. Otherwise, residual current from parallel line is not necessary.
Relevant description about parallel line to refer to section Fault Location.
6-15
Date: 2013-09-07
6 Hardware
A
B
C
13
14
15
16
17
18
19
20
13
14
15
16
17
18
19
20
6-16
6 Hardware
Ia
01
Ian
02
Ib
03
Ibn
04
Ic
05
Icn
06
IM0
07
IM0n
08
NR1401
09
10
11
12
Ua
13
Uan
14
Ub
15
Ubn
16
Uc
17
Ucn
18
Us
19
Usn
20
21
22
23
24
Definition
Definition
01
Ia
02
Ian
03
Ib
04
Ibn
05
Ic
06
Icn
07
IM0
08
IM0n
09
Reserve
10
Reserve
11
Reserve
12
Reserve
13
Ua
14
Uan
15
Ub
16
Ubn
17
Uc
18
Ucn
19
Us
6-17
Date: 2013-09-07
6 Hardware
Terminal No.
2.
Definition
20
Usn
21
Reserve
22
Reserve
23
Reserve
24
Reserve
25
GND
Definition
Synchronism voltage
Ground
For two circuit breakers configuration with two CT groups input, three phase currents
corresponding to CB1 and CB2 respectively (Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2) are input to AI module.
Terminal 01, 03, 05, 07, 09 and 11 are polarity marks. It is assumed that polarity mark of CT
installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) are input to AI module. UB1, UB2 and UL2 are the
synchronism voltage from bus VT and line VT used for synchrocheck, it could be any
phase-to-ground voltage or phase-to-phase voltage. The device can automatically switch
synchronism voltage according to auxiliary contact of CB position or DS position.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
P2
P1
P1
P2
S1
S2
A
B
S2
S1
02
01
04
03
06
05
08
07
10
09
12
11
6-18
6 Hardware
A
13
14
15
16
17
18
19
20
21
22
23
24
Ia1
01
Ia1n
02
Ib1
03
Ib1n
04
Ic1
05
Ic1n
06
Ia2
07
Ia2n
08
Ib2
09
Ib2n
10
Ic2
11
Ic2n
12
Ua
13
Uan
14
Ub
15
Ubn
16
Uc
17
Ucn
18
UB1
19
UB1n
20
UL2
21
UL2n
22
UB2
23
UB2n
24
NR1401
6-19
Date: 2013-09-07
6 Hardware
3.
Definition
Definition
01
Ia1
02
Ia1n
03
Ib1
04
Ib1n
05
Ic1
06
Ic1n
07
Ia2
08
Ia2n
09
Ib2
10
Ib2n
11
Ic2
12
Ic2n
13
Ua
14
Uan
15
Ub
16
Ubn
17
Uc
18
Ucn
19
UB1
20
UB1n
21
UL2
22
UL2n
23
UB2
24
UB2n
25
GND
Ground
For two circuit breakers configuration with two CT groups input, three phase currents
corresponding to CB1 and CB2 respectively (Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2), and residual current
from parallel line (for mutual compensation) are input to AI module. Terminal 01, 03, 05, 07, 09, 11
and 13 are polarity marks. It is assumed that polarity mark of CT installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
6-20
6 Hardware
P2
P1
P1
P2
S1
S2
A
B
S2
S1
02
01
04
03
06
05
08
07
10
09
12
11
14
13
To parallel line
From parallel line
15
16
17
18
19
20
21
22
23
24
6-21
Date: 2013-09-07
6 Hardware
Ia1
01
Ia1n
02
Ib1
03
Ib1n
04
Ic1
05
Ic1n
06
Ia2
07
Ia2n
08
Ib2
09
Ib2n
10
Ic2
11
Ic2n
12
IM0
13
IM0n
14
Ua
15
Uan
16
Ub
17
Ubn
18
Uc
19
Ucn
20
Us
21
Usn
22
NR1401
23
24
Definition
Definition
01
Ia1
02
Ia1n
03
Ib1
04
Ib1n
05
Ic1
06
Ic1n
07
Ia2
08
Ia2n
09
Ib2
10
Ib2n
11
Ic2
12
Ic2n
13
IM0
14
IM0n
15
Ua
16
Uan
17
Ub
18
Ubn
19
Uc
20
Ucn
6-22
6 Hardware
Terminal No.
Definition
Definition
21
Us
22
Usn
Synchronism voltage
23
Reserve
24
Reserve
25
GND
Ground
NR1161
This device can be equipped with 2 DSP plug-in modules at most and 1 DSP plug-in module at
least. The default DSP plug-in module is necessary, which mainly is responsible for protection
function including fault detector and protection calculation.
The default module consists of high-performance double DSP (digital signal processor),16-digit
high-accuracy ADC that can perform synchronous sampling and manage other peripherals. One
of double DSP is responsible for protection calculation, and can fulfill analog data acquisition,
protection logic calculation and tripping output. The other is responsible for fault detector, and can
fulfill analog data acquisition, fault detector and providing power supply to output relay.
When the module is connected with conventional CT/VT, it can perform the synchronous data
acquisition through AI plug-in module. When the module is connected with ECT/EVT, it can
receive the real-time synchronous sampled value from merging unit through NET-DSP plug-in
module.
The other module is optional and it is not required unless control and manual closing with
6-23
Date: 2013-09-07
6 Hardware
synchronism check are equppied with this device. The default DSP plug-in module is fixed at slot
04 and the option DSP plug-in module is fixed at slot 06.
NR1136A
NR1136C
RX
This module consists of high-performance DSP (digital signal processor), 2~8 100Mbit/s
optical-fibre interface (LC type) and selectable IRIG-B interface (ST type). It supports GOOSE and
SV by IEC 61850-9-2 protocols. It can receive and send GOOSE messages to intelligent control
device, and receive SV from MU (merging unit).
This module supports IEEE1588 network time protocol, E2E and P2P defined in IEEE1588
protocol can be selected. This module supports Ethernet IEEE802.3 time adjustment message
format, UDP time adjustment message format and GMRP.
6-24
6 Hardware
NR1213
NR1213
NR1213
NR1213
NR1214
TX
TX
TX
TX
RX
RX
RX
RX
TX
TX
RX
RX
NR1214
TX1
TX1
RX1
RX1
TX1
RX1
NR1213A
NR1213A-100
NR1213B
NR1213B-100
NR1214A
NR1214B
Wavelength
Application
NR1213A
1310nm
NR1213A-100
1550nm
NR1213B
1310nm
NR1213B-100
1550nm
NR1214A
830nm
NR1214B
830nm
PCS-902 series can exchange information with the device at the remote end through a dedicated
optical fibre channel or multiplex channel. The module transmits and receives optical signal using
FC/PC or ST optical connector.
The parameters are shown as follows:
Type1
Type2
Type3
Fiber Optic
Wavelength
1310nm
1550nm
830nm
Transmission power
-13.03.0 dBm
-12dBm~-20 dBm
Receiving sensitivity
Min.-37 dBm
Min.-36 dBm
Min.-30 dBm
Transmission distance
Max.40 km
Max.100 km
Max.2 km
Min.-3 dBm
Min.-3 dBm
Min.-8 dBm
6-25
Date: 2013-09-07
6 Hardware
Note!
When using dedicated optical fibre channel, if the transmission distance is longer than
50km, the transmitted power may be enchanced to ensure received power larger than
receiving sensitivity. Please notify supplier before ordering and it will be considered as
special project using 1550nm laser diode.
When using multiplex channel, the sending power of the device is fixed.
When using channel multiplexing equipment, the parameters are shown as follows:
1.
2.
The routine of both direction shall be same to each other, so the time delays of both direction
are the same.
2.
The maximum one-way channel propagation delay shall be less than 15 ms.
Each BI module is with a 22-pin connector for 11 binary inputs (NR1503) or 18 binary inputs
(NR1504).
For NR1503, each binary input has independent negative power input of opto-coupler, and can be
6-26
6 Hardware
configurable. The terminal definition of the connector of BI plug-in module is described as below.
[BI_n] (n=01, 02,,11 can be configured as a specified binary input by PCS-Explorer software.)
NR1503
BI_01
01
Opto01-
02
BI_02
03
Opto02-
04
BI_03
05
Opto03-
06
BI_04
07
Opto04-
08
BI_05
09
Opto05-
10
BI_06
11
Opto06-
12
BI_07
13
Opto07-
14
BI_08
15
Opto08-
16
BI_09
17
Opto09-
18
BI_10
19
Opto10-
20
BI_11
21
Opto11-
22
Symbol
Description
01
BI_01
02
Opto01-
03
BI_02
04
Opto02-
05
BI_03
06
Opto03-
07
BI_04
08
Opto04-
09
BI_05
10
Opto05-
11
BI_06
12
Opto06-
13
BI_07
14
Opto07-
15
BI_08
16
Opto08-
17
BI_09
6-27
Date: 2013-09-07
6 Hardware
Terminal No.
Symbol
Description
18
Opto09-
19
BI_10
20
Opto10-
21
BI_11
22
Opto11-
For NR1504, all binary inputs share one common negative power input, and is configurable. The
terminal definition of the connector of BI plug-in module is described as below. [BI_n] (n=01,
02,,18 can be configured as a specified binary input by PCS-Explorer software.)
NR1504
Opto+
01
BI_01
02
BI_02
03
BI_03
04
BI_04
05
BI_05
06
BI_06
07
08
BI_07
09
BI_08
10
BI_09
11
BI_10
12
BI_11
13
BI_12
14
15
BI_13
16
BI_14
17
BI_15
18
BI_16
19
BI_17
20
BI_18
21
COM-
22
Symbol
Description
01
Opto+
02
BI_01
03
BI_02
04
BI_03
05
BI_04
06
BI_05
07
BI_06
08
Blank
Not used
09
BI_07
10
BI_08
6-28
6 Hardware
Terminal No.
Symbol
Description
11
BI_09
12
BI_10
13
BI_11
14
BI_12
15
Blank
Not used
16
BI_13
17
BI_14
18
BI_15
19
BI_16
20
BI_17
21
BI_18
22
COM-
First four binary signals (BI_01, BI_02, BI_03, BI_04) in first BI plug-in module are fixed, they are
[BI_TimeSyn], [BI_Print], [BI_Maintenance] and [BI_RstTarg] respectively.
1.
It is used to receive clock synchronization signal from clock synchronization device, the binary
input [BI_TimeSyn] will change from 0 to 1 once pulse signal is received. When the device
adopts Conventional mode as clock synchronization mode (refer to section Communication
Settings), the device can receives PPM (pulse per minute) and PPS (pulse per second). If the
setting [Opt_TimeSyn] is set as other values, this binary input is invalid.
2.
It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint]=1), report will be printed
automatically as soon as it is formed.
3.
It is used to block communication export when this binary input is energized. During device
maintenance or testing, this binary input is then energized not to send reports via communication
port, local display and printing still work as usual. This binary input should be de-energized when
the device is restored back to normal.
The application of the binary input [BI_Maintenance] for digital substation communication adopting
IEC61850 protocol is given as follows.
1)
a)
The protection device should send the state of this binary input to client.
b) When this binary input is energized, the bit Test of quality (Q) in the sent message changes
to 1.
c)
When this binary input is energized, the client cannot control the isolator link and circuit
6-29
Date: 2013-09-07
6 Hardware
a) When this binary input is energized, the bit Test in the GOOSE message sent by the
protection device changes to 1.
b) For the receiving end of GOOSE message, it will compare the value of the bit Test in the
GOOSE message received by it with the state of its own binary input (i..e [BI_Maintenance]), the
message will be thought as invalid unless they are conformable.
3)
a) When this binary input of merging unit is energized, the bit Test of quality (Q) of sampling
data in the SV message sent change 1.
b) For the receiving end of SV message, if the value of bit Test of quality (Q) of sampling data
in the SV message received is 1, the relevant protection functions will be disabled, but under
maintenance state, the protection device should calculate and display the magnitude of sampling
data.
c) For duplicated protection function configurations, all merging units of control module
configured to receive sampling should be also duplicated. Both dual protection devices and dual
merging units should be fully independent each other, and one of them is in maintenance state will
not affect the normal operation of the other.
4.
It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.
Note!
The rated voltage of binary input is optional: 110V, 125V, 220V or 250V, which must be
specified when placed order. It is necessary to check whether the rated voltage of BI
module complies with site DC supply rating before put the relay in service.
There three binary signals are fixed for measurement functions, they are [BI_Rmt/Loc],
[BI_ManSynCls] and [BI_ManOpen] respectively.
5.
6 Hardware
1: the remote control, all the binary outputs can only be remotely controlled by SCADA or control
centers.
0 the local control, each binary output can only be applied to open/close CB/DS/ES locally. Each
binary output can also be applied issue a signal locally.
6.
When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
synchronism check for closing circuit breaker will be initiated if it is energized.
7.
When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
control for open circuit breaker will be initiated if it is energized.
BO_01
NR1521A
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
6-31
Date: 2013-09-07
6 Hardware
BO_01
NR1521C
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
BO plug-in module (NR1521F) is dedicatedly for remote/manual open or closing to circuit breaker,
disconnector and earth switch. 5 pairs of binary outputs (one for open and the other for closing)
can be provided by this BO plug-in module configured in slot 15 if measurement and control
function is equipped with the device. Up to 10 pairs of binary outputs can be provided by two BO
plug-in modules that can be configured in slot 14 and 15 respectively. (BO plug-in module
configured in slot 14 is optional if open or closing contacts is not enough)
A normally open contact is presented via terminal 21-22 designated as ROS (i.e. remote operation
signal). Whenever any of binary output contacts for open or closing is closed, ROS contact will
close to issue a signal indicating that this device is undergoing a remote operation.
BO plug-in module (NR1521F) is displayed as shown in the following figure.
6-32
6 Hardware
BO_CtrlOpn01
NR1521F
BO_CtrlCls01
BO_CtrlOpn02
BO_CtrlCls02
BO_CtrlOpn03
BO_CtrlCls03
BO_CtrlOpn04
BO_CtrlCls04
BO_CtrlOpn05
BO_CtrlCls05
BO_Ctrl
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
NR1521G can provide 11 output contacts without controlled by fault detector. The first four output
contacts are in parallel with instantaneous operating contacts which are recommended to be
configured as fast signaling contacts to send PLC signal.
6-33
Date: 2013-09-07
6 Hardware
NR1521G
BO_01
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
6-34
7 Settings
7 Settings
Table of Contents
7 Settings ............................................................................................. 7-a
7.1 Communication Settings ................................................................................ 7-1
7.1.1 Setting Description .......................................................................................................... 7-2
7.1.2 Access Path ...................................................................................................................... 7-6
List of Tables
Table 7.2-1 Communication settings ..........................................................................................7-1
Table 7.2-1 System settings ......................................................................................................7-6
Table 7.3-1 Device settings .......................................................................................................7-7
7-a
Date: 2013-12-25
-09-07
7 Settings
7-b
7 Settings
The device has some setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active. However, communication settings, system
settings, device settings, logic link settings and measurement and control settings are common for
all protection setting groups.
Note!
All current settings in this chapter are secondary current converted from primary current by
CT ratio. Zero-sequence current or voltage setting is configured according to 3I0 or 3U0
and negative sequence current setting according to I2 or U2.
Item
Range
IP_LAN1
000.000.000.000~255.255.255.255
Mask_LAN1
000.000.000.000~255.255.255.255
IP_LAN2
000.000.000.000~255.255.255.255
Mask_LAN2
000.000.000.000~255.255.255.255
En_LAN2
0 or 1
IP_LAN3
000.000.000.000~255.255.255.255
Mask_LAN3
000.000.000.000~255.255.255.255
En_LAN3
0 or 1
IP_LAN4
000.000.000.000~255.255.255.255
10
Mask_LAN4
000.000.000.000~255.255.255.255
11
En_LAN4
0 or 1
12
Gateway
000.000.000.000~255.255.255.255
13
En_Broadcast
0 or 1
14
Addr_RS485A
0~255
15
Baud_RS485A
4800,9600,19200,38400,57600,115200 (bps)
16
Protocol_RS485A
0, 1 or 2
17
Addr_RS485B
0~255
18
Baud_RS485B
4800,9600,19200,38400,57600,115200 (bps)
19
Protocol_RS485B
0, 1 or 2
20
Threshold_Measmt
0~100%
21
Period_Measmt
0~65535s
22
Format_Measmt
0, 1
23
Baud_Printer
4800,9600,19200,38400,57600,115200 (bps)
24
En_AutoPrint
0 or 1
25
Opt_TimeSyn
26
IP_Server_SNTP
000.000.000.000~255.255.255.255
7-1
Date: 2013-12-25
-09-07
7 Settings
No.
Item
Range
27
IP_StandbyServer_SNTP
000.000.000.000~255.255.255.255
28
OffsetHour_UTC
-12~+12 (hrs)
29
OffsetMinute_UTC
0~60 (min)
30
Opt_Display_Status
PriValue, SecValue
31
t_Dly_Net_DNP
0~10000 (ms)
32
Fmt_Setting_DNP
0, 1, 2
IP address of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
2.
Subnet mask of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
3.
4.
Gateway
5.
En_Broadcast
This setting is only used only for IEC 60870-5-103 protocol. If NR network IEC 60870-5-103
protocol is used, the setting must be set as 1.
0: the device does not send UDP messages through network
1: the device sends UDP messages through network
6.
Addr_RS485A, Addr_RS485B
They are the devices communication address used to communicate with the SCADA or RTU via
serial ports (port A and port B).
7.
Baud_RS485A, Baud_RS485B
Protocol_RS485A, Protocol_RS485B
7-2
7 Settings
1: Modbus Protocol
2: Reserved
Note!
Above table listed all the communication settings, the device delivered to the user maybe
only show some settings of them according to the communication interface configuration.
If only the Ethernet ports are applied, the settings about the serial ports (port A and port B)
are not listed in this submenu. And the settings about the Ethernet ports only listed in this
submenu according to the actual number of Ethernet ports.
The standard arrangement of the Ethernet port is two, at most four (predetermined when
ordering). Set the IP address according to actual arrangement of Ethernet numbers and
the un-useful port/ports need not be configured. If PCS-Explorer configuration tool
auxiliary software is connected with this device through the Ethernet, the IP address of
PCS-Explorer must be set as one of the available IP address of this device.
9.
Threshold_Measmt
10. Period_Measmt
The time period for equipment sends measurement data to SCADA through IEC 60870-5-103
protocol.
Default value: 60
11. Format_Measmt
The setting is used to select the format of measurement data sent to SCADA through IEC
60870-5-103 protocol.
0: GDD data type through IEC103 protocol is 12
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard
12. Baud_Printer
Baud rate of printer port
13. En_AutoPrint
If automatic print is required for fault report after protection operating, it is set as 1. Otherwise, it
should be set to 0.
14. Opt_TimeSyn
There are four selections for clock synchronization of device shown as follow.
7-3
Date: 2013-12-25
-09-07
7 Settings
Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
IRIG-B (RS-485): IRIG-B via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn]
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn]
SAS
Advanced
NoTimeSync
When no time synchronization signal is connected to the device, please select this option and the
alarm message [Alm_TimeSyn] will not be issued anymore.
Conventional mode and SAS mode are always be supported by the device, but Advanced
mode is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn]
may be issued to remind user loss of time synchronization signals.
1)
When SAS is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When Conventional mode is selected, if there
is no conventional clock synchronization signal, SAS mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] issued simultaneously.
2)
3)
When NoTimeSyn mode is selected, the device will not send alarm signals without time
synchronization signal. But the device can be still synchronized if receiving time
synchronization signal.
Note!
The clock message via IEC 60870-5-103 protocol is invalid when the device receives the
IRIG-B signal through RCS-485 port.
7-4
7 Settings
15. IP_Server_SNTP
It is the address of the SNTP time synchronization server which sends SNTP timing messages to
the relay or BCU.
16. IP_StandbyServer_SNTP
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are inefffective unless SNTP clock
synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as 000.000.000.000, the
deivce receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as 000.000.000.000, the
deivce adopt the setting whose value is not equal to 000.000.000.000 as SNTP server address
and the deivce receives unicast SNTP synchronization message.
When neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] are set as 000.000.000.000, the
deivce adopt the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive the server responses after 30s, the
deivce adopt the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast
SNTP synchronization message. The device will switch between [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] repeatedly if the device always can not receive the server responses
waiting 30s
17. OffsetHour_UTC, OffsetMinute_UTC
If the IEC61850 protocol is adopted in substations, the time tags of communication messages are
required according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the GMT
(Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone of China is
east 8th time zone, so this setting is set as 8. The setting [OffsetMinute_UTC] is used to set the
minute offset of the current time zone to the GMT zone.
Time zone
Setting
Time zone
Setting
Time zone
Setting
Time zone
Setting
GMT zone
East 1st
East 2nd
East 3rd
East 4th
East 5th
th
th
East 6
East 7
7
th
East 8
8
st
East/West 12
West 1
12/-12
-1
th
th
East 9
9
nd
West 2
-2
th
th
rd
West 3
-3
th
th
East 10
East 11th
10
11
th
West 4
-4
th
West 5th
-5
th
West 6
West 7
West 8
West 9
West 10
West 11th
-6
-7
-8
-9
-10
-11
18. Opt_Display_Status
This setting is used to set display mode of current and voltage in fault records, primary value or
secondary value. The sampled values of current and voltage are displayed as secondary value by
default. When it is set as primary value, both secondary voltage and secondary current are
converted into primary voltage and primary current according to rated secondary and primary
PCS-902 Line Distance Relay
7-5
Date: 2013-12-25
-09-07
7 Settings
Item
Unit
Range
Active_Grp
1~10
Opt_SysFreq
50 or 60
PrimaryEquip_Name
Maximum 12 character
U1n
33~65500
kV
U2n
80~220
I1n
100~65500
I2n
1 or 5
f_High_FreqAlm
50~65
Hz
f_Low_FreqAlm
45~60
Hz
Hz
Active_Grp
The number of active setting group, 10 setting groups can be configured for protection settings,
and only one is active at a time
2.
PrimaryEquip_Name
It is recognized by the device automatically. Such setting is used for printing messages
3.
Opt_SysFreq
7-6
7 Settings
4.
Un1
Un2
In1
In2
f_High_FreqAlm
It is frequency upper limit setting.The device will issue an alarm [Alm_Freq], when system
frequency is higher than the setting.
9.
f_Low_FreqAlm
It is frequency lower limit setting.The device will issue an alarm [Alm_Freq], when system
frequency is lower than the setting.
Item
Range
HDR_EncodeMode
GB18030, UTF-8
Opt_Caption_103
0, 1 or 2
Bxx.Un_BinaryInput
HDR_EncodeMode
Opt_Caption_103
7-7
Date: 2013-12-25
-09-07
7 Settings
Default value of [Opt_Caption_103] is 0 (i.e. current language), and please set it to 1 (i.e. Fixed
Chinese) if the SAS is supplied by China Manufacturer.
3.
Bxx.Un_BinaryInput
This setting is used to set voltage level of binary input module. If low-voltage BI module is
equipped, 24V, 30V or 48V can be set according to the actual requirement, and if high-voltage BI
module is equipped, 110V, 125V or 220V can be set according to the actual requirement.
Bxx: this plug-in module is inserted in slot xx.
Item
Remark
Range
X1L
(0.000~4Unn)/In (ohm)
R1L
(0.000~4Unn)/In (ohm)
X0L
(0.000~4Unn)/In (ohm)
R0L
(0.000~4Unn)/In (ohm)
X0M
(0.000~4Unn)/In (ohm)
R0M
(0.000~4Unn)/In (ohm)
LineLength
0.00~655.35 (km)
phi1_Reach
30.00~89.00 (Deg)
Real_K0
10
Imag_K0
Resistive
component
of
zero-sequence
of
zero-sequence
compensation coefficient
Imaginary
component
compensation coefficient
-4.000~4.000
-4.000~4.000
Item
Remark
Range
FD.DPFC.I_Set
(0.050~30.000)In (A)
FD.ROC.3I0_Set
(0.050~30.000)In (A)
7-8
7 Settings
Item
AuxE.OCD.t_DDO
AuxE.OCD.En
AuxE.ROC1.3I0_Set
AuxE.ROC1.En
AuxE.ROC2.3I0_Set
AuxE.ROC2.En
AuxE.ROC3.3I0_Set
AuxE.ROC3.En
AuxE.OC1.I_Set
Remark
Range
0 or 1
0.000~10.000 (s)
auxiliary
element
Enable stage 2 residual current auxiliary element
Current setting of stage 3 residual current auxiliary
element
Enable stage 3 residual current auxiliary element
Current setting of stage 1 phase current auxiliary
element
Enable stage 1 phase current auxiliary element
(0.050~30.000)In
0 or 1
(0.050~30.000)In
0 or 1
(0.050~30.000)In
0 or 1
(0.050~30.000)In
10
AuxE.OC1.En
11
AuxE.OC2.I_Set
12
AuxE.OC2.En
13
AuxE.OC3.I_Set
14
AuxE.OC3.En
0 or 1
15
AuxE.UVD.U_Set
0~Un
16
AuxE.UVD.t_Ext
17
AuxE.UVD.En
18
AuxE.UVG.U_Set
19
AuxE.UVG.En
20
AuxE.UVS.U_Set
21
AuxE.UVS.En
22
AuxE.ROV.3U0_Set
0~Un
23
AuxE.ROV.En
0 or 1
0 or 1
(0.050~30.000)In
0 or 1
(0.050~30.000)In
0.000~10.000 (s)
0 or 1
0~Un
0 or 1
0~Unn
0 or 1
Item
Remark
Range
21D.Z_Set
(0.000~4Unn)/In (ohm)
21D.En
0 or 1
7-9
Date: 2013-12-25
-09-07
7 Settings
Item
Remark
Range
LoadEnch.phi_Blinder
LoadEnch.R_Blinder
(0.05~200)/In (ohm)
recommended.
3
LoadEnch.En
0 or 1
Item
21M.ZG.phi_Shift
21M.ZP.phi_Shift
21M.ZG1.Z_Set
21M.ZG1.t_Op
21M.ZG1.En
21M.ZG1.En_BlkAR
21M.ZP1.Z_Set
21M.ZP1.t_Op
21M.ZP1.En
10
21M.ZP1.En_BlkAR
11
21M.ZG2.Z_Set
12
21M.ZG2.t_Op
13
21M.ZG2.t_ShortDly
14
21M.ZG2.En
15
21M.ZG2.En_BlkAR
16
21M.ZP2.Z_Set
Remark
Range
0, 15 or 30 (Deg)
0, 15 or 30 (Deg)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
7-10
0 or 1
(0.000~4Unn)/In (ohm)
7 Settings
Time delay of zone 2 of phase-to-phase distance
17
21M.ZP2.t_Op
18
21M.ZP2.t_ShortDly
19
21M.ZP2.En
20
21M.ZP2.En_BlkAR
21
21M.Z2.En_ShortDly
22
21M.ZG3.Z_Set
23
21M.ZG3.t_Op
24
21M.ZG3.t_ShortDly
25
21M.ZG3.En
26
21M.ZG3.En_BlkAR
27
21M.ZP3.Z_Set
28
21M.ZP3.t_Op
29
21M.ZP3.t_ShortDly
30
21M.ZP3.En
31
21M.ZP3.En_BlkAR
32
21M.Z3.En_ShortDly
33
21M.Z4.Z_Fwd
34
21M.Z4.Z_Rev
35
21M.Z4.t_Op
0.000~10.000 (s)
36
21M.ZG4.En
0 or 1
37
21M.ZG4.En_BlkAR
38
21M.ZP4.En
39
21M.ZP4.En_BlkAR
protection
Short time delay of zone 2 of phase-to-phase distance
protection
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0 or 1
0 or 1
Item
21Q.ZG1.RCA
Remark
Downward offset angle of the reactance line for zone
1 of phase-to-ground distance protection
Range
0~45 (Deg)
7-11
Date: 2013-12-25
-09-07
7 Settings
2
21Q.ZG1.Z_Set
21Q.ZG1.R_Set
21Q.ZG1.t_Op
21Q.ZG1.En
21Q.ZG1.En_BlkAR
21Q.ZP1. RCA
21Q.ZP1.Z_Set
21Q.ZP1.R_Set
10
21Q.ZP1.t_Op
11
21Q.ZP1.En
12
21Q.ZP1.En_BlkAR
13
21Q.ZG2.RCA
14
21Q.ZG2.Z_Set
15
21Q.ZG2.R_Set
16
21Q.ZG2.t_Op
17
21Q.ZG2.t_ShortDly
18
21Q.ZG2.En
19
21Q.ZG2.En_BlkAR
20
21Q.ZP2. RCA
21
21Q.ZP2.Z_Set
22
21Q.ZP2.R_Set
23
21Q.ZP2.t_Op
24
21Q.ZP2.t_ShortDly
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0 or 1
0~45 (Deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0 or 1
0~45 (Deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
7-12
0 or 1
0~45 (Deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
7 Settings
25
21Q.ZP2.En
26
21Q.ZP2.En_BlkAR
27
21Q.Z2.En_ShortDly
28
21Q.ZG3.RCA
29
21Q.ZG3.Z_Set
30
21Q.ZG3.R_Set
31
21Q.ZG3.t_Op
32
21Q.ZG3.t_ShortDly
33
21Q.ZG3.En
34
21Q.ZG3.En_BlkAR
35
21Q.ZP3. RCA
36
21Q.ZP3.Z_Set
37
21Q.ZP3.R_Set
38
21Q.ZP3.t_Op
39
21Q.ZP3.t_ShortDly
40
21Q.ZP3.En
41
21Q.ZP3.En_BlkAR
42
21Q.Z3.En_ShortDly
43
21Q.ZG4.RCA
44
21Q.ZG4.Z_Set
45
21Q.ZG4.R_Set
46
21Q.ZG4.t_Op
47
21Q.ZG4.En
48
21Q.ZG4.En_BlkAR
0 or 1
0~45 (Deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0~45 (Deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0~45 (Deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0 or 1
7-13
Date: 2013-12-25
-09-07
7 Settings
49
21Q.ZP4. RCA
50
21Q.ZP4.Z_Set
51
21Q.ZP4.R_Set
52
21Q.ZP4.t_Op
53
21Q.ZP4.En
54
21Q.ZP4.En_BlkAR
0~45 (Deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0 or 1
Item
Remark
Range
21M.Pilot.Z_Set
(0.000~4Unn)/In (ohm)
21Q.Pilot.Z_Set
(0.000~4Unn)/In (ohm)
21M.Pilot.Z_Rev
(0.000~4Unn)/In (ohm)
21Q.Pilot.Z_Rev
(0.000~4Unn)/In (ohm)
21Q.Pilot.R_Set
(0.000~4Unn)/In (ohm)
21Q.Pilot.R_Rev
(0.000~4Unn)/In (ohm)
Item
68.En
Remark
Range
0 or 1
Item
21M.Z1.En_PSBR
21Q.Z1.En_PSBR
21M.Z2.En_PSBR
21Q.Z2.En_PSBR
21M.Z3.En_PSBR
21Q.Z3.En_PSBR
21M.Pilot.En_PSBR
Remark
Range
7-14
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
7 Settings
8
21Q.Pilot.En_PSBR
21M.I_PSBR
10
21Q.I_PSBR
0 or 1
(0.050~30.000)In (A)
(0.050~30.000)In (A)
Item
Remark
21SOTF.En
Range
0 or 1
21SOTF.Z2.En_ManCls
21SOTF.Z3.En_ManCls
21SOTF.Z4.En_ManCls
21SOTF.Z2.En_3PAR
0 or 1
21SOTF.Z3.En_3PAR
0 or 1
21SOTF.Z4.En_3PAR
0 or 1
21SOTF.Z2.En_PSBR
0 or 1
21SOTF.Z3.En_PSBR
0 or 1
10
21SOTF.Z4.En_PSBR
0 or 1
21SOTF.En_PDF
12
21SOTF.t_PDF
trip when fault occurs on healthy phase under pole 0.000~10.000 (s)
discrepancy situation
13
SOTF.Opt_Mode_ManCls
0, 1 or 2
Item
Remark
Range
FO.LocID
0-65535
FO.RmtID
0-65535
FO.Protocol
G.703 or C37.94
FOx.BaudRate
64 or 2048
FOx.En_IntClock
0 or 1
FOx.En
Enable channel x
0 or 1
7-15
Date: 2013-12-25
-09-07
7 Settings
Item
Remark
Range
85.Opt_PilotMode
0~2
85.Opt_Ch_PhSeg
85.En_WI
0 or 1
85.U_UV_WI
0~Unn (V)
85.Z.En
0 or 1
85.En_Unblocking1
0 or 1
85.t_DPU_Blocking1
85.t_DPU_CR1
0.000~1.000 (s)
85.t_DDO_CR1
0.000~1.000 (s)
10
85.ZX.En
0 or 1
11
85.t_DPU_ZX
0 or 1
0.000~1.000 (s)
0.000~10.000 (s)
Item
85.DEF.En
85.DEF.En_BlkAR
85.DEF_En_IndepCh
85.En_Unblocking2
85.DEF.3I0_Set
85.DEF.t_DPU
Remark
Range
0 or 1
setting
of
pilot
directional
earth-fault
protection
Time delay of pilot directional earth-fault protection
0 or 1
0 or 1
0 or 1
(0.050~30.000)In (A)
0.001~10.000 (s)
85.t_DPU_CR2
85.t_DDO_CR2
pilot
directional
earth-fault
protection
Item
RCA_OC
RCA_ROC
Remark
The
characteristic
angle
Range
of
directional
phase
overcurrent element
The characteristic angle of directional earth fault
element
7-16
30.00~89.00 (Deg)
30.00~89.00 (Deg)
7 Settings
The
characteristic
angle
of
directional
RCA_NegOC
Z0_Comp
(0.000~4Unn)/In (ohm)
Z2_Comp
(0.000~4Unn)/In (ohm)
30.00~89.00 (Deg)
Item
50/51P.K_Hm2
50/51P1.I_Set
50/51P1.t_Op
50/51P1.En
50/51P1.En_BlkAR
50/51P1.Opt_Dir
50/51P1.En_Hm2_Blk
50/51P1.Opt_Curve
50/51P1.TMS
10
50/51P1.tmin
11
50/51P1.Alpha
12
50/51P1.C
13
50/51P1.K
14
50/51P2.I_Set
15
50/51P2.t_Op
16
50/51P2.En
17
50/51P2.En_BlkAR
18
50/51P2.Opt_Dir
19
50/51P2.En_Hm2_Blk
Remark
Setting of second harmonic component for blocking
phase overcurrent elements
Current setting for stage 1 of phase overcurrent
protection
Time delay for stage 1 of phase overcurrent
protection
Enable stage 1 of phase overcurrent protection
Enable auto-reclosing blocked when stage 1 of
phase overcurrent protection operates
Direction option for stage 1 of phase overcurrent
protection
Enable second harmonic blocking for stage 1 of
phase overcurrent protection
Option of characteristic curve for stage 1 of phase
overcurrent protection
Time multiplier setting for stage 1 of inverse-time
phase overcurrent protection
Minimum operating time for stage 1 of inverse-time
phase overcurrent protection
Constant for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Constant C for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Constant K for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Current setting for stage 2 of phase overcurrent
protection
Time delay for stage 2 of phase overcurrent
protection
Enable stage 2 of phase overcurrent protection
Enable auto-reclosing blocked when stage 2 of
phase overcurrent protection operates
Direction option for stage 2 of phase overcurrent
protection
Enable second harmonic blocking for stage 2 of
phase overcurrent protection
Range
0.000~1.000
(0.050~30.000)In (A)
0.000~20.000 (s)
0 or 1
0 or 1
0, 1 or 2
0 or 1
0~13
0.010~200.000
0.000~20.000 (s)
0.010~5.000
0.000~200.000
0.050~20.000
(0.050~30.000)In (A)
0.000~20.000 (s)
0 or 1
0 or 1
0, 1 or 2
0 or 1
7-17
Date: 2013-12-25
-09-07
7 Settings
20
50/51P2.Opt_Curve
21
50/51P2.TMS
22
50/51P2.tmin
23
50/51P3.I_Set
24
50/51P3.t_Op
25
50/51P3.En
26
50/51P3.En_BlkAR
27
50/51P3.Opt_Dir
28
50/51P3.En_Hm2_Blk
29
50/51P3.Opt_Curve
30
50/51P3.TMS
31
50/51P3.tmin
32
50/51P4.I_Set
33
50/51P4.t_Op
34
50/51P4.En
35
50/51P4.En_BlkAR
36
50/51P4.Opt_Dir
37
50/51P4.En_Hm2_Blk
38
50/51P4.Opt_Curve
39
50/51P4.TMS
40
50/51P4.tmin
0.000~20.000 (s)
(0.050~30.000)In (A)
0.000~20.000 (s)
0 or 1
0, 1 or 2
0 or 1
0~12
0.010~200.000
0.000~20.000 (s)
(0.050~30.000)In (A)
0.000~20.000 (s)
0 or 1
7-18
0.010~200.000
0 or 1
0~12
0 or 1
0, 1 or 2
0 or 1
0~12
0.010~200.000
0.010~20.000 (s)
7 Settings
Item
Remark
Setting of second harmonic component for blocking
Range
50/51G.K_Hm2
50/51G1.3I0_Set
(0.050~30.000)In (A)
50/51G1.t_Op
0.000~20.000 (s)
50/51G1.En
0 or 1
50/51G1.En_BlkAR
50/51G1.Opt_Dir
50/51G1.En_Hm2_Blk
50/51G1.En_Abnor_Blk
50/51G1.En_CTS_Blk
0.000~1.000
0 or 1
0, 1 or 2
0 or 1
0 or 1
0 or 1
10
50/51G1.Opt_Curve
11
50/51G1.TMS
12
50/51G1.tmin
13
50/51G1.Alpha
14
50/51G1.C
15
50/51G1.K
16
50/51G2.3I0_Set
(0.050~30.000)In (A)
17
50/51G2.t_Op
0.000~20.000 (s)
18
50/51G2.En
0 or 1
19
50/51G2.En_BlkAR
20
50/51G2.Opt_Dir
21
50/51G2.En_Hm2_Blk
22
50/51G2.En_Abnor_Blk
23
50/51G2.En_CTS_Blk
24
50/51G2.Opt_Curve
fault protection
Time multiplier setting for stage 1 of inverse-time
earth fault protection
Minimum operating time for stage 1 of inverse-time
earth fault protection
Constant for stage 1 of customized inverse-time
characteristic earth fault protection
Constant C for stage 1 of customized inverse-time
characteristic earth fault protection
Constant K for stage 1 of customized inverse-time
characteristic earth fault protection
0~13
0.010~200.000
0.050~20.000 (t)
0.010~5.000
0.000~20.000
0.050~20.000
0 or 1
0, 1 or 2
0 or 1
0 or 1
0 or 1
0~12
7-19
Date: 2013-12-25
-09-07
7 Settings
Time multiplier setting for stage 2 of inverse-time
25
50/51G2.TMS
26
50/51G2.tmin
27
50/51G3.3I0_Set
(0.050~30.000)In (A)
28
50/51G3.t_Op
0.000~20.000 (s)
29
50/51G3.En
0, 1 or 2
30
50/51G3.En_BlkAR
31
50/51G3.Opt_Dir
32
50/51G3.En_Hm2_Blk
33
50/51G3.En_Abnor_Blk
34
50/51G3.En_CTS_Blk
35
50/51G3.Opt_Curve
36
50/51G3.TMS
37
50/51G3.tmin
38
50/51G4.3I0_Set
(0.050~30.000)In (A)
39
50/51G4.t_Op
0.000~20.000 (s)
40
50/51G4.En
0, 1 or 2
41
50/51G4.En_BlkAR
42
50/51G4.Opt_Dir
43
50/51G4.En_Hm2_Blk
44
50/51G4.En_Abnor_Blk
45
50/51G4.En_CTS_Blk
46
50/51G4.Opt_Curve
47
50/51G4.TMS
48
50/51G4.tmin
7-20
0.010~200.000
0.050~20.000 (s)
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0~12
0.010~200.000
0.050~20.000 (s)
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0~12
0.010~200.000
0.050~20.000 (s)
7 Settings
Item
50PVT.I_Set
50PVT.t_Op
50PVT.En
50GVT.3I0_Set
50GVT.t_Op
50GVT.En
Remark
Current setting of phase overcurrent protection
when VT circuit failure
Time delay of phase overcurrent protection when
VT circuit failure
Enable phase overcurrent protection when VT
circuit failure
Current setting of ground overcurrent protection
when VT circuit failure
Time delay of ground overcurrent protection when
VT circuit failure
Enable ground overcurrent protection when VT
circuit failure
Range
(0.050~30.000)In (A)
0.000~10.000 (s)
0 or 1
(0.050~30.000)In (A)
0.000~10.000 (s)
0 or 1
Item
Remark
Range
50GSOTF.3I0_Set
(0.050~30.000)In (A)
50GSOTF.En_3I0
0 or 1
Item
Remark
Range
59P1.U_Set
Un~2Unn (V)
59P1.t_Op
0.000~30.000 (s)
59P1.En
0 or 1
59P1.Opt_1P/3P
0 or 1
59P1.Opt_Up/Upp
0 or 1
59P1.En_Alm
59P1.En_52b_TT
59P1.En_TT
59P1.Opt_Curve
0 or 1
0 or 1
0 or 1
0~13
10
59P1.TMS
11
59P1.tmin
12
59P2.U_Set
Un~2Unn (V)
13
59P2.t_Op
0.000~30.000 (s)
14
59P2.En
0 or 1
overvoltage protection
Minimum delay for stage 1 of inverse-time overvoltage
protection
0.010~200.000
0.050~20.000 (s)
7-21
Date: 2013-12-25
-09-07
7 Settings
15
59P2.Opt_1P/3P
0 or 1
16
59P2.Opt_Up/Upp
0 or 1
17
59P2.En_Alm
18
59P2.En_52b_TT
19
59P2.En_TT
20
59P2.Opt_Curve
21
59P2.TMS
22
59P2.tmin
0 or 1
0 or 1
0 or 1
0~12
0.010~200.000
0.050~20.000 (s)
Item
Remark
Range
27P1.U_Set
0~Unn (V)
27P1.t_Op
0.000~30.000 (s)
27P1.En
0 or 1
27P1.Opt_1P/3P
0 or 1
27P1.Opt_Up/Upp
27P1.En_Alm
27P1.Opt_Curve
27P1.TMS
27P1.tmin
of
characteristic
curve
for
stage
of
undervoltage protection
Time multiplier setting for stage 1 of inverse-time
undervoltage protection
Minimum delay for stage 1 of inverse-time undervoltage
protection
0 or 1
0 or 1
0~13
0.010~200.000
0.050~20.000 (s)
10
27P2.U_Set
0~Unn (V)
11
27P2.t_Op
0.000~30.000 (s)
12
27P2.En
0 or 1
13
27P2.Opt_1P/3P
0 or 1
14
27P2.Opt_Up/Upp
15
27P2.En_Alm
16
27P2.Opt_Curve
17
27P2.TMS
of
characteristic
curve
for
stage
of
undervoltage protection
Time multiplier setting for stage 2 of inverse-time
undervoltage protection
7-22
0 or 1
0 or 1
0~12
0.010~200.000
7 Settings
18
27P2.tmin
0.050~20.000 (s)
Item
Remark
Range
81U.f_Pkp
81U.df/dt_Blk
81U.UF1.f_Set
81U.UF1.t_Op
0.050~30.000 (s)
81U.UF1.En
0 or 1
81U.UF1.En_df/dt_Blk
81U.UF2.f_Set
81U.UF2.t_Op
0.050~30.000 (s)
81U.UF2.En
0 or 1
0.200~20.000 (Hz/s)
45.000~60.000 (Hz)
0 or 1
45.000~60.000 (Hz)
10
81U.UF2.En_df/dt_Blk
11
81U.UF3.f_Set
12
81U.UF3.t_Op
0.050~30.000 (s)
13
81U.UF3.En
0 or 1
14
81U.UF3.En_df/dt_Blk
15
81U.UF4.f_Set
16
81U.UF4.t_Op
0.050~30.000 (s)
17
81U.UF4.En
0 or 1
18
81U.UF4.En_df/dt_Blk
19
81O.f_Pkp
20
81O.OF1.f_Set
21
81O.OF1.t_Op
0.050~20.000 (s)
22
81O.OF1.En
0 or 1
23
81O.OF2.f_Set
24
81O.OF2.t_Op
0.050~20.000 (s)
25
81O.OF2.En
0 or 1
26
81O.OF3.f_Set
underfrequency protection
Frequency setting for stage 3 of underfrequency
protection
0 or 1
45.000~60.000 (Hz)
0 or 1
45.000~60.000 (Hz)
0 or 1
50.000~65.000 (Hz)
50.000~65.000 (Hz)
50.000~65.000 (Hz)
50.000~65.000 (Hz)
7-23
Date: 2013-12-25
-09-07
7 Settings
27
81O.OF3.t_Op
0.050~20.000 (s)
28
81O.OF3.En
0 or 1
29
81O.OF4.f_Set
30
81O.OF4.t_Op
0.050~20.000 (s)
31
81O.OF4.En
0 or 1
50.000~65.000 (Hz)
Item
Remark
Range
50BF.I_Set
50BF.3I0_Set
50BF.I2_Set
50BF.t_ReTrp
0.000~10.000 (s)
50BF.t1_Op
0.000~10.000 (s)
50BF.t2_Op
0.000~10.000 (s)
50BF.En
0 or 1
50BF.En_ReTrp
0 or 1
50BF.En_3I0_1P
10
50BF.En_3I0_3P
11
50BF.En_I2_3P
12
50BF.En_CB_Ctrl
Item
Remark
Range
49-1.K
49-2.K
49.Ib_Set
49.Tau
49-1.En_Alm
49-1.En_Trp
49-2.En_Alm
7-24
7 Settings
8
49-2.En_Trp
Name
Remark
Range
50STB.I_Set
(0.050~30.000)In (A)
50STB.t_Op
0.000~10.000 (s)
50STB.En
0 or 1
Name
Remark
Range
50DZ.I_Set
(0.050~30.000)In (A)
50DZ.t_Op
0.000~10.000 (s)
50DZ.En
0 or 1
Item
Remark
Range
62PD.3I0_Set
62PD.I2_Set
62PD.t_Op
0.000~600.000 (s)
62PD.En
0 or 1
62PD.En_3I0/I2_Ctrl
Enable
residual
current
criterion
negative-sequence current criterion for
discrepancy protection
and
pole 0 or 1
Item
Remark
Range
46BC.I2/I1_Set
0.20~1.00
46BC.t_Op
0.000~600.000 (s)
46BC.I_Min
(0.050~30.000)In (A)
46BC.En_Trp
0 or 1
46BC.En_Alm
0 or 1
Item
Remark
Range
25.Opt_Source_UL
0~5
25.Opt_Source_UB
0~5
25.U_Dd
0.05Un~0.8Un (V)
7-25
Date: 2013-12-25
-09-07
7 Settings
4
25.U_Lv
0.5Un~Un (V)
25.K_Usyn
0.20-5.00
25.phi_Diff
0~ 89 (Deg)
25.phi_Comp
25.f_Diff
25.U_Diff
10
25.t_DdChk
11
25.t_SynChk
12
25.En_fDiffChk
0 or 1
13
25.En_SynChk
0 or 1
14
25.En_DdL_DdB
0 or 1
15
25.En_DdL_LvB
0 or 1
16
25.En_LvL_DdB
0 or 1
17
25.En_NoChk
0 or 1
0~359 (Deg)
0.02~1.00 (Hz)
0.010~25.000 (s)
Item
Remark
Range
79.N_Rcls
1~4
79.t_Dd_1PS1
0.000~600.000 (s)
79.t_Dd_3PS1
0.000~600.000 (s)
79.t_Dd_3PS2
0.000~600.000 (s)
79.t_Dd_3PS3
0.000~600.000 (s)
79.t_Dd_3PS4
0.000~600.000 (s)
79.t_CBClsd
0.000~600.000 (s)
79.t_CBReady
0.000~600.000 (s)
79.t_Wait_Chk
0.000~600.000 (s)
10
79.t_Fail
11
79.t_PW_AR
0.000~600.000 (s)
12
79.t_Reclaim
Reclaim time of AR
0.000~600.000 (s)
13
79.t_PersistTrp
reclosing successful
7-26
0.000~600.000 (s)
0.000~600.000 (s)
7 Settings
Drop-off time delay of blocking AR, when blocking
14
79.t_DDO_BlkAR
15
79.t_AddDly
16
79.t_WaitMaster
0.000~600.000 (s)
0.000~600.000 (s)
79.t_SecFault
18
79.En_PDF_Blk
19
79.En_AddDly
20
79.En_CutPulse
21
79.En_FailCheck
22
79.En
23
79.En_ExtCtrl
24
79.En_CBInit
25
79.Opt_Priority
Option of AR priority
26
79.SetOpt
0 or 1
27
79.En_1PAR
0 or 1
28
79.En_3PAR
0 or 1
29
79.En_1P/3PAR
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
Item
Remark
Range
TT.t_Op
0.000~600.000 (s)
TT.En_FD_Ctrl
0 or 1
Item
En_MPF_Blk_AR
En_3PF_Blk_AR
En_PhSF_Blk_AR
Remark
Enable auto-reclosing blocked when multi-phase fault
happens
Enable auto-reclosing blocked when three-phase fault
happens
Enable auto-reclosing blocked when selection of faulty
phase fails
Range
0 or 1
0 or 1
0 or 1
7-27
Date: 2013-12-25
-09-07
7 Settings
Enable three-phase tripping mode for any fault
En_Trp3P
t_Dwell_Trp
conditions
The dwell time of tripping command, empirical value is
0.04
0 or 1
0.000~10.000 (s)
Item
Remark
Range
VTS.t_DPU
0.200~100.000
VTS.t_DDO
0.200~100.000
VTS.En_Out_VT
0 or 1
VTS.En_LineVT
0 or 1
VTS.En
0 or 1
Item
Remark
Range
Link_01
0 or 1
Link_02
0 or 1
Link_03
0 or 1
Link_04
0 or 1
Link_05
0 or 1
Link_06
0 or 1
Link_07
0 or 1
Link_08
0 or 1
7-28
7 Settings
Item
Remark
Range
MCBrd.25.Opt_Source_UL
0~5
MCBrd.25.Opt_Source_UB
0~5
MCBrd.25.U_Dd
1.000~100.000 (V)
MCBrd.25.U_Lv
1.000~100.000 (V)
MCBrd.25.K_Usyn
0.20-5.00
MCBrd.25.phi_Diff
MCBrd.25.phi_Comp
MCBrd.25.f_Diff
MCBrd.25.U_Diff
10
MCBrd.25.En_SynChk
0 or 1
11
MCBrd.25.En_DdL_DdB
0 or 1
12
MCBrd.25.En_DdL_LvB
0 or 1
13
MCBrd.25.En_LvL_DdB
0 or 1
14
MCBrd.25.En_NoChk
0 or 1
15
MCBrd.25.df/dt
0~360 (Deg)
0.00~3.00 (Hz)
0.10~5.00 (Hz/s)
MCBrd.25.t_Close_CB
17
MCBrd.25.t_Wait_Chk
and
reference
voltage
involved
in
5.000~30.000 (s)
7-29
Date: 2013-12-25
-09-07
7 Settings
If a double point binary input changes from normal status to invalid status, i.e.: double point error
occurs, [CSWIxx.t_DPU_DPS] will be applied as the debouncing time for No.xx double point
binary input.
No.
Name
Remark
Range
CSWIxx.t_DPU_DPS
0~60000 (ms)
(xx=01, 02.10)
Name
Remark
Range
CSWIxx.t_PW_Opn
0~60000 (ms)
(xx=01, 02.10)
No.xx closing time of a normal open contact of remote
2
CSWIxx.t_PW_Cls
0~60000 (ms)
(xx=01, 02.10)
Name
Remark
Range
CSWIxx.En_Opn_Blk
0 or 1
(xx=01, 02.10)
Enable No.xx closing output of the BO module be
2
CSWIxx.En_Cls_Blk
0 or 1
(xx=01, 02.10)
7-30
8-a
Date: 2013-12-25
List of Figures
Figure 8.1-1 Front panel ............................................................................................................8-1
Figure 8.1-2 Keypad buttons ....................................................................................................8-2
Figure 8.1-3 LED indications ....................................................................................................8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel ..................................8-4
Figure 8.1-5 Rear view and terminal definition of NR1102C...................................................8-5
Figure 8.2-1 Menu tree ..............................................................................................................8-7
List of Tables
Table 8.1-1 Definition of the 8-core cable ................................................................................8-4
Table 8.3-1 Tripping report messages....................................................................................8-30
Table 8.3-2 User operating event list......................................................................................8-32
8-b
The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including r.m.s. current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad is also described in details.
Note!
8.1 Overview
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user. The HMI module helps to draw your
attention to something that has occurred which may activate a LED or a report displayed on the
LCD. Operator can locate the data of interest by navigating the keypad.
HEALTHY
11
13
14
15
16
17
18
19
10
20
GRP
PCS-902
12
ALARM
ESC
1
2
ENT
4
3
8-1
Date: 2013-12-25
Item
Description
A 320240 dot matrix backlight LCD display is visible in dim lighting
LCD
LED
Keypad
Communication port
Logo
GR
P
ENT
ESC
1.
2.
3.
ESC:
ENT:
GRP
4.
5.
6.
8-2
Page up/down
Display
Off
HEALTHY
Steady Green
Off
Description
When the equipment is out of service or any hardware error is defected during
self-check.
Lit when the equipment is in service and ready for operation.
When equipment in normal operating condition.
ALARM
Steady Yellow
Lit when VT circuit failure, CT circuit failure or other abnormal alarm is issued.
Note!
HEALTHY LED can only be turned on by energizing the device and no abnormality
detected.
ALARM LED is turned on when abnormalities of device occurs like above mentioned
and can be turned off after abnormalities are removed except alarm report [CTS.Alm]
which can only be reset only when the failure is removed and the device is rebooted or
re-energized.
Other LED indicators with no labels are configurable and user can configure them to be lit
by signals of operation element, alarm element and binary output contact according to
requirement through PCS-Explorer software, but as drawn in figure, 2 LEDs are fixed as
the signals of HEALTHY (green) and ALARM (yellow), 18 LEDs are configurable with
selectable color among green, yellow and red.
8-3
Date: 2013-12-25
as well as a twisted-pair ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel
Core color
Function
Device side
Computer side
(Left)
(Right)
Orange
P1-1
P2-1
P1-2
P2-2
P1-3
P2-3
Blue
P1-4
P3-2
P1-5
P3-3
Green
P1-6
P2-6
P1-7
P3-5
8-4
NR1102C
ETHERNET
Network A
Network B
SYN+
SYNSGND
GND
RTS
TXD
SGND
Note!
If using other Ethernet port, for example, Ethernet B, the logic setting [En_LAN2] must be
set as 1.
8-5
Date: 2013-12-25
MainMenu
Language
Clock
Quick Menu
For the first powered device, there is no record in quick menu. Press to enter the main menu
with the interface as shown in the following diagram:
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
The descriptions about menu are based on the maximized configuration, for a specific project, if
some function is not available, the corresponding submenu will hidden.
8-6
Measurements
Status
Records
Settings
Local Cmd
Information
Test
Clock
Language
Under main interface, press to enter main menu, and select submenu by pressing ,
and ENT. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all main menus (first-level menus) under menu tree of the
device.
Measurements
Measurements1
Measurements2
Measurements3
This menu is used to display real-time measured values, including AC voltage, AC current, phase
angle and calculated quantities. These data can help users to acquaint the devices status. This
menu comprises following submenus. Please refer to section Measurement about the detailed
measured values.
8-7
Date: 2013-12-25
Item
Measurements1
Measurements2
Measurements3
Function description
Display measured values from protection calculation DSP (Displayed in
secondary value)
Display measured values from fault detector DSP (Displayed in
secondary value)
Display measured primary values and other calculated quantities
8.2.3.2 Status
Main Menu
Status
Inputs
Outputs
Superv State
This menu is used to display real time input signals, output signals and alarm signals of the device.
These data can help users to acquaint the devices status. This menu comprises following
submenus. Please respectively refer to section Signal List about the detailed introduction of input
signals and output signals, and section Supervision Alarms about the detailed introduction of
alarm signals.
No.
Item
Function description
Inputs
Outputs
Superv State
Status
Inputs
Contact Inputs
GOOSE Inputs
Prot Ch Inputs
No.
1
Item
Contact Inputs
Function description
Display states of binary inputs derived from opto-isolated channels
8-8
GOOSE Inputs
Prot Ch Inputs
Status
Outputs
Contact Outputs
GOOSE Outputs
Interlock Status
Prot Ch Outputs
No.
Item
Function description
Contact Outputs
GOOSE Outputs
Interlock Status
Prot Ch Outputs
Status
Superv State
Prot Superv
FD Superv
GOOSE Superv
SV Superv
No.
Item
Function description
Prot Superv
FD Superv
GOOSE Superv
8-9
Date: 2013-12-25
SV Superv
8.2.3.3 Records
Main Menu
Records
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records
This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
This menu comprises the following submenus.
No.
Item
Function description
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records
8.2.3.4 Settings
Main Menu
Settings
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
This menu is used to check the device setup, system parameters, protection settings and logic
8-10
links settings, as well as modifying any of the above setting items. Moreover, it can also execute
the setting copy between different setting groups.
This menu comprises the following submenus.
No.
Item
Function description
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
Check or modify the logic links settings, including function links, SV links,
GOOSE links and spare links
Check or modify the device setup
8-11
Date: 2013-12-25
Settings
Prot Settings
Line Settings
FD Settings
AuxE Settings
Direction Settings
Pilot Scheme Settings
Rmt CommCh Settings
DPFC Dist Settings
LoadEnch Settings
Mho Dist Settings
Quad Dist Settings
ROC Settings
SOTF Settings
OC Settings
VTF OC Settings
BRC Settings
BFP Settings
Deadzone Settings
OV Settings
UV Settings
ThOvld Settings
PD Settings
Stub Settings
FreqProt Settings
MiscProt Settings
VTS/CTS Settings
Trip Logic Settings
AR/Syn Settings
Copy Settings
8-12
No.
Item
Function description
Line Settings
FD Settings
AuxE Settings
Direction Settings
LoadEnch Settings
10
11
ROC Settings
12
SOTF Settings
13
OC Settings
14
VTF OC Settings
15
BRC Settings
16
BFP Settings
17
Deadzone Settings
18
OV Settings
19
UV Settings
20
ThOvld Settings
21
PD Settings
22
Stub Settings
23
FreqProt Settings
24
MiscProt Settings
25
VTS/CTS Settings
26
27
AR/Syn Settings
28
Copy Settings
8-13
Date: 2013-12-25
Settings
BCU Settings
Syn Settings
BI Settings
Control Settings
Interlock Settings
No.
Item
Function description
Syn Settings
BI Settings
Control Settings
Interlock Settings
Settings
Logic Links
Function Links
GOOSE Links
SV Links
Spare Links
No.
Item
Function description
Function Links
GOOSE Links
SV Links
Spare Links
8-14
Settings
Logic Links
GOOSE Links
No.
Item
Function description
Settings
Device Setup
Device Settings
Comm Settings
Label Settings
No.
Item
Function description
Device Settings
Comm Settings
Label Settings
8-15
Date: 2013-12-25
8.2.3.5 Print
Main Menu
Device Info
Settings
Disturb Records
Superv Events
IO Events
Prot Ch Superv
Prot Ch Statistics
Device Status
Waveforms
IEC103 Info
Cancel Print
This menu is used to print device description, settings, all kinds of records, waveforms, information
related with IEC60870-5-103 protocol, channel state and channel statistic.
This menu comprises the following submenus.
No.
1
Item
Device Info
Function description
Print the description information of the device, including software
version.
Print device setup, system parameters, protection settings and logic
Settings
Disturb Records
Superv Events
IO Events
Prot Ch Superv
Prot Ch Statistics
Device Status
Print the statistic report of optical fibre channel, which is formed A.M.
9:00 every day
Print the current state of the device, including the sampled value of
voltage and current, the state of binary inputs, setting and so on
8-16
Waveforms
10
IEC103 Info
Cancel Print
Settings
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
All Settings
Latest Chgd Settings
No.
Item
Function description
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
All Settings
8-17
Date: 2013-12-25
Settings
Prot Settings
Line Settings
FD Settings
AuxE Settings
Direction Settings
Pilot Scheme Settings
Rmt CommCh Settings
DPFC Dist Settings
LoadEnch Settings
Mho Dist Settings
Quad Dist Settings
ROC Settings
SOTF Settings
OC Settings
VTF OC Settings
BRC Settings
BFP Settings
Deadzone Settings
OV Settings
UV Settings
ThOvld Settings
PD Settings
Stub Settings
FreqProt Settings
MiscProt Settings
VTS/CTS Settings
Trip Logic Settings
AR/Syn Settings
All Settings
8-18
No.
Item
Function description
Line Settings
FD Settings
AuxE Settings
Direction Settings
LoadEnch Settings
10
11
ROC Settings
12
SOTF Settings
13
OC Settings
14
VTF OC Settings
15
BRC Settings
16
BFP Settings
17
Deadzone Settings
18
OV Settings
19
UV Settings
20
ThOvld Settings
21
PD Settings
22
Stub Settings
23
FreqProt Settings
24
MiscProt Settings
25
VTS/CTS Settings
26
27
AR/Syn Settings
28
All Settings
8-19
Date: 2013-12-25
Settings
BCU Settings
Syn Settings
BI Settings
Control Settings
Interlock Settings
All Settings
No.
Item
Function description
Syn Settings
BI Settings
Control Settings
Interlock Settings
All Settings
Settings
Logic Links
Function Links
GOOSE Links
SV Links
Spare Links
All Settings
No.
1
Item
Function Links
Function description
Print function links settings
8-20
GOOSE Links
SV Links
Spare Links
All Settings
Settings
Logic Links
GOOSE Links
No.
Item
Function description
Settings
Device Setup
Device Settings
Comm Settings
Label Settings
All Settings
No.
Item
Function description
Device Settings
Comm Settings
8-21
Date: 2013-12-25
Label Settings
All Settings
Prot Ch Superv
Channel 1
Channel 2
No.
Item
Channel 1
Channel 2
Function description
Print the self-check information of optical fibre channel 1, which is made of some
hexadecimal characters and used to developer analyze channel state
Print the self-check information of optical fibre channel 2, which is made of some
hexadecimal characters and used to developer analyze channel state
Prot Ch Statistics
Channel 1
Channel 2
No.
Item
Channel 1
Channel 2
Function description
Print the statistic report of optical fibre channel 1, which is formed A.M. 9:00 every
day
Print the statistic report of optical fibre channel 2, which is formed A.M. 9:00 every
day
8-22
Waveforms
Wave
No.
1
Item
Function description
Wave
Local Cmd
Reset Target
Trig Oscillograph
Control
Download
Clear Counter
Clear AR Counter
Clear Energy Counter
This menu is used to reset the tripping relay with latch, indicator LED, LCD display, and as same
as the reset function of binary inputs. This menu provides a method of manually recording the
current waveform data of the device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download, clear statistic information about
GOOSE, SV, AR, FO channel and energy.
This menu comprises the following submenus.
No.
Item
Function description
Reset Target
Trig Oscillograph
Control
Download
Clear Counter
Clear AR Counter
8-23
Date: 2013-12-25
8.2.3.7 Information
Main Menu
Information
Version Info
Board Info
In this menu, LCD can display software information of all kinds of intelligent plug-in modules,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, plug-in module information can also be viewed.
This menu comprises the following command menus.
No.
Item
Function description
Display software information of DSP module, MON module and HMI module,
Version Info
Board Info
8.2.3.8 Test
Main Menu
Test
Prot Ch Counter
GOOSE Comm Counter
SV Comm Counter
Device Test
AR Counter
This menu is mainly used for developers to debug the program and for engineers to maintain the
device. It can be used to fulfill the communication test function. It is also used to generate all kinds
of reports or events to transmit to the SAS without any external input, so as to debug the
communication on site. Besides, it can also display statistic information about GOOSE, SV, AR
and FO channel.
This menu comprises the following submenus.
8-24
Item
Function description
Prot Ch Counter
GOOSE Counter
SV Counter
Device Test
AR Counter
Check AR counters
Test
Prot Ch Counter
Ch1 Counter
Ch2 Counter
No.
Item
Function description
Ch1 Counter
Ch2 Counter
Test
Device Test
Disturb Events
Superv Events
IO Events
No.
Item
Disturb Events
Superv Events
Function description
View the relevant information about disturbance records (only used for
debugging persons)
View the relevant information about supervision events (only used for
8-25
Date: 2013-12-25
View the relevant information about binary events (only used for debugging
IO Events
persons)
Users can respectively execute the test automatically or manually by selecting commands All
Test or Select Test.
The submenu Disturb Events comprises the following command menus.
Main Menu
Test
Device Test
Disturb Events
All Test
Select Test
No.
Item
Description
All Test
Select Test
Test
Device Test
Superv Events
All Test
Select Test
No.
Item
Description
All Test
Select Test
8-26
Test
Device Test
IO Events
All Test
Select Test
No.
Item
Description
All Test
Select Test
8.2.3.9 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
8.2.3.10 Language
This menu is mainly used to set LCD display language.
8-27
Date: 2013-12-25
Under normal condition, LCD will display the following interface. LCD adopts white color as its
backlight that is activated if once there is any keyboard operation, moreover, the backlight will be
extinguished automatically if no keyboard operation is detected for a duration.
2010-06-08 10:10:00
Ia
0.00A
Ib
0.00A
Ic
0.00A
3I0
0.00A
Ua
0.02V
Ub
0.00V
Uc
0.00V
3U0
0.02V
U_Syn
0.00V
50.00Hz
Addr 24343
Group 01
The content displayed on the screen contains: the current date and time of the device (with a
format of yyyy-mm-dd hh:mm:ss:), the active setting group number, three-phase current sampling
value, residual current sampling value, three-phase voltage sampling value, residual voltage
sampling value, the synchronism voltage sampling value, line frequency and the address relevant
to IP address of Ethernet A. If all the sampling values of the voltage and the current cant be fully
displayed within one screen, they will be scrolling-displayed automatically from the top to the
bottom.
If IP address of Ethernet A is xxx.xxx.a.b, the displayed address equals to (a256+b). For
example, If IP address of Ethernet A is 198.087.095.023, the displayed address will be 95
256+23=24343.
If the device has detected any abnormal state, itll display the self-check alarm information.
S indicates that device clock is synchronized. If S disappears, it means that device clock is not
synchronized.
are listed in the upper half part: record No., record name, generation time of the disturbance
record. If there is protection element operation, faulty phase and relative operation time (with
reference to the corresponding fault detector element) will be displayed. If the disturbance records
can not be displayed in one page, they will be displayed in several pages alternately.
If there is no supervision event, disturbance records will be displayed as shown in the following
figure.
2013-01-15 13:22:23:669
NO.001
0000ms
Disturb
FD.DPFC.Pkp
0024ms
AB
21Q.Z1.Op
If the device has the supervision event, the display interface will show the disturbance record and
the supervision event at the same time.
2013-01-15 13:22:23:669
NO.001
0000ms
Disturb
FD.DPFC.Pkp
0024ms
AB
21Q.Z1.Op
Superv Events
Alm_Device
NO.001
8-29
Date: 2013-12-25
2013-01-15 13:22:23:669
Disturb
0000ms FD.DPFC.Pkp
0024ms
AB
21Q.Z1.Op
All the protection elements have been listed in chapter Operation Theory, and please refer to
each protection element for details. The reports related to oscillography function are showed in the
following table.
Table 8.3-1 Tripping report messages
No.
Message
Description
TrigDFR_Man
TrigDFR_Rmt
TrigDFR_BI
Superv Events
Alm_Device
Alm_Version
8-30
Superv Events
Alm_Device
Alm_Version
NO.001
2013-01-15 13:31:23:669
BI_Maintenance
IO Chg
0
NO.001
2013-01-15 13:31:23:669
shows date and time when the report occurred, the format is
yyyy-mm-dd hh:mm:ss:fff.
IO Chg
BI_Maintenance
01
8-31
Date: 2013-12-25
2008-11-28 10:18:47:569
shows date and time when the report occurred, the format is
yearmonth-date and hour:minute:second:millisecond
Reboot
Message
Description
Reboot
Settings_Chg
ActiveGrp_Chgd
Report_Cleared
All reports have been deleted. (Device logs can not be deleted)
Waveform_Cleared
Process_Exit
Counter_Cleared
Clear counter
It will be displayed on LCD before disturbance records and supervision events are confirmed. Only
pressing both ENT and ESC at the same time can switch among disturbance records,
supervision events and the normal running state of the device to display it. IO events will be
displayed for 5s and then it will return to the previous display interface automatically.
2.
Press the or to move the cursor to the Measurements menu, and then press
8-32
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
4.
Press the or to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most);
5.
6.
Press the ENT or ESC to exit this menu (returning to the Measurements menu);
2.
Press the key or to move the cursor to the Status menu, and then press the
ENT or to enter the menu.
3.
Press the key or to move the cursor to any command menu item, and then press
the key ENT to enter the submenu.
4.
Press the or to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
5.
6.
Press the key ENT or ESC to exit this menu (returning to the Status menu).
2.
Press the or to move the cursor to the Records menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
4.
5.
6.
7.
Press the ENT or ESC to exit this menu (returning to the Records menu);
8-33
Date: 2013-12-25
2.
Press the or to move the cursor to the Print menu, and then press the ENT or
to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
Selecting the Disturb Records, and then press the or to select pervious
or next record. After pressing the key ENT, the LCD will display Start Printing... ,
and then automatically exit this menu (returning to the menu Print). If the printer
doesnt complete its current print task and re-start it for printing, and the LCD will
display Printer Busy. Press the key ESC to exit this menu (returning to the
menu Print).
Selecting the command menu Superv Events or IO Events, and then press the
key or to move the cursor. Press the or to select the starting and
ending numbers of printing message. After pressing the key ENT, the LCD will
display Start Printing, and then automatically exit this menu (returning to the
menu Print). Press the key ESC to exit this menu (returning to the menu Print).
4.
If selecting the command menu Device Info, Device Status or IEC103 Info, press
the key ENT, the LCD will display Start printing.., and then automatically exit this menu
(returning to the menu Print).
5.
If selecting the Settings, press the key ENT or to enter the next level of menu.
6.
After entering the submenu Settings, press the key or to move the cursor, and
then press the key ENT to print the corresponding default value. If selecting any item to
printing:
Press the key or to select the setting group to be printed. After pressing the key
ENT, the LCD will display Start Printing, and then automatically exit this menu
(returning to the menu Settings). Press the key ESC to exit this menu (returning to the
menu Settings).
7.
After entering the submenu Waveforms, press the or to select the waveform
item to be printed and press ENT to enter. If there is no any waveform data, the LCD will
display No Waveform Data! (Before executing the command menu Waveforms, it is
necessary to execute the command menu Trig Oscillograph in the menu Local Cmd,
otherwise the LCD will display No Waveform Data!). With waveform data existing:
Press the key or to select pervious or next record. After pressing the key ENT, the LCD
will display Start Printing, and then automatically exit this menu (returning to the menu
Waveforms). If the printer does not complete its current print task and re-start it for printing, and
the LCD will display Printer Busy. Press the key ESC to exit this menu (returning to the menu
Waveforms).
8-34
1.
2.
Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
4.
5.
6.
7.
Press the ESC to exit this menu (returning to the menu Settings).
Note!
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side of
the LCD to indicate the quantity of all displayed information of the command menu and the
relative location of information where the current cursor points at.
2.
Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
4.
5.
6.
7.
Press the ESC to exit this menu (returning to the menu Settings );
8.
If selecting the command menu System Settings, move the cursor to the setting item
to be modified, and then press the ENT;
Press the or to modify the value (if the modified value is of multi-bit, press the or
to move the cursor to the digit bit, and then press the or to modify the value), press the
ESC to cancel the modification and return to the displayed interface of the command menu
System Settings. Press the ENT to automatically exit this menu (returning to the displayed
interface of the command menu System Settings).
Move the cursor to continue modifying other setting items. After all setting values are modified,
press the , or ESC, and the LCD will display Save or Not?. Directly press the ESC or
8-35
Date: 2013-12-25
press the or to move the cursor. Select the Cancel, and then press the ENT to
automatically exit this menu (returning to the displayed interface of the command menu System
Settings).
Press the or to move the cursor. Select No and press the ENT, all modified setting item
will restore to its original value, exit this menu (returning to the menu Settings).
Press the or to move the cursor to select Yes, and then press the ENT, the LCD will
display password input interface.
Password:
____
Input a 4-bit password (, , and ). If the password is incorrect, continue inputting it,
and then press the ESC to exit the password input interface and return to the displayed interface
of the command menu System Settings. If the password is correct, LCD will display Save
Setting Now, and then exit this menu (returning to the displayed interface of the command
menu System Settings), with all modified setting items as modified values.
Note!
For different setting items, their displayed interfaces are different but their modification
methods are the same. The following is ditto.
9.
If selecting the submenu Prot Settings, and press ENT to enter. After selecting
different command menu, the LCD will display the following interface: (take FD
Settings as an example)
8-36
Line Settings
01
Selected Group:
02
Press the or to modify the value, and then press the ENT to enter it. Move the cursor to
the setting item to be modified, press the ENT to enter.
Take the setting [FD.DPFC.I_Set] as an example is selected to modify, then press the ENT to
enter and the LCD will display the following interface. is shown the or to modify the value
and then press the ENT to confirm.
FD.DPFC.I_Set
Current Value
0.200
Modified Value
0.202
Min Value
0.050
Max Value
30.000
Note!
After modifying protection settings in current active setting group or system parameters of
the device, the HEALTHY LED indicator the device will be lit off, and the MON module
will check the new settings. If the abnormality is detected during the setting check,
corresponding alarm signals will be issued. Moreover, if the critical error is detected, the
device will be blocked.
8-37
Date: 2013-12-25
2.
Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to the command menu Copy Settings, and
then press the ENT to enter the menu.
Copy Settings
Active Group:
01
Copy To Group:
02
Press the or to modify the value. Press the ESC, and return to the menu Settings.
Press the ENT, the LCD will display the interface for password input, if the password is incorrect,
continue inputting it, press the ESC to exit the password input interface and return to the menu
Settings. If the password is correct, the LCD will display copy setting OK!, and exit this menu
(returning to the menu Settings).
2.
8-38
Active Group:
01
Change To Group:
02
Press the or to modify the value, and then press the ESC to exit this menu (returning to
the main menu). After pressing the ENT, the LCD will display the password input interface. If the
password is incorrect, continue inputting it, and then press the ESC to exit the password input
interface and return to its original state. If the password is correct, the HEALTHY indicator lamp
of the protection device will go out, and the protection device will re-check the protection setting. If
the check doesnt pass, the protection device will be blocked. If the check is successful, the LCD
will return to its original state.
2.
Press the , , , and ENT; Press the ESC to exit this menu (returning to
the original state). Press the ENT to carry out the deletion.
8-39
Date: 2013-12-25
Note!
The operation of deleting device message will delete all messages saved by the protection
device, including disturbance records, supervision events, binary events, but not including
device logs. Furthermore, the message is irrecoverable after deletion, so the application of
the function shall be cautious.
2.
Press the key or to move the cursor to the command menu Local Cmd, and
then press the key ENT to enter submenus. Press the key or to move the
cursor to the command menu Control, and then press the key ENT to enter and the
following display will be shown on LCD.
Password:
000
Input a 3-bit password (111). If the password is incorrect, continue inputting it, and then press the
ESC to exit the password input interface and return to the displayed interface of the command
menu Control. If the password is correct, it will go to the following step.
3.
Press the key or to move the cursor to the control object and press the key
ENT to select control object.
8-40
Control
4.
1.
2.
CSWI02
3.
CSWI03
4.
CSWI04
5.
CSWI05
6.
CSWI06
7.
CSWI07
8.
CSWI08
9.
CSWI09
10.
CSWI10
Press the key or to select control command press the key ENT to the next step.
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterlockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
5.
Press the key or to select synchronism check mode and press the key ENT to
the next step.
8-41
Date: 2013-12-25
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterlockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
6.
Press the key or to select interlock mode and press the key ENT to next step.
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterLockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
7.
Press the key or to select control type and press the key ENT.
As shown in the following figure, operation results will be shown after Result at the bottom of the
LCD.
8-42
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterLockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
Note!
Exectue operation must be operated after Select operation.
2.
Press the or to move the cursor to the Clock menu, and then press the ENT
to enter clock display
3.
4.
Press the + or - to modify value, and then press the ENT to save the modification
and return to the main menu;
5.
Press the ESC to cancel the modification and return to the main menu.
8-43
Date: 2013-12-25
Clock
Year:
2008
Month:
11
Day:
28
Hour:
20
Minute:
59
Second:
14
2.
Press the or to move the cursor to the Information menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to the command menu Board Info, and then
press the ENT to enter the menu;
4.
5.
Press the ENT or ESC to exit this menu (returning to the Information menu).
2.
Press the or to move the cursor to the Information menu, and then press the
ENT to enter the submenu.
3.
Press the key or to move the cursor to the command menu Version Info, and
then press the key ENT to display the software version.
4.
2.
Press the key or to move the cursor to the Test menu, and then press the key
ENT or to enter the menu.
8-44
3.
Press the key or to move the cursor to the submenu Device Test, and then
press the key ENT to enter the submenu,to select test item. If Disturb Events
Superv Events or IO Events is selected, two options All Test and Select Test are
provided.
4.
Press the key or to move the cursor to select the corresponding command menu
All Test or Select Test. If selecting the All Test, press the ENT, and the device will
successively carry out all operation element message test one by one.
5.
If Select Test is selected, press the key ENT. Press the or to page up/down,
and then press the key or to move the scroll bar. Move the cursor to select the
corresponding protection element. Press the key ENT to execute the communication
test of this protection element, the substation automatic system (SAS) will receive the
corresponding message.
Note!
If no input operation is carried out within 60s, exit the communication transmission and
return to the Test menu, at this moment, the LCD will display Communication Test
Timeout and Exiting....
Press the key ESC to exit this menu (returning to the menu Test, at this moment, the LCD will
display Communication Test Exiting.
2.
Press the key or to move the cursor to the command menu Language, and
then press the key ENT to enter the menu and the following display will be shown on
LCD.
English
8-45
Date: 2013-12-25
3.
Press the key or to move the cursor to the language user preferred and press
the key ENT to execute language switching. After language switching is finished, LCD
will return to the menu Language, and the display language is changed. Otherwise,
press the key ESC to cancel language switching and return to the menu Language.
Note!
LCD interface provided in this chapter is only a reference and available for explaining
specific definition of LCD. The displayed interface of the actual device may be some
different from it, so you shall be subject to the actual protection device.
8-46
9 Configurable Function
9 Configurable Function
Table of Contents
9 Configurable Function..................................................................... 9-a
9.1 Overview .......................................................................................................... 9-1
9.2 Introduction on PCS-Explorer Software ........................................................ 9-1
9.3 Signal List ........................................................................................................ 9-1
9.3.1 Input Signal ........................................................................................................................ 9-2
9.3.2 Output Signal ................................................................................................................... 9-10
List of Tables
Table 9.3-1 Input signals ...........................................................................................................9-2
Table 9.3-2 Output signals ......................................................................................................9-10
9-a
Date: 2013-12-25
9 Configurable Function
9-b
9 Configurable Function
9.1 Overview
By adoption of PCS-Explorer software, it is able to make device configuration, function
configuration, LCD configuration, binary input and binary output configuration, LED indicator
configuration and programming logic for PCS-902.
9-1
Date: 2013-12-25
9 Configurable Function
Item
Description
Circuit breaker position supervision
52b_PhA
52b_PhB
52b_PhC
ManCls
52b
52a
TCCS.Input
AuxE.OCD.En
AuxE.OCD.Blk
10
AuxE.ROC1.En
11
AuxE.ROC1.Blk
12
AuxE.ROC2.En
13
AuxE.ROC2.Blk
14
AuxE.ROC3.En
15
AuxE.ROC3.Blk
16
AuxE.OC1.En
17
AuxE.OC1.Blk
18
AuxE.OC2.En
19
AuxE.OC2.Blk
20
AuxE.OC3.En
9-2
9 Configurable Function
No.
Item
Description
binary input or programmable logic etc.
21
AuxE.OC3.Blk
22
AuxE.UVD.En
23
AuxE.UVD.Blk
24
AuxE.UVG.En
25
AuxE.UVG.Blk
26
AuxE.UVS.En
27
AuxE.UVS.Blk
28
AuxE.ROV.En
29
AuxE.ROV.Blk
30
21D.En
31
21D.Blk
32
LoadEnch.En
33
LoadEnch.Blk
34
21M.En
35
21M.Blk
36
21M.ZGx.En
37
21M.ZGx.Blk
38
21M.ZPx.En
39
21M.ZPx.Blk
40
21M.Zx.En_ShortDly
41
21M.Zx.Blk_ShortDly
9-3
Date: 2013-12-25
9 Configurable Function
No.
Item
Description
42
21M.Z1.En_Instant
43
21Q.En
44
21Q.Blk
45
21Q.ZGx.En
46
21Q.ZGx.Blk
47
21Q.ZPx.En
48
21Q.ZPx.Blk
49
21Q.Zx.En_ShortDly
50
21Q.Zx.Blk_ShortDly
51
21Q.Z1.En_Instant
52
68.En
53
68.Blk
54
21M.En_PSBR
55
21Q.En_PSBR
56
21M.Blk_PSBR
57
21Q.Blk_PSBR
58
21SOTF.En
59
21SOTF.Blk
60
FOx.En
Enabling channel x
61
FOx.Send1
62
FOx.Send2
63
FOx.Send3
64
FOx.Send4
65
FOx.Send5
66
FOx.Send6
67
FOx.Send7
68
FOx.Send8
69
FOx.Send9
70
FOx.Send10
9-4
9 Configurable Function
No.
Item
Description
permissive signal (only for phase-segregated command scheme))
71
FOx.Send11
72
FOx.Send12
73
85.Z.En1
74
85.Z.En2
75
85.Z.Blk
76
85.Abnor_Ch1
77
85.Abnor_Ch2
Input signal of receiving permissive signal via channel No.1, or input signal of
78
85.Recv1
79
85.Recv2
80
85.RecvB
81
85.RecvC
82
85.ExTrp
Input signal of initiating sending permissive signal from external tripping signal
83
85.Unblocking1
Unblocking signal 1
84
85.Unblocking2
Unblocking signal 2
85
85.ZX.En1
86
85.ZX.En2
87
85.ZX.Blk1
88
85.ZX.Blk2
89
85.DEF.En1
90
85.DEF.En2
91
85.DEF.Blk
Input signal of receiving permissive signal of B-phase via channel No.1 (only
for phase-segregated command scheme)
Input signal of receiving permissive signal of C-phase via channel No.1 (only
for phase-segregated command scheme)
9-5
Date: 2013-12-25
9 Configurable Function
No.
Item
92
50/51Px.En1
93
50/51Px.En2
94
50/51Px.Blk
Description
Stage x of phase overcurrent protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage x of phase overcurrent protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage x of phase overcurrent protection blocking input, it is triggered from
binary input or programmable logic etc.
Earth fault protection
95
50/51Gx.En1
96
50/51Gx.En2
97
50/51Gx.Blk
98
50PVT.En1
99
50PVT.En2
100
50PVT.Blk
101
50GVT.En1
102
50GVT.En2
103
50GVT.Blk
104
50GSOTF.En1
105
50GSOTF.En2
106
50GSOTF.Blk
107
59Px.En1
108
59Px.En2
109
59Px.Blk
110
27Px.En1
9-6
9 Configurable Function
No.
Item
111
27Px.En2
112
27Px.Blk
Description
Stage x of undervoltage protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of undervoltage protection blocking input, it is triggered from binary
input or programmable logic etc.
Frequency protection
113
81U.En1
114
81U.En2
115
81U.Blk
116
81O.En1
117
81O.En2
118
81O.Blk
119
50BF.ExTrp3P_L
120
50BF.ExTrp3P_GT
121
50BF.ExTrpA
122
50BF.ExTrpB
123
50BF.ExTrpC
50BF.ExTrp_WOI
125
50BF.En
126
50BF.Blk
input.
When the input is 1, breaker failure protection is reset and time delay is
cleared.
Thermal overload protection
127
49.Clr_Cmd
128
49.En
129
49.Blk
130
50STB.En1
131
50STB.En2
9-7
Date: 2013-12-25
9 Configurable Function
No.
Item
Description
programmable logic etc.
132
50STB.Blk
133
50STB.89b_DS
134
50DZ.En1
Dead zone protection enabling input 1, it can be binary inputs or logic link.
135
50DZ.En2
Dead zone protection enabling input 2, it can be binary inputs or logic link.
136
50DZ.Blk
137
50DZ.Init
Dead zone protection blocking input, such as function blocking binary input.
When the input is 1, dead zone protection is reset and time delay is cleared.
Initiation signal input of the dead zone protection.
Pole discrepancy protection
138
62PD.En1
139
62PD.En2
140
62PD.Blk
141
46BC.En1
142
46BC.En2
143
46BC.Blk
144
25.Blk_Chk
145
25.Blk_SynChk
146
25.Blk_DdChk
147
25.Start_Chk
148
25.Blk_VTS_UB
149
25.Blk_VTS_UL
150
25.MCB_VT_UB
151
25.MCB_VT_UL
Input signal of blocking synchronism check for AR. If the value is 1, the
output of synchronism check is 0.
Input signal of blocking dead charge check for AR.
Input signal of starting synchronism check, usually it was starting signal of AR
from auto-reclosing module.
Auto-reclosing
Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1, enabling
152
79.En
153
79.Blk
154
79.Sel_1PAR
155
79.Sel_3PAR
9-8
9 Configurable Function
No.
Item
Description
156
79.Sel_1P/3PAR
157
79.Trp
158
79.Trp3P
159
79.TrpA
160
79.TrpB
161
79.TrpC
162
79.Lockout
79.PLC_Lost
Input signal of indicating the alarm signal that signal channel is lost
164
79.WaitMaster
165
79.CB_Healthy
166
79.Clr_Counter
167
79.Ok_Chk
Input signal of waiting for reclosing permissive signal from master AR (when
reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to perform
the close function
Transfer trip
168
TT.Init
169
TT.En
170
TT.Blk
171
VTS.En
172
VTS.Blk
173
VTNS.En
174
VTNS.Blk
175
VTS.MCB_VT
176
CTS.En
177
CTS.Blk
178
CSWIxx.CILO.EnOpn
179
CSWIxx.CILO.EnCls
180
Sig_Ok_Chk
9-9
Date: 2013-12-25
9 Configurable Function
No.
Item
Description
synchronism check(or dead check) can meet the criteria.
Within the duration of [MCBrd.25.t_Wait_Chk], if the synchronism check(or
dead check) criteria are not met, [Sig_Ok_Chk] will be set as 0; if the
synchronism check(or dead check) criteria are met, [Sig_Ok_Chk] will be set
as 1.
Access the menu Local CmdControl to issue control command locally.
181
CSWIxx.Cmd_LocCtrl
182
CSWIxx.Cmd_RmtCtrl
When the remote control is active, No.xx binary outputs can only be remotely
controlled by SCADA or control centers.
It is used to disable the interlock blocking function for control output. If the
183
CSWIxx.CILO.Disable
184
BIinput.RmtCtrl
When the remote control is active, all binary outputs can only be remotely
controlled by SCADA or control centers.
It is used to select the local control to No.xx controlled object (CB/DS/ES).
185
BIinput.LocCtrl
When the local control is active, all binary outputs can only be locally
controlled.
It is used to disable the interlock blocking function for control output. If the
186
BIinput.CILO.Disable
187
CSWI01.ManSynCls
the
condition
of
local
control
is
met
and
the
signal
188
CSWI01.ManOpn
Signal
Description
Circuit breaker position supervision
Alm_52b
CB position is abnormal
TCCS.Alm
FD.Pkp
FD.DPFC.Pkp
FD.ROC.Pkp
9-10
9 Configurable Function
No.
Signal
Description
Auxiliary element
AuxE.St
AuxE.OCD.St_Ext
AuxE.OCD.On
AuxE.ROC1.St
10
AuxE.ROC1.On
11
AuxE.ROC2.St
12
AuxE.ROC2.On
13
AuxE.ROC3.St
14
AuxE.ROC3.On
15
AuxE.OC1.St
16
AuxE.OC1.StA
17
AuxE.OC1.StB
18
AuxE.OC1.StC
19
AuxE.OC1.On
20
AuxE.OC2.St
21
AuxE.OC2.StA
22
AuxE.OC2.StB
23
AuxE.OC2.StC
24
AuxE.OC2.On
25
AuxE.OC3.St
26
AuxE.OC3.StA
27
AuxE.OC3.StB
28
AuxE.OC3.StC
29
AuxE.OC3.On
30
AuxE.UVD.St
31
AuxE.UVD.St_Ext
32
AuxE.UVD.On
33
AuxE.UVG.St
34
AuxE.UVG.StA
35
AuxE.UVG.StB
36
AuxE.UVG.StC
37
AuxE.UVG.On
38
AuxE.UVS.St
39
AuxE.UVS.StAB
40
AuxE.UVS.StBC
41
AuxE.UVS.StCA
42
AuxE.UVS.On
43
AuxE.ROV.St
44
AuxE.ROV.On
45
21D.Op
9-11
Date: 2013-12-25
9 Configurable Function
No.
Signal
Description
46
21D.On
47
LoadEnch.St
48
21M.Z1.On
49
21M.Z2.On
50
21M.Z3.On
51
21M.Z4.On
52
21M.Z1.Op
53
21M.Z2.Op
54
21M.Z3.Op
55
21M.Z4.Op
56
21Q.Z1.On
57
21Q.Z2.On
58
21Q.Z3.On
59
21Q.Z4.On
60
21Q.Z1.Op
61
21Q.Z2.Op
62
21Q.Z3.Op
63
21Q.Z4.Op
64
68.St
65
21M.Z1.Rls_PSBR
66
21Q.Z1.Rls_PSBR
67
21M.Z2.Rls_PSBR
68
21Q.Z2.Rls_PSBR
69
21M.Z3.Rls_PSBR
70
21Q.Z3.Rls_PSBR
71
21M.Pilot.Rls_PSBR
72
21Q.Pilot.Rls_PSBR
73
21SOTF.Op
74
21SOTF.Op_PDF
75
21SOTF.On
PSBR
operates
to
release
pilot
to
release
pilot
distance
protection
(Mho
characteristic)
PSBR
operates
distance
protection
(Quad
characteristic)
Accelerate distance protection to trip when manual closing or
auto-reclosing to fault
Accelerate distance protection to trip when another fault happening
under pole discrepancy conditions
Accelerate distance protection is enabled.
Optical pilot channel
76
FOx.On
Channel x is enabled.
77
FOx.Recv1
78
FOx.Recv2
79
FOx.Recv3
80
FOx.Recv4
81
FOx.Recv5
82
FOx.Recv6
9-12
9 Configurable Function
No.
Signal
Description
83
FOx.Recv7
84
FOx.Recv8
85
FOx.Recv9
86
FOx.Recv10
permissive
signal
of
B-phase
via
channel
No.1
(only
for
FOx.Recv11
permissive
signal
of
C-phase
via
channel
No.1
(only
for
FOx.Recv12
89
FOx.Alm
Channel x is abnormal
90
FOx.Alm_ID
85.Z.On
92
85.ZX.On
93
85.Op_Z
94
85.Send1
95
85.SendB
96
85.SendC
97
85.Op_ZX
98
85.ZX_St
99
85.DEF.On
100
85.Op_DEF
101
85.DEF_BlkAR
85.Send1
103
85.Send2
104
FwdDir_ROC
9-13
Date: 2013-12-25
9 Configurable Function
No.
Signal
Description
105
RevDir_ROC
106
FwdDir_NegOC
107
RevDir_NegOC
108
FwdDir_A
109
FwdDir_B
110
FwdDir_C
111
RevDir_A
112
RevDir_B
113
RevDir_C
114
FwdDir_AB
115
FwdDir_BC
116
FwdDir_CA
117
RevDir_AB
118
RevDir_BC
119
RevDir_CA
120
50/51Px.On
121
50/51Px.Op
122
50/51Px.St
123
50/51Px.StA
124
50/51Px.StB
125
50/51Px.StC
126
50/51Gx.On
127
50/51Gx.Op
128
50/51Gx.St
129
50PVT.On
130
50PVT.Op
131
50PVT.St
132
50PVT.StA
133
50PVT.StB
134
50PVT.StC
135
50GVT.On
136
50GVT.Op
137
50GVT.St
138
50GSOTF.On
139
50GSOTF.Op
140
50GSOTF.St
141
59Px.On
9-14
9 Configurable Function
No.
Signal
Description
142
59Px.Op
143
59Px.St
144
59Px.St1
145
59Px.St2
146
59Px.St3
147
59Px.Op_InitTT
148
59Px.Alm
149
27Px.On
150
27Px.Op
151
27Px.Alm
152
27Px.St
153
27Px.St1
154
27Px.St2
155
27Px.St3
156
81O.OFx.On
157
81O.OFx.Op
158
81O.St
159
81U.UFx.On
160
81U.UFx.Op
161
81U.St
162
50BF.On
163
50BF.Op_ReTrpA
164
50BF.Op_ReTrpB
165
50BF.Op_ReTrpC
166
50BF.Op_ReTrp3P
167
50BF.Op_t1
168
50BF.Op_t2
49.On
170
49.St
171
49-1.Op
172
49-2.Op
173
49-1.Alm
174
49-2.Alm
175
50STB.On
176
50STB.Op
177
50STB.St
178
50STB.StA
9-15
Date: 2013-12-25
9 Configurable Function
No.
Signal
Description
179
50STB.StB
180
50STB.StC
181
50DZ.On
182
50DZ.St
183
50DZ.Op
184
62PD.On
185
62PD.Op
186
62PD.St
187
46BC.On
188
46BC.St
189
46BC.Op
190
46BC.Alm
191
25.Ok_fDiffChk
192
25.Ok_UDiffChk
193
25.Ok_phiDiffChk
194
25.Ok_DdL_DdB
195
25.Ok_DdL_LvB
196
25.Ok_LvL_DdB
197
25.Chk_LvL
198
25.Chk_DdL
199
25.Chk_LvB
200
25.Chk_DdB
201
25.Ok_DdChk
202
25.Ok_SynChk
203
25.Ok_Chk
204
25.Alm_VTS_UB
205
25.Alm_VTS_UL
206
79.On
207
79.Off
208
79.Close
209
79.Ready
9-16
9 Configurable Function
No.
Signal
Description
210
79.AR_Blkd
211
79.Active
212
79.Inprog
213
79.Inprog_1P
214
79.Inprog_3P
215
79.Inprog_3PS1
216
79.Inprog_3PS2
217
79.Inprog_3PS3
218
79.Inprog_3PS4
219
79.WaitToSlave
220
79.Perm_Trp1P
221
79.Perm_Trp3P
222
79.Rcls_Status
223
79.Fail_Rcls
Auto-reclosing fails
224
79.Succ_Rcls
Auto-reclosing is successful
225
79.Fail_Chk
226
79.Mode_1PAR
227
79.Mode_3PAR
228
79.Mode_1/3PAR
Transfer trip
229
TT.Alm
230
TT.Op
231
TT.On
232
On
233
TrpA
234
TrpB
235
TrpC
236
Trp
237
Trp3P
238
BFI_A
239
BFI_B
240
BFI_C
241
BFI
9-17
Date: 2013-12-25
9 Configurable Function
No.
Signal
Description
242
Trp3P_PSFail
243
BlockAR
Blocking auto-reclosing
VT circuit supervision
244
VTS.Alm
245
VTNS.Alm
246
CTS.Alm
247
CSWIxx.Op_Opn
248
CSWIxx.Op_Cls
249
BIinput.RmtCtrl
250
BIinput.LocCtrl
output signals with input signals are available. The relationship with 10
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can
251
BIinput.CILO.Disable
252
PhSA
253
PhSB
254
PhSC
255
GndFlt
Earth fault
9-18
10 Communication
10 Communication
Table of Contents
10 Communication ............................................................................ 10-a
10.1 Overview ...................................................................................................... 10-1
10.2 Rear Communication Port Information ..................................................... 10-1
10.2.1 RS-485 Interface ............................................................................................................ 10-1
10.2.2 Ethernet Interface .......................................................................................................... 10-3
10.2.3 IEC60870-5-103 Communication ................................................................................... 10-4
10-a
Date: 2013-09-16
10 Communication
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements.....................................................10-2
Figure 10.2-2 Ethernet communication cable .......................................................................10-3
Figure 10.2-3 Ethernet communication structure .................................................................10-4
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance .........................10-8
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance .......................10-9
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances ..................10-10
10-b
10 Communication
10.1 Overview
This section outlines the remote communications interfaces of NR Relays. The protective device
supports a choice of three protocols via the rear communication interface (RS-485 or Ethernet),
selected via the model number by setting. The protocol provided by the protective device is
indicated in the menu SettingsDevice SetupComm Settings.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection of whichever
protocol is selected. The advantage of this type of connection is that up to 32 protective devices
can be daisy chained together using a simple twisted pair electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.
10-1
Date: 2013-09-16
Master
EIA RS-485
10 Communication
120 Ohm
120 Ohm
Slave
Slave
Slave
10-2
10 Communication
Note!
It is extremely important that the 120 termination resistors are fitted. Failure to do so will
result in an excessive bias voltage that may damage the devices connected to the bus.
As the field voltage is much higher than that required, NR cannot assume responsibility for
any damage that may occur to a device connected to the network as a result of incorrect
application of this voltage.
Ensure that the field voltage is not being used for other purposes (i.e. powering logic inputs)
as this may cause noise to be passed to the communication network.
10-3
Date: 2013-09-16
10 Communication
SCADA
Switch: Net A
Switch: Net B
Initialization (reset)
Time synchronization
General interrogation
General commands
Disturbance records
10-4
10 Communication
10.3.2 Initialization
Whenever the protective device has been powered up, or if the communication parameters have
been changed, a reset command is required to initialize the communications. The protective
device will respond to either of the two reset commands (Reset CU or Reset FCB), the difference
is that the Reset CU will clear any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10-5
Date: 2013-09-16
10 Communication
that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined in the
IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.
IEC 61850-5: Communications and requirements for functions and device models
IEC 61850-7-1: Basic communication structure for substation and feeder equipment
Principles and models
IEC 61850-7-2: Basic communication structure for substation and feeder equipment - Abstract
communication service interface (ACSI)
10-6
10 Communication
IEC 61850-7-3: Basic communication structure for substation and feeder equipment
Common data classes
IEC 61850-7-4: Basic communication structure for substation and feeder equipment
Compatible logical node classes and data classes
IEC 61850-8-1: Specific Communication Service Mapping (SCSM) Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
IEC 61850-9-1: Specific Communication Service Mapping (SCSM) Sampled values over
serial unidirectional multidrop point to point link
IEC 61850-9-2: Specific Communication Service Mapping (SCSM) Sampled values over
ISO/IEC 8802-3
IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
2.
Client/server
This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation equipment such
as protection relays, meters, RTUs, transformer, tap changers, or bay controllers.
3.
Peer-to-peer
A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has
10-7
Date: 2013-09-16
10 Communication
an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the individual ICD files and the SSD file, moreover, add
communication system parameters (MMS, GOOSE, control block, SV control block) and the
connection relationship of GOOSE and SV to SCD file.
Client
Client
Net A
Net B
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 1
RptEna = true
IED (Server)
IED (Server)
TCP Link
MMS Link
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance
10-8
10 Communication
Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: RptEna in above figure) is still true. Only when
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
false.
In normal operation status of this mode, IED provides the same MMS service for Net A and Net B.
If one net is physically disconnected (i.e.: Abnormal operation status in above figure), the
working mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In this mode, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.
10.4.3.2 Dual-net Hot-standby Mode Sharing the Same RCB Instance
Client
Net A
Client
Net B
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 1
RptEna = true
IED (Server)
IED (Server)
TCP Link
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance
In this mode, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:
Main MMS Link: Physically connected, TCP level connected, MMS report service available.
Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.
If the main net fails to operate (i.e.: Abnormal operation status in the above figure), the IED will
set RptEna to false. Meanwhile the client will detect the failure by heartbeat message or
keep-alive, it will automatically enable the RCB instance by setting RptEna back to true
PCS-902 Line Distance Relay
10-9
Date: 2013-09-16
10 Communication
through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCBs buffer function is limited.
Note!
The first mode and second mode, Net A IED host address and Net B IED host address
must be the same.
For example, if the subnet mask is 255.255.0.0, network prefix of Net A is 198.120.0.0,
network prefix of Net B is 198.121.0.0, Net A IP address of the IED is 198.120.1.2, and
then Net B IP address of the IED must be configured as 198.121.1.2, i.e., Net A IED host
address =1x256+2=258, Net B IED host address =1x256+2=258, Net A IED host address
equals to Net B IED host address.
10.4.3.3 Dual-net Full Duplex Mode with 2 Independent RCB Instances
Client
Net A
Client
Net B
Report Instance 1
RptEna = true
Report Instance 2
RptEna = true
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 2
RptEna = true
IED (Server)
IED (Server)
TCP Link
MMS Link
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances
In this mode, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of any net will not affect the other net at all. Tow report instances are
required for each client. Therefore, the IED may be unable to provide enough report instances if
there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.
10-10
10 Communication
As a conclusion, for the second mode, its difficult to realize seamless switchover between dual
nets, however, for the third mode, the IED may be unable to provide enough report instances if too
many clients are applied on site. Considering client treatment and IED implementation, the first
mode (Dual-net full duplex mode sharing the same report instance) is recommended for MMS
communication network deployment.
MMXU.MX.Hz: frequency
10-11
Date: 2013-09-16
10 Communication
PTUC: Undercurrent
PTOC: Phase overcurrent, zero-sequence overcurrent and overcurrent when VT circuit failure
PTUV: Undervoltage
PTOF: Overfrequency
PTUF: Underfrequency
RBRF:Breaker failure
RSYN: Synchronism-check
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags PTRC.ST.Str.general. The operate flag for PTOC1 is PTOC1.ST.Op.general. For
PCS-902 series relays protection elements, these flags take their values from related module for
the corresponding element. Similar to digital status values, the protection trip information is
reported via BRCB, and BRCB also locates in LLN0.
10.4.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
10-12
10 Communication
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defines for the whole device; the
common settings include all the setting items of communication settings, system settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. In
PCS-900 series relays, besides the logical nodes we describe above, there are some other logical
nodes below in the IEDs:
MMXU: This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as r.m.s. values for current and voltage or power flows out of the acquired voltage and
current samples. These values are normally used for operational purposes such as power
flow supervision and management, screen displays, state estimation, etc. The requested
accuracy for these functions has to be provided.
LPHD: Physical device information, the logical node to model common issues for physical
device.
PTRC: Protection trip conditioning, it shall be used to connect the operate outputs of one or
more protection functions to a common trip to be transmitted to XCBR. In addition or
alternatively, any combination of operate outputs of protection functions may be combined to
a new operate of PTRC.
RDRE: Disturbance recorder function. It triggers the fault wave recorder and its output refers
to the IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System
(IEC 60255-24). All enabled channels are included in the recording, independently of the
trigger mode.
10-13
Date: 2013-09-16
10 Communication
Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.4.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a GOOSE control block to configure and control the transmission.
10-14
10 Communication
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic link
settings in device.
The PCS-900 series relays support IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-900 series relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.
Client
Server
PCS-900 Series
B11
C1
B12
C1
Client-Server Roles
SCSMS Supported
B21
B22
B23
B24
SCSM: other
Publisher side
B32
Subscriber side
Publisher side
B42
Subscriber side
Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y:
N:
Logical device
Client
Server
PCS-900 Series
C2
C2
10-15
Date: 2013-09-16
10 Communication
M2
Logical node
C3
C3
M3
Data
C4
C4
M4
Data set
C5
C5
M5
Substitution
M6
M7
M7-1
sequence-number
M7-2
report-time-stamp
M7-3
reason-for-inclusion
M7-4
data-set-name
M7-5
data-reference
M7-6
buffer-overflow
M7-7
entryID
M7-8
BufTm
M7-9
IntgPd
M7-10
GI
M8
M8-1
sequence-number
M8-2
report-time-stamp
M8-3
reason-for-inclusion
M8-4
data-set-name
M8-5
data-reference
M8-6
BufTm
M8-7
IntgPd
M9
Log control
M9-1
IntgPd
M10
Log
M12
GOOSE
M13
GSSE
M14
Multicast SVC
M15
Unicast SVC
M16
Time
M17
File transfer
Reporting
Logging
GSE
Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared
10-16
10 Communication
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y:
N:
Server/Publisher
PCS-902
Server
S1
ServerDirectory
Application association
S2
Associate
S3
Abort
S4
Release
Logical device
S5
LogicalDeviceDirectory
Logical node
S6
LogicalNodeDirectory
S7
GetAllDataValues
S8
GetDataValues
S9
SetDataValues
S10
GetDataDirectory
S11
GetDataDefinition
S12
GetDataSetValues
S13
SetDataSetValues
S14
CreateDataSet
S15
DeleteDataSet
S16
GetDataSetDirectory
Data
Data set
Substitution
S17
SetDataValues
SelectActiveSG
M/O
S19
SelectEditSG
M/O
S20
SetSGValuess
M/O
S21
ConfirmEditSGValues
M/O
S22
GetSGValues
M/O
S23
GetSGCBValues
M/O
Reporting
Buffered report control block
S24
Report
10-17
Date: 2013-09-16
10 Communication
S24-1
data-change
S24-2
qchg-change
S24-3
data-update
S25
GetBRCBValues
S26
SetBRCBValues
Report
S27-1
data-change
S27-2
qchg-change
S27-3
data-update
S28
GetURCBValues
S29
SetURCBValues
Logging
Log control block
S30
GetLCBValues
S31
SetLCBValues
S32
QueryLogByTime
S33
QueryLogAfter
S34
GetLogStatusValues
Log
SendGOOSEMessage
S36
GetGoReference
S37
GetGOOSEElementNumber
S38
GetGoCBValues
S39
SetGoCBValuess
S51
Select
S52
SelectWithValue
S53
Cancel
S54
Operate
S55
Command-Termination
S56
TimeActivated-Operate
Control
File transfer
S57
GetFile
M/O
S58
SetFile
S59
DeleteFile
S60
GetFileAttributeValues
M/O
Time
SNTP
10-18
10 Communication
PCS-902 Series
YES
YES
PDIS: Distance
YES
YES
YES
PTOF: Overfrequency
YES
PTOV: Overvoltage
YES
YES
YES
PTUC: Undercurrent
PPDP: Pole discrepancy
YES
PTUV: Undervoltage
YES
YES
YES
10-19
Date: 2013-09-16
10 Communication
RBDR: Disturbance recorder channel binary
YES
YES
YES
RREC: Autoreclosing
YES
YES
CILO: Interlocking
YES
YES
MMTR: Metering
MMXU: Measurement
YES
10-20
10 Communication
X: Logical Nodes For Switchgear
TCTR: Current transformer
YES
YES
ZBAT: Battery
ZBSH: Bushing
ZCON: Converter
ZGEN: Generator
ZMOT: Motor
ZREA: Reactor
10-21
Date: 2013-09-16
10 Communication
2.
3.
Function Code
Object
Variation
Qualifier
Master
0x17
Slave
0x81
0x34
0x02
0x07
Master/Slave
Function Code
Object
Variation
Qualifier
Master
0x01
0x34
0x00, 0x01
0x07-
Slave
0x81
0x32
0x01
0x07
Function Code
Object
Variation
Qualifier
Master
0x02
0x32
0x01
Slave
0x81
2.
Function Code
Object
Variation
Qualifier
Master
0x02
0x50
0x01
0x00, 0x01
Slave
0x81
2.
Supported qualifiers
Master Qualifier
0x00
0x01
0x06
0x07
0x08
Slave Qualifier
0x00
0x01
0x01
0x07
0x08
0x00
0x01
0x02
Slave Variation
0x02
0x01
0x02
The protection operation signals, alarm signals and binary input state change signals are
transported respectively according to the variation sequence in above table.
Object 2, SOE
Master Variation
0x00
0x01
10-22
0x02
0x03
10 Communication
0x02
Slave Variation
0x01
0x02
0x03
If the master qualifier is 0x07, the slave responsive qualifier is 0x27; and if the master
qualifier is 0x01, 0x06 or 0x08, the slave responsive qualifier is 0x28.
0x00
0x01
0x02
0x03
0x04
Slave Variation
0x01
0x01
0x02
0x03
0x04
The measurement values are transported firstly, and then the measurement values are
transported.
0x00
0x01
0x02
Slave Variation
0x01
0x01
0x02
3.
4.
5.
0x17
0x27
0x18
0x28
10-23
Date: 2013-09-16
10 Communication
Slave Qualifier
0x17
0x27
0x18
0x28
0x01
Slave Variation
0x01
Control Code
0x01: closing
0x10: tripping
10-24
11 Installation
11 Installation
Table of Contents
11 Installation .................................................................................... 11-a
11.1 Overview ....................................................................................................... 11-1
11.2 Safety Information ........................................................................................ 11-1
11.3 Checking Shipment ...................................................................................... 11-2
11.4 Material and Tools Required........................................................................ 11-2
11.5 Device Location and Ambient Conditions.................................................. 11-2
11.6 Mechanical Installation ................................................................................ 11-3
11.7 Electrical Installation and Wiring ................................................................ 11-4
11.7.1 Grounding Guidelines .................................................................................................... 11-4
11.7.2 Cubicle Grounding ......................................................................................................... 11-4
11.7.3 Ground Connection on the Device ................................................................................. 11-5
11.7.4 Grounding Strips and their Installation............................................................................ 11-6
11.7.5 Guidelines for Wiring ...................................................................................................... 11-6
11.7.6 Wiring for Electrical Cables ............................................................................................ 11-7
List of Figures
Figure 11.6-1 Dimensions and panel cut-out of PCS-902 ..................................................... 11-3
Figure 11.6-3 Demonstration of plugging a board into its corresponding slot .................. 11-4
Figure 11.7-1 Cubicle grounding system ............................................................................... 11-5
Figure 11.7-2 Ground terminal of this relay ........................................................................... 11-6
Figure 11.7-3 Ground strip and termination .......................................................................... 11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ................................... 11-7
11-a
Date: 2013-09-11
11 Installation
11-b
11 Installation
11.1 Overview
The device must be shipped, stored and installed with the greatest care.
Choose the place of installation such that the communication interface and the controls on the
front of the device are easily accessible.
Air must circulate freely around the equipment. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the equipment and terminated correctly
and pay special attention to grounding. Strictly observe the corresponding guidelines contained in
this section.
11-1
Date: 2013-09-11
11 Installation
modules, bus backplanes are sensitive to electrostatic discharge when not in the unit's
housing.
The basic precautions to guard against electrostatic discharge are as follows:
Should boards have to be removed from this relay installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.
Only hold electronic boards at the edges, taking care not to touch the components.
Only works on boards that have been removed from the cubicle on a workbench designed for
electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
11-2
11 Installation
1.
The location should not be exposed to excessive air pollution (dust, aggressive substances).
2.
Severe vibration, extreme changes of temperature, high levels of humidity, surge voltages of
high amplitude and short rise time and strong induced magnetic fields should be avoided as
far as possible.
3.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
(visibility of markings).
WARNING!
Excessively high temperature can appreciably reduce the operating life of this relay.
Note!
It is necessary to leave enough space top and bottom of the cut-out in the cubicle for heat
emission of this relay.
The safety instructions must be abided by when installing the boards, please see Section 11.2 for
the details.
PCS-902 Line Distance Relay
11-3
Date: 2013-09-11
11 Installation
Following figure shows the installation way of a module being plugged into a corresponding slot.
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11 Installation
forming a resonant circuit at certain frequencies that would amplify the transmission of
interference by the devices installed and also reduce their immunity to induced interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
Note!
For metallic connections please observe the voltage difference of both materials according
to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a grounding strip
(braided copper).
Door or hinged
equipment frame
Cubicle ground
rail close to floor
Braided
copper strip
Station
ground
Conducting
connection
11-5
Date: 2013-09-11
11 Installation
Braided
copper strip
Terminal bolt
Contact surface
Power supply, binary inputs & outputs: brained copper cable, 1.0mm2 ~ 2.5mm2
11-6
11 Installation
Tighten
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
01
Figure 11.7-4 Glancing demo about the wiring for electrical cables
DANGER!
Never allow the current transformer (CT) secondary circuit connected to this equipment to
be opened while the primary system is live. Opening the CT circuit will produce a
dangerously high voltage.
11-7
Date: 2013-09-11
11 Installation
11-8
12 Commissioning
12 Commissioning
Table of Contents
12 Commissioning ............................................................................ 12-a
12.1 Overview ...................................................................................................... 12-1
12.2 Safety Instructions ...................................................................................... 12-1
12.3 Commission Tools ...................................................................................... 12-2
12.4 Setting Familiarization ................................................................................ 12-2
12.5 Product Checks ........................................................................................... 12-3
12.5.1 With the Relay De-energized ......................................................................................... 12-3
12.5.2 With the Relay Energized............................................................................................... 12-5
12.5.3 Print Fault Report ........................................................................................................... 12-8
12.5.4 On-load Checks ............................................................................................................. 12-8
12-a
Date: 2011-02-28
12 Commissioning
12-b
12 Commissioning
12.1 Overview
This relay is fully numerical in their design, implementing all protection and non-protection
functions in software. The relay employs a high degree of self-checking and in the unlikely event of
a failure, will give an alarm. As a result of this, the commissioning test does not need to be as
extensive as with non-numeric electronic or electro-mechanical relays.
To commission numerical relays, it is only necessary to verify that the hardware is functioning
correctly and the application-specific software settings have been applied to the relay.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the equipment, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the equipments rating label.
The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
The limit values stated in the Chapter Technical Data must not be exceeded at all, not even
during testing and commissioning.
When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
maybe also close commands to the circuit breakers and other primary switches are
disconnected from the device unless expressly stated.
12-1
Date: 2011-02-28
12 Commissioning
DANGER!
Current transformer secondary circuits must have been short-circuited before the current
leads to the device are disconnected.
WARNING!
Primary test may only be carried out by qualified personnel, who are familiar with the
commissioning of protection system, the operation of the plant and safety rules and
regulations (switching, earthing, etc.).
Multifunctional dynamic current and voltage injection test set with interval timer.
Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440V and 0~250V
respectively.
Optional equipment:
An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
12 Commissioning
and event records cleared. However, menu cells will require the appropriate password to be
entered before changes can be made.
Alternatively, if a portable PC is available together with suitable setting software (such as
PCS-9700 SAS software), the menu can be viewed one page at a time to display a full column of
data and text. This PC software also allows settings to be entered more easily, saved to a file on
disk for future reference or printed to produce a setting record. Refer to the PC software user
manual for details. If the software is being used for the first time, allow sufficient time to become
familiar with its operation.
Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware
defect. Defects of hardware circuits other than the following can be detected by
self-monitoring when the DC power is supplied.
Function tests
These tests are performed for the following functions that are fully software-based. Tests of
the protection schemes and fault locator require a dynamic test set.
Timers test
12-3
Date: 2011-02-28
12 Commissioning
Conjunctive tests
The tests are performed after the relay is connected with the primary equipment and other
external equipment.
On load test.
Protection panel
Carefully examine the protection panel, protection equipment inside and other parts inside to
see that no physical damage has occurred since installation.
The rated information of other auxiliary protections should be checked to ensure it is correct
for the particular installation.
Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section
meeting the requirement.
Carefully examine the wiring to see that they are no connection failure exists.
Label
Check all the isolator binary inputs, terminal blocks, indicators, switches and push buttons to
make sure that their labels meet the requirements of this project.
Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
12-4
12 Commissioning
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
DC power supply
Output contacts
Communication ports
12-5
Date: 2011-02-28
12 Commissioning
The current and voltage transformer connections must remain isolated from the relay for these
checks. The trip circuit should also remain isolated to prevent accidental operation of the
associated circuit breaker.
12.5.2.1 Front Panel LCD Display
Connect the relay to DC power supply correctly and turn the relay on. Check program version and
forming time displayed in command menu to ensure that are corresponding to what ordered.
12.5.2.2 Date and Time
If the time and date is not being maintained by substation automation system, the date and time
should be set manually.
Set the date and time to the correct local time and date using menu item Clock.
In the event of the auxiliary supply failing, with a battery fitted on CPU board, the time and date will
be maintained. Therefore when the auxiliary supply is restored the time and date will be correct
and not need to set again.
To test this, remove the auxiliary supply from the relay for approximately 30s. After being
re-energized, the time and date should be correct.
12.5.2.3 Light Emitting Diodes (LEDs)
On power up, the green LED HEALTHY should have illuminated and stayed on indicating that
the relay is healthy.
The relay has latched signal relays which remember the state of the trip, auto-reclose when the
relay was last energized from an auxiliary supply. Therefore these indicators may also illuminate
when the auxiliary supply is applied. If any of these LEDs are on then they should be reset before
proceeding with further testing. If the LED successfully reset, the LED goes out. There is no testing
required for that that LED because it is known to be operational.
It is likely that alarms related to voltage transformer supervision will not reset at this stage.
12.5.2.4 Testing HEALTHY and ALARM LEDs
Apply the rated DC power supply and check that the HEALTHY LED is lighting in green. We
need to emphasize that the HEALTHY LED is always lighting in operation course except that the
equipment find serious errors in it.
Produce one of the abnormal conditions listed in Chapter Supervision, the ALARM LED will
light in yellow. When abnormal condition reset, the ALARM LED extinguishes.
12.5.2.5 Testing AC Current Inputs
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.
The measurement accuracy of the protection is 2.5% or 0.02In. However, an additional allowance
12-6
12 Commissioning
must be made for the accuracy of the test equipment being used.
Note!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
Group No.
Item
Input Value
Input Angle
Display Value
Display Angle
Ia
Three-phase current 1
Ib
Ic
Ia
Three-phase current 2
Ib
Ic
Ia
Three-phase current 3
Ib
Ic
Ia
Three-phase current
Ib
Ic
Item
Input Value
Input Angle
Display Value
Display Angle
Ua
Three-phase voltage 1
Ub
Uc
Ua
Three-phase voltage 2
Ub
Uc
Three-phase voltage 3
Ua
12-7
Date: 2011-02-28
12 Commissioning
Group No.
Item
Input Value
Input Angle
Display Value
Display Angle
Ub
Uc
Ua
Three-phase voltage
Ub
Uc
Signal Name
BI Status on LCD
Correct?
Confirm the external wiring to the current and voltage inputs is correct.
12-8
12 Commissioning
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the protection in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and voltage
transformer wiring.
12-9
Date: 2011-02-28
12 Commissioning
12-10
13 Maintenance
13 Maintenance
Table of Contents
13 Maintenance ................................................................................. 13-a
13.1 Appearance Check ...................................................................................... 13-1
13.2 Failure Tracing And Repair ......................................................................... 13-1
13.3 Replace Failed Modules ............................................................................. 13-1
13.4 Cleaning ....................................................................................................... 13-3
13.5 Storage ......................................................................................................... 13-3
13-a
Date: 2011-02-28
13 Maintenance
13-b
13 Maintenance
NR numerical relay PCS-902 is designed to require no special maintenance. All measurement and
signal processing circuit are fully solid state. All input modules are also fully solid state. The output
relays are hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals are
not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
13-1
Date: 2011-02-28
13 Maintenance
Replacing a module
Short circuit all AC current inputs and disconnect all AC voltage inputs
2)
Unplug the ribbon cable on the front panel by pushing the catch outside.
3)
13-2
13 Maintenance
After replacing the CPU module, input the application-specific setting values again.
Warning!
Units and modules may only be replaced while the supply is switched off and only by
appropriately trained and qualified personnel. Strictly observe the basic precautions to
guard against electrostatic discharge.
Warning!
When handling a module, take anti-static measures such as wearing an earthed wrist band
and placing modules on an earthed conductive mat. Otherwise, many of the electronic
components could suffer damage. After replacing the CPU module, check the settings.
Danger!
After replacing modules, be sure to check that the same configuration is set as before the
replacement. If this is not the case, there is a danger of the unintended operation of
switchgear taking place or of protections not functioning correctly. Persons may also be
put in danger.
13.4 Cleaning
Before cleaning the relay, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
13.5 Storage
The spare relay or module should be stored in a dry and clean room. Based on IEC standard
60255-1 the storage temperature should be from -40oC to +70oC, but the temperature of from 0oC
to +40oC is recommended for long-term storage.
13-3
Date: 2011-02-28
13 Maintenance
13-4
14-a
Date: 2011-02-28
14-b
14.1 Decommissioning
1.
Switching off
To switch off the PCS-902, switch off the external miniature circuit breaker of the power supply.
2.
Disconnecting Cables
Disconnect the cables in accordance with the rules and recommendations made by relational
department.
Danger!
Before disconnecting the power supply cables that connected with the PWR module of the
PCS-902, make sure that the external miniature circuit breaker of the power supply is
switched off.
Danger!
Before disconnecting the cables that are used to connect analog input module with the
primary CTs and VTs, make sure that the circuit breaker for the primary CTs and VTs is
switched off.
3.
Dismantling
The PCS-902 rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
Danger!
When the station is in operation, make sure that there is an adequate safety distance to
live parts, especially as dismantling is often performed by unskilled personnel.
14.2 Disposal
In every country there are companies specialized in the proper disposal of electronic waste.
Note!
Strictly observe all local and national regulations when disposing of the device.
14-1
Date: 2011-02-28
14-2
R1.00
Software
Date
New
Version
R1.00
R1.00
2011-07-06
R1.01
R1.00
2011-08-18
Description of change
Form the original manual
Add frequency protection
Add stub overcurrent protection
Add the description about C37.94
Rewrite datas of ambient temperature and humidity
range and binary input
Amend fault detector (FD)
Add load encroachment element
R1.01
R1.02
R1.10
2011-12-23
R1.02
R1.03
R1.10
2012-03-15
R1.03
R1.04
R1.10
2012-05-09
2012-07-02
2012-07-07
R1.04
R1.05
R2.00
2012-08-14
2012-11-27
2012-11-30
2012-12-10
2013-02-19
R1.05
R1.06
R2.11
sequence
Modify mechanical installation size of the device
Modify the logic of AR
Add output sigals of function enabled and element
2013-05-29
15-1
Date: 2013-12-25
New
Software
Version
Date
Description of change
Modify function number of overcurrent protection for VT
circuit failure
Modify the setting description of clock synchronization
Add settings for broken conductor protection and modify
the logic
Add function block diagram for power swing blocking
releasing, current direction, trip logic, faulty phase
R1.05
R1.06
R2.12
2013-09-12
2013-11-11
R1.06
R1.07
R2.13
2013-12-25
the
seting
items
of
([Opt_Display_Status],
communication
setting
[t_Dly_Net_DNP],
[Fmt_Setting_DNP])
Add
the
setting
items
of
Quadrilateral
Distance
15-2
Date: 2013-12-25