3264.TI ECG Fundamentals Condensed v08 PDF

Analog Fundamentals of the ECG
Signal Chain
Prepared by
Matthew Hann,
Texas Instruments
Precision Analog Applications Manager
Presented by
Jose Duenas,
Precision Analog Product Marketing Engineer
Objectives
Introduce Basic ECG Concepts
Motivate the Need for TINA and SPICE
Simulation for ECG Analysis
Introduce Discrete Analog Functions of
the ECG Signal Chain
Motivate Need for Low Cost Integrated
ECG Conditioning System
Introduce the ADS1298 and Its
Embedded ECG Circuitry and Functions
2
Analog Fundamentals of the

ECG Signal Chain
What is a Biopotential?
What is ECG?
The Einthoven Triangle
Analog Lead Definitions, Derivations, and Purpose
Modeling the Electrode Interface
Input Filtering and Defibrillation Protection
The INA front end
AC vs. DC coupling
Right Leg Drive (RLD) Amplifier Selection and Design
The ECG Shield Drive
Lead Off Detection
PACE Detection
INA post Gain + Analog Filtering
A/D Conversion Options and Filtering
ADS129x Introduction, Features, and Advantages
3
What is a Biopotential?
41
What is a Biopotential
An electric potential measured between living cells
Every cell is like a little battery
Cell membrane
(lipids)
Intracellular medium/
Cytoplasmic fluid
Extracellular
medium/fluid
Resting ion chs.
Ion channels
Active ion pumps
(proteins)
Gated ion chs.
K+ is 30 to 50x
higher @ rest
Cell membrane
(lipids)
Electrostatic
Force
Na+ conc. is 10x

higher @ rest
Ion channels Resting ion chs.

Active ion pumps
(proteins)
Gated ion chs.
Diffusional
force
Cell membrane
(lipids)
Intracellular medium/
Cytoplasmic fluid
Extracellular
medium/fluid
Neurotransmitter are
received at dendrites
Resting ion chs.
Ion channels Active ion pumps

(proteins)
Gated ion chs.
Biopotentials from cells
electrodes
What is ECG?
101
What is ECG?
A measure of the electrical activity of the heart
11
What is ECG?
ECG and blood pressure waves
12
What is ECG?
Actual ECG-normal
13
What is ECG?
ECG irregular tracings due to external artifacts
14
What is ECG?
Modeling the electrode interface
Electrical characteristics include a DYNAMIC resistance,

capacitance, and offset voltage
15
Analog Lead Derivation
161

ECG Einthoven Triangle, 1907
3 Body Electrodes,
3 Derived Leads = I, II, III
LEAD I = VLA-RL VRA-RL
LEAD II = VLL-RL VRA-RL
LEAD III = VLL-RL VLA-RL
Einthovens Law
Right Leg
Reference,
RL
In electrocardiogram at any
given instant the potential of
any wave in Lead II is equal
to the sum of the potentials
in Lead I and III.
17

The Wilson Central (WCT) Provides Chest Lead
Reference at Center of Einthoven Triangle
Assuming:
RRA = RLA = RLL
Then:
3
WCT
RA LA LL
RRA
RRA
WCT
RA LA LL
3
18
*Drawing Taken From Bioelectromagnetism, Jaako Malmivuo and Robert Plonsey

The Wilson Central is the AVERAGE potential
between RA, LA, and LL
RRA
RLA
RLL
VOUT = V(1-6) - VWCT

The Wilson Central
is used to derive a
reference potential
for the Chest Leads,
V1 V6
19

Chest Lead Signals Provide Different Information at
Different Cross-Sectional Angles
Different Chest Leads

Provide:
*Unique ECG Signature
*Enhanced Pattern
Recognition
*Isoelectric Point @ V3-V4
20

Augmented Leads Derived via WCT to Provide
Enhanced Vector Information
Each lead provides

unique information about
the ECG Output Signal
Multiple Angles Give a

Better Than 2-D Picture
of the ECG Output
AVR, AVL, AVF derived
via midpoint of 2 limbs
(resistor divider) with
Respect to 3rd limb
21

IEC60601-2-51Diagnostic
Standards
Electrodes Needed
1 Lead
3 Lead
6 Leads
12 Leads
LA, RA
LA, RA, LL
LA, RA, LL
LA, RA, LL, V1-6
22

Different Lead Combinations Reveal Axis Deviation
Left Axis
Deviation
(LAD)
QRS in AVF
QRS in LEAD I
and
=
+
Mean QRS Vector Points Toward Area of Infarction (Damage)
23

Different Lead Combinations Reveal Axis Deviation
I
AVF
or
m
al
AVF
LA
AVF
Ex
tr
R em
A
D e
AVF
24
ECG Input Filtering, Defibrillation

Protection, and Isolation
251
ECG Input Filtering and Protection

Example: LEAD I Protection with Input Filtering
Series Resistance
Limits Input Current
CF, Ccm, and Cdiff +

Rfilter form LPF
Protection
Diodes
+Vs
RPatient
Rfilter1
Rfilter2
LA
CF
NE2H
RPatient
CCM
Rfilter2
Rfilter1
Cdiff
+Vs
-Vs
Zener
Diode
RA
NE2H
CF
CCM
-Vs
Patient
Protection 10
-20k ohms
Ne2H Lamps/TVS Protect

Against Defibrillation
Voltages
Cdiff = 10 x Ccm
26
System Block Diagram
271
System Block Diagram

Wilson
INA
MUX
I
dV/dt
II
RA
QRS and PACE

Detect
III
LA
aVR
LL
aVL
aVF
RL
Filter
Isolation
MUX
WCT
INA
V1
V2
A/D
DIO
V3
V4
V5
V6
28
The INA Front End
291
The INA Front End

Key Features of the INA Front End
*Important*
Less Important
Input Bias Current
Input Offset Voltage
Input Impedance
Input Offset Voltage Drift
Input Current Noise
Gain Error
Input Voltage Noise
Nonlinearity
Power Consumption
PSRR
DC/AC CMRR
*DC Errors such as VOS are swamped out by the

Offsets Introduced by the Skin-Electrode Contacts
30
The INA Front End

Ideal Simulation Circuit with Current and Voltage Noise
Sources
ECG + Skin
Impedance
R20 1k
ECGp
C9 47n
C8 100p
V5 0
R23 1k
R25 1k
R22 100k
R4 63.4k
nV
R1 63.4k
V n12 Vnoise
R3 63.4k
R5 63.4k
C10 33p C18 33p
V4 0
C20 330p
R19 1k
R14 100k
Vref
Ideal INA
Front End
C7 47n
C12 33p C19 33p
C6 100p
R21 1k
Input CM +
Differential
Filtering
Electrode
Impedance +
Offset
Vout
+
INA 1
Vref
R24 1k
fA
In12 In_fA
31
The INA Front End

Simulation Showing Output-Referred Total RMS Noise
vs. Bandwidth (G = 1-10)
-Vdif
2
Vin-
+
-
Rg 1k
VCM
+
Va1
A1
150k
50k
Noise may NOT necessarily

increase linearly with gain
(INA or PGA topology
dependent)
150k
A3
Vout
+
50k
+
150k
T 32.00u
A2
Va2
28.00u
Vin+
24.00u
Total noise (V)
Vdif
2
150k
20.00u
16.00u
12.00u
8.00u
4.00u
0.00
1.00
10.00
100.00
1.00k
Frequency (Hz)
32
The INA Front End

TINA Simulations Showing Output-Referred ECG Signal
(G = 1-10)
Snapshot of R
Wave from
ECG Waveform
Voltage (V)
T 2.51
2.50
ECG Signal Varies

LINEARLY with
Increase in Gain
33
2.50
8.37m
366.11m
Time (s)
723.85m
The INA Front End

What is the MAX gain on the INA When Using a DC
Removal Circuit?
Integrator Removes
Gained up DC offsets and
servos INA output to Vref
(1)
(3)
Vref
(2)
(1) Electrode Offset MAX = +/- 300mV

(2) Swing of INA = V(+) 50mV
(3) Integrator Compliance = (ECGp + ECGn +VOS + VOSelectrode)* Gain < VCC - Vref
34
The INA Front End

Simulation Circuit with Ideal INA and Vref = 2.5V as
Integrator Input
47n
63.4k
63.4k
Vref
Vout
-150m
33p
33p
47n
ECGn
33p
52k
Vref
1k
VCVS1 1
+
+
100k
63.4k
33p
ECGp
63.4k
100n
150m
330p
1k
VCC
OPA333
52k
OPA333 Used as Integrator

to Remove DC and Simulate
Real Response During
Saturation
35
The INA Front End

ECG + Integrator Output of INA vs. Gain for Vref = 2.5V
2.50
Vout[G = 1]
2.50
2.50
Vout[G = 3]
As the output of the

Integrator Saturates from
Increased Gain, Vout of the
INA pulls away from Vref
2.50
2.50
Vout[G = 6]
2.50
2.50
Vout[G = 8]
2.49
2.71
Vout[G=9]
2.70
3.01
Vout[G=10]
3.00
0.00
750.00m
Time (s)
1.50
36
The INA Front End

If it is Advantageous to Maximize Gain with a Low Noise
INA up Front, Why not AC Couple?
ECGp
VCM + ECGp +
VOSelectrode1
(ECGp ECGn)*Gain
VCM + ECGn +
VOSelectrode2
ECGn
*AC Coupling Removes Electrode

Offsets so that Higher Gain Can Be
Used for Potentially Better SNR in the
Signal Chain Path
37
The INA Front End

TINA Simulation Circuit to Show AC-Coupled INA Gain
Sweep
C2 47n
R14 10M
Vref
ECGn
C8 33p
ECGp
C4 47n
V4 0
R10 63.4k
R11 63.4k
CCp 1u
C5 33p
C6 33p
R4 52k
R9 63.4k
C7 33p
R8 63.4k
C9 330p
V3 0
Vref
INA 1
CCn 1u
Vout
Vref
R7 52k
Vref
R13 10M
38
The INA Front End

INA Gain = 1-1000 with VREF = 2.5V AC Coupled
3.06
2.79
Voltage (V)
2.52
2.25
1.98
1.71
723.18m
969.60m
Time (s)
1.22
39
The INA Front End

What is CMRR? Why is it Important in ECG?
ECGp
V out
VCM
Lower CMRR = More

Unwanted Output Signal
ECGn
V CM
CMRR 20log 10
V OS
Vout
V OS Gain
V CM Gain
20
V out
V CM
ECGp ECGn VOSelectrode VOSOPA

CMRR
20
10
Gain
40
The INA Front End

What is CMRR? Why is it Important in ECG?
RP1
ECGp
CC1
The INA includes the
R and C and must be
considered in the
overall CMRR Analysis
Amp
VCM
CC2
ECGn
RP2
Mismatch in Rp and Cc
causes a differential
signal error
Vdiff_actual
Vinp
Rp1
j
Rp1
Cc1
2
Vinn
Rp2
j
Rp2
Cc2
2
Even a 1% tolerance
on Cc cause a 20dB
attenuation in CMRR
41
The INA Front End

50/60Hz Common Mode Simulation Circuit with 1F
Coupling Capacitors Mismatched
CMR TINA Circuit Test By
Sweep of Mismatch of Input
Coupling Capacitors
C2 47n
R14 10M
C4 47n
V4 0
VCM
R10 63.4k
R11 63.4k
C1 1u
+
R1 20k
C5 33p
C6 33p
C8 33p
R4 52k
R9 63.4k
C7 33p
R8 63.4k
C9 330p
V3 0
VCC Vref
Vref
C12 1u
RG
V+
Vout
Ref
Out
RG
V-
U1 INA333_C
R7 52k
Vref
R13 10M
42
The INA Front End

Plot of CMRR vs. Frequency for .01 - .5% Coupling
Capacitor Mismatch
T
-40.00
.5% Mismatch
Voltage (V)
-60.00
-80.00
0% Mismatch
-100.00
100.00m
1.00
10.00
Frequency (Hz)
100.00
43
The INA Front End

Plot of ECG Response to 5Hz CM Input Signal (0%.5%) CC Mismatch
T 2.51
Voltage (V)
Lower Frequency
Signals Couple
Directly Into the ECG
Signal to the Output
2.50
0.00
400.00m
Time (s)
800.00m
44
The INA Front End

Plot of ECG Response to 50/60 Hz CM Input Signal
50/60Hz Noise Rejection is

Virtually Unaffected by AC
Coupling
2.51
Dependent Primarily on the

Noise Magnitude and the
CMRR of the Front End INA
Vout
2.50
0.00
400.00m
Time (s)
800.00m
45
The Right Leg Drive Amplifier
461
The RL Drive Amplifier

The RL Drive Amplifier Serves 2 Purposes: (1)
Common Mode Bias (2) Noise Cancellation
ECGp
CMnoise
CMnoise
ECGn
Average VCM is
Inverted and Fed
Back to RL;
Cancels 50/60Hz
noise
*Tapping off center of split gain

resistor feeds the following
voltage to the RL Drive Circuit
[(Vcm+ ECGP )+ (Vcm+ ECGn )]/ 2
= Vcm + (ECGp + ECGn )/2
47

NS
C2 47n
U1 OPA333
R15 1M
R4 1k
R9 63.4k
R10 63.4k
C5 33p
C10 1u
+
RG
RG1 10k
V+
Ref
Vout
Out
RG
C7 33p
C8 33p
ECGn
C9 330p
C6 33p
+
+
ECGp
R11 63.4k
C4 47n
RG2 10k
VU3 INA333
NS
NS2 2.5
R7 1k
R5 1M
Vref
NS1 2.5
NS
R6 1k
R3 10k
-
U2 OPA333
+
VCC
Vref
U4 OPA333
+
R14 1M
R13 1M
= Included for
TINA spice
Convergence
VCC
R16 1M
+
Noise
VCC
R8 63.4k
R2 1k
R12 1M
R1 1k
Vref
NS3 2.5
VCC
Simulation Circuit for Response to 50/60 Hz CM Noise

Injection Source
48
The RL Drive Amplifier TINA

Simulation with NO RL Drive; CM Noise is Coupled to
Output
T
750.00u
ECGn
-150.00u
750.00u
ECGp
-150.00u
1.00
Noise
-1.00
2.51
Vout
2.50
0.00
665.73m
Time (s)
1.33
49

TINA Simulation with RL Drive; Output Noise is
Reduced
T
750.00u
ECGn
-150.00u
750.00u
ECGp
-150.00u
1.00
Noise
-1.00
2.51
Vout
2.50
5.46m
282.16m
Time (s)
558.86m
50

Analyzing the RLD Amplifier Loop
VECGp + Vep + VCM
Vref VoutA1
VRL
RF Vref
RI
ECGp
Vep
RG/2
RG/2
More Gain = Better CMRR

Loop Corrects for
Electrode Offset, VOSA1,
and VOSRLD
RF
RA
Ven
ECGn
VREF
VoutA1
RA
RI
Vcm VECGp Vep Vcm VECGn Ven RG
2 VOSA1
RG
VECGn + Ven + VCM
51

Sweep Feedback
Resistor Gain to
show Effects of
CMRR @ 50/60Hz
U1 OPA333
R15 1M
C2 47n
Vref
VCC
Simulation Circuit for CMRR of RLD Loop
VCC
R7 52k
R10 63.4k
R11 63.4k
RG
RG1 25k
V+
R12 1M
C5 33p
C10 1u
+
Ref
Vout
Out
RG
RG2 25k
V-
R17 1M
C8 33p
V4 0C4 47n
C_RLD 47n
U3 INA333
VCC
NS1 2.5
NS
R2 100k
RF 10k
Vref
V1 2.5
U4 OPA333
Vref
VCC
U2 OPA333
R14 100k
VCC
R16 10M
R3 10k
R13 100k
R_RLD 52k
Vcm
C9 330p
C6 33p
V3 0
R9 63.4k
C7 33p
R8 63.4k
R4 52k
V2 2.5
52

CMRR Plots vs. Gain in RLD Loop
T
-80.00
CMRR (dB)
RF = 10k
RF = 100k
-100.00
RF = 1M
RF = 10M
-120.00
10.00
100.00
Frequency (Hz)
53
RL Drive Stability Simulation Circuit

Electrode
Resistance Varies
With Contact and
Moisture, Presents
Problems for RLD
Stability
VCC
R7 52k
R10 63.4k
C5 33p
RG1 25k
RG
R11 63.4k
RG2 25k
V+
Ref
V-
U3 INA333
VCC
R5 10M
Vref
R2 100k
L1 1G
U4 OPA333
+
Vloop
VoA
V2 2.5
VCC
VCC
U2 OPA333
C1 1G
Vref
R14 100k
V1 2.5
R3 10k
Local RLD Loop is

Broken to Ensure
Proper Phase Margin
Over Range of
Electrode Resistance
RG
Out
C7 33p
C8 33p
C9 330p
C6 33p
C_RLD 47n
C4 47n
C10 1u
+
R12 1M
R9 63.4k
R4 52k
R17 1M
R8 63.4k
V3 0
V4 0
R_RLD 52k
U1 OPA333
R15 1M
C2 47n
Vref
VCC
Vin
54

RL Drive Simulation Showing Instability in the RLD
Feedback Loop
T 120.00
100.00
> 20dB/dec ROC (Rate of

Closure) = INSTABILITY
Gain (dB)
80.00
AOL
60.00
40.00
1/Beta
20.00
0.00
-20.00
1.00
10.00
100.00
1.00k
10.00k
Frequency (Hz)
100.00k
1.00M
10.00M
55

Using RLD Simulation to Compensate for 1/Beta
Variation With Electrode Resistance
T 120.00
100.00
Intersection
of 1/ and
AOL curve > 40dB/dec
Gain (dB)
80.00
60.00
40.00
20.00
0.00
Feedback Comp
Placed vs. Worst
Case Electrode
Resistance and
RLD AOL
-20.00
1.00
10.00
100.00
1.00k
10.00k
Frequency (Hz)
100.00k
1.00M
10.00M
56
R18 10M
C2 47n
U1 OPA333
R15 1M
VCC
RG
RG1 25k
V+
Ref
Out
R11 63.4k
RG
RG2 25k
V-
U3 INA333
R19 10M
L1 1G
R12 1M
C10 1u
+
R17 1M
R10 63.4k
C9 330p
C8 33p
R7 52k
C_RLD 47n
VCC
R3 10k
Vref
Vloop
+
U4 OPA333
VoA
Vin
R14 100k
C1 1G
Vref
VCC
U2 OPA333
V1 2.5
VCC
R16 10M
R2 100k
R13 100k
R_RLD 52k
V4 0C4 47n
C5 33p
R4 52k
C6 33p
V3 0
R9 63.4k
C7 33p
R8 63.4k
Vref
VCC
RL Drive Stability Simulation Circuit of Feedback #1
V2 2.5
57

+
U1 OPA333
R15 1M
C2 47n
Vref
VCC
RL Drive Stability Simulation Circuit of Feedback #2
VCC
R10 63.4k
C5 33p
RG
RG1 25k
V+
Ref
Out
C7 33p
R7 52k
C_RLD 47n
R11 63.4k
RG
RG2 25k
V-
U3 INA333
R1 10M
VCC
Vref
L1 1G
R2 100k
R3 10k
Vref
Vloop
U4 OPA333
VoA
C1 1G
+
VCC
U2 OPA333
Vin
R14 100k
Vref
V1 2.5
VCC
R16 10M
R13 100k
R_RLD 52k
V4 0
C9 330p
C6 33p
C8 33p
C4 47n
C10 1u
+
R12 1M
R9 63.4k
R4 52k
R17 1M
R8 63.4k
V3 0
V2 2.5
58

+
U1 OPA333
R15 1M
C2 47n
Vref
VCC
RLD Stability Circuit with Compensated Amplifier
VCC
R7 52k
R10 63.4k
R11 63.4k
RG
RG1 25k
V+
R12 1M
C5 33p
C10 1u
+
Ref
Vout
Out
RG
RG2 25k
V-
R17 1M
C8 33p
V4 0C4 47n
C_RLD 47n
U3 INA333
VCC
R5 10M
NS1 2.5
R2 100k
NS
C3 3.3n
R1 10k
Vref
V1 2.5
U4 OPA333
Vref
VCC
U2 OPA333
R14 100k
VCC
R16 10M
R3 10k
R13 100k
R_RLD 52k
Vcm
C9 330p
C6 33p
V3 0
R9 63.4k
C7 33p
R8 63.4k
R4 52k
V2 2.5
59

RL Drive Stability Simulation of Separate Feedback
Paths
T 120.00
AOL
INA+ Electrode
Loop Feedback
RLD Local R
Feedback
100.00
Gain (dB)
80.00
60.00
40.00
20.00
Composite
Feedback
1/
Compensation
Feedback
0.00
-20.00
1.00
10.00
100.00
1.00k
10.00k
Frequency (Hz)
100.00k
1.00M
10.00M
60

Compensated RLD Circuit Simulation of 1/Beta and
AOL Intersection
T 120.00
100.00
Intersection of 1/Beta and

AOL curve is 20dB/dec =
STABLE
Gain (dB)
80.00
60.00
40.00
20.00
0.00
-20.00
1.00
3.16k
Frequency (Hz)
10.00M
61

Gain and Phase Margin Plots of Compensated RLD
Amplifier
T 120.00
Gain (dB)
100.00
80.00
60.00
Loop Gain Phase Margin

@ 0dB = 70 degrees
40.00
20.00
0.00
Phase [deg]
180.00
135.00
90.00
45.00
0.00
1.00
3.16k
10.00M
Frequency (Hz)
62

Step Response of RLD Amplifier and ECG Output
T 100.00m
Vin
-100.00m
2.55
VoA
2.45
2.80
Vout
2.20
0.00
5.00m
Time (s)
10.00m
63
641

Shield drive eliminates leakage to ECG Inputs
CP1
ECGP
ECGN
CP2
VCC/2
+ +
Shield is driven to
(VIN(+) VIN()) /2
Eliminates Leakage
from CP1 and CP2
Capacitance of cable can be 500 pF to 1.5 nF

Isolation resistor Necessary for improved EMI/RFI filtering
65

NS
C8 33p
Vref
C4 47n
R7 1k
R10 63.4k
R11 63.4k
RG
R1 10k
V+
Ref
R12 1M
VF1
Out
RG
R2 10k
VCC
R3 10k
VCC
C10 1u
C5 33p
R5 1k
R9 63.4k
C7 33p
R8 63.4k
C9 330p
C2 47n
C6 33p
R4 10k
U1 OPA333
R15 1M
VF2
Vref
NS3 2.5
VCC
AC Stability Simulation Circuit for OPA333 as Shield Driver
VU2 INA333
VF3
VinP
VinN
U3 OPA333
L1 1T
VF
Vout
+
C3 1T
VG1
C1 1n
Effective
Cable Shield
Capacitance
66

AOL + 1/Beta Response of OPA333 Shield Drive and 1nF
Cable Capacitance
120.00
100.00
Gain (dB)
80.00
60.00
-40dB/decade Intersection
of AOL and 1/Beta =
UNSTABLE
40.00
20.00
0.00
-20.00
1.00
10.00
100.00
1.00k
10.00k
Frequency (Hz)
100.00k
1.00M
67

NS
C8 33p
Vref
C4 47n
R10 63.4k
R1 10k
RG
R2 10k
U3 OPA333
+
VF1
VU2 INA333
C3 1T
L1 1T
VF
VG1
C1 1n
Ref
VF3
VinP
Shield Drive
Compensation
Network
V+
Out
R11 63.4k
R6 2k
RG
R12 1M
VCC
R3 10k
R7 1k
VCC
C10 1u
C5 33p
R5 1k
R9 63.4k
C7 33p
R8 63.4k
C9 330p
C2 47n
C6 33p
R4 10k
U1 OPA333
R15 1M
VF2
Vref
NS3 2.5
VCC
TINA Simulation Circuit for Stabilized OPA333 Shield Driver
Vout
C11 1n
R13 10k
68

TINA Simulation Shows > 45 Degrees Phase Margin for
OPA333 Shield Driver
120.00
Gain (dB)
100.00
80.00
60.00
40.00
20.00
0.00
Phase [deg]
0.00
-45.00
-90.00
-135.00
-180.00
1.00
1.00k
1.00M
Frequency (Hz)
69
Lead Off Detection
701
Lead Off Detection

Lead Off Differentiates a Bad Lead from an Arrythmia
Body-Electrode
Model
VREF
VCC
VTH
VTH
Pull up Resistors Force +IN to Comparator High When Lead is Removed

Comparator Voltage triggers ALERT
Lead Off Indicative of Weak Lead
71
Lead Off Detection

TINA Simulation Circuit for Lead Off Detect
U1 TLV3701
R15 10M
C4 47n
R3 10M
+
V+
RG
RG1 10k
Vout
Ref
Out
R11 63.4k
SW2 1
R10 63.4k
C5 33p
C6 33p
C8 33p
NS
RG
RG2 10k
V-
VS
U3 INA333
VF2
VG1
VCC
C1 10n
R22 10k
VS2
U2 TLV3701
R18 100k
+
-
R16 10k
U5 OPA348
R19 1M
VCC
VM2
VG2
VCC
U4 OPA348
R20 1M
R21 52k
R5 1M
VR
R17 1M
VS2
C3 47n
VM1
R9 63.4k
NS1 2.5
R7 52k
VCC Vref
C7 33p
SW1 1
R8 63.4k
R4 52k
R2 1k
VF1
C9 330p
C2 47n
VCC
R6 1M
R14 13.5M
VS
R1 1k
VCC
VF3
VR
R12 1M
Voltage-Controlled
Switches Simulate
Disconnected Lead
R13 10M
VCC
VCC
Vref
72
Lead Off Detection

TINA Simulation Results for Lead Off Detect
T
2.00
Vswitch
0.00
4.99
VComparator
0.00
401.55u
559.69u
Time (s)
717.83u
73
Pace Detection
741
Pace Detect
Pace Maker Pulse Specifications
dp
ap
t0
ao
ap = Amplitude (2-700mV)
ao = Overshoot
dp = Pulse Width (.1-100us)
t0 = Overshoot Time Constant (4-100ms)
Rise Time = 100us
75
Pace Detect
Pace Detect Circuitry in Parallel with ECG Signal Path
C2 100p
Vpace Pos
VCC Vref
Vout
10k
RG
Ref
VU5 INA333
10n
R6 2M
10k
V+
R2 1k
OPA348
VCC
R18 10k
R22 1M
VCC
Vref
U6 OPA348
VCC
Vpace1
VCC
VPDetect
OPA348
10n
U7 OPA348
Vref
R20 100k
TLV3701
+
52k
R23 1M
100k
63.4k
Vpace Neg
RG
Out
33p
47n
ECGn
C9 330p
33p
AC Coupled Input Blocks ECG

Signal and Retains the PACER
Pulse
Window Comparator Triggers if
PACER Signal Detected
Separate PACER Processing
Circuitry
VCC
VCC
R7 2M
52k
R4 100k
R3 1M
ECGp
VECG_block
R17 1M
63.4k
R1 100k
VCC
Vpace2
TLV3701
R8 400k
47n
R5 2M
VCC
76
Pace Detect
PACE Signal Extracted From PACE + ECG Waveform
2.51
Vout
2.50
1.00m
Vpace Pos
0.00
153.93m
209.78m
Time (s)
265.62m
77
INA Post Gain and Filtering
781

Choice of High Gain + SAR ADC OR Low Gain + 24 bit Delta
Sigma ADC
HighGain
Gain
High
withlow
lownoise
noise
with
amplifiers
amplifiers
x200
At
At
electrode
electrode
At
At
ADC
ADC
Noisefree
free
Noise
Dynamicrange
range
Dynamic
Amplitude
Amplitude
Amplitude
Amplitude
At
At
electrode
electrode
Lowgain
gain
Low
At
At
ADC
ADC
x5
Noise
Noisefree
free
Dynamic
Dynamicrange
range
Amp
Amp
noise
noise
ADC
ADC
Noise
Noise
Signal
SignalChain
Chain
a)
a)Using
Usingaalow
lowresolution
resolutionADC
ADC
Signal
SignalChain
Chain
b)
b)Using
Usingaahigh
highresolution
resolutionADC
ADC
SAR + filter Option Results in Same Input-Referred Noise as

the DC Coupled Delta-Sigma, but at what COST?
79

INA + Post Gain Amp With Differential Noise Source
C1 10p
C2 47n
U1 OPA333
R22 1M
VCC
R9 63.4k
R19 10k
C5 33p
+
RG
RG1 10k
V+
Ref
Out
RG
C7 33p
R10 63.4k
C9 330p
C6 33p
C8 33p
NS4 2.5
NS
R20 2M
ECGn
C10 1u
R11 63.4k
VU3 INA333
VF1
U5 OPA333
NS
NS2 2.5
VCC
R12 1M
C4 47n
RG2 10k
Vref
Vout
R17 10M
R8 63.4k
ECGp
R7 1k
R5 1M
NS1 2.5
NS
R3 10k
-
U2 OPA333
+
VCC
Vref
U4 OPA333
+
R14 1M
VCC
R16 1M
R6 1k
R13 1M
R15 2M
R18 2M
R4 1k
R2 1k
R23 1M
R1 1k
NS
Vref
NS5 2.5
Noise
+
VCC
R21 2M
80

Noise Coupled Differentially Translates to Output
1.00
50/60Hz
-1.00
4.33
50/60 Hz Couples Differentially;

How Do We Get Rid of It?
Vout
2.16
0.00
187.93m
Time (s)
375.86m
81

Use Filter Pro to Design a 50/60 Hz Notch
82

U3 OPA333
VCC
ECG Circuit with Added 50/60Hz Notch + Post Gain
Vref
R21 2M
+
Noise
+
Vref
C1 10p
R19 10k
VCC
VCC
R9 63.4k
NS1 2.5
NS
R3 10k
R13 1M
U6 OPA348
R26 8.06k
VCC
C3 330n
R22 1M
R29 8.06k
VF2
NS
U1 OPA348
+
NS3 2.5
VCC
R28 8.06k
VCC
R16 1M
U2 OPA348
Vref
R14 1M
R24 64.9k
U5 INA333_C
Vref
-
R5 1M
V-
U7 OPA378
R25 64.9k
RG
RG2 10k
C10 1n
R30 1M
C5 33p
R11 63.4k
R6 1k
C12 330n
Ref
VF1
R27 8.06k
R7 52k
V+
Vout
Out
C4 47n
R2 1k
RG
RG1 10k
C7 33p
R10 63.4k
C9 330p
C6 33p
C8 33p
NS4 2.5
NS
R20 2M
ECGn
U4 OPA348
R12 1M
R8 63.4k
R18 1M
C11 1u
ECGp
R15 2M
R4 52k
R17 1M
C2 47n
R23 1M
R1 1k
VCC
83

Plots of ECG Output with Gain and 60Hz Notch
968.42m
Noise
-1.00
3.40
Vout_Filter
2.37
2.51
Vout_PostGain
2.50
2.51
Vout_INA
2.50
94.83m
237.76m
Time (s)
380.69m
84

Line Cycle Sampling with SAR converter on T Wave at
Common Frequency Multiples of 50/60Hz
494.51m
ECG (V)
370.88m
247.25m
123.63m
0.00
400m
417m
433m
450m
467m 483m
Time (s)
500m
517m
533m
550m
Fsample (Hz) = n*(1/50Hz + 1/60Hz)-1 = n*(27.27) Hz

85

Comparison of Delta Sigma ADC vs. Lower
Resolution SAR ADC
Using a low resolution ADC00
x5
0.05 Hz
x32
100 Hz
Elec 1
INA
Elec 2
DC blocking
HPF
Patient
Protection,
Lead
selection
Additional
gain
High order
Anti aliasing
filter
MUX
ADC
DOUT
16 bit,
100KSps
`
Elec 8
Reduced Hardware
Filter Requirements Relaxed
Lower Power
Lower System Cost
Electrode Offset Info
Retained
INA
Elec 9
RL
Using a high resolution ADC

x5
100 Hz
ADS1258
Elec 1
INA
Elec 2
Patient
Protection,
Lead
selection
Elec 8
Simple RC filter
INA
MUX
DOUT
ADC
24 bit,
100KSps
`
Elec 9
RL
86

Block Diagram of INA Gain, Simple RC Filter, and ADS1258
x5
Elec 1
Elec 1
lec 2
Elec 2
Elec 9
Elec 9
100 Hz
INA
Patient
Patient
Protection, Protection,
Lead
Lead
selection selection
Elec 8
100 Hz
ADS1258 ADS1258
INA
lec 8
RL
x5
Simple RC filter
Simple RC filter
INA
MUX
INA
MUX
DOUT
ADC ADC
24 bit,
24 bit,
100KSps
100KSps
`
`
RL
A single ADC in the MUX approach does not

necessarily mean lower power due to the higher
speed needed to perform MUX switching
87
DO
ADS1298 Introduction
881
The ADS129x
The All-In-One ECG Chip
89
ADS129x
Input Amplifier Specifications for Single Channel AFE
CH1P
+
+
PGA
BUF
24-bit
RLD
Delta-Sigma
ADC
+
+
PGA
CMOS input PGA

High input impedance
Low input current noise
Rail to rail input
CH1M
BUF
Low Input Voltage Noise

Current Noise = 0.1pAHz Over Bandwidth
No Output Phase Reversal
100dB AOL @ 50/60 Hz
90dB CMR @ 50/60 Hz
IB = 150pA MAX vs. Temperature
ZIN >100M, CIN = 100pF max
90
ADS129x
Noise Model for ECG AFE
Noise is optimized with amplifier gain=4
The 4uV p-p includes the crest factor of 6.6 to convert rms to pk-pk
Noise is referred to the input
CH1P
AFE
CH1M
+
ADC
91
ADS129x
Programmable Data Rates for Low Power and High
Resolution Modes
92
ADS129x
MUX Selects Inputs to Front End PGA
Normal Electrode
Input Shorted
RLD Input
VDD
TMP Sensor
Input Test Signal
93
ADS129x
Wilson Central Terminal
Wilson Central
Voltage
0.333(RA+LA+LL)
Augmented Lead
Voltages
0.5(RA+LA)
0.5(LA+LL)
0.5(RA+LL)
*The Same Amplifiers Used to Derive the WCT Voltage Can be
Switched to Obtain the Augmented Leads
94
ADS129x
Input Amplifier and RLD Selection
VO = VS(1+R2/R1) + VCM1 + (VCM2 VCM1) x (R2/R1)
Lead I configuration
+/-VCM2 + VS
AVDD
+
RS
VO1
Right leg drive

External R-C
5M
100K
R1
R2
RLD Sum
(Register set)
AVDD
ADC2
200K
RS
200K
VCM1 = AVDD/2
AVDD
+/-VCM2 + VS
+
RS
VO2
R1
R2
*Compensation of RLD Amplifier is Based on the Gain Selected

and the Number of Amplifiers in the Loop
95
ADS129x
RLD Selection8 Channel Case
+
220K
RLDP2
50K
20K
220K
RLDM1
RLDP4
RLDM3
CH7P
50K
220K
RLDM4
50K
RLDP5
220K
RLDP6
50K
50K
50K
220K
RLDM5
220K
RLDP7
50K
RLDP8
50K
50K
RLD_OUT
RLD
AMP
AVDD - AVSS
2
RLDREF_INT
R1
CH4N
RLD_REF
/RLDREF_INT
CH6P
R2
CH6N
220K
50K
220K
RLDM8
RLD
AMP
All switches can be controlled

by register settings
CH8N
RLDREF_INT
RLDREF_INT
CH8P
20K
RLDM7
Rext
10M
RLDOUT
RLDREF
220K
RLDINV
Cext
264pF
RLIM
220K
20K
CH7N
RLD
Electrode
CH8M
20K
RLDM6
264pF
220K
20K
CH5N
2M
220K
220K
CEXT
20K
50K
CH5P
50K
CH4P
CH3N
220K
50K
20K
CH2N
REXT
220K
RLDP3
220K
RLDM2
220K
CH1P
50K
CH3P
RLD_INV
20K
50K
CH1N
ADS129x
CH2N
50K
220K
RLDP1
CH1P
WCT_TO_RLD
AVDD - AVSS
2
WCT
*Multiple PGA Outputs Can Be Switched to

Derive Inverting RLD
96
ADS129x
VA1-8
Device 2
Power Down
+
RLD
IN
RLD
INV
RLD
OUT
Device n
Power Down
+
VA1-8
RLD
REF
RLD
REF
RLD
OUT
RLD
IN
Device 2
Power Down
+
VA1-8
RLD
REF
RLD
IN
RLD
REF
RLD
OUT
RLD
INV
RLD
OUT
Device 1
RLD
INV
VA1-8
RLD
INV
RLD
OUT
RLD
IN
To Input Mux
RLD
REF
To Input Mux
RLD
IN
VA1-8
Device 1
To Input Mux
To Input Mux
Device 1
To Input Mux
To Input Mux
RLD with Multiple Devices
VA1-8
RLD
INV
RLD
IN
RLD
REF
RLD
OUT
RLD
INV
*With Multiple Devices the RLD Output Becomes the

Amplified Difference Between RLD REF and the
Summation of Multiple Lead Outputs
97
ADS129x
Pace Detect
PACE_ODD [4:1]
+
50K
00xx
500K
xx00
20K
500K
00xx
xx00
500K
01xx
xx01
xx01
10xx
xx10
500K
xx10
xx11
50K
50K
500K
VREFCM
xx11
CH7P
200K
(AVDD-AVSS)/2
PACE
AMP
200K
PDB_PACE
PACE_ODD[0:1]
CH1M
250K
100K
250K
CH7M
From CH6N<
VREFCM
PACE_OUT2
From CH8P<
250K
CH2P
PACE
AMP
From CH8N<
250K
CH8P
250K
100K
GPIO1
PACE
AMP
CH1P
250K
PDB_PACE_EVEN
50K
11xx
100K
TESTP_PACE_OUT1
PACE
AMP
20K
500K
PDB_PACE
TESTN_PACE_OUT2
500K
100K
>From CH7N
From CH6P<
500K
11xx
50K
20K
50K
500K
250K
PDB_PACE_ODD
20K
10xx
ADS129x
100K
>From CH7P
50K
50K
500K
20K
>From CH5N
From CH4N<
500K
50K
VREFCM
PACE_OUT1
100K
500K
50K
01xx
500K
>From CH5P
20K
50K
50K
From CH4P<
>From CH3N
500K
50K
20K
From CH2N<
*Separate Pace Amplifiers Allow

External Processing of Pace
Signal; All Channels do Not Have
to Operate at Higher Data Rates
50K
20K
500K
>From CH3P
From CH2P<
+
>From CH1N
50K
50K
500K
>From CH1P
PACE_EVEN[0:1]
CH2M
250K
PACE_IN(GPIO1)
CH8M
PACE ODD
PACE EVEN
PACEO1 PACEO0 PACEE1
x
0
x
0
x
1
x
1
x
0
x
1
x
0
x
1
0
x
0
x
1
x
1
x
PACEE0
CHANNEL
SELECTED
0
x
1
x
0
x
1
x
Channel #1
Channel #2
Channel #3
Channel #4
Channel #5
Channel #6
Channel #7
Channel #8
98
ADS129x
Lead Off Detection
AVSS
AVDD
LOFF_FLIP
FLEAD_OFF[0:1]
FREQ = DC, FDR/2 or FDR/4

VX
FLEAD_OFF[[1:0]
Anti-Aliasing Filter
<512KHz
>
Patient
Protection
Resistor
< R1 ~ 10M
Patient Skin Electrode

Contact Model
Z1
LOFF_STATP
LOFF_SENSP
& VLEAD_OFF_EN
47nF
LOFF_SENSM
& VLEAD_OFF_EN
R2
51K
100K
51K
R2
VINP
EMI
Filter
VINM
100K
LOFF_SENSP
& VLEAD_OFF_EN
47nF
Z2
+
To ADC
LOFF_SENSM
& VLEAD_OFF_EN
LOFF_STATM
LOFF_FLIP
25, 17.275, 12.5, &

6.25nA
Z3
AVDD
4-bit
DAC
COMP_TH[2:0]
AVSS
ILEAD_OFF[0:1]
R3
51K
100K
RLD OUT
99
ADS129x
Respiration Testing Measures the Change in Thoracic
Impedance with Inhalation of O2
ADS129x
PATIENT
S CHEST
E4
PATIENT
S CHEST
RPROTEC
RPROTEC
E2
100K
RTHORAX
100K
RPROTEC
E3
ADS129x
V
RPROTEC
E1
64KHz
100K
RTHORAX
100K
V
RPROTEC
E2
100K
64KHz
*AC Current is injected into the

Patients Thorax and the Change
in Voltage is Measured to
Calculate Change in Impedance
RPROTEC
E1
100K
100
ADS129x
Respiration Functions
ADS129x
GPIO
GPIO1
GPIO2
RESPIRATION
GPIO3/
RESP_OUT
RESP_MODE
GPIO4/
RESP_PH_OUT
Changing Phase Allows

Measurement/Compensation for
Complex Impedance Phase Shifts
Between Modulator and
Demodulator
RESP_PH [4:2]
RESP_PH[4:2] bit CODE

PHASE
RESP_ RESP_ RESP_P SELECTED
PH2
PH1
H0
0
22.5 Deg
45 Deg
67.5 Deg
90 Deg
112.5 Deg
135 Deg
157.5 Deg
180 Deg
101
ADS129x
Internal Voltage Reference
Simplified ADS129x internal reference block diagram
The Internal Band Gap Accuracy = 1%

Internal REF can be Powered Down
VREFP Can Be Supplied Externally
102
Thank You
Contact Information:
hann_matthew@ti.com
103
Questions?
1041
Acknowledgements
Beraducci, Mark and Soundarapandian, Karthik. Sbaa160, Application Report: Analog

Front End Design of ECG Systems Using Delta-Sigma ADCs. March 2009.
Brown, John --Burr Brown Strategic Marketer, general information
Brown, John and Joseph Carr. Introduction to Biomedical Equipment Technology.
Prentice Hall Inc. New Jersey. 1981, 1993.
Dubin, Dale. Rapid Interpretation of EKGs. Cover Publishing Company. Fort Myers.
2000.
Fraden, Jacob. Handbook of Modern SensorsPhysics, Designs, and Applications.
Advanced Monitors Corporation. San Diego. 2004.
Franco, Sergio. Design with Operational Amplifiers. McGraw-Hill Inc. NY. 1988.
Fredericksen, Thomas M. Intuitive Operational Amplifiers. McGraw-Hill Inc. 1988.
Graeme, Toby, Huelsman. Operational AmplifiersDesign and Applications. McGrawHill Publishing Company. New York. 1971.
Gray, Paul R. and Meyer, Robert G. Analysis and Design of Analog Integrated Circuits.
John Wiley & Sons. New York. 1977
Green, Timothy - Linear Applications Manager, general information
Kuehl, Thomas--Linear Applications Engineer, general information
Norton, Harry N. Sensor and Analyzer Handbook. Prentice Hall Inc. New Jersey. 1982.
Soundarapandian, Karthik--Over sampling Manager, general information
105

3264.TI ECG Fundamentals Condensed v08 PDF

Transféré par

Informations du document

Description originale:

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

3264.TI ECG Fundamentals Condensed v08 PDF

Transféré par

Droits d'auteur :

Formats disponibles

Analog Fundamentals of the ECG

Analog Fundamentals of the

Resting ion chs.

Na+ conc. is 10x

Ion channels Resting ion chs.

Resting ion chs.

Ion channels Active ion pumps

Electrical characteristics include a DYNAMIC resistance,

Analog Lead Derivation

Analog Lead Derivation

Analog Lead Derivation

*Drawing Taken From Bioelectromagnetism, Jaako Malmivuo and Robert Plonsey

Analog Lead Derivation

VOUT = V(1-6) - VWCT

Analog Lead Derivation

Different Chest Leads

Analog Lead Derivation

Each lead provides

Multiple Angles Give a

Analog Lead Derivation

Analog Lead Derivation

Mean QRS Vector Points Toward Area of Infarction (Damage)

Analog Lead Derivation

ECG Input Filtering, Defibrillation

ECG Input Filtering and Protection

CF, Ccm, and Cdiff +

Ne2H Lamps/TVS Protect

System Block Diagram

System Block Diagram

QRS and PACE

The INA Front End

The INA Front End

Input Bias Current

Input Offset Voltage

Input Offset Voltage Drift

Input Current Noise

Input Voltage Noise

*DC Errors such as VOS are swamped out by the

The INA Front End

C10 33p C18 33p

C12 33p C19 33p

The INA Front End

Noise may NOT necessarily

Total noise (V)

The INA Front End

ECG Signal Varies

The INA Front End

(1) Electrode Offset MAX = +/- 300mV

The INA Front End

OPA333 Used as Integrator

The INA Front End

As the output of the

The INA Front End

*AC Coupling Removes Electrode

The INA Front End

The INA Front End

The INA Front End

Lower CMRR = More

ECGp ECGn VOSelectrode VOSOPA

The INA Front End

The INA Front End

The INA Front End

Fsample (Hz) = n(1/50Hz + 1/60Hz)-1 = n(27.27) Hz