list of all inputs to start PD flow and whats inside.

In which file standard cel

ls height and row information's mentioned.
Sanity checks?
whats the effects with input floating nets in netlist and what do you do ?
channel length calculation and where is the information's of macros given.
setup and hold time definitions with diagram.
why clock period is not required in hold time calculation.
basics of latchup and remedies
how does tools do placement optimizations
crosstalk and remedies.
Antenna and remedies.
time borrowing concepts in latches.
Draw INV, AND and OR gate using 2 inputs mux.
why we need setup and hold time for flops.
define meta-stable state and Noise margins.
inter gate clocking (IGT) why do we use it? (what is static and dynamic power co
nsumption's).
define CMOS operating modes with drain current equation.
what is crosstalk window concepts.
Antenna effects and remedies.
who is your client?, what are the tools did you used?
what are the inputs did you get form synthesis guy?
how did you validate that?
some questions on SDC check
pick any one of block and explain PD flow.how did you place macros?
what is the minimum space did you follow in your design?
present technologies not using straps for macros, then what is the use to give V
DD and VSS in between two macros
what are the metal layers did you used in your design?
M1 is used for standard cells, so which layer did you connected this M1 - means
did you connected to M9 or M8?
what are the checks you have done after placement
what are the inputs required to start CTS?
what is the spec file consists of: he is expecting each and every statements in
the spec file
how did you analyse setup reports?
what is the reasons for set up (by seeing the report we should give the answer-n
ot theoretically
how did you overcome that?
what is DRV, what are those?
how did you fixed tran violation?
Do you know IR drop, did you work on IR drop tool?
what is the important of clock gating?
where will you place the clock gating cells-near to source or sync?
what are the DRC's did you faced?
list out any 10 DRC.
insertion and skew delay for your design.
How did you overcome the congestion?
Out of all paths how did you know which cell is giving setup violation and how d
id you overcome that.
what is the minimum space did you follow in your design?
present technologies not using straps for macros, then what is the use to give V
DD and VSS in between two macros
M1 is used for standard cells, so which layer did you connected this M1 - means
did you connected to M9 or M8?
where will you place the clock gating cells-near to source or sync?
what are the DRC's did you faced? 22. list out any 10 DRC.
how did you start your Project flow? (Expectation was to mention all inputs and
from whom we get, sanity checks and why we do it)
Floorplan (expectation was to explain wrt one block)

Do we need to keep spacing between macro if it doesn t have pins facing each other.(
expectation was to justify our answer)
In the flow why macros were placed only at the bottom
How do we Qualify floorplan
Before starting placement what we do?
Congestion and solution
Checks after placement
Qualifying placement
Before starting cts what we need to do (analyze the quality of placement)
Inputs to CTS
What we analyze after CTS
How we can tell CTS is build properly
Clock path (why do we set transition limit) If library has max tran limit of 1ns
and you are getting 900ps as transition value, can you take it further (No as c
lock tree has a chain of buffer we will see min pulse width violation clock absorpt
ion )
What you did in routing
Steps in routing
Have you run caliber (inputs to DRC and LVS)
List some DRC s and LVS issues
timing problem to calculate setup and hold slack
explain vth ( on what it depends )
explain latchup( how do you reduce )
why are fillers used
what are end cap cells ?
what are decap cells ?
Power planning, EM violation - he expected more :-)
Do we place anything b/w Macros?
How do you estimate die size?
How do you calculate Aspect Ratio?
How you place macros? For my exp, 10-15 Macros was not sufficient. He was expect
ing 100/150+ M
Do you know test mode? How do you insert scan chains? How it is done?
Do you know about set_false_path, clock_groups, mutually_exclusive, asynchronous
, case_analysis?
Case 1: there is a 2:1 mux. set_case_analysis is set to 0 .Case 2: there is another 2:1
mux. set_disable_timing is set on B->Y.What is the difference? Explain w.r.t ti
ming arcs.
What is the difference b/w Exclude pin and Ignore Pin?
Command to spread the cells.
During Placement if more cells are added(utilization increases) by the tool, wha
t could be the reason?
How setup/hold analysis are done on CGCs?
Why ENDCAP and WELL TAP are added before Placement only?
During FloorPlan, if IO info is not given, then how will you proceed? Say, you c
ant ask the manager(he too doesn't know) nor you can assume and add.
Let's say after Placement there is setup violation. What will you do? How will y
ou analyze? How will you validate the violation?
Why power stripes routed in the top metal layers?
Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizonta
l/Vertical-Horizontal-Vertical)?
What are several factors to improve propagation delay of standard cell?
How do you compute net delay (interconnect delay) / decode RC values present in
tech file?
What are various ways of timing optimization in synthesis tools?
What would you do in order not to use certain cells from the library?
How delays are characterized using WLM (Wire Load Model)?
What are various techniques to resolve congestion/noise?
Let s say there enough routing resources available, timing is fine, can you increase
clock buffers in clock network? If so will there be any impact on other paramet

ers?
How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?
What are pros/cons of latch/FF (Flip Flop)?
How you go about fixing timing violations for latch- latch paths?
As an engineer, let s say your manager comes to you and asks for next project die si
ze estimation/projection, giving data on RTL size, performance requirements. How
do you goabout the figuring out and come up with die size considering physical
aspects?
How will you design inserting voltage island scheme between macro pins crossing
core and are at different power wells? What is the optimal resource solution?
What are various formal verification issues you faced and how did you resolve?
How do you calculate maximum frequency given setup, hold, clock and clock skew?
What are effects of meta-stability?
What are the challenges you faced in place and route, FV (Formal Verification),
ECO(Engineering Change Order) areas?
How long the design cycle for your designs?
What part are your areas of interest in physical design?
Explain ECO (Engineering Change Order) methodology.
Explain CTS (Clock Tree Synthesis) flow.
What kind of routing issues you faced?
How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done
? How do you set OCV (On Chip Variation) in IC compiler? How is timing correlati
on done before and after place and route?
If there are too many pins of the logic cells in one place within core, what kin
d of issues would you face and how will you resolve?
Define hash/ @array in perl.
Using TCL (Tool Command Language, Tickle) how do you set variables?
What is ICC (IC Compiler) command for setting derate factor/ command to perform
physical synthesis?
What are nano route options for search and repair?
What were your design skew/insertion delay targets?
How is IR drop analysis done? What are various statistics available in reports?
Explain pin density/ cell density issues, hotspots?
How will you relate routing grid with manufacturing grid and judge if the routin
g grid is set correctly?
What is the command for setting multi cycle path?
If hold violation exists in design, is it OK to sign off design? If not, why?
How are timing constraints developed?
Explain timing closure flow/methodology/issues/fixes.
Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Ex
change Format) timing correlation flow.
Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analys
is) performed in order to meet timing in both modes and corners, how are PVT (Pr
ocess-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
With respect to clock gate, what are various issues you faced at various stages
in the physical design flow?
What are synthesis strategies to optimize timing?
Explain ECO (Engineering Change Order) implementation flow. Given post routed da
tabase and functional fixes, how will you take it to implement ECO (EngineeringC
hange Order) and what physical and functional checks you need to perform?
In building the timing constraints, do you need to constrain all IO (Input-Outpu
t) ports?
Can a single port have multi-clocked? How do you set delays for such ports?
How is scan DEF (Design Exchange Format) generated?
What is purpose of lock up latch in scan chain?
How do you set inter clock uncertainty?
In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, m
axcap,max tran?
What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to
post

How is clock gating done?

what constraints you add in CTS (Clock Tree Synthesis) for clock gates?
What is tradeoff between dynamic power (current) and leakage power (current)?
How do you reduce standby (leakage) power?
Explain top level pin placement flow? What are parameters to decide?
Given block level netlists, timing constraints, libraries, macro LEFs (Layout Ex
change Format/Library Exchange Format), how will you start floor planning?
With net length of 1000um how will you compute RC values, using equations/tech f
ile info?
What do noise reports represent?
What does glitch reports contain?
What are CTS (Clock Tree Synthesis) steps in IC compiler?
What do clock constraints file contain?
How to analyze clock tree reports?
What do IR drop Voltagestorm reports represent?
Where /when do you use DeCAP (Decoupling Capacitor) cells?
What are various power reduction techniques?
What is setup/hold? What are setup and hold time impacts on timing? How will you
fix setup and hold violations?
Explain function of Muxed FF (Multiplexed Flip Flop) /scan FF (Scal Flip Flop).
What are tested in DFT (Design for Testability)?
In equivalence checking, how do you handle scan en signal?
In terms of CMOS (Complimentary Metal Oxide Semiconductor), explain physical par
ameters that affect the propagation delay?
Why is power signal routed in top metal layers?
How do you minimize clock skew/ balance clock tree?
Given 11 minterms and asked to derive the logic function.
Given C1= 10pf, C2=1pf connected in series with a switch in between, at t=0 swit
ch is open and one end having 5v and other end zero voltage; compute the voltage
across C2 when the switch is closed?
Explain the modes of operation of CMOS (Complimentary Metal Oxide Semiconductor)
inverter? Show IO (Input-Output) characteristics curve.
Implement a ring oscillator.
How to slow down ring oscillator?
How do you optimize power at various stages in the physical design flow?
What timing optimization strategies you employ in pre-layout /post-layout stages
?
What are process technology challenges in physical design?
Design divide by 2, divide by 3, and divide by 1.5 counters. Draw timing diagram
s.
What are multi-cycle paths, false paths? How to resolve multi-cycle and false pa
ths?
Given a flop to flop path with combo delay in between and output of the second f
lop feedback to combo logic. Which path is fastest path to have hold violation a
nd how will you resolve?
What are RTL (Register Transfer Level) coding styles to adapt to yield optimal b
ackend design?
Draw timing diagrams to represent the propagation delay, set up, hold, recovery,
removal, minimum pulse width.
Do you know about input vector controlled method of leakage reduction?
How can you reduce dynamic power?
What are the vectors of dynamic power?
How will you do power planning?
If you have both IR drop and congestion how will you fix it?
Is increasing power line width and providing more number of straps are the only
solution to IR drop?
In a reg to reg path if you have setup problem where will you insert buffer-near
to launching flop or capture flop? Why?
How will you decide best floorplan?
What is the most challenging task you handled?

What is the most challenging job in P&R flow?

How will you synthesize clock tree?
How many clocks were there in this project?
How did you handle all those clocks?
Are they come from seperate external resources or PLL?
Why buffers are used in clock tree?
What is cross talk?
How can you avoid cross talk?
How shielding avoids crosstalk problem? What exactly happens there?
How spacing helps in reducing crosstalk noise?
Why double spacing and multiple vias are used related to clock?
How buffer can be used in victim to avoid crosstalk?
What parameters (or aspects) differentiate Chip Design & Block level design??
How do you place macros in a full chip design?
Differentiate between a Hierarchical Design and flat design?
Which is more complicated when u have a 48 MHz and 500 MHz clock design?
Name few tools which you used for physical verification?
What are the input files will you give for primetime correlation?
What are the algorithms used while routing? Will it optimize wire length?
How will you decide the Pin location in block level design?
If the routing congestion exists between two macros, then what will you do?
How will you place the macros?
How will you decide the die size?
If lengthy metal layer is connected to diffusion and poly, then which one will a
ffect by antenna problem?
If the full chip design is routed by 7 layer metal, why macros are designed usin
g 5LM instead of using 7LM?
How did u handle the Clock in your design?
What are the Input needs for your design?
What is SDC constraint file contains?
How did you do power planning?
How to find total chip power?
How to calculate core ring width, macro ring width and strap or trunk width?
How to find number of power pad and IO power pads?
What are the problems faced related to timing?
How did u resolve the setup and hold problem?
If in your design 10000 and more numbers of problems come, then what you will do
?
In which layer do you prefer for clock routing and why?
If in your design has reset pin, then it ll affect input pin or output pin or both?
During power analysis, if you are facing IR drop problem, then how did u avoid?
Define antenna problem and how did u resolve these problem?
How delays vary with different PVT conditions? Show the graph.
Explain the flow of physical design and inputs and outputs for each step in flow
.
What is cell delay and net delay?
What are delay models and what is the difference between them?
What is wire load model?
What does SDC constraints has?
Why higher metal layers are preferred for Vdd and Vss?
What is logic optimization and give some methods of logic optimization.
What is the significance of negative slack?
What is signal integrity? How it affects Timing?
What is IR drop? How to avoid .how it affects timing?
What is EM and it effects?
What are types of routing?
What is a grid .why we need and different types of grids?
What is core and how u will decide w/h ratio for core?
What is effective utilization and chip utilization?
What is latency? Give the types?

How the width of metal and number of straps calculated for power and ground?
What is negative slack ? How it affects timing?
What is track assignment?
What is grided and gridless routing?
What is a macro and standard cell?
What is congestion?
Whether congestion is related to placement or routing?
What are clock trees?
What are clock tree types?
Which layer is used for clock routing and why?
What is cloning and buffering?
What are placement blockages?
How slow and fast transition at inputs effect timing for gates?
What is antenna effect?
What are DFM issues?
What is .lib, LEF, DEF, .tf?
What is the difference between synthesis and simulation?
What is metal density, metal slotting rule?
What is OPC, PSM?
Why clock is not synthesized in DC?
What are high-Vt and low-Vt cells?
What corner cells contains?
What is the difference between core filler cells and metal fillers?
How to decide number of pads in chip level design?
What is tie-high and tie-low cells and where it is used
What is LEF?
What is DEF?
what is techfile?
what is .tf?
what is .lib?
what is .db file?
What are the steps involved in designing an optimal pad ring?
What are the steps that you have done in the design flow?
What are the issues in floor plan?
How can you estimate area of block?
How much aspect ratio should be kept (or have you kept) and what is the utilizat
ion?
How to calculate core ring and stripe widths?
What if hot spot found in some area of block? How you tackle this?
After adding stripes also if you have hot spot what to do?
What is threshold voltage? How it affect timing?
What is content of lib, lef, sdc?
What is meant my 9 track, 12 track standard cells?
What is scan chain? What if scan chain not detached and reordered? Is it compuls
ory?
What is setup and hold? Why there are ? What if setup and hold violates?
In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps,
tskew is 100ps. Then what is the maximum operating frequency?
How R and C values are affecting time?
How ohm (R), fared (C) is related to second (T)?
What is transition? What if transition time is more?
What is difference between normal buffer and clock buffer?
What is antenna effect? How it is avoided?
What is ESD?
What is cross talk? How can you avoid?
How double spacing will avoid cross talk?
What is difference between HFN synthesis and CTS?
What is hold problem? How can you avoid it?
For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other ite
ration 0.29ns insertion delay and 0.25 skew for the same circuit then which one

you will select? Why?

What is partial floor plan?