Vous êtes sur la page 1sur 60

# The University of Alabama in Huntsville

## Electrical & Computer Engineering

CPE/EE 422/522 01
Homework #1 Solution
Spring 2005
1.

2.

3.

(10 points) Prove that the following identities are valid using algebraic manipulation.
a. ab + bc + ca = ab + bc + ca
ab + bc + ca = ab(c+c)+bc(a+a)+ca(b+b)
= abc+abc+abc+abc+abc+abc
= ab(c+c)+bc(a+a)+ac(b+b)
ab+bc+ca
b. ab + ac + bcd = ab + ac
ab + ac + bcd = ab(c + c)(d + d) + ac(b + b)(d + d) + bcd(a + a)
= abcd+abcd+abcd+abcd+abcd+abcd+abcd+abcd+abcd+abcd
= abc(d+d)+abc(d+d)+abc(d+d) + abc(d+d)
= ab(c+c)+ac(b+b)
= ab + ac
(10 points) Find the complements of the following functions.
a. f = a + bc
f = (a + bc) = a(bc) = a(b + c) = ab + ac
b. f = ab + bc + cad
f = (ab + bc + cad) = (ab)(bc)(cad) = (a + b)(b + c)(c + a + d) = (ab + ac +
bb + bc)(c + a + d) = (ab + ac + bc)(c + a + d) = abc + aba + abd + acc +
aca + acd + bcc + abc + bcd = abc + abd + ac + acd + bc + abc +
bcd = ac(b + 1 + d) + bc(1 + a + d) + abd = ac + bc + abd
(15 points) Obtain the truth table of the following functions and express each function in sum of
minterms and product of maxterms,
b. abc + abc + abc
a. xyz + xyz
=m(0, 4, 7)=M(1, 2, 3, 5, 6)
=m(4, 7)=M(0, 1, 2, 3, 5, 6)
x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

a
0
0
0
0
1
1
1
1

f
0
0
0
0
1
0
0
1

b
0
0
1
1
0
0
1
1

c
0
1
0
1
0
1
0
1

f
1
0
0
0
1
0
0
1

c. YZ + WXY + WX Z + W XZ = m(1,3,5,9,12,13,14)=M(0,2,4,6,7,8,10,11,15)
W
0
0
0
0
0
0
0
0

X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

F
0
1
0
1
0
1
0
0

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
0
1
1
1
0

4.

## (20 points) Simplify the following expressions by means of a four-variable map.

a.

AD + BD + BC + ABD = D + BC
C
1

1
B

A
1

b.

XZ + W XY + W (XY + XY ) = X Z + W X Y + X Y
Y
1
1

1
X

W
1

c.

## ABC + B CD + BCD + ACD + A BC + ABCD = B D + CD + AC + ABD

C
1

1
1

1
B
1

A
1
D

d.

ABC + CD + BCD + BC = AC + BD + BC
C
1

B
A
D

5.

(10 points) Implement the following expression with two-input NOR gates.

## (AB + AB)(CD + CD)

A

NOR
NOR

NOR

NOR
NOR

NOR

NOR
NOR

NOR

D
6.

(15 points) Design a combinational circuit whose input is a four-bit number and whose
output is the 2s complement of the input number.

A3A2A1A0

F3F2F1F0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

F3

F2

A1

A2
1

A0

A3

F3 = A3 A2 + A3 A1 + A3 A0 + A3 A2 A1 A0
F2 = A2 A0 + A2 A1 + A2 A1 A0
F1 = A1 A0 + A1 A0
F1 = A0

A0
F0

A1
1

1
A0

1
A3

F1

1
A2

A3

A1

A2
A3

A1
1

1
A0

A2

7.

(10 points) Construct a 5-to-32-line decoder with two 4-to-16 decodes with enable input
and one 1-to-2-line decoder.
0
1

B
C
D
E
EN

15

15

A
1
0
1

16

15

31

B
C
D
E
EN

8.

(10 points) Construct a 5-to1 line multiplexer with as many 2-to-1 line multiplexers as are
needed.
s2
w0
0

s0
w1

w2

s0

s1
0
1

w3

w4

## The University of Alabama in Huntsville

Electrical and Computer Engineering
CPE/EE 422/522
Spring 2005
Homework #2 Solution
1.7

(20 points) Construct a clocked D flip-flop, triggered on the rising edge of CLK, using two
transparent D latches and any necessary gates. Complete the following timing diagram, where Q1
and Q2 are latch outputs. Verify that the flip-flop output changes to D after the rising edge of the
clock.

CLK
D

Q1

Q1
Q2

CLK

1.8

Q2D

(30 points) A synchronous sequential network has one input and one output. If the input sequence
0101 or 0110 occurs, an output of two successive 1s will occur. The first of these 1s should occur
coincident with the last input of the 0101 or 0110 sequence. The network should reset when the
second 1 output occurs. For example,

input sequence:
output sequence:

X = 010011101010 101101
Z = 000000000011 000000..

(a) Derive a Mealy state graph and table with a minimum number of states (6 states).
NS
PS
S0
S1
S2
S3
S4
S5

X=0
S1
S1
S3
S1
S5
S0

Z
X=1
S0
S2
S4
S5
S0
S0

X=0
0
0
0
0
1
1

X=1
0
0
0
1
0
1

I
II
III

## {S0, S1,S3}{S0 ,S4, S5}

{S0, S1}{S1, S2}{S3, S4}{S1, S5}{S0, S5}
{S0, S1, S2}
QB
S5

QA

S4

S0

S1

S3

S2

QC

## S0 = 011, S1 = 010, S2 = 110, S3 = 111, S4 = 001, S5 = 000

NS
Z
PS X = 0 X = 1 X = 0 X = 1
000 011
011
1
1
001 000
011
1
0
010 010
110
0
0
011 010
011
0
0
100 ddd
ddd
d
d
101 ddd
ddd
d
d
110 111
001
0
0
111 010
000
0
1
DA

QA

DB

QC

QC

DC

QC

QB
QA

QB
QA

QB
QA

QC
1

QB

D A = Q A QB QC X + Q A QC X
DB = Q A QC + Q A X + QB X
DC = Q A QC + QB QC + Q A QC X
Z = QB X + QB QC X + Q A QC X
(b) Try to choose a good state assignment. Realize the network using D flip-flops.

1.12

(25 points) A sequential network has the following form. The delay through the combinational
network is in the range 5 tc 20 ns. The propagation delay from the rising edge of the clock to
the change in the flip-flop output is in the range 5 tp 10 ns. The required setup and hold times
for the flip-flop are tsu = 10 ns and th = 5 ns. Indicate on the diagram the times at which X is
allowed to change.
Z
D

X
PLA
Clk

Clk
changing
X
0

stable

changing
40

tx = tcmax + tsu = 20 ns + 10 ns = 30 ns
ty = th tcmin = 5 ns 5 ns = 0 ns

80

stable

changing
120

160

1.15

(25 points) A D flip-flop has a setup time of 4 ns, a hold time of 2 ns, and a propagation delay
from the rising edge of the clock to the change in the flip-flop output in the range of 6 to 12 ns.
The XOR gate dely is in the range of 1 to 8 ns.
(a) What is the minimum clock period for proper operation of the following network?
(b) What is the earliest time after the rising edge that X is allowed to change?

Z
D
X
CLK
(a) tck tpmax + tcmax + tsu
tck 12 ns + 8 ns + 4 ns
tck 24 ns
(b) ty = th tcmin = 2 ns 1 ns = 1 ns

## The University of Alabama in Huntsville

Electrical and Computer Engineering
CPE/EE 422/522
Spring 2005
Homework #3 Solution
1.5

(20 points) (a) Find all the static hazards in the following network. For each hazard, specify the
values of the input variables and which variable is changing when the hazard occurs. For one of
the hazards, specify the order in which the gate outputs must change.
(b) Design a NAND-gate network that is free of static hazards to realize the same function.

## (a) F = ((ab)(a + c) + (a + d))

= ab + (a + c)(a + d)
= ab + aa + ad + ac + cd
For zero hazards
F = ab + (a + c)(a + d) Using X + YZ = (X +Y)(X + Z), X = ab, Y = a+c, Z=a+d
= (ab + a + c)(ab + a + d)

## = (a(b + 1) + c)(a + d + a)(a + d + b)

= (a + c) (a + d + a)(a + d + b)
1-hazard
bcd = 110, a changing
0-hazard
bcd = 000, a changing

c
0

b
a
d

1.9

(15 points) A sequential network has one input (X) and two outputs (Z1 and Z2). An output Z1
=1 occurs every time the sequence 010 is completed provided that the sequence 100 has never
ooccurred. An output Z2 =1 occurs every time the input sequence 100 is completed. Note that
once a Z2=1 output has occurred, Z1 =1 can never occur, but not vice versa.
(a) Derive a Mealy state graph and table with a minimum number of states (8 states).
NS
PS
S0
S1
S2
S3
S4
S5
S6
S7

X=0
S1
S1
S4
S4
S5
S5
S7
S5

Z1Z2
X=1
S3
S2
S3
S3
S2
S6
S6
S6

X=0
00
00
10
00
01
00
00
01

X=1
00
00
00
00
00
00
00
00

1.17

(15 points) Assume that CS (and also ) change 2 ns after the rising edge of the clock.
(a) Plot CK and Q on the timing diagram. A precise plot is not required; just show the relative
times at which the signals change.
(b) If X changes at the falling edge of Clock, as shown, what is the maximum clock frequency?
(c) With respect to the rising edge of Clock, what is the earliest that X can change and still
satisfy the hold-time requirement?

D
X
CS
Clock

CK

## flip-flop propagation delay=10 to 15 ns

setup time =4 ns
hold time =2 ns
XORgate delay= 4to 8 ns
ORgate delay =2 to 6 ns

Clock
CS
CS
CK
X
Q

## (b) Check both X and Q paths:

For Q: tck tpmax + tcmax + tsu = 15 ns + 8 ns + 4 ns = 27 ns
For X: tck/2 tcmax + tsu
tck 2(tcmax + tsu) = 2(8 ns + 4 ns) = 24 ns
Must use the longer, fclk <= 1/27 ns
(c) The setup time is relative to CK, but the question asks relative to the rising edge of clock. So,
the max value for the OR gate must be used so the input is definitely held long enough.
tyClock = tyCK + 6 ns = -2ns + 6 ns = 4 ns
CK(ty = th tcmin = 2 ns 4 ns = -2 ns)
2.2

(15 points) (a) Write VHDL code for a full subtractor using logic equations.
entity FULL_SUB is
port (X, Y, BIN : in bit;
SUM, BOUT : out bit);
end FULL_SUB;
architecture EQUATIONS of FULL_SUB is
begin
SUM <= (X and not Y and not BIN) or (not X and not Y and BIN) or
(X and Y and BIN) or (not X and Y and not BIN);
BOUT <= (not X and BIN) or (not X and Y) or (Y and BIN);
end EQUATIONS;

(b) Write VHDL code for a 4-bit subtractor using the module defined in (a) as a component.
entity SUB4 is
port (A, B : in bit_vector (3 downto 0); BIN : in bit;
S: out bit_vector (3 downto 0); BOUT : out bit);
end SUB4;

## architecture STRUCTURAL of SUB4 is

component FULL_SUB
port (X, Y, BIN : in bit;
SUM, BOUT : out bit);
end component;
for ALL : FULL_SUB use entity work.FULL_SUB(EQUATIONS);
signal BORROW : bit_vector (3 downto 1);
begin
FS0 : FULL_SUB port map (A(0), B(0), BIN, S(0), BORROW(1));
FS1 : FULL_SUB port map (A(1), B(1), BORROW(1), S(1), BORROW(2));
FS2 : FULL_SUB port map (A(2), B(2), BORROW(2), S(2), BORROW(3));
FS3 : FULL_SUB port map (A(3), B(3), BORROW(3), S(3), BOUT);

(20 points) Reduce the following state table to a mininum number of states using the implication
technique.
Present State Next State, X1X2 Output Z, X1X2
00 01 11 10 00 01 11 10
S1
S2 S5 S4 S1 0 1 1 0
S2
S1 S8 S3 S5 1 0 1 1
S3
S6 S5 S4 S1 0 1 1 0
S4
S2 S5 S3 S4 0 1 1 0
S5
S2 S5 S3 S7 1 1 0 0
S6
S3 S8 S1 S5 1 0 1 1
S7
S1 S6 S4 S5 1 0 1 1
S8
S4 S2 S1 S4 1 0 1 1
S2

S2

S3

2=6

S4

3=4
4=1

2=6
3=4
4=1

S5

S2

S3

2=6

S4

3=4
4=1

2=6
3=4
4=1

S5
1=3

S6
S7

6=8
3=4

S8

1=4
1=3
4=5

S1

S2

S3

S4

S5

4=1
2=6
4=5

S6

S7

2=6

S4

3=4
4=1

2=6
3=4
4=1

S5
1=3

S6
1=3
6=8
4=1
4=3
2=8
4=5

S3

S7

6=8
3=4

S8

1=4
1=3
4=5

S1

S2

1=3

S6

S3

S4

S5

1=3
6=8
4=1
4=3
2=8
4=5

4=1
2=6
4=5

S6

S7

S7

6=8
3=4

S8

1=4
1=3
4=5

S1

S2

S3

S4

S5

1=3
6=8
4=1
4=3
2=8
4=5

4=1
2=6
4=5

S6

S7

So, state S2 is equivalent to S6 and States S1, S3, and S4 are all equivalent. The reduced
state table is as follows:
Present State Next State, X1X2 Output Z, X1X2
S1
S2
S5
S7
S8

00
S2
S1
S2
S1
S1

01
S5
S8
S5
S2
S2

11
S1
S1
S1
S1
S1

10
S1
S5
S7
S5
S1

00
0
1
1
1
1

01
1
0
1
0
0

11
1
1
0
1
1

10
0
1
0
1
1

## The University of Alabama in Huntsville

Electrical and Computer Engineering
CPE/EE 422/522
Spring 2005
Homework #4 Solution
2.3

In the following VHDL process A, B, C, and D are all integers that have a value of 0 at time = 10
ns. If E changes from 0 to 1 at time = 20 ns, specify the time(s) at which each signal will
change and the value to which it will change. List these changes in chronological order (20, 20 +
, 20 + 2, etc.)
p1:process
begin
A <= 0 after 10 ns;
B <= 0 after 10 ns;
C <= 0 after 10 ns;
D <= 0 after 10 ns;
wait on E;
A <= 1 after 5 ns;
B <= A + 1;
C <= B after 10 ns;
wait for 0 ns;
D <= B after 3 ns;
A <= A + 5 after 15 ns;
B <= B + 7;
wait;
end process p1;

ns delta A B C D E
0
+0
0 0 0 0 0
20 +0
0 0 0 0 1
20 +1
0 1 0 0 1
20 +2
0 8 0 0 1
23 +0
0 8 0 1 1
25 +0
1 8 0 1 1
28 +0
5 8 0 1 1
2.8

(modified) An inhibited toggle flip-flop has inputs I0, T, and Reset, and outputs Q and QN. Reset
is active high and overrides the action of the other inputs. The flip-flop works as follows. If I0 =
1, the flip-flop changes state on the rising edge of T, if I0 = 0, no state change occurs (except
on reset). Assume the propagation delay from T to output is 8 ns and from reset output is 5 ns.
entity INHIBITED_T_FF is
port (I0, T, RESET, CLK : in bit;
Q, QN : out bit);
end INHIBITED_T_FF;
architecture BEHAVE of INHIBITED_T_FF is
signal QTEMP : bit;
begin
process(RESET, CLK)
begin
if (RESET = '1') then

## QTEMP <= '0' after 5 ns;

elsif (CLK'event and CLK = '1') then
if (I0 = '1') then
QTEMP <= not QTEMP after 8 ns;
end if;
end if;
end process;
Q <= QTEMP;
QN <= not QTEMP;
end BEHAVE;

2.9

(using 1.8 instead of 1.11) (a) only, using the test sequence from 1.8. Write a behavioral VHDL
description of the state machine that you designed in Problem 1.8. Assume that state changes
occur on the falling edge of the clock pulse. Use a case statement together with if-then-else
statements to represent the state table. Compile and simulate your code using the test sequence
from 1.8.
entity SEQUENCE_DETECTOR is
port(X, CLK : in bit;
Z : out bit);
end SEQUENCE_DETECTOR;
architecture IF_CASE of SEQUENCE_DETECTOR is
type STATE_TYPE is (S0, S1, S2, S3, S4, S5);
signal STATE, NEXT_STATE : STATE_TYPE;
begin
process(STATE, X)
begin
case STATE is
when S0 => if(X = '0') then
NEXT_STATE <= S1;
Z <= '0';
else
NEXT_STATE <= S0;
Z <= '0';
end if;
when S1 => if(X = '0') then
NEXT_STATE <= S1;
Z <= '0';
else
NEXT_STATE <= S2;
Z <= '0';
end if;
when S2 => if(X = '0') then
NEXT_STATE <= S3;
Z <= '0';
else
NEXT_STATE <= S4;
Z <= '0';
end if;
when S3 => if(X = '0') then
NEXT_STATE <= S1;
Z <= '0';
else
NEXT_STATE <= S5;
Z <= '1';

end if;
when S4 => if(X = '0') then
NEXT_STATE <= S5;
Z <= '1';
else
NEXT_STATE <= S0;
Z <= '0';
end if;
when S5 => if(X = '0') then
NEXT_STATE <= S0;
Z <= '1';
else
NEXT_STATE <= S0;
Z <= '1';
end if;
end case;
end process;
process (CLK)
begin
if (CLK'event and CLK = '0') then
STATE <= NEXT_STATE;
end if;
end process;
end IF_CASE;
entity TEST_SEQ_DET is
end TEST_SEQ_DET;
architecture BEHAVE of TEST_SEQ_DET is
component SEQUENCE_DETECTOR
port (X, CLK : in bit;
Z : out bit);
end component;
signal CLOCK, SEQ_IN, SEQ_OUT : bit := '0';
begin
U1 : SEQUENCE_DETECTOR port map(SEQ_IN, CLOCK, SEQ_OUT);
CLOCK <= not CLOCK after 50 ns;
process
begin
SEQ_IN <= '0' after 25 ns, '1' after 125 ns, '0' after 225 ns,
'1' after 425 ns, '0' after 725 ns, '1' after 825 ns,
'0' after 925 ns, '1' after 1025 ns, '0' after 1125 ns,
'1' after 1225 ns, '0' after 1325 ns, '1' after 1425 ns,
'0' after 1625 ns, '1' after 1725 ns;
wait;
end process;
end BEHAVE;

## The University of Alabama in Huntsville

Electrical and Computer Engineering
CPE/EE 422/522
Spring 2005
Homework #5 Solution
3.2 (a)(10), (e)(20), 3.3(30), 3.6(20), 4.6(a)(20)
3.2

An older-model Thunderbird car has three left and three right tail lights, which flash in unique
patterns to indicate left and right turns.
Left-turn pattern:
LC LB LA RA RB RC

Right-turn pattern:
LC LB LA RA RB RC

Design a Moore sequential network to control these lights. The network has three inputs, LEFT,
RIGHT, and HAZ. LEFT and RIGHT come from drivers turn-signal switch and cannot be 1 at
the same time. As indicated above, when LEFT = 1, the lights flash in a pattern LA on, LA and
LB on, LA, LB, and LC on and all off; then the sequence repeats. When RIGHT = 1, the light
sequence is similar. IF a switch from LEFT to RIGHT (or vice versa) occurs in the middle of a
flashing sequence, the network should immediately go to the IDLE state (lights off) and then start
the new sequence. HAZ comes from the hazard switch, and when HAZ = 1, all six lights flash on
and off in unison. HAZ takes precedence if LEFT or RIGHT is also on. Assume that a clock
signal is available with a frequency equal to the desired flashing rate.
(a)
Draw the state graph (8 states).
LRH

000
S0
000000

010

100

dd1

0d0

S1
001000

100

0d0

S2
011000

100

dd0

S3
111000

dd1

dd1
dd1

dd1

S7
111111

dd1

dd1
dd1

S4
000100

d00

010
S5
000110

d00

010
S6
000111

## (e) Write a VHDL model

library ieee;
use ieee.std_logic_1164.all;
entity THUNDERBIRD is
port (L, R, H, CLK : in std_logic;
LC, LB, LA, RA, RB, RC : out std_logic);
end THUNDERBIRD;

dd0

## architecture BEHAVE of THUNDERBIRD is

type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
process(CURRENT_STATE, L, R, H)
variable INPUTS : std_logic_vector(2 downto 0);
begin
INPUTS := L&R&H;
case CURRENT_STATE is
when S0 => if (INPUTS = "000") then
NEXT_STATE <= S0;
elsif (INPUTS = "100") then
NEXT_STATE <= S1;
elsif (INPUTS = "010") then
NEXT_STATE <= S4;
else
NEXT_STATE <= S7;
end if;
when S1 => if (INPUTS(0) = '1') then
NEXT_STATE <= S7;
elsif (INPUTS = "100") then
NEXT_STATE <= S2;
else
NEXT_STATE <= S0;
end if;
when S2 => if (INPUTS(0) = '1') then
NEXT_STATE <= S7;
elsif (INPUTS = "100") then
NEXT_STATE <= S3;
else
NEXT_STATE <= S0;
end if;
when S3|S6 => if (INPUTS(0) = '1') then
NEXT_STATE <= S7;
else
NEXT_STATE <= S0;
end if;
when S4 => if (INPUTS(0) = '1') then
NEXT_STATE <= S7;
elsif (INPUTS = "010") then
NEXT_STATE <= S5;
else
NEXT_STATE <= S0;
end if;
when S5 => if (INPUTS(0) = '1') then
NEXT_STATE <= S7;
elsif (INPUTS = "010") then
NEXT_STATE <= S6;
else
NEXT_STATE <= S0;
end if;
when S7 => NEXT_STATE <= S0;
end case;
end process;

process (CLK)
begin
if (CLK'event and CLK = '1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
process(CURRENT_STATE)
begin
LC <= '0'; LB <= '0'; LA <= '0';
RA <= '0'; RB <= '0'; RC <= '0';
case CURRENT_STATE is
when S0 => null;
when S1 => LA <= '1';
when S2 => LA <= '1'; LB <= '1';
when S3 => LA <= '1'; LB <= '1';
when S4 => RA <= '1';
when S5 => RA <= '1'; RB <= '1';
when S6 => RA <= '1'; RB <= '1';
when S7 => LA <= '1'; LB <= '1';
RA <= '1'; RB <= '1';
end case;
end process;
end BEHAVE;

3.3

LC <= '1';

RC <= '1';
LC <= '1';
RC <= '1';

## Find a minimum-row PLA table to implement the following set of functions.

(a) (15 points) f1(A, B, C, D) = m(4, 5, 10, 11, 12),
f2(A, B, C, D) = m(0, 1, 3, 4, 8, 11)
f3(A, B, C, D) = m(0, 4, 10, 12, 14)

f1

C
0 0 0 0
1 1 0 0

1 0 0 0
A
0 0 1 1
D

f2
B

(b)

f1

C
0 0 1 0

1 0 0 1
B
0 0 0 0
A
0 1 1 0
D

C
1 1 1 0
1 0 0 0

0 0 0 0
A
1 0 1 0
D

f3
B

C
1 0 0 0
1 0 0 0

1 0 0 1
A
0 0 0 1
D

A
0
1
0
0
1

B
1
1
0
0
0
0
-

C
0
0
1
0
1
0
1

D
0
0
1
0
1
0

f1
1
1
1
0
0
0
0
0

f2
0
0
0
1
1
1
1
0

f3
0
1
0
0
0
1
0
1

A
1
0
1
1
0

B
0
0
1
0
0
1
1

C
1
1
1
0
0
1

D
1
1
0
0
0
0
-

f1
1
1
1
0
0
0
0
0

f2
0
0
0
1
1
1
1
0

f3
0
1
0
1
0
0
0
1

## f1(A, B, C, D) = m(3, 4, 6, 9, 11),

f2(A, B, C, D) = m(2, 4, 8, 10, 11, 12)
f3(A, B, C, D) = m(3, 6, 7, 10, 11)

f2

C
0 0 0 1

1 0 0 0
B
1 0 0 0
A
1 0 1 1
D

f3

C
0 0 1 0

0 0 1 1
B
0 0 0 0
A
0 0 1 1
D

3.6 (modified) Write a VHDL model on a 6-bit binary up-down counter with reset. Simulate the model
and verify that the counter works.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity UP_DOWN_COUNTER is
port (UP, DOWN, CLK, RESET : std_logic;
QOUT : out UNSIGNED(5 downto 0));
end UP_DOWN_COUNTER;
architecture BEHAVE of UP_DOWN_COUNTER is
begin
process(UP, DOWN, RESET, CLK)
variable QTEMP : UNSIGNED(5 downto 0);
begin
if (RESET = '1') then
QTEMP := "000000";
elsif (CLK'event and CLK = '1') then
if (UP = '1') then
if (QTEMP = UNSIGNED'("111111")) then
QTEMP := "000000";
else
QTEMP := QTEMP + '1';
end if;
elsif (DOWN = '1') then
if (QTEMP = UNSIGNED'("000000")) then
QTEMP := "111111";
else
QTEMP := QTEMP - '1';
end if;
end if;
end if;
QOUT <= QTEMP;
end process;
end BEHAVE;

4.6

In Section 4.4 we developed an algorithm for multiplying signed binary fractions, with negative
fractions represented in 2s complement. (a) Illustrate this algorithm by multiplying 1.0111 by
1.101.
0
1
1
1
1
1
1
1
0
0

.
.
.
.
.
.
.
.
.
.

0
0
0
1
1
0
0
1
1
0

0
1
1
0
1
1
1
0
0
0

0
1
1
1
0
1
0
1
0
1

0
1
1
1
1
1
0
0
1
1

shift w/sign extend
shift w/sign extend

1
1

1
0

1
1

shift w/sign extend

## The University of Alabama in Huntsville

Electrical and Computer Engineering
CPE/EE 422/522
Spring 2005
Homework #6 Solution
5.3(a)(20), 5.6(c)(20), 5.12(20), 8.2(20), 8.8(20)
5.3 (a) For the following SM chart: Draw a timing chart that shows the clock, the state (S0, S1 or S2),
the inputs (X1, X2 and X3) and the outputs. The input sequence is X1 X2 X3 = 011, 101, 111, 010,
110, 101, 001. Assume that all state changes occur on the rising edge of the clock, and the inputs
change on the falling edge of the clock.

S0/
1

X2

CLK

Z2

Z1

X1
0

Z3

X1

S1/ Z1

X3
1

X2
X3

X2

STATE S0

S2

Z1

S2/Z1

Z2
X1

Z3

5.6(c) For the given SM chart: Write a VHDL description of the system.
S0/
0

X1

1
0

X2

Z1
S1/Z3

S2/
0

X3

X4

Z2

Z3

X4
1

S0

S2

S1

S2

S0

S1

library ieee;
use ieee.std_logic_1164.all;
entity SM_CHART5_6 is
port (X1, X2, X3, X4, X5 : in std_logic;
Z1, Z2, Z3 : out std_logic;
CLK, RESET : in std_logic);
end SM_CHART5_6;
architecture BEHAVE of SM_CHART5_6 is
type STATE_TYPE is (S0, S1, S2);
signal STATE, NEXT_STATE : STATE_TYPE;
begin
process(X1, X2, X3, X4, X5, STATE)
begin
Z1 <= '0'; Z2 <= '0'; Z3 <= '0';
case STATE is
when S0 => if (X1 = '0') then
NEXT_STATE <= S0;
else
if (X2 = '0') then
Z1 <= '1';
NEXT_STATE <= S1;
else
NEXT_STATE <= S2;
end if;
end if;
when S1 => Z3 <= '1';
if (X3 = '0') then
NEXT_STATE <= S2;
else
Z2 <= '1';
NEXT_STATE <= S1;
end if;
when S2 => if (X4 = '0') then
if (X5 = '0') then
NEXT_STATE <= S2;
else
NEXT_STATE <= S0;
end if;
else
Z3 <= '1';
NEXT_STATE <= S1;
end if;
end case;
end process;
process(CLK, RESET)
begin
if (RESET = '1') then
STATE <= S0;
elsif (CLK = '1' and CLK'event) then
STATE <= NEXT_STATE;
end if;
end process;
end BEHAVE;

5.12

The block diagram for an elevator controller for a building with two floors is shown below. The
inputs FB1 and FB2 are floor buttons in the elevator. The inputs CALL1 and CALL2 are call
buttons in the hall. The inputs FS1 and FS2 are floor switches that output a 1 when the elevator is
at the first or second floor landing. Outputs UP and DOWN control the motor, and the elevator is
stopped when UP = DOWN = 0. N1 and N2 are flip-flops that indicate when the elevator is
needed on the first or second floor. R1 and R2 are signals that reset these flip-flops. DO = 1
causes the door to open, and DC = 1 indicates that the door is closed. Draw an SM chart for the
elevator controller (four states).

FB1
CALL1

FB2
CALL2

R2

Storage
Network N1

Storage
Network

R1

Elevator
Control
Network

N2

UP
DOWN

FS1
FS2

DO

DC

F21/

F12/

DOWN

UP
0

FS2

FS1

1
R2, DO

R1, DO

F22/

F11/
R2, DO

N2

R1, DO

0
0

N2

1
DC

N1

0
N1

Door
Mechanism

1
0

DC
DOWN

1
UP

8.2

Design an address decoder. One input to the address decoder is an 8-bit address, which can have
any range with a length of 8, for example: std_logic_vector addr(8 to 15). The second input is
check : std_logic_vector(5 down to 0). The address decoder will output Sel = 1 if the upper 6
bits of the 8-bit address match the 6-bit check vector. For example, if addr = 10001010 and
check = 1000-- then Sel = 1. Only the 6 leftmost bits of addr will be compared; the remaining
bits are ignored. An - in the check vector is a dont care.

library ieee;
use ieee.std_logic_1164.all;
CHECK : in std_logic_vector(5 downto 0);
SEL : out std_logic);
begin
variable MATCH : boolean;
begin
MATCH := TRUE;
if ((ADDR(I) /= CHECK(I-2)) and (CHECK(I-2) /= '-')) then
MATCH := FALSE;
end if;
end loop;
if (MATCH) then
SEL <= '1';
else
SEL <= '0';
end if;
end process;
end BEHAV;

8.8

Write a VHDL function to compare two IEEE std_logic_vectors to see whether they are equal.
Report an error if any bit in either vector is not 0, 1, or - (dont care), or if the lengths of the
vector are not the same. The function call should pass only the vectors. The function should
return TRUE if the vectors are equal, else FALSE. When comparing the vectors, consider that 0
= - and 1 = -. Make no assumptions about the index range of the two vectors.

library ieee;
use ieee.std_logic_1164.all;
package MINE is
function "=" (L, R : std_logic_vector) return boolean;
end MINE;

## package body MINE is

function "=" (L, R : std_logic_vector) return boolean is
variable EQUAL : boolean;
alias LEFT : std_logic_vector(L'length-1 downto 0) is L;
alias RIGHT : std_logic_vector(L'length-1 downto 0) is R;
begin
assert L'length = R'length
report "Vectors are not the same length"
severity error;
EQUAL := TRUE;
for I in LEFT'range loop
case LEFT(I) is
when '0' => case RIGHT(I) is
when '0'|'-' => null;
when others => EQUAL := FALSE;
end case;
when '1' => case RIGHT(I) is
when '1'|'-' => null;
when others => EQUAL := FALSE;
end case;
when '-' => case RIGHT(I) is
when '0'|'1' => null;
when others => EQUAL := FALSE;
end case;
when others => assert FALSE
report "First vector has invalid value"
severity error;
end case;
assert (RIGHT(I)='0' or RIGHT(I)='1' or RIGHT(I)='-')
report "Second vector has invalid value"
severity error;
end loop;
return EQUAL;
end "=";
end MINE;

## The University of Alabama in Huntsville

Electrical and Computer Engineering
CPE/EE 422/522
Spring 2005
Homework #7
Solution
From the book,
10.1 (20 points) (a) & (b) for q s-a-0 and d s-a-1
(a) Determine the necessary inputs to the following network to test for q s-a-0 and d s-a-1.
(b) For this set of inputs, determine which other stuck-at faults can be tested.
q s-a-0

d s-a-1

ABCD = 1000 detects q s-a-0 and also detects c s-a-1, d s-a-1, r s-a-0, t s-a-1, v s-a-0, and
F s-a-0
ABCD = 1100 detects q s-a-0 and also detects a s-a-0, r s-a-0, t s-a-1, v s-a-0, and F s-a-0
ABCD = 1000 detects d s-a-1 and also detects q s-a-0, c s-a-1, r s-a-0, t s-a-1, v s-a-0, and
F s-a-0
ABCD = 0000 detects d s-a-1 and also detects c s-a-1, p s-a-1, q s-a-0, r s-a-0, s s-a-0,
and t s-a-1
ABCD = 0100 detects d s-a-1 and also detects a s-a-1, c s-a-1, p s-a-0, r s-a-1, t s-a-1,
u s-a-1, v s-a-1, and F s-a-0

10.2 (20 points) Find a minimum set of tests that will test all single stuck-at-0 and stuck-at-1 faults in the
following network. For each test, specify which faults are tested for s-a-1 and s-a-1.
abcdefi = 0001001 a s-a-1, b s-a-1, c s-a-1, g s-a-1
abcdefi = 1000001 d s-a-1, e s-a-1, f s-a-1, h s-a-1
abcdefi = 1001001 g s-a-0, h s-a-0, i s-a-0, Z s-a-0
abcdefi = 0101001 b s-a-0
abcdefi = 0011001 c s-a-0
abcdefi = 1000101 e s-a-0
abcdefi = 1000011 f s-a-0
abcdefi = 1001000 i s-a-1, Z s-a-1
10.7 (10 points) State graphs for two sequential machines are given below. The first graph represents a
correctly functioning machine, and the second represents the same machine with a malfunction.
Assuming that the two machines can be reset to their starting states (S0 and T0), determine the shortest
input sequence that will distinguish the two machines.

Input:
Correct Output:
Incorrect Output:

0
1
1

0
1
1

0
1
1

1
0
0

1
0
0

1
0
0

1
1
0

## From other sources

(25 points) Design a hardware multiplier circuit (M) that computes the product of two, positive 2-bit
binary numbers.
A0
A1
B0
B1

M0
M1
M2
M3

A1A0 represents one 2-bit number, B1B0 represents the second 2-bit number and M3M2M1M0 represents
the 4-bit product. For example, if A1A0 = 10 and B2B1B0 = 11, then M3M2M1M0 0110. Model your
circuit by performing the following steps.
a. Develop a VHDL entity declaration for the multiplier.
b. Develop an algorithmic behavioral architectural body for the multiplier.
c. Simulate to verify the correctness of your model.
entity MULTIPLIER is
port (A:in bit_vector (1 downto 0);
B: in bit_vector (1 downto 0);
M: out bit_vector (3 downto 0));
end MULTIPLIER;
architecture BEHAVE of MULTIPLIER is
begin
process(A,B)
variable temp : bit_vector (3 downto 0);
begin
temp := A & B;
case TEMP is
when "0000"|"0001"|"0010"|"0011"|"0100"|"1000"|"1100"
when "0101" => M <= "0001";
when "0110"|"1001" => M <= "0010";
when "0111"|"1101" => M <= "0011";
when "1010" => M <= "0100";
when "1011"|"1110" => M <= "0110";
when "1111" => M <= "1001";
end case;
end process;
end BEHAVE;

## => M <= "0000";

(25 points) Design a sequential circuit that converts a 4-bit Gray code into a 4-bit BCD code. The inputs
and outputs are timed by the same system clock. Assume that the device receives a START pulse
coincident with the left most bit of the Gray code. The remaining bits of the Gray code are received one
bit at a time (from left to right). At the end of each 4-bit Gray code, the device outputs the corresponding
4-bit BCD code in parallel along with a DAV signal. The next input could start during the clock period
following the last input bit or at any time after that. The device must have a RESET input that initializes
the device to the correct starting state. The figure given shows a block diagram and sample timing
diagram. Use the table below for the Gray and BCD codes.
Decimal Digit
0
1
2
3
4
5
6
7
8
9

Gray Code
0000
0001
0011
0010
0110
1110
1010
1011
1001
1000

BCD Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

Model the device using VHDL and do a simulation to verify your model.
4

START
SI
RESET
CLOCK

BCD
DAV

SGTBCD

CLOCK
START
SI

DAV
BCD

0101

0000

entity SGRAY2BCD is
port (R, SI, START, CLK: in BIT;
BCD: out BIT_VECTOR(3 downto 0);
DAV: out BIT);
end SGRAY2BCD;
architecture FSM_RTL of SGRAY2BCD
type STATE_TYPE is (S0, S1, S2,
signal STATE: STATE_TYPE;
signal SHIFT_REG: BIT_VECTOR (3
begin
-- Process to update state at end

is
S3, S4);
downto 0);
of each clock period.

## NEXT_STATE: process (R, CLK)

begin
if (R = '0') then
STATE <= S0;
elsif (CLK='1'and CLK'event) then
case STATE is
when S0 =>
if (START = '1') then
STATE <= S1;
SHIFT_REG <= SHIFT_REG(2 downto 0)
end if;
when S1 =>
SHIFT_REG <= SHIFT_REG(2 downto 0) &
STATE <= S2;
when S2 =>
SHIFT_REG <= SHIFT_REG(2 downto 0) &
STATE <= S3;
when S3 =>
SHIFT_REG <= SHIFT_REG(2 downto 0) &
STATE <= S4;
when S4 =>
if (START = '1') then
STATE <= S1;
SHIFT_REG <= SHIFT_REG(2 downto 0)
else
STATE <= S0;
end if;
end case;
end if;
end process NEXT_STATE;
--- Output process
-OUTPUT: process (STATE)
Begin
case STATE is
when S0|S1|S2|S3 =>
BCD <= "0000";
DAV <= '0';
when S4 =>
DAV <= '1';
case SHIFT_REG is
when "0000" => BCD <= "0000";
when "0001" => BCD <= "0001";
when "0011" => BCD <= "0010";
when "0010" => BCD <= "0011";
when "0110" => BCD <= "0100";
when "1110" => BCD <= "0101";
when "1010" => BCD <= "0110";
when "1011" => BCD <= "0111";
when "1001" => BCD <= "1000";
when "1000" => BCD <= "1001";
when others => BCD <= "0000";
end case;
end case;
end process OUTPUT;
end FSM_RTL;

&SI;

SI;

SI;

SI;

& SI;

## CPE/EE 422/522 SP2005, Lab Assignment 1

Decimal up-Counter
PART A (90/60 points)
The purpose of this laboratory project is to give each student the opportunity to
develop a practical logic design using either schematic capture and/or VHDL that will
implement a decimal up-counter that counts up to 99, using two four 4-bit binary counter
developed in the previous lab and a modified bintohex file called bintodec. The result
should display the decimal equivalent on the two Altera UP1 Educational Trainers
seven-segment LEDs.
PART B (10/20 points)
Add a reset button that clears the display and restarts the counter when pressed.
Pin Assignment
Altera Pin Numbers for the FLEX DIGIT Segment I/O Connections
FLEX_PB1 Push Button
Display Segment
A
B
C
D
E
F
G
Decimal

6
7
8
9
11
12
13
14

28
Pin for Digit 2
17
18
19
20
21
23
24
25

## CPE/EE 422/522 S2005, Laboratory Assignment 2

PS 2, PC Keyboard Interface
75/60 Points (422/522)
The purpose of this laboratory project is to give each student the opportunity to develop a
practical logic design that interfaces a 104 key PS-2 style keyboard to the Altera UP 1
Educational Trainer. The design should be created in a manner that will allow it to
display in hexadecimal format on two seven-segment LEDs, the final byte of the socalled make/break scan code sequence that is produced by the keyboard when each key is
pressed.

Background
PS-2 type keyboards contain the embedded logic necessary to scan all 104 keys and
produce a unique scan code for each key that is pressed. This logic performs a similar
function to that which was performed by the scanning keypad design that was developed
by CPE/EE 422/502 students in Laboratory Assignment 3. To greatly minimize the
number of lines that connect the PS 2 keyboard to an external device (such as a PC,
Altera UP-1, etc.) the embedded processor translates the scan code into a serial format.
This effectively reduces the number of wires needed for a 104 key keyboard from 22 to
about four, which include VCC, Ground, a keyboard clock, and a keyboard data line. The
VCC and ground line are used to power the keyboard and data is transferred in and out of
the keyboard using the bidirectional keyboard clock (KEY_CLK) and data (DATA) lines.
In this lab, we will use the keyboard as an output only device meaning the from the
digital design's point of view the keyboard clock and keyboard data lines are always
inputs to the design. (It is possible, and common, for an external design to drive these
lines in the other direction to perform such functions as resetting the keyboard, switching
keyboards scan code character sets, etc. The keyboard is very flexible. We will only be
using its basic default features in this laboratory assignment.)
In its default mode, every time a key is press a sequence of bytes is sent serially across
the data line from the keyboard to the external device. There is a separate sequence of
bytes that is sent when each key is pressed and another sequence that is sent when each
key is released. The sequence that is sent when the key is pressed is often called the Make
Code and the sequence that is sent when the key is released is called the Break Code .
Except for a few special keys, the last byte that is sent in the make code and break code
sequence for a given key are identical to one another with its value uniquely represents

the key that was pressed. Table 1 lists the final byte of the make/break sequences for each
of the keys on the PS/2 keyboards that will be used in the laboratory assignment. This
table assumes the key labeling that is shown in Figure 1.
Make/Break Codes for PS/2 Keyboard
Key Final Byte of
Key Final Byte of
Key Final Byte of
#
Make/Break Sequence #
Make/Break Sequence #
Make/Break Sequence
1

76

36

4A

71

6B

05

37

7C

72

73

06

38

7B

73

74

04

39

0D

74

79

0C

40

15

75

12

03

41

1D

76

1A

0B

42

24

77

22

83

43

2D

78

21

0A

44

2C

79

2A

10

01

45

35

80

32

11

09

46

3C

81

31

12

78

47

43

82

3A

13

07

48

44

83

41

14

7C

49

4D

84

49

15

7E

50

54

85

4A

16

77

51

5B

86

59

17

0E

52

5A

87

75

18

16

53

71

88

69

19

1E

54

69

89

72

20

26

55

7A

90

7A

21

25

56

6C

91

5A

22

2E

57

75

92

14

23

36

58

7D

93

1F

24

3D

59

58

94

11

25

3E

60

1C

95

29

26

46

61

1B

96

11

27

45

62

23

97

27

28

4E

63

2B

98

2F

29

55

64

34

99

14

30

5D

65

33

100 6B

31

66

66

3B

101 72

32

70

67

42

102 74

33

6C

68

4B

103 70

34

7D

69

4C

104 71

35

77

70

52
Table 1

Figure 1

Each byte that is sent from the keyboard utilizes the keyboard clock and data lines, which
are labeled, KEY_CLK and DATA, respectively, in the manner shown in Figure 2. If no
external device force either of these lines to go low, then for each key pressed the
keyboard will send each byte in the make/break byte sequence across the data line at a
data transfer rate of approximately 14285 bits per second. It does this by first forcing the
DATA line low to create a start bit and then initiating the keyboard clock sequence by
first forcing the KEY_CLK line low for one half clock cycle. Information is then sent
from the keyboard, with each bit being valid at the leading edge of each clock pulse. First
the start bit is sent, then eight data bits, then a parity bit, and then a stop bit. After which
the DATA and KEY_CLK lines are returned to the inactive state until the next byte is
sent. Figure 2 illustrates the waveform that will appear when the keyboard sends out the
value 76 hexadecimal (which corresponds to the last byte of the make/break code for key
1 shown in Figure 1 and Table 1.
The Altera UP 1 board supports the use of PS/2 devices with a standard PS/2 on-board
connector. The connector is wired in a manner so that VCC and GND are connected to
the appropriate pins of the PS/2 keyboard to power it up and the KEY_CLK, DATA lines
are connected as shown in Table 2. For detailed connection information see page 13 of
University Program Design Laboratory User Guide.

Altera Pin Numbers for the PS/2 Keyboard and Clock Lines
Line

Pin Numbers

KEY_CLK

30

DATA

31

Assignment
A

60/40

All students are to develop a design that will display in hexadecimal the last byte of each
make/break code sequence on two seven segment displays. There are to be two separate
designs that are to be developed and demonstrated.
(30/20) I. Schematic capture based with only the binary to hexadecimal
conversion sections of the design being implemented in VHDL.
(30/20) II. The second design should be entered entirely in VHDL.
Both designs must be demonstrated to the course or lab instructor and fully
documented.

15/20

## Develop an adder/subtractor of the make/break (Make Break) codes displayed on the

LEDS as decimals. Use the PB1 switch to enable the add/subtract option. Design should
be done in VHDL.

Due 2-25-05 6pm NO late labs will be accepted. Early birds are welcomed

## CPE/EE 422/522 S2005, Laboratory Assignment 3

Computer Display Interface (Due: 3/11)
The purpose of this laboratory project is to give each student the opportunity to
understand the basic concepts of computer display techniques and to develop a practical
logic design that will drive an EGA type video display. The techniques that are explored
here can easily be adapted and applied to drive more modern display elements.

Background
The Enhanced Graphics Adapter, EGA, is a video display standard developed by IBM
corporation in the late 1980's. It supports 64 distinct colors and allows for a resolution of
640 by 350 picture elements (pixels). All video signals utilize standard digital TransistorTransistor Logic, TTL voltage levels.
EGA monitors contain a color Cathode Ray Tube, CRT. At one end of the CRT is the
phosphor screen and at the other end is an electron gun. During normal operation
magnetic and electrostatic fields cause a set of electron beams to leave the electron gun
and be deflected to the desired position on the phosphor screen of the CRT resulting in
that portion of the screen being illuminated in proportion to the intensity of the electrons
that strike the phosphor. To achieve color, three types of phosphor are placed on each
screen, one for each of the primary colors of red, green, and blue. This phosphor is
deposited on the screen in small dots. The screen is then divided up into a set of picture
elements (Pixels) with each pixel being composed of three phosphor dots of different
types that are placed in close proximity to one another. During normal operation the
electron gun produces three separate electron beams which can simultaneously illuminate
all three dots at various levels of intensity allowing for a wide range of colors to be
created. In the EGA standard, these three electron beams are controlled separately in an
on/off manner by applying the appropriate TTL logic level to the associated inputs to the
monitor. For each of the three primary colors there are two logical inputs, one which
controls whether or not the phosphors for that particular color should be illuminated, and
another to select which level of brightness (intensity) that the pixel should have if it is
illuminated. By varying the intensity and color bits it is possible for each pixel to be
colored in 64 separate ways.
Figure 1 shows the pixel configuration for a standard EGA monitor. Notice that the pixels
are arranged as a two dimensional array of 350 rows by 640 columns. During standard
operation, the electron gun is directed to point to each of the pixels on the screen. As
shown in the figure, it begins at the upper left had corner at pixel 0,0 and points to (and
illuminates when directed) each pixel along the row going from the left to the right until
it points to the last pixel in the row (pixel 639,0). It then retraces back to the left had side

of the screen and starts illuminating the selected pixels from left to right along the second
row. This process continues this until all the pixels of the 350 rows have been visited in
this manner (starting at pixel 0,1). This process is continuous, beginning each time at the
upper left most screen postion.

All of this of course occurs at a rate that is much faster than the human eye can observe.
In the EGA standard the screen has a 60 HZ refresh rate which means that all pixels are
updated once every 1/60 of a second. The EGA monitor uses two synchronization
signals. One is the Vertical Sync signal which is used to signal the monitor that a new
image (frame) is to be displayed and the other one is the Horizontal Sync which is used to
signal the monitor that a new row is to be displayed. The timing for the corresponding
vertical and horizontal refresh cycles are shown in Figures 2 and 3.

The basic timing for the vertical refresh cycle is shown in Figure 2. The cycle begins with
a 595 us negative going vertical sync pulse, after which 350 horizontal refresh cycles
occur one for each of the 350 rows to be displayed.
Each horizontal refresh cycle, is in turn given by the timing diagram shown in Figure 3.
Note that each cycle begins with a 4.92 us positive going horizontal sync pulse, which is
to be followed (after a delay of 1.48 us) by the pixel data. This data is the intensity and
red/green/blue color bit information for each of the 640 pixels along the corresponding
row. The rate at which the horizontal sync pulse is set is 21.85 KHZ, and the pixel data
transfer rate is 16.3840 MHZ. During the horizontal sync phase, when the electronic
beam is returning to the left most column to begin the next line, all pixel data should be
turned off to avoid seeing the horizontal and vertical retrace lines that are shown in
below.

Since the on-board 25.175MHZ clock on the Altera UP 1 cannot be divide evenly enough
to provide stable displays each student will be provided with a 16.3840 MHZ crystal
oscillator. This oscillator can be used to generate all synchronization, and pixel data
signals. Each station in the rapid prototyping laboratory has an EGA monitor which in
turn has a cable that is connected the Altera UP-1 board. All nine EGA signals from the
monitor are run out of the cable through separate wires that have connectors on them that
can plug directly into the protoboard. Table below illustrates the color code convention
that has been used.

## EGA Connection Information for Rapid Prototyping Laboratory

EGA Function

Wire Color

EGA Function

Wire Color

Ground

Brown

Green

Yellow

Vertical Sync

Black

Green Intensity

Blue

Horizontal Sync

White

Blue

Green

Red

Red

Red Intensity

Orange

Blue Intensity

Purple

Suggested wiring information is presented below. If this wiring scheme is not followed
then all signals that run into the EGA monitor must be properly buffered using a TTL line
driver device, such as a 74xx244. All EGA configurations which do not conform to the
handout must be approved by the laboratory or course instructor before power is applied
to the boards.
The following is the recommended interface connections to be made between the Altera
UP 1 board, the external 16.3840MHZ Oscillator, and the EGA monitor.

## EGA Standardized Connections

EGA
Function

Wire Color

Ground

Brown

Vertical
Sync
Horizontal
Sync
Red

Black

UP1
EXPAN_A
Connection
Ground
Pin 2 or 4
Pin 23

White

Pin 21

Red

Pin 15

Red
Intensity

Orange

Ground
Pin 2 or 4

EGA
Function

Wire Color

Green

Yellow

Green
Intensity
Blue

Blue
Green

Blue
Purple
Intensity
Case Ground Shielded

UP1
EXPAN_A
Connection
Pin 17
Ground
Pin2 or 4
Pin 19
Ground
Pin 2 or 4
Ground
Pin 2 or 4

You are to use an external 16.3840 MHZ TTL oscillator IC to provide the base timing
signal. The output of this oscillator is to drive one of the Altera 10k20 pins (Pin25) that
are connected to the EXPAN_A connected in the manner shown below.

16.3840 MHZ
Oscillator

No Connection

## A vhdl template will be handed to you in class

Assignment
Part A 65/50
All students are to develop a design that will clearly display in at least one color on the
EGA screen a character assigned by the instructor. This character will move to the four
different locations on the screen in a timely manner as shown below for a k example.
This design must be demonstrated to the course or lab instructor and fully documented.

After 0 secs
K

After 2 secs
K

After 4 secs

After 6 secs

After 8 secs
K

Part B 10/15
10/15 Display the current position of your letter on the LED 1, 2, 3 or 4
and use your reset button to reset he screen back to position 1 at any time.

CPE/EE 422/522
Logic Design Building Blocks
Dr. Rhonda Kay Gaede

UAH
1

UAH

Alternate Source

CPE/EE 422/522

Multiplexers
Decoders
Encoders
Code Converters
Comparators
Multipliers
Shifters

Page 2 of 13

UAH

CPE/EE 422/522

Alternate Source

## Multiplexers: - 2-to-1 Multiplexer

Think of a multiplexer as selecting between multiple
sources which may be multiple bits wide.
w0

s
w0
w1

s
w1

s

0
1

w0

w1

f = s' w0 + sw1

Page 3 of 13

UAH

CPE/EE 422/522

Alternate Source

s0
s1
w0
w1
w2
w3

s1 s0
00
01
10
11

0
0
1
1

0
1
0
1

f
w0
w1
w2
w3

s0
w0
s1
w1

## (b) Truth table

w2

w3
(c) Circuit

f=
Electrical and Computer Engineering

Page 4 of 13

UAH

CPE/EE 422/522

Alternate Source

Multiplexers
s1

s0
s1

s0

w0
w3

w0

w1

s2
s3

w4
0

w7

w2

w3

w8
w11

## (b) 16-to-1 using 4-to-1

(a) 4-to-1 using 2-to-1

w12

Page 5 of 13

UAH

CPE/EE 422/522

Alternate Source

## Synthesis of Logic Functions

Using Multiplexers
w1 w2
0
0
1
1

0
1
0
1

w2
w1

0
1
1
0

0
1
1
0

## (a) Implementation using a 4-to-1 multiplexer

w1 w2

w1

w2

w2

w1
w2
f

(c) Circuit
(b) Modified truth table
Electrical and Computer Engineering

Page 6 of 13

UAH

CPE/EE 422/522

Alternate Source

## Synthesis of Logic Functions

Using Multiplexers - Another Example
w1 w2 w3

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

w1 w2

0
0
0
1
0
1
1
1

0
0
1
1

0
1
0
1

w2
w1

0
w3
w3

0
w3

1
(b) Circuit

Page 7 of 13

UAH

Alternate Source

CPE/EE 422/522

## Decoders - n-to-2n Decoder

If En = 1, __________________________
If En = 0, ___________________
One-hot encoded output
_______________________________________
w0
n
inputs
Enable

2n
outputs

wn 1
En

y 0 = w n 1'...w1' w0' En
y1 = w n 1'...w1' w0En

y0

y2n 1

## Electrical and Computer Engineering

y 2 = wn 1'...w1w0' En
...
y 2n 1 = wn 1...w1w0En
Page 8 of 13

UAH

Alternate Source

CPE/EE 422/522

y0 y1 y2 y3

En w1 w0
1
1
1
1
0

0
0
1
1
x

0
1
0
1
x

1
0
0
0
0

0
1
0
0
0

0
0
1
0
0

w0

0
0
0
1
0

y0
w1
y1

w0
w1
En

y2

y0
y1
y2
y3

y3
En

Page 9 of 13

## Electrical and Computer Engineering

UAH

Alternate Source

CPE/EE 422/522

Encoders
Opposite of decoders
_______________________________________

Binary encoders
______________________________
Exactly_________ of the input signals should have a value of 1,
and outputs present the _________________ that identifies which input
is equal to 1

## Use: reduce the number of bits

(transmitting and
storing information)

w0

2n
inputs
w2n 1
Electrical and Computer Engineering

y0

yn 1
Page 10 of 13

UAH

Alternate Source

CPE/EE 422/522

0
0
0
1

0
0
1
0

0
1
0
0

w0

y1 y0

w3 w2 w1 w0

0
0
1
1

1
0
0
0

w1

0
1
0
1

y0

w2
y1

w3

(b) Circuit

Page 11 of 13

UAH

Alternate Source

CPE/EE 422/522

## Encoders: Priority Encoders

Each input has a priority level associated with it
The encoder outputs indicate the active input
that has the highest priority
(a) Truth table for a 4-to-2 priority encoder

w3 w 2 w 1 w 0
0
0
0
0
1

0
0
0
1
x

0
0
1
x
x

0
1
x
x
x

## Electrical and Computer Engineering

y1 y0

d
0
0
1
1

0
1
1
1
1

d
0
1
0
1

Page 12 of 13

UAH

CPE/EE 422/522

Alternate Source

Code Converters
Convert from one type of input encoding to a different
output encoding
E. g., BCD-to-7-segment decoder
w 3 w 2 w1 w0
w0
w1
w2
w3

a
b
c
d
e
f
g

## (a) Code converter

a
f
e

b
g

d
(b) 7-segment display

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

1
0
1
1
0
1
1
1
1
1

1
1
1
1
1
0
0
1
1
1

1
1
0
1
1
1
1
1
1
1

1
0
1
1
0
1
1
0
1
1

1
0
1
0
0
0
1
0
1
0

1
0
0
0
1
1
1
0
1
1

0
0
1
1
1
1
1
0
1
1

## (c) Truth table

Electrical and Computer Engineering

Page 13 of 13

## The University of Alabama in Huntsville

ECE Department
CPE/EE 422/522 01
Midterm Exam
March 1, 2005
Name: ____________________________
1.

(10 points) A sequential network consists of a PLA and a D flip-flop, as shown. The propagation
delay for the PLA is in the range 5 to 10 ns, and the propagation delay from clock to output of the
D flip-flop is 5 to 10 ns. Assuming that X always changes at the same time as the falling edge of
the clock, what is the maximum setup and hold time specifications that the flip-flop can have and
still maintain proper operation of the network?
Z

Clk

PLA
Clk

X
Q
Z
20

2.

40

60

80

100

(10 points) Write a short VHDL description of a 4-to-1 multiplexer using a VHDL process.
entity MUX4_1 is
port (I3, I2, I1, I0, S1,S0 : in bit;
F : out bit);
end MUX4_1;
architecture MUX4_1of MUX4_1is
begin

end MUX4_1;

3.

(15 points) For the following VHDL, assume that A changes to 1 at 5 ns. Give the values of A,
B, C, D, E, and F each time a change occurs. Carry this out until no further change occurs. I
entity prob is
port (D : inout bit);
end prob;
architecture PROB of PROB is
signal A, B, C, E, F : bit;
begin
P1: process (A, C)
begin
B <= A after 3 ns;
E <= C after 5 ns;
end process P1;
C <= A after 10 ns;
P2: process (C, E)
begin
F <= C and E after 4 ns;
end process P2;
D <= A or B or C or F after

Time
0 ns
5 ns

A
0
1

B
0
0

C
0
0

D
0
0

E
0
0

F
0
0

1 ns;
end PROB;

4.

(5 points) Obtain a minimum product of sums expression for the following function:
f(A, B, C, D) = M(0, 1, 2, 4, 5, 8, 9, 10)

5.

(15 points) A Mealy sequence detector detects a sequence of four consecutive 1 inputs. The
detector has a single binary input, X, and a single binary output, Z. Signal Z should be logic 1 if
and only if the last four inputs were all logic 1. Here is an example input-output sequence:
X
Z

010111111101101011110
000000111100000000010

Derive a Mealy state graph and table with a minimum number of states for this sequence detector

6.

(10 points) For the following Ft, find all static-1 hazards. For each hazard, specify the values of
the input variables and which variable is changing when the hazard occurs.
Ft = ab + ac + bb + bc + ad

7.

(10 points) Reduce the following state table to a minimum number of states. Show all your work
in determining the state equivalents.
Next State
Present State X = 0 X = 1 Output
A
I
C
1
B
B
I
1
C
C
G
1
D
I
C
0
E
D
E
0
F
I
C
0
G
E
F
0
H
H
A
1
I
A
C
1

8.

(5 points) Write out the truth table for the following equation.
F = (A B) + C

9.

(5 points) Draw a timing diagram that illustrates the difference between a D flip-flop and a D
latch.

10.

## (1 point) ____________________ design is a technique that uses a clock to coordinate the

operation of all flip-flops, registers and counters in the system.

11.

12.

## (1 point) A process with a sensitivity list is activated whenever ____________________

_____________________________________.

13.

14.

## (1 point) ___________________ networks commonly use flip-flips as storage devices.

15.

(10 points) Draw the state diagram for the following state machine. Is it a Moore machine or a
Mealy machine?

ENTITY state_machine IS
PORT (sig_in ; IN BIT; clk : IN BIT;
sig_out : OUT BIT);
END state_machine;
ARCHITECTURE state_machine OF state_machine IS
TYPE state_type IS (a, b, c, d, e);
SIGNAL current_state, next_state : state_type;
BEGIN
PROCESS (sig_in, current_state)
BEGIN
sig_out <= 0; next_state <= b;
CASE current_state
WHEN a =>
IF sig_in = 0 THEN next_state <= e; sig_out <= 1;
ELSE next_state <= d;
END IF;
WHEN b =>
IF sig_in = 0 THEN next_state <= b;
ELSE next_state <= d; sig_out <= 1;
END IF;
WHEN c =>
IF sig_in = 1 THEN next_state <= a;
ELSE next_state <= d;
END IF;
WHEN d =>
IF sig_in = 0 THEN next_state <= e;
END IF;
WHEN e =>
IF sig_in = 1 THEN next_state <= a;
END IF;
END CASE;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clkEVENT AND clk = 1) THEN
current_state <= next_state;
END IF;
END PROCESS;
END state_machine;

## The University of Alabama in Huntsville

ECE Department
CPE/EE 422/522 01
Midterm Exam Solution
1.

(10 points) A sequential network consists of a PLA and a D flip-flop, as shown. The propagation
delay for the PLA is in the range 5 to 10 ns, and the propagation delay from clock to output of the
D flip-flop is 5 to 10 ns. Assuming that X always changes at the same time as the falling edge of
the clock, what is the maximum setup and hold time specifications that the flip-flop can have and
still maintain proper operation of the network?
Z

Clk

PLA
Clk

X
Q
Z
20

40

60

80

100

For both the setup time and hold time, there are two paths to consider, one from X to the D input of the
flip-flop and the other from Q to the D input of the flip-flop. From the timing diagram, tck = 40 ns, tx =
20 ns and ty = 20 ns, where tck is the clock period, tx is the time from a change on X to the active edge of
the clock and ty is the time from the active edge of the clock to a change on X. The following equations
apply: For Q: (1) tck tpdmax + tcmax + tsu, (2) th tpdmin + tcmin
For X: (3) tx tsu + tcmax, (4) th ty + tcmin
where tpd is the propagation delay through the flip-flop and tc is the propagation delay through the
combinational circuit (PLA)
So, for setup,
(1) 40 ns 10 ns + 10 ns + t su, tsu 20 ns
(3) 20 ns tsu + 10 ns , tsu 10 ns

## So, for hold,

(2) th 5 ns + 5 ns, th 10 ns
(4) th 20 ns + 5 ns, th 25 ns

For both the setup and the hold times to be always satisfied, we must take the smaller numbers so
tsu = th = 10 ns
2.

(10 points) Write a short VHDL description of a 4-to-1 multiplexer using a VHDL process.
entity MUX4_1 is
port (I3, I2, I1, I0, S1,S0 : in bit;
F : out bit);
end MUX4_1;
architecture MUX4_1of MUX4_1 is
begin
process (I3, I2, I1, I0, S1, S0)
begin
if (S1 = 0 and S0 = 0) then
F <= I0;
elsif (S1 = 0 and S0 = 1) then
F <= I1;
elsif (S1 = 1 and S0 = 0) then
F <= I2;
else
F <= I3;
end if;
end MUX4_1;

3.

(15 points) For the following VHDL, assume that A changes to 1 at 5 ns. Give the values of A,
B, C, D, E, and F each time a change occurs. Carry this out until no further change occurs. I
entity prob is
port (D : inout bit);
end prob;

Time
0 ns
5 ns
6 ns
8 ns
15 ns
20 ns
24 ns

## architecture PROB of PROB is

signal A, B, C, E, F : bit;
begin
P1: process (A, C)
begin
B <= A after 3 ns;
E <= C after 5 ns;
end process P1;
C1: C <= A after 10 ns;
P2: process (C, E)
begin
F <= C and E after 4 ns;
end process P2;
C2: D <= A or B or C or F after 1 ns;
end PROB;

Time Event
5 ns A 1

Process Triggered
P1
P1
C1
C2
none
C2
P1
P1
P2
C2
P2
C2

6 ns D 1
8 ns B 1
15 ns C 1

20 ns E 1
24 ns F 1
4.

A B
0 0
1 0
1 0
1 1
1 1
1 1
1 1

C D E
0 0 0
0 0 0
0 0 0
0 1 0
1 1 0
1 1 1
1 1 1

Scheduled Transaction
B 1 8 ns
E 0 10 ns
C 1 15 ns
D 1 6 ns

Event?
Yes
No
Yes
Yes

D 1 9 ns
B 1 18 ns
E 1 20 ns
F 0 19 ns
D 1 16 ns
F 1 24 ns
D 1 25 ns

No
No
Yes
No
No
Yes
No

(5 points) Obtain a minimum product of sums expression for the following function:
f(A, B, C, D) = M(0, 1, 2, 4, 5, 8, 9, 10)
f = (BC + AC + BD)
= (BC)(AC)(BD)
= (B + C)(A + C)(B + D)

C
0

B
A

F
0
0
0
0
0
0
1

5.

(15 points) A Mealy sequence detector detects a sequence of four consecutive 1 inputs. The
detector has a single binary input, X, and a single binary output, Z. Signal Z should be logic 1 if
and only if the last four inputs were all logic 1. Here is an example input-output sequence:
X
Z

010111111101101011110
000000111100000000010

Derive a Mealy state graph and table with a minimum number of states for this sequence detector

Next State
Output
Present State X = 0 X = 1 X = 0 X = 1
S0
S0
S1
0
0
S1
S0
S2
0
0
S2
S0
S3
0
0
S3
S0
S3
0
1

0/0

S0
1/0

0/0
S1
1/0
0/0

S2
1/0

0/0

6.

S3

1/1

(10 points) For the following Ft, find all static-1 hazards. For each hazard, specify the values of
the input variables and which variable is changing when the hazard occurs.

Ft = ab + ac + bb + bc + ad
1

2
c

## For hazard 1, a is changing and bcd = 000

For hazard 2, a is changing and bcd = 010
b

7.

(10 points) Reduce the following state table to a minimum number of states. Show all your work
in determining the state equivalents
Next State
Present State X = 0 X = 1 Output
A
I
C
1
B
B
I
1
C
C
G
1
D
I
C
0
E
D
E
0
F
I
C
0
G
E
F
0
H
H
A
1
I
A
C
1

Next State
Present State X = 0 X = 1 Output
A
A
C
1
B
B
A
1
C
C
G
1
D
A
C
0
E
D
E
0
G
E
D
0

I=B
C=I

I=C
C=G

I=G

I=B
C=I

I=C
I=G
C=G

D
I=D
C=E

D=E
I=C

I=H
C=A I=A A=G

E=H
F=A

A=B A=C
I=A C=I C=G

E=A
F=C

H=A
A=C

I=B
C=I

I=C
C=G

I=E
C=F

D=E
I=C

F
I=E
C=F

I=D
C=E

I=H
C=A I=A A=G

E=H
F=A

A=B A=C
I=A C=I C=G

E=A
F=C

H=A
A=C

I=G

D
I=D
C=E

D=E
I=C

I=E
C=F

G
H
I

I=H
I=A A=G
C=A

E=H
F=A

A=B A=C
C=I C=G

E=A
F=C

H=A
A=C

I=A

8.

(5 points) Write out the truth table for the following equation.
F = (A B) + C
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1

9.

(5 points) Draw a timing diagram that illustrates the difference between a D flip-flop and a D
latch.

QF

CLK

QL

CLK/G

CLK

QF

QL

10.

(1 point) __Synchronous_ design is a technique that uses a clock to coordinate the operation of all
flip-flops, registers and counters in the system.

11.

## (1 point) The value of a ___variable__ changes instantaneously in VHDL

12.

(1 point) A process with a sensitivity list is activated whenever _an event occurs on any signal_
__in the sensitivity list_.

13.

14.

## (1 point) __Sequential__ networks commonly use flip-flips as storage devices.

15.

(10 points) Draw the state diagram for the following state machine. Is it a Moore machine or a
Mealy machine?

ENTITY state_machine IS
PORT (sig_in ; IN BIT; clk : IN BIT;
sig_out : OUT BIT);
END state_machine;
ARCHITECTURE state_machine OF state_machine IS
TYPE state_type IS (a, b, c, d, e);
SIGNAL current_state, next_state : state_type;
BEGIN
PROCESS (sig_in, current_state)
BEGIN
sig_out <= 0; next_state <= b;
CASE current_state
WHEN a =>
IF sig_in = 0 THEN next_state <= e; sig_out <= 1;
ELSE next_state <= d;
END IF;
WHEN b =>
IF sig_in = 0 THEN next_state <= b;
ELSE next_state <= d; sig_out <= 1;
END IF;
WHEN c =>
IF sig_in = 1 THEN next_state <= a;

## ELSE next_state <= d;

END IF;
WHEN d =>
IF sig_in = 0 THEN next_state <= e;
END IF;
WHEN e =>
IF sig_in = 1 THEN next_state <= a;
END IF;
END CASE;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clkEVENT AND clk = 1) THEN
current_state <= next_state;
END IF;
END PROCESS;
END state_machine;
Mealy
1/0

1/0

0/1

0/0

1/0
0/0

d
1/0

1/1

0/0

b
0/0

## Extra Credit (5 points): Rework problem 6 using a Moore machine.

Next State
Present State X = 0 X = 1 Output
S0
S0
S1
0
S1
S0
S2
0
S2
S0
S3
0
S3
S0
S4
0
S4
S0
S4
1

S0
0
1

S1
0

S2
0

1
0

S3
0
1

S4
1

## CPE/EE 522 S2005, Laboratory Project

Computer Display Interface (Due: 4/15)
The purpose of this laboratory project is to give each student the opportunity to
understand the basic concepts of computer display techniques and to develop a practical
logic design that will drive an EGA type video display. The techniques that are explored
here can easily be adapted and applied to drive more modern display elements.

Background
The Enhanced Graphics Adapter, EGA, is a video display standard developed by IBM
corporation in the late 1980's. It supports 64 distinct colors and allows for a resolution of
640 by 350 picture elements (pixels). All video signals utilize standard digital TransistorTransistor Logic, TTL voltage levels.
EGA monitors contain a color Cathode Ray Tube, CRT. At one end of the CRT is the
phosphor screen and at the other end is an electron gun. During normal operation
magnetic and electrostatic fields cause a set of electron beams to leave the electron gun
and be deflected to the desired position on the phosphor screen of the CRT resulting in
that portion of the screen being illuminated in proportion to the intensity of the electrons
that strike the phosphor. To achieve color, three types of phosphor are placed on each
screen, one for each of the primary colors of red, green, and blue. This phosphor is
deposited on the screen in small dots. The screen is then divided up into a set of picture
elements (Pixels) with each pixel being composed of three phosphor dots of different
types that are placed in close proximity to one another. During normal operation the
electron gun produces three separate electron beams which can simultaneously illuminate
all three dots at various levels of intensity allowing for a wide range of colors to be
created. In the EGA standard, these three electron beams are controlled separately in an
on/off manner by applying the appropriate TTL logic level to the associated inputs to the
monitor. For each of the three primary colors there are two logical inputs, one which
controls whether or not the phosphors for that particular color should be illuminated, and
another to select which level of brightness (intensity) that the pixel should have if it is
illuminated. By varying the intensity and color bits it is possible for each pixel to be
colored in 64 separate ways.

Figure 1 shows the pixel configuration for a standard EGA monitor. Notice that the pixels
are arranged as a two dimensional array of 350 rows by 640 columns. During standard
operation, the electron gun is directed to point to each of the pixels on the screen. As
shown in the figure, it begins at the upper left had corner at pixel 0,0 and points to (and
illuminates when directed) each pixel along the row going from the left to the right until
it points to the last pixel in the row (pixel 639,0). It then retraces back to the left had side
of the screen and starts illuminating the selected pixels from left to right along the second
row. This process continues this until all the pixels of the 350 rows have been visited in
this manner (starting at pixel 0,1). This process is continuous, beginning each time at the
upper left most screen postion.

All of this of course occurs at a rate that is much faster than the human eye can observe.
In the EGA standard the screen has a 60 HZ refresh rate which means that all pixels are
updated once every 1/60 of a second. The EGA monitor uses two synchronization
signals. One is the Vertical Sync signal which is used to signal the monitor that a new
image (frame) is to be displayed and the other one is the Horizontal Sync which is used to
signal the monitor that a new row is to be displayed. The timing for the corresponding
vertical and horizontal refresh cycles are shown in Figures 2 and 3.

The basic timing for the vertical refresh cycle is shown in Figure 2. The cycle begins with
a 595 us negative going vertical sync pulse, after which 350 horizontal refresh cycles
occur one for each of the 350 rows to be displayed.
Each horizontal refresh cycle, is in turn given by the timing diagram shown in Figure 3.
Note that each cycle begins with a 4.92 us positive going horizontal sync pulse, which is
to be followed (after a delay of 1.48 us) by the pixel data. This data is the intensity and
red/green/blue color bit information for each of the 640 pixels along the corresponding
row. The rate at which the horizontal sync pulse is set is 21.85 KHZ, and the pixel data
transfer rate is 16.3840 MHZ. During the horizontal sync phase, when the electronic
beam is returning to the left most column to begin the next line, all pixel data should be
turned off to avoid seeing the horizontal and vertical retrace lines that are shown in
Figure 1.

Since the on-board 25.175MHZ clock on the Altera UP 1 cannot be divide evenly enough
to provide stable displays each student will be provided with a 16.3840 MHZ crystal
oscillator. This oscillator can be used to generate all synchronization, and pixel data
signals. Each station in the rapid prototyping laboratory has an EGA monitor which in
turn has a cable that is connected the Altera UP-1 board. All nine EGA signals from the
monitor are run out of the cable through separate wires that have connectors on them that
can plug directly into the proto board. Table 1 illustrates the color code convention that
has been used.

## EGA Connection Information for Rapid Prototyping Laboratory

EGA Function

Wire Color

EGA Function

Wire Color

Ground

Brown

Green

Yellow

Vertical Sync

Black

Green Intensity

Blue

Horizontal Sync

White

Blue

Green

Red

Red

Red Intensity

Orange

Blue Intensity

Purple

Assignment

All students are to develop a design that will clearly display the character used in lab3
work 8 different colors at a two seconds interval on the EGA monitor. Use the same pin
assignments and color as used in lab3