74 Als 867

SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869

SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C DECEMBER 1982 REVISED JANUARY 1995
Fully Programmable With Synchronous

Counting and Loading
SN74ALS867A and AS867 Have
Asynchronous Clear; SN74ALS869 and
AS869 Have Synchronous Clear
Fully Independent Clock Circuit
Simplifies Use
Ripple-Carry Output for n-Bit Cascading
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
SN54AS867, SN54AS869 . . . JT PACKAGE

SN74ALS867A, SN74ALS869, SN74AS867,
SN74AS869 . . . DW OR NT PACKAGE
(TOP VIEW)
S0
S1
A
B
C
D
E
F
G
H
ENT
GND
description
These counters are fully programmable; they may

be preset to any number between 0 and 255. The
load-input circuitry allows parallel loading of the
cascaded counters. Because loading is
synchronous, selecting the load mode disables
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the counter and causes the outputs to agree with
the data inputs after the next clock pulse.
24
23
22
21
20
19
18
17
16
10
15
11
14
12
13
VCC
ENP
QA
QB
QC
QD
QE
QF
QG
QH
CLK
RCO
A
S1
S0
NC
VCC
SN54AS867, SN54AS869 . . . FK PACKAGE

(TOP VIEW)
B
C
D
NC
E
F
G
2 1 28 27 26
25
24
23
22
21
10
20
19
11
12 13 14 15 16 17 18
QB
QC
QD
NC
QE
QF
QG
H
ENT
GND
NC
RCO
CLK
QH
These synchronous, presettable, 8-bit up/down

counters feature internal-carry look-ahead
circuitry for cascading in high-speed counting
applications. Synchronous operation is provided
by having all flip-flops clocked simultaneously so
that the outputs change coincidentally with each
other when so instructed by the count-enable
(ENP, ENT) inputs and internal gating. This mode
of operation eliminates the output counting spikes
normally associated with asynchronous (rippleclock) counters. A buffered clock (CLK) input
triggers the eight flip-flops on the rising (positivegoing) edge of the clock waveform.
ENP
QA
NC No internal connection
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output are instrumental
in accomplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined
by the levels of the select (S0, S1) inputs as shown in the function table. ENT is fed forward to enable RCO. RCO
thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting
up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages.
Transitions at ENP and ENT are allowed regardless of the level of CLK. All inputs are diode clamped to minimize
transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the
SN74ALS867A and AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q
outputs until clocking occurs. For the AS867 and AS869, any time ENP and/or ENT is taken high, RCO either
goes or remains high. For the SN74ALS867A and SN74ALS869, any time ENT is taken high, RCO either goes
or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely
by the conditions meeting the stable setup and hold times.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
description (continued)
The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of
55C to 125C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for
operation from 0C to 70C.
FUNCTION TABLE
S1
S0
FUNCTION
Clear
Count down
Load
Count up
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2
DALLAS, TEXAS 75265
logic symbols
SN74ALS867A
S0
S1
ENT
ENP
CLK
A
B
C
D
E
F
G
H
1
2
11
23
14
0
1
CTRDIV 256
0
M
3
G4
1,4CT=0
G5
3,4CT=255
13
RCO
C6/1,4,5 /3,4,5 +
0R
22
2,6D
21
20
19
18
17
16
10
15
QA
QB
QC
QD
QE
QF
QG
QH
SN74ALS869
S0
S1
ENT
ENP
CLK
A
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B
C
D
E
F
G
H
1
2
11
23
14
0
1
CTRDIV 256
0
M
3
G4
1,4CT=0
G5
3,4CT=255
13
RCO
C6/1,4,5 /3,4,5 +
0,6R
22
2,6D
21
20
19
18
17
16
10
15
QA
QB
QC
QD
QE
QF
QG
QH
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
DALLAS, TEXAS 75265
logic symbols (continued)

AS867
S0
S1
ENT
ENP
CLK
A
B
C
D
E
F
G
H
1
2
11
23
14
0
1
CTRDIV 256
0
M
3
G4
1,4,5CT=0
G5
3,4,5CT=255
13
RCO
C6/1,4,5 /3,4,5 +
0R
22
2,6D
21
20
19
18
17
16
10
15
QA
QB
QC
QD
QE
QF
QG
QH
AS869
S0
S1
ENT
ENP
CLK
A
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B
C
D
E
F
G
H
1
2
11
23
14
0
1
CTRDIV 256
0
M
3
G4
1,4,5CT=0
G5
3,4,5CT=255
RCO
C6/1,4,5 /3,4,5 +
0,6R
22
2,6D
21
20
19
18
17
16
10
15
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
13
DALLAS, TEXAS 75265
QA
QB
QC
QD
QE
QF
QG
QH
logic diagram (positive logic)

SN74ALS867A, SN74ALS869
14
CLK
1
S0
S1 2
SN74ALS867A Only
(asynchronous clear)
ENP 23
A 3
1D
C1
R
B 4
1D
C1
R
C 5
1D
C1
R
D 6
1D
C1
R
E 7
1D
C1
R
F 8
1D
C1
R
G 9
1D
C1
R
H 10
1D
C1
R
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22 Q
A
21 Q
B
20 Q
C
19 Q
D
18 Q
E
17 Q
F
16 Q
G
15 Q
H
13
RCO
ENT 11
DALLAS, TEXAS 75265
logic diagram (positive logic)

AS867, AS869
S0
S1
ENT
ENP
CLK
AS867 Only
(asynchronous clear)
11
13
23
14
22
3
QD
1D
C1
R
18
E
QC
1D
C1
R
19
D
QB
1D
C1
R
20
C
QA
1D
C1
R
21
B
RCO
QE
1D
C1
R
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17
F
16
G
10
1D
C1
R
6
QG
1D
C1
R
15
H
QF
1D
C1
R
DALLAS, TEXAS 75265
QH
typical clear, preset, count, and inhibit sequences

The following sequence is illustrated below:
1. Clear outputs to zero (SN74ALS867A and AS867 are asynchronous;
SN74ALS869 and AS869 are synchronous.)
2. Preset to binary 252
3. Count up to 253, 254, 255, 0, 1, and 2
4. Count down to 1, 0, 255, 254, 253, and 252
5. Inhibit
S0
S1
A
B
C
Data
Inputs
D
E
F
G
H
CLK
ENP
ENT
QA
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QB
QC
QD
Outputs
QE
QF
QG
QH
RCO
Sync
252 253 254 255 0 1
Clear
Count Up
255 254 253 252

Count Down
Inhibit
Async Preset
Clear
ENT and ENP both must be low for counting to occur.
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA: SN74ALS867A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions

SN74ALS867A
MIN
NOM
MAX
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
fclock
Low-level output current
tw(clock)
tw(clear)
Pulse duration, CLK high or low
14
ns
Pulse duration of clear pulse, S0 and S1 low
10
ns
tsu
High-level input voltage
V
0.8
High-level output current
0.4
Clock frequency
Setup time before CLK
th
Hold time after CLK
TA
Operating free-air temperature
Data inputs A H
10
ENP or ENT
15
S0 low and S1 high (load)
12
S0 high and S1 low (count down)
12
S0 and S1 high (count up)
12
S0 high after S1 or S1 high after S0
Data inputs A H
V
V
mA
mA
35
MHz
ns
ns
70
electrical characteristics over recommended operating free-air temperature range (unless

noted)
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otherwise
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = 18 mA
IOH = 0.4 mA
VOL
5V
VCC = 4
4.5
IOL = 4 mA
IOL = 8 mA
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
SN74ALS867A
TYP
MAX
MIN
1.2
VCC 2
30
UNIT
V
V
0.25
0.4
0.35
0.5
0.1
mA
20
0.2
mA
112
mA
ICC
VCC = 5.5 V
28
45
mA
All typical values are at VCC = 5 V, TA = 25C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
8
DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,

CL = 50 pF,
RL = 500 ,
TA = MIN to MAX
SN74ALS867A
MIN
fmax
tPLH
RCO
CLK
Any Q
tPHL
tPHL
ENT
RCO
S0 or S1 (clear mode)
Any Q
tPLH
tPHL
S0 or S1
(count up/down)
RCO
tPHL
tPLH
MAX
35
CLK
tPHL
tPLH
MHz
14
14
16
16
14
26
16
16
tPLH
S0 or S1 (clear mode)
RCO
4
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
UNIT
16
ns
ns
ns
ns
ns
ns
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DALLAS, TEXAS 75265
Operating free-air temperature range, TA: SN74ALS869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C

SN74ALS869
VCC
VIH
Supply voltage
VIL
IOH
IOL
fclock
tw(clock)
tsu
MIN
NOM
MAX
4.5
5.5
0.4
0
Set p time before CLK

Setup
th
Hold time after CLK
TA
10
ENP or ENT
15
S0 and S1 low (clear)
13
13
13
13
S0 high after S1 or S1 high after S0
Data inputs A H
V
mA
mA
35
MHz
14
Data inputs A H
V
V
0.8
Clock frequency
UNIT
ns
ns
ns
70

noted)
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otherwise
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = 18 mA
IOH = 0.4 mA
VOL
VCC = 4
4.5
5V
IOL = 4 mA
IOL = 8 mA
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
SN74ALS869
TYP
MAX
MIN
1.2
VCC 2
30
UNIT
V
V
0.25
0.4
0.35
0.5
0.1
mA
20
0.2
mA
112
mA
ICC
VCC = 5.5 V
28
45
mA
10
DALLAS, TEXAS 75265
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,

CL = 50 pF,
RL = 500 ,
TA = MIN to MAX
SN74ALS869
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
MAX
35
CLK
RCO
CLK
Any Q
ENT
RCO
S1
(count up/down)
RCO
MHz
14
14
16
16
14
15
15
4
S0
RCO
(clear/load)
tPHL
4
UNIT
16
12
ns
ns
ns
ns
ns
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DALLAS, TEXAS 75265
11
Operating free-air temperature range, TA: SN54AS867 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C
SN74AS867 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C

SN54AS867
SN74AS867
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
0.8
0.8
mA
IOL
fclock*
tw(clock)*
tw(clear)*
12.5
10
ns
Pulse duration of clear pulse, S0 and S1 low
12.5
10
ns
20
Clock frequency
Data inputs A H
ENP or ENT
tsu*

Setup
40
11
10
11
10
42
40
42
40
th*
Hold time after CLK
Data inputs A H
tskew*
Skew time between S0 and S1

(maximum to avoid inadvertent clear)
20
mA
50
MHz
ns
ns
7
ns
TA
55
125
0
70
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* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
12
DALLAS, TEXAS 75265

otherwise noted)
PARAMETER
VIK
VOH
VOL
RCO
IIH
IIL
ENT
Other inputs
ENT
Other inputs
MIN
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = 18 mA
IOH = 2 mA
VCC = 4.5 V
IOL = 20 mA,
VIL on ENT = 0.7 V
VCC = 5.5 V,
IOL = 20 mA
VI = 7 V
Other outputs
II
SN54AS867
TYP
MAX
TEST CONDITIONS
VCC = 5
5.5
5V
V,
VI = 2
2.7
7V
VCC = 5
5.5
5V
V,
VI = 0
0.4
4V
SN74AS867
TYP
MAX
MIN
1.2
VCC 2
1.2
VCC 2
0.34
UNIT
V
V
0.5
V
0.34
0.5
0.1
0.1
40
40
20
20
mA
A
mA
IO
VCC = 5.5 V,
VO = 2.25 V
30
112
30
112
mA
ICC
VCC = 5.5 V
134
195
134
195
mA
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,

CL = 50 pF,
RL = 500 ,
TA = MIN to MAX
SN54AS867
SN74AS867
MIN
fmax*
tPLH
tPHL
tPLH
tPHL
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tPLH
tPHL
tPLH
tPHL
tPHL
MAX
40
CLK
RCO
CLK
Any Q
ENT
RCO
ENP
RCO
Clear (S0 or S1 low)
Any Q
MIN
UNIT
MAX
50
MHz
31
22
19
16
12
11
16
15
19
10
21
17
16
14
21
17
23
21
ns
ns
ns
ns
ns
DALLAS, TEXAS 75265
13
Operating free-air temperature range, TA: SN54AS869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C
SN74AS869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C

SN54AS869
SN74AS869
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
0.7
0.8
mA
IOL
fclock*
20
20
mA
Clock frequency
40
45
MHz
tw(clock)*
12.5
11
ENP or ENT
10
13
11
13
11
52
50
52
50
Data inputs A H
tsu*
th*
TA

Setup
Hold time after CLK
Data inputs A H
0
55
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14
DALLAS, TEXAS 75265
ns
ns
0
125
ns
70

otherwise noted)
PARAMETER
VIK
VOH
VOL
RCO
IIH
IIL
ENT
Other inputs
ENT
Other inputs
MIN
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = 18 mA
IOH = 2 mA
VCC = 4.5 V,
VCC = 4.5 V
IOH = 2 mA
IOL = 20 mA,
VIL on ENT = 0.7 V
VCC = 5.5 V,
IOL = 20 mA
VI = 7 V
Other outputs
II
SN54AS869
TYP
MAX
TEST CONDITIONS
5V
VCC = 5
5.5
V,
7V
VI = 2
2.7
VCC = 5
5.5
5V
V,
VI = 0
0.4
4V
SN74AS869
TYP
MAX
MIN
1.2
1.2
VCC 2
V
V
VCC 2*
0.34
UNIT
0.5
V
0.34
0.5
0.1
0.1
40
40
20
20
mA
A
mA
IO
VCC = 5.5 V,
VO = 2.25 V
30
112
30
112
mA
ICC
VCC = 5.5 V
134
195
134
195
mA
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,

CL = 50 pF,
RL = 500 ,
TA = MIN to MAX
SN54AS869
MIN
fmax*
tPLH
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tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
MAX
40
CLK
RCO
CLK
Any Q
ENT
RCO
ENP
RCO
UNIT
SN74AS869
MIN
MAX
45
MHz
35
35
20
18
12
11
16
15
25
15
21
17
27
19
tPHL
6
21
6
18
DALLAS, TEXAS 75265
ns
ns
ns
ns
15
PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR

BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
tPLZ
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Waveform 1
S1 Closed
(see Note B)
tPHZ
[ 3.5 V
VOL
0.3 V
VOH
1.3 V
3.5 V
1.3 V
Input
1.3 V
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
0.3 V
[0 V
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
16
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SN54AS867, SN54AS869

SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869

Fully Programmable With Synchronous

SN54AS867, SN54AS869 . . . JT PACKAGE

These counters are fully programmable; they may

SN54AS867, SN54AS869 . . . FK PACKAGE

These synchronous, presettable, 8-bit up/down

Copyright 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

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logic symbols (continued)

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logic diagram (positive logic)

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logic diagram (positive logic)

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typical clear, preset, count, and inhibit sequences

255 254 253 252

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recommended operating conditions

Low-level input voltage

Low-level output current

Pulse duration, CLK high or low

Pulse duration of clear pulse, S0 and S1 low

High-level input voltage

High-level output current

Setup time before CLK

Hold time after CLK

Operating free-air temperature

S0 low and S1 high (load)

S0 high and S1 low (count down)

S0 and S1 high (count up)

S0 high after S1 or S1 high after S0

electrical characteristics over recommended operating free-air temperature range (unless

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switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V,

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recommended operating conditions

Low-level input voltage

Low-level output current

Pulse duration, CLK high or low

High-level input voltage

High-level output current

Set p time before CLK

Hold time after CLK