Digital Circuits Assignment #4 Due Tuesday July 30th/2013

Digital Circuits Assignment #4

Question 1

Lecture #7 covered implementing functions with different mux/decoders. Implement the following with:
a) An 8:1 Mux
b) A 4:1 Mux
c) A 3:8 Decoder
Perform each of the above implementation techniques for the following:

f ( A, B, C ) = mi (0,1, 4,5)

i)
ii)

f ( A, B, C ) = M i (0,1, 4,5)

iii)

f ( A, B, C ) = ABC+AC

Question 2
In class you were shown the RS Latch built from NOR gates. This question will use NAND gates to build a
similar latch (and flip-flop).
a) Design a RS Latch using two NAND gates. The general form is as in the NOR gate based RS latch
but with NAND gates replacing the NOR gates. Note the inputs for the latch will be called R and

S since they are active low that is the hold state will be R =1, S =1. The order of the inputs
may differ from the NOR-based RS latch.
b) The following table shows that the initial state of Q is 0 and
following procedure:

is 1. Fill in the table with the

1. The previous state of Q + becomes the current state of Q. For example if Q + was 0
in row 1, the Q value for row 2 would be 0. Likewise if Q + was 1 for row 1, the Q
value for row 2 would be 1.
2. Find the new values for Q + Q + by tracing through the schematic.
Q
0

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1
0
1
1
1
0
1

1
1
1
0
1
0
1

Q+

Q+

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Digital Circuits Assignment #4 Due Tuesday July 30th/2013

c) Complete the timing diagram for your design in part (A) by drawing the Q and Q outputs:

d) Design a RS Flip-Flop with four NAND Gates. Note the RS Flip-Flop implies there is a CLOCK input.
e) Complete the timing diagram for your design in part (C) by drawing the Q and Q outputs:

f)

Modify the design above to add asynchronous PRESET and CLEAR inputs. This modified design
should use two 2-input NAND gates, and two 3-input NAND gates. Are the inputs active high or
active low?

g) Complete the timing diagram from your design in part (D) by drawing the Q and Q outputs:

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Digital Circuits Assignment #4 Due Tuesday July 30th/2013

Question 3
Use flip-flop conversion techniques to implement the following:
a) A JK Flip-Flop from a D Flip-Flop
b) A T Flip-Flop from a JK Flip-Flop
c) A RS Flip-Flop from a T Flip-Flop

Question 4
Design a shift register which takes a Serial Clock, Serial Data, and active-low Slave Select (SS) line. Data is
shifted in Least Significant Bit (LSB) first on the rising clock edge. Data is present on the eight data lines
only AFTER all eight bits are shifted in.
For example here is a diagram showing the inputs and expected outputs when transferring the single
byte 0x23. Note how the output changes only when the SS line goes HIGH.

Question 5
Design a counter which counts through the sequence 000 -> 001 -> 010 -> 011 -> 100 -> 10 1-> 110 ->
111 and repeats. Design this counter with:
a) D Flip-Flops
b) T Flip-Flops

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This work by Colin OFlynn is licensed under a Creative Commons Attribution-ShareAlike

3.0 Unported License .