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QucsStudio: A second generation Qucs software package for

compact semiconductor device model development based


on interactive and compiled equation-defined modelling techniques
plus circuit simulation
M. E. Brinson
Centre for Communications Technology
London Metropolitan University
London N78DB, UK
mbrin72043@yahoo.co.uk

Introduction: scope of presentation and background

Fundamentals of equation defined modelling

Quantity modelling

Verilog-A code for equation-defined models

An npn phototransistor model

Template device modelling

A step-recovery diode model

A Curtice RF MESFET model

Summary and references

Presented at the COMON 2nd International Training Course on Compact Modelling, June 28-29, 2012
Tarragona, Spain

Introduction: Scope of presentation


and background

The primary purpose of this presentation is to introduce the fundamentals


of equation-defined device modelling and there application in compact
semiconductor device development
Starting with the SPICE circuit simulator as a reference point both interpretive
and compiled code for compact device models are introduced
Throughout the presentation a series of compact semiconductor modelling
case studies are discussed to demonstrate equation-defined model construction
techniques
Particular emphasis is given to Verilog-A compact model development
The Qucs and QucsStudio open source circuit simulators are employed in most
of the demonstration case studies when simulating model performance

Introduction : Qucs development roadmap


Date

Release Notes [Highlights]

Dec. 2003
Jun. 2004
Sep. 2004

0.0.1
0.0.2
0.0.3

Mar. 2005
May 2005
Jul. 2005

0.0.5
0.0.6
0.0.7

Jan. 2006

0.0.8

May 2006

0.0.9

Sept. 2006

0.0.10

Mar. 2007

0.0.11

Jun. 2007

0.0.12

Nov. 2007
Apr. 2008

0.0.13
0.0.14

Apr. 2009
Mar. 2011

0.0.15
0.0.16

First public version of simulator - very basic.


First MacOS version.
Implemented S-parameters and noise analysis. Added microstrip components and
BJT and MOSFET devices.
Implemented AC analysis and basic transient analysis.
Mainly bug fixes and extensions to implemented analysis.
Windows 32 version. Simulator renamed as Qucs. New device library manager.
Added post simulation data processing mathematical functions.
Support for pure digital simulation using FreeHDL. Added many new component
models. Improved post simulation data plotting features. Added a filter synthesis tool.
New functions in equation solver. Harmonic Balance simulation introduced. Many
new components added.
Qucs converter tool improved. Support for nine-valued VHDL logic. Circuit optimization
introduced using ASCO. Added attenuator design tool.
Added device parameters to equations and parameters to subcircuits. New models plus
improvements to existing models. Using ADMS to translate Verilog-A device models for
use in Qucs.
Lots of new components, bug fixes and small improvements. Added support for Verilog
using Icarus Verilog. Support for symbolically equation-defined devices (EDD). Explicit
equations allowed.
General improvements plus implementation of immediate vectors and matrices in equations.
Implemented multi-port equation-defined RF device (RFEDD) S, Y and Z parameters
available. Two-port equation-defined device also supported.
Mainly bug fixes, small improvements and the addition of new models.
Implemented interactive post simulation data processing using Octave. Again many bug
fixes, small improvements and the addition of new models.

Introduction : QucsStudio development roadmap


Date

Release Notes [Highlights]

Feb. 2011

1.0.0

First public version of simulator- features include more than 100 different circuit components,
DC analysis, AC analysis (including noise analysis and noise distribution analysis), Sparameter analysis (including noise simulation), transient analysis, Harmonic Balance
analysis (including noise simulation), system simulation, parameter sweep and optimization
of analogue circuits, digital simulation with ICARUS Verilog,PCB layout using KiCAD,
numerical data processing using Octave, RF transmission line calculation (coaxial, microstrip,
coupled microstrip, coplanar line, stripline, twisted pair rectangular wavequide etc.,
filter synthesis (LC ladder, stepped-impedance, microstrip, active filters etc., attenuator
synthesis, and GPIB control.

Mar. 2011

1.1.0

Added VHDL digital simulation with GHDL plus numerous bug fixes.

Jun. 2011

1.2.0

Many small improvements plus bug fixes.

Nov. 2011

1.3.0

Feb. 2012

1.3.1

April 2012

1.3.2

Added compiled C++ and Verilog-A device and circuit models using MinGW and ADMS,
more bug fixes and small improvements. Released QucsStudio-light: QucsStudio without
Octave and model Compiler.
Verilog-A: new syntax for highlighting, $given() function, preprocessor flag 'insideQucsStudio',
better parameter extraction in Verilog-A files, port names in Verilog-A symbols. Linear branches
in Verilog-A. Added stoh() function. Windowing for time2freq() function. HB now allows
Frequency sweeps. Many small improvements plus bug fixes.
Added functions length(), arcsin() and arccos() in equations. Added export filter for Xfig3.2
format. Added system simulation icon to simulation group. Added German translation for text
editor. Many small improvements plus bug fixes.

Introduction: SPICE and Qucs circuit simulation

DC

Circuit
encoding
SPICE
2g6
and
3f5
NETLIST

AC

TRAN

Qucs
Schematic
diagram

S-parameter*

*Implementation 1. Qucs: built-in; 2. SPICE: via RCL networks

Introduction: Qucs post-simulation MATLAB*/Octave** data processing features


Equation blocks + simulation data sets

Data processing

Tables and plots

Constants: i, j, pi, e, kB, q


Number suffixes: E, P, T, G, M, k, m, u, n, p, f, a
Immediate: 2.5, 1.4+j5.1, [1, 3, 4, 5, 7], [11, 12; 21, 22] Matrices: M, M[2,3], M[:,3]
Ranges: Lo:Hi, :Hi, Lo:, :
Arithmetic operators: +x, -x, x+y, x-y, x*y, x/y, x%y, x^y
Logical operators: !x, x&&y, x||y, x^^y, x?y:z, x==y, x!=y, x<y, x<=y,x>y, x>=y
abs adjoint angle arccos arccosec arccot arcosech arcosh arcoth arcsec arcsin arctan arg arsech arsinh artanh
avg besseli0 besselj bessely ceil conj cos cosec cosech cosh cot coth cumavg cumprod cumsum dB dbm dbm2w
deg2rad det dft diff erf erfc erfcinv erfinv exp eye fft fix floor Freq2Time GaCircle GpCircle hypot idft ifft imag
integrate interpolate inverse kbd limexp linspace ln log10 log2 logspace mag max min Mu Mu2 NoiseCircle norm
phase PlotVs polar prod rad2deg random real rms Rollet round rtoswr rtoy rtoz runavg sec sech sign sin sinc sinh
sqr sqrt srandom StabCircleL StabCircleS StabFactor StabMeasure stddev step stos stoy stoz sum tan tanh
Time2Freq transpose twoport unwrap variance vt w2dbm xvalue ytor ytos ytoz yvalue ztor ztos ztoy

* MATLAB, Mathworks, http://www.mathworks.com/


** Octave, http://www.gnu.org/software/octave/
Limitations: NO user defined functions
or control loops

Introduction: SPICE/ Qucs modelling tools subcircuits


with parameters

Emitter follower
subcircuit
Voltage gain

Input resistance

Output resistance

Introduction: SPICE/Qucs modelling tools macromodels with


parameters
Single pole OP AMP macromodel
specification:

Macromodel body

Macromodel symbol

Voff = Input offset voltage


Rd = differential input resistance
Cd = differential input capacitance
AOLDC = DC open loop differential voltage gain
GBP = Gain bandwidth product
Vlimit = output voltage saturation limit
Ro = Output resistance

Closed loop
amplifier
with x10 gain

VBP=

j f/f0
1 f / f 0 2 j /Q f / f 0

f 0=

1
1
=
2 R 3 C 1 2 R4 C 3
R
1
Q= 1 6
3
R7

Three OP AMP state variable filter

Fundamentals of equation-defined device modelling


The QucsStudio circuit simulator provides a mature mix of simulation and
analysis routines which are launched from a graphical environment
specifically designed for schematic drawing, netlist entry, and simulation control

+
Compact device modelling and circuit macromodelling tools

A convenient, interactive and powerful modelling system for


building and testing multi-domain simulation models in the
following categories

Hand crafted
C++ models

Component based
Component based
circuit macromodels
subcircuit models
Radio frequency equation
Verilog-A compact
defined device (RFEDD)
device models
models

Non-linear equation defined


device (EDD) models
Verilog-A circuit
macromodels

Equation based compact model and circuit macromodel construction


START
Model equations
representing
physical operation
of device / circuit

Add new features


by extending model
equation set

Generate equation
defined models from
physical equations

Modify model

CHANGES
NEEDED

Interactive
testing

Display
results

Further testing to
confirm model
performance

OK

Verilog-A
code
generation

Compile Verilog-A
code to C++ and
link model with main
body of simulator
code

STOP
10

Basic equation-defined device (EDD) modelling features


The Qucs EDD is a multi-terminal non-linear component with branch currents that can be
a function of the branch voltages, and stored charge that can be a function of both branch
voltages and currents.
EDD is similar, but more advanced, to the B type controlled source implemented in SPICE 3f5.
EDD is capable of realizing the same models as the SPICE B device plus an extensive range
of more complex compact device models.
EDD is an advanced component, allowing users to construct their own models from a set of
equations derived from physical device properties.
EDDmodelscanbecombinedwithconventionalcircuitcomponentstoformcompactdevice
subcircuitmodels.
AnEDDisanonlinearcomponentwithuptoeighttwoterminalbranches.
EachbranchischaracterizedbycurrentI ,voltageV andchargeQ ,where1<=n<=8.
n
n
n

EDDtwoterminalbranchcomponentsarecharacterizedbytheexpressionsgiveninthefollowing
equations: I = I V and g =dI / dV; Q=Q V , I
and c=dQ /dV =dQ V / dV dQ I / dV =dQ V /dV dQ I / dIg

where g is the branch conductance and c the branch capacitance.

EDD branch capacitance is extracted from branch charge, allowing implementation of


differentiation rather than numeric or symbolic integration that is needed to derive branch
charge from non-linear branch capacitance.
Similarly, branch conductance is determined by Qucs from the derivative of branch current.
EDD equations may include constants, branch variables, variables from Qucs equation blocks
subcircuit parameters, the operators and functions defined in verilog-A.
Variables, constants and equations may be entered in any order in Qucs equation blocks.
Conditional branch current and charge equations can be selected by if-then-else statements
with a C-like ternary syntax (?:). Nested if-then-else statements are also allowed.

11

Equation-defined device model for a semiconductor diode :


Part 1 DC characteristics
I d = f V d
I d = I s exp qV d /nkT 1 V dGMIN
5nkT
for
V d 0
q
I d =I s V dGMIN for BV V d

5nkT
q

I d =BV for V d =BV

I d =I s exp qV d / nkT 1qBV / kT


for V d BV
EDD diode current Id is the sum of branch currents I1 to I4,
where I1 represents the forward bias region, I2 the reverse
bias region and I3 plus I4 the reverse breakdown region.
12

Equation-defined device model for a semiconductor diode :


Part 2 capacitance

The next stage in the development


of the EDD diode model is to add
capacitance effects: depletion layer
and diffusion capacitance for the
reverse and forward bias regions
of operation respectively. Fig. 2
illustrates the diode EDD model
with these added via contributions
to the device charge. The same
syntax to the SPICE diode model
has been employed in the
derivation of the EDD charge
equations. A device area factor
has also been added to the
EDD model presented in Fig. 2.

13

Equation-defined device model for a semiconductor diode :


Part 3 temperature effects

The EDD diode model illustrated in Fig. 3


employs SPICE temperature parameters
Tnom and Temp to determine the
temperature dependencies of the model
parameters. In Fig. 3 only EDD diode
parameters Is, Vj and Cj0 are defined as
functions of temperature. This was done
in this demonstration model because of
space restrictions. Comparison between
the Qucs built-in diode model and the
EDD compact model shows good
agreement in the I-V DC characteristics
over a wide range of temperature.

14

Compact device subcircuits with package parasitic components :


tunnel diode example

Fig. 4 shows a model for a p+ - n+


tunnel diode with series R and L
connection components plus diode
capacitance modelled by a parallel
fixed value capacitor. By adding
conventional components to EDD
models compact device subcircuits
can be easily constructed for testing
and performance evaluation. Fig. 5
illustrates a basic monostable pulse
generator derived from the EDD
tunnel diode compact subcircuit
model.

15

Quantity modelling: a support vehicle for compact device model construction


and circuit macromodelling; Part 1 basic concepts

High quality models are an essential prerequisite for accurate circuit simulation
of established and emerging technologies.
In contrast to hand-coded C, the Verilog-A hardware description language provides a
highly expressive standardized language which embodies features for the automatic
generation of partial derivatives.
Once written, Verilog-A model descriptions are normally compiled to C or C++ code,
and linked to the main code of circuit simulator.
Traditional macromodeling adopts a different approach where a subcircuit is used
to represent model connectivity. The body of the subcircuit being assembled from
predefined components and user defined subcircuits, whose parameters are normally
numerical quantities rather than non-linear algebraic equations.
Macromodeling supports both functional modelling and interactive testing without the
need for code compilation and linking.

The next few slides present a unified modelling approach for constructing of compact
semiconductor device models and circuit macromodels which retains the best features
of interactive subcircuit macromodeling while promoting a straight forward procedure
for the generation of high performance Verilog-A model code. The presented technique
is called QUANTITY modelling.
16

Quantity modelling: a support vehicle for compact device model construction


And circuit macromodelling; Part 2 basic concepts continued

In (a) current Iname is a non-linear function of the voltages applied to the EDD terminals
connected to branches two to eight. NOTE: EDD branches with current set at zero act as
high impedance voltage probes.
In (b) charge Q1 represents the stored charge in branch 1. Changes in Q1 over a period of time
result in a change in the current flowing in branch one.
The listed Verilog-A code fragments clearly identify the strong relationship between the EDD
equation defined quantity block structure and the corresponding Verilog-A code.
The above EDD structures represent the simplest quantity elements. Other combinations
with different numbers of current or charge equations and voltage probes are possible.

17

Quantity modelling: a support vehicle for compact device model construction


And circuit macromodelling; Part 3 basic concepts continued

Equivalence between
Qucs/QucsStudio
standard components
and Verilog-A code
blocks.

18

Quantity modelling: a support vehicle for compact device model construction


and circuit macromodelling; Part 4 basic concepts continued

Qucs/QucsStudio use a
noise voltage generator
of the form given by the
following equation to
generate noise signals:

VPSD f =

U
,
ac f e

Where VPSD(f) is the voltage


spectral noise density at frequency f in
2
V /Hz, U is the voltage spectral density
as f goes to zero Hz, a, c and e are
coefficients that determine the type of
noise generated:

White and shot noise: U=1, e=0,


c=1 and a =0.
Flicker noise: U=Kf, e=Ffe,
c=1 and a =0.

19

Generating Verilog-A code from Qucs/Qucstudio equation-defined quantity


models: Part 1 the three stage process

Although the current and charge EDD blocks shown in the previous slide are presented
as separate items the Qucs/QucsStudio equation-defined quantity modelling technique
naturally proceeds in a top-down fashion rather than the conventional bottom-up design
process.
The following diagram illustrates the three principle stages in the construction of a
Qucs/QucsStudio equation-defined quantity model.

In QUANTITY modelling variables specified by equations


are represented (and calculated) as model currents and converted to
voltages for input into other EDD blocks or controlled sources.

20

Generating Verilog-A code from Qucs/Qucstudio equation-defined quantity


models: Part 2 more details

Starting with a set of equations that characterize the physical properties of a device,
or the functionality of a circuit, a subcircuit schematic symbol is drawn with signal
connection pins and a default parameter list attached.
The next step in the model development sequence involves drawing a second schematic
composed of EDD current and charge equation-defined blocks which represent the body
of a model, including currents, charges, resistance, voltage controlled currents, current to
voltage conversion blocks and noise generators.
Interactive testing of the model follows, allowing a full evaluation of a model function.
On satisfactory completion of the testing phase the Verilog-A code for a Qucs
equation-defined quantity model is generated by inspection of the model symbol and the
body schematic, simultaneously entering the Verilog-A code for each item in the various
sections indicated as comments in the Verilog-A template shown on the previous slide.

21

Generating Verilog-A code from Qucs/Qucstudio equation-defined quantity


Models: A long channel EKV v2.6 compact device model

The list on this slide gives the fundamental


DC and charge equations for a simplified
long channel EPFL-EKV nMOS model,
Where, VP is the pinch-off voltage, n is the slope
factor, BETA is a transconductance parameter,
Ispecific is the specific current, If is the forward
current, Ir is the reverse current and Ids is the
drain to source current.
The parameters for the long channel model are:
VTO the theshold voltage, PHI the bulk Fermi
potential, GAMMA the body effect parameter, W
the channel width, L the channel length, COX the
gate oxide capacitance per unit area and vt is the
thermal voltage at the device temperature.

EPFL-EKV v2.6 equation numbers are


given in { } brackets at the left-hand
side of each equation.

22

Generating Verilog-A code from Qucs/Qucstudio equation-defined quantity


Models: A long channel EKV v2.6 compact device model
Qucs EDD model for a long channel nMOS
transistor

The schematic presented on this slide demonstrates


how device equations are represented by a set of Qucs
EDD structures where each of physical quantity is
calculated as a branch current.
Currents output from an EDD, and passed as input to
other EDD, are converted to voltages by setting
individual input branch currents to be identical in value
to their branch voltage using

I n =V n
Where subscript n is the EDD branch number in the
range 1 to 8.

23

Generating Verilog-A code from Qucs/Qucstudio equation-defined quantity


Models: A long channel EKV v2.6 compact device model

Qucs charge partition model for a long channel


nMOS transistor

The dynamic charge properties of the simplified


EPFL-EKV nMOS transistor model are determined
by device parameter Xpart, which allows users to
set the device charge partition ratio.
The default value of Xpart is 0.4 which gives a
ratio of 40/60 for QD/QS (QI=QS+QD).

24

A long-channel EPFL-EKV nMOS transistor Verilog-A model


// Qucs EPL-EKV 2.6 nMOS long channel model: EKV26nMOSLC.va
// Charge partition Xpart/Spart.
`include "disciplines.vams"
`include "constants.vams"
//
module EKV26nMOSLC (Drain, Gate, Source, Bulk);
inout Drain, Gate, Source, Bulk;
electrical Drain, Gate, Source, Bulk;
`define attr(txt) (*txt*)
// Device dimension parameters
parameter real L = 2e-6 from [0.0 : inf)
`attr(info="length parameter" unit = "m" );
parameter real W = 2e-6 from [0.0 : inf)
`attr(info="Width parameter" unit = "m");
// Basic intrinsic model parameters
parameter real VTO = 0.6 from [1e-6 : 2.0)
`attr(info="long channel threshold voltage" unit="V" );
parameter real GAMMA = 0.71 from [0.0 : 2.0)
`attr(info="body effect parameter" unit="V**(1/2)");
parameter real PHI = 0.97 from [0.3 : 2.0]
`attr(info="bulk Fermi potential" unit="V");
parameter real KP = 150e-6 from [10e-6 : inf)
`attr(info="transconductance parameter" unit = "A/V**2");
parameter real THETA = 50e-3 from [0 : inf)
`attr(info="mobility reduction coefficient" unit = "1/V");
parameter real COX = 3.45e-3 from [1e-20 : inf) `attr(info="gate oxide capacitance per unit area" unit="f/m**2");
parameter real Xpart = 0.4 from [0.0 : 1.0]
`attr(info="intrinsic charge partition factor");
parameter real Kf=1e-27 from [0.0 : inf)
`attr(info="flicker noise coefficient");
parameter real Af=1.0 from [0.0 : inf)
`attr(info="flicker noise exponent");
parameter real Temp = 26.85 from [-150.0 : 200.0] `attr(info="Device temperature" unit ="deg C");
// Local variables
real P1, P2, P3, P4, P5, P6, P7, P8, P9, P21, coxide, Qg, Qb, Spart;
real VGprime, VP, n, Beta, iff1, iff, irr1, irr, nq, xf, xr, qi, qb, qg;
real fourkt,Sthermal,Sflicker,Ispecific,gm;
// Branches
branch (Gate, Bulk) Bgb; branch (Source, Bulk) Bsb; branch (Drain, Bulk) Bdb;
branch (Drain, Source) Bds; branch (Gate, Drain) Bgd; branch (Gate, Source) Bgs;

25

A long-channel EPFL-EKV nMOS transistor


Verilog-A model
analog begin
@(initial_model) begin
P1 = -VTO+PHI+GAMMA*sqrt(PHI); P2 = GAMMA/2; P3 = P2*P2; P4 = GAMMA*P2-PHI;
P5 = PHI+4*$vt+1e-12; P6 = KP*W/L; P7 = 1/(2*$vt); P8 = 2*$vt*$vt; P21 = PHI+1e-6;
coxide = W*L*COX; Spart = 1-Xpart; fourkt = 4.0*`P_K*(Temp+273.15);
end
VGprime = V(Bgb)+P1;
if (VGprime > 0.0) begin VP = P4+VGprime-GAMMA*sqrt(VGprime+P3); end
else begin VP = -PHI; end
n = 1+P2/sqrt(VP+P5); Beta = P6/(1+THETA*VP);
iff1 = ln(1+limexp((VP-V(Bsb))*P7)); iff = iff1*iff1; irr1 = ln(1+limexp((VP-V(Bdb))*P7)); irr = irr1*irr1;
I(Bds) <+ P8*n*Beta*(iff-irr);
// Charge contribution equations
nq = 1.0+GAMMA/(2*sqrt(VP+P21)); xf = sqrt(0.25+iff); xr = sqrt(0.25+irr);
qi = -nq*(1.33333333*(xf*xf+xf*xr+xr*xr)/(xf+xr+1e-20)-1);
if(VGprime>0) begin qb = (-GAMMA*sqrt(VP+P21))/$vt-((nq-1)/nq)*qi; end
else begin qb = -Vgprime/$vt; end
qg = -qi-qb; Qb = coxide*$vt*qb; Qg = coxide*$vt*qg;
I(Bgs) <+ Spart*ddt(Qg); I(Bgd) <+ Xpart*ddt(Qg); I(Bsb) <+ Spart*ddt(Qb); I(Bdb) <+ Xpart*ddt(Qb);
// Noise contribution equations
Sthermal = fourkt*Beta*abs(qi); Ispecific = 2.0*n*Beta*$vt*$vt;
gm = Beta*$vt*(sqrt((4.0*iff/Ispecific)+1.0)-sqrt((4.0*irr/Ispecific)+1.0));
Sflicker = (Kf*gm*gm)/coxide;
I(Bds) <+ white_noise(Sthermal, "thermal"); I(Bds) <+ flicker_noise(Sflicker, Af, "flicker");
end
endmodule

26

Long-channel EPFL-EKV MOS transistor DC characteristics

27

Long-channel EPFL-EKV MOS capacitor characteristic

28

Generating Verilog-A code: Qucs equation defined devices via Verilog-A code fragments
to a Verilog-A standardised template

Equation-defined device
model

Model symbol
pin names

Verilog-A
code
fragments

//Verilog-A model template


`include disciplines.vams
`include constants.vams
module name (P1, P2, P3, ....... Pn);
inout P1, P2, P3, ....Pn;
electrical P1, P2, P3, ..... Pn;
// Definition of local internal nodes
// Parameter values and descriptions
// Definition of internal variables
analog begin
// Initialisation code
// Quantity equations
// Current contributions
// Noise contributions
end
endmodule

1. Compile Verilog-A template code with ADMS


2. Add new model to Qucs by patching C++ code
3. Add new model symbol to Qucs C++ code
4. Compile and link Qucs static C++ code to
generate a new version of Qucs

29

QucsStudio: Compact semiconductor device and circuit macromodel


construction using ADMS and MinGW dynamically linked models
Generate Verilog-A code
with the QucsStudio
colour highlighted text editor

Compact
Compact
Semiconductor
Semiconductor
device or circuit
Device or circuit
physical
macromodels
equations

Pin1

Pout1

Equation-defined
device model
or circuit
macromodel

Symbol

Poutn

:
Pinn

Subcircuit
symbol

Verilog-A
fragments

Poutn

C++

File XXX.va

C++ Compiled
model

Pin1

Pout1

Verilog-A
model
code
[Template
structure]

File XXX.va.cpp

File XXX.dll

MinGW tools

ADMS

Pinn
Subcircuit body

API functions for C++


component creation

Other QucsStudio components may be included in a


subcircuit with one or more compiled C++ models
Turn-Key Verilog-A compact model development system WHERE the Verilog-A
code is automatically recompiled ONLY if it has been changed prior to the start of a simulation

30

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Schematic symbol, default parameter list and equivalent
circuit of an npn bipolar phototransistor
Light bus

The phototransistor model


is constructed from an
Ebers-Moll bipolar junction
transistor model which
has been extended to
include depletion and
diffusion capacitance,
forward and reverse Early
effects, high current
forward and reverse beta
degradation,thermal and
shot noise, plus a light
bus which connects
external light signals
to the phototransistor.

31

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Phototransistor model parameters
Name
BF
BR
Is
Nf
Nr
Var
Vaf
Mje
Vje
Cje
Mjc
Vjc
Cjc
Tr
Tf
Ikf
Ikr
Rc
Re
Rb
Kf
Ffe
Af
Responsivity

Symbol
f
r
Is
Nf
Nr
Var
Vaf
Mje
Vje
Cje
Mjc
Vjc
Cjc
Tr
Tf
Ikf
Ikr
Rc
Re
Rb
Kf
Ffe
Af
Responsivity

Description
Forward beta
Reverse beta
Saturation current
Forward emission coefficient
Reverse emission coefficient
Reverse Early voltage
Forward Early voltage
Base-emitter exponential factor
Base-emitter built-in potential
Base-emitter zero-bias depletion capacitance
Base-collector exponential factor
Base-collector built-in potential
Base-colector zero-bias depletion capacitance
Ideal reverse transit time
Ideal forward transit time
High current corner for forward beta
High current corner for reverse beta
Collector series resistance
Emitter series resistance
Base series resistance
Flicker noise coefficient
Flicker noise frequency exponent
Flicker noise exponent
Responsivity at peak wavelength

Unit

P0

P0

Relative selectivity polynomial coefficient

P1

P1

Relative selectivity polynomial coefficient

%/nm

P2

P2

Relative selectivity polynomial coefficient

P3

P3

Relative selectivity polynomial coefficient

P4

P4

Relative selectivity polynomial coefficient

A
V
V
V
F
V
F
s
s
A
A

A/W

Default
100
0.1
1e-10
1
1
100
100
0.33
0.75
1p
0.33
0.75
1p
100n
0.1n
0.5
0.5
2
1
100
1e-12
1
1
1.5
2.6122x103
-1.4893x101

%/nm2 3.0332x10-2
%/nm3 -2.5708x10-5
%/nm4 7.6923x10-9

32

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Bipolar phototransistor model equations
DC I/V characteristics

[
[

]
]

IEC= Is exp

IEC
V BI , CI
1 IDC 2= r GMINV BI , CI
Nrvt 300

ICC=Is exp

V BI , EI
1
Nfvt 300

CBC=

Capacitance

dQ BI , CI
=
dV BI , CI

=2 MjcCjc
CBE=

q1
1 14q2
2

V BI , CI
Vjc

Mjc

Tr

dIEC
dV BI , CI

V BI , CI

dQ BI , EI
=
dV BI , EI

q1=1

Cjc

Cje

V BI , EI
Vje

Mje

Tr

ICC
GMINV BI , EI
f

V BI , CI V BI , EI

Vaf
Var
ICC IEC
KT
q2=

vt T =
Ikf
Ikr
q

[ ICCIEC ]

2MjcV BI , CI
dIEC
1 Mjc Tr
Vjc
dV BI , CI

=2 MjeCje

Photocurrent

ICT =

IDE 2=

dICC
dV BI , EI

Vjc
2

V BI , CI >=
V BI , EI

Vjc
2

Vje
2

2MjeV BI , EI
Vje
1Mje + Tr dICC
V BI , EI >=
Vje
2
dV BI , EI

Iopt=GpbcPopt

Gpbc =

RelSensitivityRe sponsivity
f 100

RelSensitivity =P0P1P22P33P4 4

Noise

4KT
f
Rc
8KT
iRban 2=
f
Rb
iRcn 2=

4KT
f
Re
8KT
iRbbn2 =
f
Rb
i Ren2=

iICTsn 2=2qICf
2

ibsn =2qIBf

ibfn 2= Kf

IB Af
f
f Ffe

Where K is the Boltzmann constant, T is the temperature in Kelvin, q is the electron charge, GMIN is a small
admittance in parallel with the device junctions, fisthenoisefrequencybandwidthinHzandisthelight
wavelengthinnm.Othersymbolsandnodenamesaredefinedinthepreviousslides.
33

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 1 the basic npn transistor model
Large signal DC model
Generate symbol
Equation defined device

34

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 2 DC simulation tests

35

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 3 Adding capacitance to the phototransistor model
Charge equations
V BI ,CI

Q BI , CI

CBCdV =TrIEC2

[ {
[
[ {

V BI , CI
CjcVjc
= TrIEC
1 1
1Mjc
Vjc

V BI , EI

Q BI , EI

V BI , CI
Cjc Mjc
1Mjc V BI , CI
Vjc

Mjc

CBEdV

=TfICC2

= TfICC

} ]

1 Mjc

V BI , CI <=

V BI , EI
Cje Mje
1Mje V BI , EI
Vje

MjE

V BI , EI
CjeVje
1 1
1Mje
Vje

V BI , CI

} ]
1Mje

Vjc
2

V BI , EI

V BI , EI <=

Vjc
2

Vje
2

Vje
2

EDD blocks

36

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 4 simulating capacitive effects
AC gain

Cbe and Rbe extraction

37

Buildingacompactsemiconductormodelofannpnbipolarphototransistor

Construction: stage 5 Adding photoelectric effects


Si phototransistor relative
Curve fitting program
Measured data
sensitivity data

RelSensitivity =P 0P 1 P22 P 33 P 44
Where P 0=2.6122e3, P 1 =1.4893e1, P2 =3.0332e-2, P 3 =2.5708e-5, P 4 =7.69e-9

EDD light
bus model

38

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 6 simulating photoelectric effects
Phototransistor output
Phototransistor responsivity
characteristics
characteristics

39

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 7 adding noise to the phototransistor model
Qucs noise voltage source
ibsn= 2qIB A/ Hz

VPSD f =

U
acf e

Af

Kf
ibfn=
f Ffe

A/ Hz

Where VPSD(f) is the voltage spectral


density at frequency f in V2 / Hz, U is
the voltage spectral density as f goes
to zero, a, c and e are coefficients that
determine the type of noise generated;
white and shot noise with U=1, e=0,
c=1 and a=0, and flicker noise with
U=Kf, e=Ffe, c=1 and a=0.

iICTsn= 2qIC A/ Hz

Noise parameters

40

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 8 simulating phototransistor noise
Variable light power

Variable wavelength

41

Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 9 producing a distribution standard model

Model
Generate Verilog-A
code

Store in Qucs
library

Use Create Library from Project menu

`include "disciplines.vams"
`include "constants.vams"
module phototransistor (Collector, Base, Emitter, Power, Wavelength);
inout Collector, Base, Emitter, Power, Wavelength;
electrical Collector, Base, Emitter, Power, Wavelength;
// Definition of internal local nodes
electrical CI, BI, BI2, EI;
// Parameter values and description text
`define attr(txt) (*txt*)
parameter real Bf=100 from [1:inf] `attr(info="forward beta");
parameter real Br=0.1 from [1e-6:inf] `attr(info="reverse beta");
:
parameter real P3=-2.5708e-5 from[-inf:inf]
`attr(info="relative selectivity polynomial coefficient" );
parameter real P4=7.6923e-9 from[-inf:inf]
`attr(info="relative selectivity polynomial coefficient" );
// Definition of internal variables and quantities
real VT, con1, con2, con3, con4, con5, con6, con7, con8, con9, con10, TwoQ, FourKT,
GMIN;
real ICC, IEC, q1, q2, IB, IC, IE, Q1, RelSensitivity;
// Quantities
analog begin
// Module initialisation code
@(initial_model)
begin
VT = `P_K*300/`P_Q; con1=1/(Nf*VT); con2=1/(Nr*VT); con3=1-Mje; // VT = vt(300)
con4=1-Mjc, con5=pow(2, Mje); con6=pow(2, Mjc); con7=Rb/2; con8=2/Rb;
con9=1/Rc; con10=1/Re; TwoQ=2*`P_Q; GMIN=1e-12;
// TwoQ = 2*q
FourKT=4*`P_K*$temperature;
// FourKT = 4*K*T
end;
// Model quantity equations and current contributions
ICC=Is*(limexp(V(BI,EI)*con1)-1); IEC=Is*(limexp(V(BI,CI)*con2)-1);
q1=1+V(BI,CI)/Vaf + V(BI,EI)/Var; q2=(ICC/Ikf) + (IEC/Ikr); IB=V(BI2,BI)*con8;
IC=V(Collector,CI)*con9; IE=V(EI,Emitter)*con10; I(Collector,CI) <+ IC;
I(Base,BI2) <+ V(Base, BI2)*con8; I(BI2, BI) <+ IB; I(EI, Emitter) <+ IE;
I(BI,CI) <+ (IEC/Br) + GMIN*V(BI,CI); I(BI,EI) <+ (ICC/Bf) + GMIN*V(BI,EI);
I(CI,EI) <+ (ICC-IEC)/(1e-20+(q1/2)*(1+sqrt(1+4*q2)));
Q1=(V(BI,CI) >Vjc/2) ? Tr*IEC+Cjc*con6*(Mjc*V(BI,CI)*V(BI,CI)/Vjc+con4*V(BI,CI))
: Tr*IEC+Cjc*((Vjc/con4)*(1-pow((1-V(BI,CI)/Vjc),con4)));
I(BI,CI) <+ ddt(Q1);
Q1=(V(BI,EI) >Vje/2) ? Tf*ICC+Cje*con5*(Mje*V(BI,EI)*V(BI,EI)/Vje+con3*V(BI,EI))
: Tf*ICC+Cje*((Vje/con3)*(1-pow((1-V(BI,EI)/Vje),con3)));
I(BI,EI) <+ ddt(Q1);
RelSensitivity = P0+P1*V(Wavelength)+P2*pow(V(Wavelength),2)
+P3*pow(V(Wavelength),3)+P4*pow(V(Wavelength),4);
I(CI,BI2) <+ ( (Responsivity*RelSensitivity)/(Bf*100) )*V(Power);
// Noise contributions
I(Collector,CI) <+ white_noise(FourKT*con9, "thermal");
I(Base,BI2)
<+ white_noise(FourKT*con8, "thermal");
I(BI2,BI)
<+ white_noise(FourKT*con8, "thermal");
I(EI,Emitter)
<+ white_noise(FourKT*con10, "thermal");
I(CI,EI)
<+ white_noise(TwoQ*IC, "shot");
I(BI,EI)
<+ white_noise(TwoQ*IB, "shot");
I(BI,EI)
<+ flicker_noise(Kf*pow(IB, Af), Ffe, "flicker");
end
endmodule

Phototransistor.va
file

42

Template modelling new approaches to equation-defined device modelling:


trends from SPICE to Modellica via Qucs/QucsStudio

Recent trends in compact device modelling suggest that there is a growing interest in

equation-defined device techniques and Verilog-A among the device modelling community
Current releases of the popular GPL Qucs/QucsStudio circuit simulators, the freely available
LinearTechnology LTspiceIV circuit simulator and the open source Modelica Consortium
OpenModelica simulation environment all include equation-defined features for compact
semiconductor device modelling
A primary aim of compact equation-defined device modelling is the generation of efficient
high-level hardware description language models that support a wide range of circuit
simulation domains, including DC, AC, transient, S-parameter, AC and time domain noise,
plus harmonic balance analysis, which can be translated to Verilog-A easily
A second equally important aim is a high level of portability for equation-defined device
models across circuit simulation platforms
Equation-defined device models based on a simple template structure encourage the
development of readable and accurate simulation models
An extension of equation-defined model parameters allows model functionality to be
selected by users, reducing the number of arithmetic computations which in turn
decreases simulation times
Production versions of equation-defined device models are easily translated to Verilog-A
or the Modelica simulation language prior to compiling to C++ and merging with the
control and analysis C++ code sections of a simulator
43

AcompactsemiconductormodeltemplateforQucs/QucsStudio,SPICEandModelica
Template

Qucs

LTspice

Verilog-A

Header

.Def:name nodes param=xx.. .subckt name nodes param = xx..

module name (nodes ..)

Model
Initialisation
Code

Eqn:EqnX param=yy

parameter type name=yy


Analog begin
@(initial_model)

.param = {yy}

Modelica
model name
Interface pin descriptions
parameter type name=yy

end
Functional
body of
Model

EDD
VCVS
CCVS
VCCS
CCCS
C
R
Current contributions
Noise contributions
[Voltage and current
noise generators]
.Def.End

B
H
E
G
C
R

Current contributions

Current contributions
Noise contributions
[Diode noise generators]

Noise contributions

.ends

endmodule

Simulation
Capabilities

DC
.OP
AC
.DC
TRAN
.TRAN
S parameter analysis
.TEMP
Noise (freq and time domains) .TF
HB (single input signal)
.STEP
Parameter sweep
.noise (freq domain)
Digital (VHDL, Verilog)
.FOUR
Optimisation
Digital (mixed-mode)

Compact
Modelling
Tools

1. Interactive subckts
2. ADMS Verilog-A
compiler

Interactive subckts

Equation
R
G
C
Controlled sources
Current contributions
Interface node current
and voltage equations

endname
Transient

Verilog-A to C/C++
compiler

Modelica to C/C++
compiler

NOTE: Mathematical expressions require a full range of operators and functions (similar to Verilog-A)
plus some form of if then else statement [for example, a ? b : c or if(a, b, c) syntax]

44

SpecificationforanextendedSPICEsemiconductordiodemodel
Format

User Selection
switches
[0=off, 1=on]

Physical parameters

Operating region
or
property

BVSWITCH
CdepSWITCH
CdiffSWITCH
AcnoiseSWITCH

IS, N, XTI, EG,AREA


TEMP, TNOM
BV, IBV
CJ0, M, VJ
TT
KF, AF, FFE

Non-linear DC I-V
characteristics
Reverse breakdown
Depletion capacitance
Diffusion capacitance
Small signal AC noise

IrecovSWITCH

TAU

SWSH
SWF

ScaleR
ScaleSH
ScaleF

Reverse recovery
characteristics
Large signal time
domain noise

SPICE

EXTENDED
MODEL

User selection switches allow different levels of model to be


constructed to meet specific circuit and simulation requirements:
other physical effects can be added as needed, for example very
low current or high current I-V effects
45b

QucsequationdefineddeviceequivalentcircuitfortheSPICE
semiconductordiodemodel

Model
Function
Control
Parameters

Shot noise
1/f noise

BVSWITCH
CdepSWITCH
CdiffSWITCH
ACnoiseSWITCH

Noise free
resistor

Q1=Qdep
Q2=Qdiff

Id
Breakdown
Id

Equation EqnX blocks contain variable initialisation equations and constants. Variable
expressions are converted into numerical values before a simulation starts.

46

Typical SPICE diode model properties


4. Flicker and shot noise
[ ACnoiseSWITCH=1]
1. I-V characteristics
[ BVSWITCH=0 ]

2. Reverse
breakdown
[ BVSWITCH = 1 ]

3. Capacitance

[CdepSWITCH=1, CdiffSWITCH=0]

[CdepSWITCH=1, CdiffSWITCH=1]
[CdepSWITCH=0, CdiffSWITCH=1]

47

SPICEequationdefineddeviceequivalentcircuitforthebasic
semiconductordiodemodel
SPICE test code
.subckt ModDiodeSlide8 1 2 BVSWITCH=0 CDEPSWITCH = 0 CDIFFSWITCH = 0 ACSWITCH=0
Vid 2 0 dc 0.6
+
IRECSWITCH=0 AREA=1.0 N=1 XTI=3.0 ISat=1e-14 TEMP=26.85
Vm 2 22 dc 0
+
TNOM=26.85 EG=1.16 BV=100 IBV=1e-30 CJ0=1p VJ=1 M=0.5
Rs 22 3 1
+
TT=1n TAU=100e-9 AF=1 KF=1e-16 RS=0.01
X1 3 0 ModDiode BVSWITCH=1 CDEPSWITCH=0 CDIFFSWITCH=0 AREA=1 N=1 XTI=2.0
*
+ ISat=1e-14 TEMP=26.85 TNOM=26.85 BV=4.5 IBV=1e-3 CJ0=1p VJ=1 M=0.5 TT=1n
.param CJ0T2 = {CJ0*AREA}
.op
.param ISEFF = {ISat*AREA}
.dc Vid -4.95 1 0.01
.param T1 = {TNOM+273.15}
.end
.param T2 = {TEMP+273.15}
.param EGT1 = {EG-7.02e-4*T1*T1/(1108+T1)}
.param EGT2 = {EG-7.02e-4*T2*T2/(1108+T2)}
Variable expressions
.param P7 = 1-M
.param P6 = {CJ0T2*VJ/P7}
.param P11 = {M/(2*VJ)}
.param PK = 1.3806503e-23
Constants
.param PQ = 1.602176472e-19
.param VTT2 = {Pk*T2/PQ}
.param VJT2 = {(T2*VJ/T1)-2*VTT2*(LN(T2/T1)**1.5)-((T2*EGT1/T1)-EGT2)}
.param IST2 = {ISEFF*((T2/T1)**(XTI/N))*EXP((-EGT1/VTT2)*(1-T2/T1))}
.param K2 = {1/(N*VTT2)}
.param K5 = {N*VTT2}
.param IBVEFF = {IBV*AREA}
.param IDBV = {-IST2*(exp(-BV*K2)-1.0)}
.param BVEFF = {if(IBVEFF/(2*IDBV), BV-K5*ln(IBVEFF/IDBV), BV)}
.param GMIN = 1e-12
.param CDEPPARAM = {if(CDEPSWITCH, 1, 0)}
.param CDIFFPARAM = {if(CDIFFSWITCH, 1, 0)}
*
RS 1 n5 {RS}
* Diode I-V characteristics
B1 n5 n1 I = IST2*(exp(V(n5, n1)*K2)-1.0)+GMIN*V(n5, n1)
Vsense n1 2 DC 0
B2 1 2 I = if( {BVSWITCH}, -IST2*(exp( -( BVEFF+V(n5, n1) )*K2)-1.0+BVEFF*K2), 0 )
* Depletion capacitance
Cd 1 2 Q = CDEPPARAM*(if(x+0.501, CJ0T2*(x+P11*x*x), P6*(1-(1-x/VJT2)**P7) ))
* diffusion capacitance
Cdiff 1 2 Q = CDIFFPARAM*TT*(IST2*(exp(V(n5,N1)*K2)-1.0))
* Diode shot and 1/f noise
F1 0 n2 Vsense 1
Vid (V)
Lnoise n2 n3 1000
cnoise n3 n4 1000
If..then..else statement
Free versions of SPICE:
Vnoise n4 0 dc 0
f n5 n1 Vnoise {if(ACSWITCH, 1, 0)}
LTspice , ngspice, SPICEOPUS
Dn n3 0 Dnoise
.model Dnoise D(Is=ISat N=N AF=Af KF=KF)
NO
C expressed as charge Q
.ends

Function selection

standardisation of extended
features!

Noise current generated using built-in diode SPICE model

48

Qucsnonlinearmodelofasteprecoverydiode*

Q3 represents Cdep

Q4 and Q5 represent Cdiff

If IrecSWITCH == 1 then CdepSWITCH


and CdiffSWITCH over-riden

Small signal AC shot and 1/f


noise model not included

* EagleWare Application note 22, May 2007

49

Qucstestcircuitforasteprecoverydiode

50

SPICEnonlinearmodelofasteprecoverydiode
*SPICE Interpretive compact semiconductor diode model.
*
Based on modular compact device structure.
*
.subckt ModDiodeSlide10 1 2 BVSWITCH=0 CDEPSWITCH = 0 CDIFFSWITCH = 0
+
IRECSWITCH=0 AREA=1.0 N=1 XTI=3.0 ISat=1e-14 TEMP=26.85
+
TNOM=26.85 EG=1.16 BV=100 IBV=1e-30 CJ0=1p VJ=1 M=0.5
+
TT=1n TAU=100e-9 AF=1 KF=1e-16 RS=0.01
*
.param CJ0T2 = {CJ0*AREA}
RS 1 n5 {RS}
.param ISEFF = {ISat*AREA}
B1 n5 n1 I = IST2*(exp(V(n5, n1)*K2)-1.0)+GMIN*V(n5, n1)
.param T1 = {TEMP+273.15}
Vsense n1 2 DC 0
.param T2 = {TNOM+273.15}
B2 n5 n1 I = if( {BVSWITCH}, -IST2*(exp( -( BVEFF+V(n5, n1) )*K2)-1.0+BVEFF*K2), 0 )
.param EGT1 = {EG-7.02e-4*T1*T1/(1108+T1)}
* Depletion capacitance
.param EGT2 = {EG-7.02e-4*T2*T2/(1108+T2)}
Cd n5 n1 Q = CDEPPARAM*(if(x+0.501, CJ0T2*(x+P11*x*x), P6*(1-(1-x/VJT2)**P7) ))
.param P7 = 1-M
* diffusion capacitance
.param P6 = {CJ0T2*VJ/P7}
Cdiff n5 n1 Q = CDIFFPARAM*TT*(IST2*(exp(V(n5,N1)*K2)-1.0))
.param P11 = {M/(2*VJ)}
CQ3 n5 n1 Q = IrecSWITCH*if(x+0.5 <= 0.5, CJ0*x, 0)
.param PK = 1.3806503e-23
CQ4 n5 n1 Q = IrecSWITCH*if((x+0.5 > 0.5) & (x+0.5 <= FCP+0.5), C1*(x+C2)**2-C3, 0)
.param PQ = 1.602176472e-19
CQ5 n5 n1 Q = IrecSWITCH*if(x+0.5 > FCP+0.5, CF*x-C4, 0)
.param VTT2 = {Pk*T2/PQ}
.ends
.param VJT2 = {(T2*VJ/T1)-2*VTT2*(LN(T2/T1)**1.5)-((T2*EGT1/T1)-EGT2)}
*
.param IST2 = {ISEFF*((T2/T1)**(XTI/N))*EXP((-EGT1/VTT2)*(1-T2/T1))}
Vtran 2 0 dc 0 pulse(0.9 -5 0.2n 0.001n 0.001n 400n 800n)
.param K2 = {1/(N*VTT2)}
Vm 2 3 dc 0
.param K5 = {N*VTT2}
X1 3 0 ModDiodeSlide10 BVSWITCH=0 CDEPSWITCH=1 CDIFFSWITCH=1
.param IBVEFF = {IBV*AREA}
+
IRECSWITCH=1 AREA=1 N=1 XTI=3.0 ISat=1e-14 TEMP=26.85
.param IDBV = {-IST2*(exp(-BV*K2)-1.0)}
+
TNOM=26.85 EG=1.16 BV=4.5 IBV=1e-3 CJ0=1p VJ=1 M=0.5
.param BVEFF = {if(IBVEFF/(2*IDBV), BV-K5*ln(IBVEFF/IDBV), BV)}
+
TT=1e-9 TAU=10e-9 AF=1 KF=1e-16 RS=1
.param GMIN = 1e-12
.op
.param CDEPPARAM = {(1-IrecSWITCH)*if(CDEPSWITCH, 1, 0)}
.tran 0.0001n 5n
.param CDIFFPARAM = {(1-IrecSWITCH)*if(CDIFFSWITCH, 1, 0)}
.end
.param FCP
= {VJ}
.param CF
= {TAU/RS}
.param CM
= {CF-CJ0}
.param C1
= {CF-CJ0/2*FCP}
.param C2
= {(CJ0*FCP)/CM}
.param C3
= {(CJ0*CJ0*FCP)/(2*CM)}
.param C4
= {CM*FCP/2}
*

51

Verilog-A code for an extended diode model


`include "disciplines.vams"
`include "constants.vams"
//
module ModDiodeMOSAK (PA, CA);
inout PA, CA;
electrical PA, AN, CA;
parameter integer BVSWITCH=0 from [0 : 1];
parameter integer CDEPSWITCH=0 from [0 : 1];
parameter integer CDIFFSWITCH=0 from [0 : 1]; parameter integer ACSWITCH=0 from [0 : 1];
parameter integer IRECSWITCH=0 from [0 : 1];
parameter real AREA = 1.0 from [1.0 : inf];
parameter real N = 1.0 from [1.0 : inf];
parameter real XTI = 3.0 from [1.0 : inf];
parameter real ISat = 1e-14 from [1e-30 : inf];
parameter real TEMP = 26.85 from [-100.0 : inf]; parameter real TNOM = 26.85 from [-100 : inf];
parameter real EG = 1.16 from [1 : inf];
parameter real BV = 100 from [0 : inf];
parameter real IBV = 1e-3 from [1e-20 : inf];
parameter real CJ0 = 1e-12 from [1e-30 : inf];
parameter real VJ = 1.0 from [0 : inf];
parameter real M = 0.5 from [1e-2 : inf];
parameter real TT = 1e-9 from [1e-20 inf];
parameter real TAU = 100e-9 from [1e-20 : inf];
parameter real AF = 1 from [0.1 : inf];
parameter real KF = 1e-16 from [1e-30 : inf];
parameter real RS = 0.01 from [1.0e-6 : inf];
real CJ0T2,ISEFF,T1,T2,EGT1, EGT2, P7, P6, P11, PK, PQ, VTT2, VJT2, IST2, K2, K5, IBVEFF, IDBV, BVEFF;
real GMIN, CdepPARAM, CdiffPARAM, FCP, CM, C1, CF, C2, C3, C4, Id;
//
analog begin
// Equation initialization
@(initial_model)
begin
CJ0T2=CJ0*AREA; ISEFF=ISat*AREA; T1=TNOM+273.15; T2=TEMP+273.15; EGT1=EG-7.02e-4*T1*T1/(1108+T1);
EGT2=EG-7.02e-4*T2*T2/(1108+T2); P7=1-M; P11=M/(2*VJ);PK=1.3806503e-23;PQ=1.602176472e-19;
VTT2=PK*T2/PQ; VJT2=(T2*VJ/T1)-2*VTT2*(pow(ln(T2/T1), 1.5))-((T2*EGT1/T1)-EGT2);
IST2=ISEFF*pow(T2/T1, XTI/N)*exp((-EGT1/VTT2)*(1-T2/T1)); K2=1/(N*VTT2); K5=N*VTT2;
IBVEFF=IBV*AREA; P6=CJ0T2*VJT2/P7;
IDBV=-IST2*(limexp(-BV*K2)-1.0);GMIN=1e-12;
if (IBVEFF > IDBV) BVEFF=BV-K5*ln(IBVEFF/IDBV); else BVEFF=BV;
if (IRECSWITCH==1) CdepPARAM=0; else if (CDEPSWITCH==1) CdepPARAM=1; else CdepPARAM=0;
if (IRECSWITCH==1) CdiffPARAM=0; else if (CDIFFSWITCH==1) CdiffPARAM=1; else CdiffPARAM=0;
FCP=VJ; CF=TAU/RS; CM=CF-CJ0; C1=CF-CJ0/2*FCP; C2=(CJ0*FCP)/CM; C3=(CJ0*CJ0*FCP)/(2*CM); C4=CM*FCP/2;
end

52

Verilog-A code for an extended diode model


RS

Diode I and
dQ/dt terms

Diode step
recovery I

Diode small
signal I noise

// Contributions
I(PA,AN) <+ V(PA,AN)/RS;
Id = IST2*(limexp(V(AN,CA)*K2)-1.0)+GMIN*V(AN,CA);
I(AN,CA) <+ Id;
if (CdepPARAM == 1)
if (V(AN,CA) >= 0.0) I(AN,CA) <+ ddt(CJ0T2*(V(AN,CA)+P11*V(AN,CA)*V(AN,CA)));
else I(AN,CA) <+ ddt(P6*(1-pow(1-V(AN,CA)/VJT2, P7)));
else I(AN,CA) <+ 0.0;
if ( BVSWITCH == 1)
if (V(AN,CA) < -BV) I(AN,CA) <+ -IST2*(limexp(-(BVEFF+V(AN,CA))*K2-1+BVEFF*K2));
else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if (CdiffPARAM == 1) I(AN,CA) <+ ddt(TT*Id); else I(AN,CA) <+ 0.0;
if ( BVSWITCH == 1)
if (V(AN,CA) == -BV) I(CA,AN) <+ IBV; else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if (IRECSWITCH == 1)
if (V(AN,CA) <=0.0) I(AN,CA) <+ ddt(CJ0*V(AN,CA)); else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if (IRECSWITCH == 1)
if ((V(AN,CA) > 0.0) && (V(AN,CA) < FCP)) I(AN,CA) <+ ddt(C1*pow(V(AN,CA)+C2, 2)-C3);
else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if ( IRECSWITCH == 1)
if (V(AN,CA) >= FCP) I(AN,CA) <+ ddt(CF*V(AN,CA)-C4);
else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if (ACSWITCH == 1) begin
I(PA,AN) <+ white_noise((4*PK)/RS,"thermal");
I(AN,CA) <+ white_noise(2*PQ*Id, "shot");
I(AN,CA) <+ flicker_noise(KF*pow(Id,AF), 1, "flicker");
end
end
Endmodule

53

Modelica code for a basic diode model


model ModDiode
Modelica.Electrical.Analog.Interfaces.NegativePin Cathode; Modelica.Electrical.Analog.Interfaces.PositivePin Anode;
parameter Integer CdepSWITCH = 0; parameter Integer CdiffSWITCH = 0; parameter Integer AREA = 1;
parameter Real N = 1.0; parameter Real XTI = 3.0; parameter Real ISat = 1e-14;
parameter Real TEMP = 26.85; parameter Real TNOM = 26.85; parameter Real EG = 1.16; parameter Real BV = 100;
parameter Real IBV = 0.001; parameter Real CJ0 = 1e-12; parameter Real VJ = 1.0; parameter Real M = 0.5;
parameter Real TT = 1e-12; parameter Real CJ0EFF = CJ0 * AREA; parameter Real T1 = TNOM + 273.15;
parameter Real T2 = TEMP + 273.15; constant Real PQ = 1.602176462e-19; constant Real PK = 1.3806503e-23;
constant Real A = 0.000702; constant Real B = 1108.0;
constant Real MAXEXP = 80.0 "Maximum argument in exp function before linearisation - same function as limexp in Verilog-A";
constant Real GMIN = 1e-12;
parameter Real CJ0EFF = CJ0 * AREA;
parameter Real CJ0EFFT2 = CJ0EFF * (1 + M * 0.0004 * (T2 T1)); parameter Real T1 = TNOM + 273.15;
parameter Real T2 = TEMP + 273.15; parameter Real VtT2 = (PK * T2) / PQ;
parameter Real EGT1 = EG - (A * T1 * T1) / (B + T1); parameter Real EGT2 = EG - (A * T2 * T2) / (B + T2);
parameter Real IST2 = ISat * AREA * (T2 / T1) ^ (XTI / N) * exp((-EGT1 / VtT2) * (1 - T2 / T1));
parameter Real K2 = 1.0 / (N * VtT2); parameter Real K3 = IST2 * K2;
Real v,i,gd,Cdep,Cdiff,CT,i1,i2,i3;
equation
v = Anode.v Cathode.v; 0 = Anode.i + Cathode.i;i = Anode.i;
i1 = if v / VtT2 > MAXEXP then IST2 * (exp(MAXEXP) * (1.0 + v / VtT2 - MAXEXP) - 1.0) + GMIN*v else IST2*(exp(K2 v) - 1.0) + GMIN*v;
gd = if v / VtT2 < MAXEXP then K3 * exp(K2 * v) + GMIN else K3 * exp(MAXEXP) + GMIN;
Cdep = if CdepSWITCH == 1 then if v > 0.0 then CJ0EFF * (1 + (M * v) / VJ) else CJ0EFF * (1 - v / VJ) ^ (-M) else 1e-20;
Cdiff = if CdiffSWITCH == 1 then if v >= 0.0 then TT * gd else 1e-20 else 1e-20; CT = Cdep + Cdiff;
i2 = Cdep * der(v); i3 = Cdiff * der(v); i = i1 + i2 + i3;
end ModDiode;

Device parameters

Model initialisation code

Equivalent to limexp

Model
equations

54

QucsStudio: RF Curtice MESFET compact model


Part 1: Verilog-A code
// Verilog-A Curtice MESFET: hyperbolic tangent model
// with fixed capacitance and noise ; Curtice.va.
// This is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// Copyright (C), Mike Brinson, mbrin72043@yahoo.co.uk
//
QucsStudio version September 2011.
//
`include "disciplines.vams"
`include "constants.vams"
//
module Curtice(Drain, Gate, Source);
inout Drain, Gate, Source;
electrical Drain, Gate, Source;
//
`define attr(txt) (*txt*)
`define CTOK 273.15
`define K1 7.02e-4
`define K2 1108.0
`define K3 400e-6
`define GMIN 1e-12
//
parameter real Area = 1 from (1 : inf)
`attr(info="area factor" );
parameter real Vto = -1.8 from (-inf : inf) `attr(info="pinch-off voltage" unit = "V");
parameter real Beta = 3e-3 from [1e-9 : inf) `attr(info="transconductance parameter" unit = "A/(V*V)");
parameter real Alpha = 2.25 from [1e-9 : inf) `attr(info="saturation voltage parameter" unit="1/V" );
parameter real Lambda = 0.05 from [1e-9 :inf) `attr(info="channel length modulation parameter" unit="1/V");
parameter real Vtotc = 0 from (-inf : inf) `attr(info="Vto temperature coefficient");
parameter real Betatc = 0 from (-inf : inf) `attr(info="Beta temperature coefficient" unit = "%/Celsius");
parameter real Alphatc = 0 from (-inf : inf] `attr(info="Alpha temperature coefficient" unit = "%/Celsius");
parameter real Eg = 1.11 from [1e-6 : inf) `attr(info="energy gap" unit = "eV");
parameter real Tau = 1e-9 from [1e-20 : inf) `attr(info="transit time under gate" unit = "s");
parameter real Is = 1e-14 from [1e-20 : inf) `attr(info="diode saturation current" unit = "I");
parameter real N = 1 from [1e-9 : inf)
`attr(info="diode emission coefficient");
parameter real Xti = 3.0 from [1e-9 : inf) `attr(info="diode saturation current temperature coefficient");
parameter real Af = 1 from [0 : inf)
`attr(info="flicker noise exponent");
parameter real Kf = 0 from [0 : inf)
`attr(info="flicker noise coefficient");
parameter real Gdsnoi = 1 from [0 : inf)
`attr(info="shot noise coefficient");
parameter real Bv = 1e9 from (-inf : inf) `attr(info="drain-gate junction reverse bias breakdown voltage" unit = "V" );
parameter real R1 = 1e9 from [1e-9 : inf) `attr(info="breakdown slope resistance" unit = "Ohms");
parameter real Nsc = 1 from [1e-9 : inf)
`attr(info="subthreshold conductance parameter");
parameter real Temp = 26.85 from [-273 : inf) `attr(info="circuit temperature" unit = "Celsius");
parameter real Tnom = 26.85 from [-273 : inf) `attr(info="parameter measurement temperature" unit = "Celsius");

54

QucsStudio: RF Curtice MESFET compact model


Part 1: Verilog-A code continued
real T1, T2, Vt_T2, Vto_T2, Rg_T2, Rd_T2, Rs_T2, Vf, Ah, Beta_T2, Ids;
real Tr, con1, Eg_T1, Eg_T2, Qds;
real Cgs_T2,Cgd_T2, Vbi_T2;
real Igs1, Igs2, Is_T2;
real con2, con3, VfDC; real fourkt, gm, An, thermal_pwr, flicker_pwr, Alpha_T2;
// Model branches
branch (Drain, Source) bDS; branch (Gate, Source) bGS; branch (Gate, Drain) bGD;
//
analog begin
T1=Tnom+`CTOK; T2 = $temperature; Tr=T2/T1;
Vt_T2 = $vt;
Eg_T1=Eg-`K1*T1*T1/(`K2+T1); Vto_T2=Vto+Vtotc*(T2-T1);
Beta_T2=Area*Beta*pow(1.01, Betatc*(T2-T1));
Is_T2=Area*Is*pow( Tr, (Xti/N))*limexp(-(`P_Q*Eg_T1)*(1-Tr)/(`P_K*T2));
con2 = -5.0*N*Vt_T2;
con3 = 1.0/(N*Vt_T2); fourkt=Area*4.0*`P_K*T2;
Alpha_T2=Alpha*( pow( 1.01, Alphatc*(T2-T1)));
// Drain to source current with subthreshold modification
VfDC = V(bGS)-Vto_T2; Ah = 1/(2*Vt_T2*Nsc); Vf = ln(1+exp(Ah*VfDC))/Ah;
Ids = Beta_T2*Vf*Vf*(1+Lambda*V(bDS))*tanh(Alpha*V(bDS));
// Charge equations
Qds = Tau*Ids;
// Diode DC equations
Igs1 = (V(bGS) > con2) ? Is_T2*( limexp(V(bGS)*con3) -1.0) : -Is_T2;
Igs2 = (V(bGS) < -Bv) ? (V(bGS)+Bv)/R1 : 0.0;
// Current contributions
I(bGS) <+ Igs1+Igs2+`GMIN*V(bGS); I(bDS) <+ Ids; I(bDS) <+ ddt(Qds);
// Model noise equations
gm = 2*Ids/VfDC;
if ( V(bDS) < 3/Alpha )
begin
An=1-V(bDS)/VfDC;
thermal_pwr= (8*`P_K*T2*gm/3)*((1+An+An*An)/(1+An))*Gdsnoi;
end
else
thermal_pwr=(8*`P_K*T2*gm/3)*Gdsnoi;
I(bDS) <+ white_noise(thermal_pwr, "thermal"); flicker_pwr = Kf*pow(Ids,Af);
I(bDS) <+ flicker_noise(flicker_pwr,1.0, "flicker");
end
endmodule

55

QucsStudio: RF Curtice MESFET compact model


Part 2: Model Schematic

MESFET Symbol
and parameters
MESFET subcircuit body

56

QucsStudio: RF Curtice MESFET compact model


Part 3: Test simulations

DC

AC

57

QucsStudio: Octave post-simulation data processing

Harmonic Balance

Post-simulation
data processing
control file

FFT

Octave plot of
Vout amplitude
spectra against
frequency

Includes User defined functions

58

Summary
1. Qucs and QucsStudio are freely available circuit simulators distributed as open
source software under the GNU General Public Licence (GPL).
2. This presentation has attempted to outline the history and the fundamental features
of the packages, the available equation-defined components, built in modelling
aids, analysis types and post-simulation data analysis and visualisation capabilities.
3. The presentation also introduced a number of basic approaches to circuit simulation
with Qucs and QucsStudio.
4. A series of slides also showed how the compact semiconductor modelling and circuit
macromodeling features implemented in the current QucsStudio release can be
used to develop equation-defined component models of established and emerging
technology devices.
5. A turn-key approach to compact device modelling using the Verilog-A hardware
description language was introduced and the proposed modelling system
demonstrated via the development of a MESFET RF device simulation model.

Qucs and QucsStudio are freely available under the open source General Public Licence
Download from:
Qucs version 0.0.16
http://qucs.sourceforge.net
QucsStudio version 1.3.2 http://mydarc.de/DD6UM/QucsStudio/qucsstudio.html
QucsStudio-1.3.2_light.zip {without Octave and model compiler}]

59

References
Brinson M. and Jahn S., Interactive compact device modelling using Qucs equation defined devices,
International Journal of Numerical Modelling: Electrical Networks, Devices and Fields, 21(5) pp. 335-349,
September/October 2008. DOI : 10.1002/jnm.676.
Brinson M. and Jahn S., Qucs: A GPL software package for circuit simulation, compact device modelling and
circuit macromodelling from DC to RF and Beyond, International Journal of Numerical Modelling: Electrical
Networks, Devices and Fields, 22(4) pp. 297-319, July/August 2009. DOI : 10.1002/jnm.702.
Brinson M. and Jahn S., Compact macromodelling of operational amplifiers with equation defined devices,
International Journal of Electronics, 96(2), pp. 109-122, February 2009, DOI:10.1080/00207210802580288, ISSN :
0020-7217.
Brinson M. and Jahn S., Modelling of high-frequency inductance with Qucs non-linear radio frequency
equation-defined devices, International Journal of Electronics, 96(3), March 2009,
DOI:10.1080/00207210802640603, ISSN : 0020-7217.
Brinson M.E., Jahn S. and Nabijou H., Z Domain delay subcircuits and compact Verilog-A macromodels for
mixed-mode sampled data circuit simulation, Test Technology Technical Council (TTTC) of the IEEE Computer
Society, Radioelectronics & Informatics Journal, Vol. 45, No. 2, pp. 14-20, April/June 2009. ISSN 1563-0064.
Brinson M.E. and Nabijou H., Adaptive subcircuits and compact Verilog-A macromodels as integrated design
and analysis blocks in Qucs circuit simulation,International Journal of Electronics, Vol. 98 (5), pp. 631-645, May
2011. DOI: 10.1080/00207217.2011.562452.
Brinson M.E., Jahn S. and Nabijou H., A tabular source approach to modelling and simulating device and circuit
noise in the time domain, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol
26(6), pp. 555-567, November/December 2011. DOI: 10.1002/jnm801.
Brinson M. and Jahn S., Compact device modelling for established and emerging technologies with the Qucs
GPL circuit simulator, Mixed design of Integrated Circuits and Systems (MIXDES) 2009, Proceedings of
the 16 International Conference, pp. 39-44, Lodz, Poland, June 2009. ISBN 978-1-4244-4798-5. INSPEC
Accession Number: 10928855. Available from: http://ieeexplore.org .

60

References
Brinson M.E., Jahn S. and Nabijou H., A hybrid Verilog-A and equation-defined subcircuit approach to MOS
switched current analog cell modeling and simulation in the transient and large signal AC domains, Mixed
design of Integrated Circuits and Systems (MIXDES) 2010, Proceedings of the 17 International Conference, pp.
3-48, Wroclaw, Poland, June 2010.ISBN 978-1-4244-7011-2, INSPEC Accession Number: 11487844. Available
from:http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5551306
Brinson M.E., Jahn S. and Nabijou H., Adaptive EPFL-EKV long and short channel MOS device models for
Qucs, SPICE and Modelica circuit simulation, Mixed design of Integrated Circuits and Systems (MIXDES)
2011, Proceedings of the 18 International Conference, pp. 65-70, Gliwice, Poland, June 2011. ISBN 978-1-45770304-1. INSPEC Accession Number: 12219696. Available fro
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6016035
Jahn S., Brinson M.E., Margraf M., Parruitte H., Ardouin B., Nenzi P., and Lemaitre L., GNU simulators
supporting Verilog-A compact model standardization, MOS-AK International Meeting, Premstaetten,
Germany, March 2007. Available from:
http://www.mos-ak.org/premstaetten/papers/MOS-AK_QUCS_ngspice_ADMS.pdf
Brinson M. and Jahn S., Building device models and circuit macromodels with the Qucs GPL simulator : A
demonstration, Presentation to the European Network on Compact Modelling (COMON), Frankfurt(O), Germany,
2 April 2009. Available from:
http://www.mos-ak.org/frankfurt_o/papers/M_Brinson_Qucs_COMON_April_2_2009_final.pdf
Brinson M., Jahn S. and Cullinan M., Advances in compact semiconductor device modelling and circuit
macromodelling with the Qucs GPL circuit simulator, MOS-AK International Meeting, Frankfurt(O), Germany,
3 April 2009. Available from:
http://www.mos-ak.org/frankfurt_o/papers/P_7_Brinson_MOS-AK_April_2009_final.pdf
Brinson M.E., Jahn S. and Nabijou H., Qucs, SPICE and Modelica equation-defined modelling techniques for
the construction of compact device models based on a common model template structure, MOS-AK/GSA
International workshop on the frontiers of compact modeling for advanced analog/RF applications, Universit
Pierre et Marie Curie, Paris, April 2011. Available from:
http://www.mos-ak.org/paris/papers/P06_Brinson_MOS-AK_Paris.pdf

61

References

Brinson M.E.and Nabijou H., Adaptive EPFL-EKV long and short channel MOS device models for Qucs,
SPICE and Modelica circuit simulation, Mixed design of Integrated Circuits and Systems (MIXDES) 2011,
Proceedings of the 18 International Conference, pp. 65-70, Gliwice, Poland, June 2011.ISBN 978-1-4577-0804-1,
INSPEC Accession Number: 12219696. Available from http://ieeexplore.org.
Brinson M.E.and Margraf M., Verilog-A compact semiconductor device modelling and circuit
macromodelling with the QucsStudio-ADMS Turn-Key modelling system , Mixed design of Integrated
Circuits and Systems (MIXDES) 2012, Proceedings of the 19 International Conference, pp. 65-70, Warsaw,
Poland, May 2011.ISBN 978-83-62954-43-8, INSPEC Accession Number: 12219696. Available from
http://ieeexplore.org
Brinson M.E. From Qucs to QucsStudio: An international project to develop a freely available GU Public
Licence circuit simulator with compact device modelling tools, data processing capabilities,
manufacturing features and an analogue/RF design environment for engineers, MOS-AK/GSA International
workshop on Device modeling for Microsystems, Jaypee Institute of Information Technology, Nodia, March 2012.
Available from: http://www.mos-ak.org/india/presentations/Brinson_MOS-AK_India12.pdf .
Brinson M.E., Jahn S. and Nabijou H., A hybrid Verilog-A and equation-defined subcircuit approach to MOS
switched current analog cell simulation, IETE Journal of research, Vol 58(3), pp. 177=185, May-June 2012.

NEW BOOK: Open Source/GNU CAD for Compact Modelling, Editors: Wladek Grabinski and Daniel
Tomaszewski. Publisher: Mark de Jongh [Mark.de.Jongh@springer.sbm.com], www.springer-sbm.com.
Chapter 5: M.E. Brinson, Schematic entry and circuit simulation with Qucs.
Chapter 6: M.E. Brinson, Qucs modelling and simulation of analogue/RF devices and circuits.

62