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Published in IET Power Electronics
Received on 24th September 2013
Revised on 18th January 2014
Accepted on 19th February 2014
doi: 10.1049/iet-pel.2013.0736

ISSN 1755-4535

Rapid prototyping of power electronics converters

for photovoltaic system application using Xilinx
System Generator
Rajasekar Selvamuthukumaran, Rajesh Gupta
Department of Electrical Engineering, Motilal Nehru National Institute of Technology, Allahabad, Uttar Pradesh 211004,
India
E-mail: rajeshgupta@mnnit.ac.in

Abstract: The aim of this study is to develop a research platform for rapid prototyping of the power electronics converters for
solar photovoltaic (PV) system applications. This study describes the eld-programmable gate array (FPGA)-based hardware-inthe-loop (HIL) simulation of voltage source inverter (VSI) used for PV system power conversion. The PV system and inverter
models are realised in simulation as part of the HIL to test the real-time functionality of the FPGA controller. The generation
of switching control signals for the VSI and its interface with the PV system is developed through the Xilinx System
Generator (XSG) domain. The XSG automatically generates the VHSIC hardware description language (VHDL) code using
hardware description language co-simulation for generation of gating signal for modulation of the VSI. To validate the
proposed approach, the sinusoidal pulse-width modulation using bipolar and unipolar switching schemes and current control
method have been tested for the PV supported VSI. The proposed approach of the rapid prototype model has been designed
and implemented in the laboratory through XSG and MATLAB/SIMULINK interface. Performance comparison between the
software simulation and real-time HIL simulation has been demonstrated.

Introduction

The power electronics converters play a vital role in wide range

of applications such as grid integration of renewable energy
systems, industrial drives, vehicular system, consumer
electronics products etc. [13]. The digital controls are more
attractive solution of implementing algorithm for embedded
system applications. Conventionally, the digital embedded
controllers like microprocessor, microcontroller and digital
signal processors (DSPs) are used to implement the
pulse-width modulation (PWM) algorithms for power
electronics converters. However, these controllers-based
techniques have the disadvantages of limited functionality
and low computational speed for complex PWM circuits.
Digital PWM control with a DSP has the advantages of a
simple circuitry, software control and exibility in adaptation
to various applications. However, for complex controllers the
DSP requires high processing power and system architecture
which is not possible in affordable cost [4, 5].
The Xilinx Inc. has developed programmable logic device
called a eld-programmable gate array (FPGA) [6]. These
FPGA comprises of thousands of logic gates, some of
which are grouped together as a congurable logic block to
simplify the higher-level circuit design. The FPGAs are
designated as the better option for prototyping an
application-specic integrated circuit (ASIC) because of
their congurability and programmability. However, the
implementation of control algorithms in high performance
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FPGA for real-time control applications has been found

difcult and requires specialised training in the hardware
description language (HDL). With increase in the level of
complexity in the controllers, the processing time for
prototype development is time consuming and tiresome
even for skilled researchers or engineers [710].
The photovoltaic (PV) system characteristics are highly
non-linear in nature and real-time testing of the control
algorithms are expensive, time consuming and depends
upon the environmental conditions [11]. It requires either
actual PV system or real-time PV simulator. Using PV
simulators, the control and energy yield performance of the
PV inverters can be tested before actually implementing the
control system for the PV inverter in eld. The simulators
are accurate and exible, thus the performance and
reliability of the system can easily be tested without any
risk [12, 13]. However, the PV simulators are expensive
and require actual converters for testing.
Different platforms like digital signal processing and
control engineering (dSPACE), Opal-RT (real time) etc. are
commercially available for hardware-in-the-loop (HIL)
simulation of power electronics converter applications [14,
15]. These platforms are costlier with limited functionality
in the lower versions. For PV applications these RT
platforms have been used for controller implementation and
uses actual power electronics converters and PV system or
PV simulator [1517]. With the wide usage of FPGA
controllers in power electronics converters control in
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Fig. 1 At constant cell temperature of T = 25C and varying solar radiations

a IV and
b PV characteristics, of TATA BP solar module under varying solar radiation

various applications there is a need of low cost digital

platform used to implement HIL simulation of the FPGA
controller.
The FPGA-based Xilinx System Generator (XSG) HIL
simulation is a low cost, easily available platform for
effective method to design, test and develop new hardware
prototype rapidly without the knowledge of HDL [18, 19].
The XSG automatically generates the VHDL code using
HDL co-simulation rapidly. The FPGA controller designed
in the HIL simulation can readily be used with the actual
system. This enables the researchers/users for rapid
prototyping of the FPGA-based power electronics circuits
using XSG [2023]. Other controllers generally used in
rapid prototyping are based on microcontrollers and DSPs.
However, these controllers are not suitable for the high
performance ASIC controller for power electronics
applications [2426]. The main advantages of the
FPGA-based XSG HIL simulation are (i) it provides a
functional test of the FPGA as controller before connecting
it to the actual system, (ii) sample delay effect of the digital
controller can be tested, (iii) realisation of lags involved in
interface of analogue variables and (iv) reduces the
controller development time owing to HDL co-simulation
tool.
This paper attempts to provide a low cost rapid prototyping
platform using XSG for power electronics converters
supported by solar PV system. The PV system is realised in
the MATLAB/SIMULINK and interfaced to the voltage

source inverter (VSI). An H-bridge DCAC inverter is

considered to convert the DC output of the PV into the AC
using bipolar and unipolar sinusoidal PWM (SPWM). The
XSG HIL simulation creates the automatic VHDL code
which can be used to develop and test various control
algorithms quickly in actual physical systems through
FPGAs. The proposed approach is based on the
step-by-step procedure that combines HDL co-simulation
studies, HIL simulation verication and experimental testing
of power conversion of the PV system using VSC.

VSI for PV system

A PV module comprised of series connected solar cells which

can produce power in the range of 75150 W. To obtain the
required higher power output the modules can be connected
in series and parallel to form a PV string. The detailed
modelling, characteristics and nomenclature of the PV
system is described in [27]. Fig. 1 shows the IV and PV
characteristics of the TATA BP (TBP 1275) solar PV
module, at constant cell temperature of T = 25C and
varying solar radiations. Fig. 2 shows the IV and PV
characteristics of the TATA BP (TBP 1275) solar PV
module, at constant solar radiation of G = 1000 W/m2, and
varying cell temperature. The characteristics clearly show
that the PV module current has solar radiation dependency,

Fig. 2 At constant solar radiation of G = 1000 W/m2, and varying cell temperature
a IV characteristics and
b PV characteristics of TATA BP solar module under varying cell temperature
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3

Fig. 3 PV supported single phase H-bridge inverter

whereas the PV module voltage has cell temperature

dependency.
Solar energy available from the PV module requires
efcient and quality conversion techniques to make them
utilisable to the end users. The power available from the PV
module is DC in nature and in many applications AC power
is required. Power electronics inverter is employed to
convert available DC power from the PV module into
useful AC power. Fig. 3 shows the PV supported H-bridge
inverter topology. It consist of four switching device, S1
and S2 on leg A and, S3 and S4 on leg B. The capacitor Cpv
is connected across the PV module and the inverter, and it
supplies constant voltage to the inverter. Load is connected
across the terminals A and B, which produces two-level or
three-level output voltages according to the switching
pattern generated. The H-bridge inverter is modeled in the
MATLAB/SIMULINK and the modulating signal for the
inverter is generated in real-time through FPGA using XSG
discussed in the next section.

Generation of PWM signal in XSG

The common SPWM techniques such as unipolar and bipolar

switching schemes are implemented through FPGA using
XSG HIL simulation toolset. The digitalised signals, that is,
modulating sine wave signal and triangular carrier signal are
generated in MATLAB through XSG interface. After
generation of digitalised signal, HIL simulation testing is
carried out by connecting Xilinx Spartan 3E FPGA kit to
verify the generation of the PWM signal. Once the model
working behaviour is veried through the simulations, then the
VHDL code can be generated automatically using XSG token
compilation. This VHDL code is synthesised in integrated
software environment (ISE) simulator and test bench
waveform is generated for all the PWM techniques. The
resulting coding is then downloaded in the Spartan-3E FPGA
kit through JTAG programming [18]. The pulses at the output
ports are isolated and amplied at the gating power levels and
fed to the respective insulated gate bipolar transistors (IGBTs).
3.1

Triangular carrier wave generation

The digitised triangular waveform is generated at the

frequency of 2 kHz as shown in Fig. 4. The following steps
are used in MATLAB/XSG to generate the digitised
triangular signal:
1. Up counter block set in XSG is used to digitally
increments the count limit value from 0 to 8192. The
resultant waveform obtained from these up counters
resembles the ramp signal varying from 0 to 8192 as shown
Fig. 4(a). The counter count limit is obtained by using the
following formula
Counter count limit = Actual time period required/explicit
period, that is, 5 e4/6 e8 = 8333. Number of bit
required = 213 = 8192, which is the nearest count limit of the
above calculated value.

Fig. 4 XSG realisation of sine and triangle waveforms

a Digitised triangular waveform generated at the frequency of 2 kHz
b Digitised sine waveform generated at the frequency of 50 Hz
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Fig. 5 SPWM signal generation

2. The signal obtained from the Xilinx up counter block is

passed through the bit slicer extractor. The extractor block
is used to slice-off the sequence of bits from the input data
and creates a new data value. The output data type used is
unsigned with its binary point at zero. From Fig. 4(i), we
can see that the bit slice extractor has sliced off the upper
bit location, that is, 213 = 8192. After slice off it become
212 = 4096.
3. Logical operator Xilinx NOT block is used to compliment
the signal available from the Xilinx block bit slice extractor.
This makes the up/down counter block to generate the
digitised triangular waveform.
4. Xilinx up/down counter block is used to perform the
counter increment when input port value is 1 and the
decrement operation starts when the input port value is 0,
that is, down counter. The counter digitally increases the
counter value from 4096 to 4096 and then subsequently
decreases it back to the value 4096 to 4096 again over the
range of time.
5. Xilinx reinterpret block does not consume any hardware
resource in the FPGA, it changes the signal type from
signed to unsigned without relocating the binary point.
3.2

3.3

SPWM signal generation

The SPWM is generated by comparing the 50 Hz digitised

reference sine wave modulating signal with the 2 kHz
digitised triangular carrier waveform. Xilinx relational block
is used to perform the operation of comparator, which
compares the signals and generates gating signal. Fig. 5
shows the SPWM signal generation. The different
modulation index is achieved by changing the gain value in
the sine wave generator.
3.4

Automatic code generation and HIL simulation

The XSG is a high performance design tool used for

modelling, simulating and analysing dynamic systems for
rapid hardware prototyping, which runs as a part of
SIMULINK in MATLAB. These simulations can be used
as a co-simulation tool for software blocks and also
hardware block for Xilinx FPGA, because XSG block in

Reference sine wave generation

The digitised reference sine waveform is generated at the

frequency of 50 Hz in the MATLAB/XSG domain as
shown in Fig. 4(b), following the steps listed below:
1. Xilinx up counter block digitally increments the count
limit value from 0 to 332 and the number of bits required is
29 = 512, where the counter count limit is calculated similar
to calculated in triangular wave generation.
2. ROM block is a read only memory block used in the XSG.
The block has one input port for memory address and one
output port for data output. The address port should be an
unsigned xed point integer. The initial vector value of the
ROM block is dened as sin(2 pi f ), where f varies
from 0 to 332.
3. The amplitude of the sine wave is varied using the gain
block by taking gain equal to desired modulation index Mi.
In this example, Mi = 0.66 is considered. Hence the output
of the digitised sine waveform amplitude is 0.66 V as
shown in Fig. 4(ii).
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Fig. 6 Schematic view of the automatic code generation in XSG

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Fig. 7 Schematic view of the HDL co-simulation and HIL circuit

the Simulink is automatically lled with an S-function

(corresponding component in the functional prototype).
Fig. 6 shows the schematic view of the automatic code
generation. After carefully testing and ne turning the
system, the automatic code is generated in between the
gate-in and gate-out block [28].
Where gate-in block is used at the input of the XSG to
convert oating-point into the xed-point format and
gate-out block is used to convert xed point format into the
oating point format which is required by the Simulink
data. When the simulation is carried out in the Simulink
environment with XSG block set, it will generate the HDL
code and automatically invokes the ISE Foundation
software to generate the bit stream, which is called HDL
co-simulation. Further, while the simulation is carried out
by connecting the hardware run-time model, that is, Spartan
3e FPGA kit, to design and perform the simulation, it is
called as HIL verication. Fig. 7 shows the view of the
HDL co-simulation and HIL circuit.

Result and discussion

The MATLAB/SIMULINK software with add-on of XSG

facilities is used for the HDL co-simulation and HIL
verication studies [29]. In this section, different PWM
signals are generated in the HIL verication mode for
different PV supported power inverter topologies;

(i) H-bridge inverter using bipolar PWM and, (ii) H-bridge

inverter using unipolar PWM, for carrier frequency fc = 3
kHz and modulation index Mi = 0.9.

4.1 FPGA-based HIL simulation for PV supported

H-bridge inverter using bipolar SPWM
This section discusses about the HIL simulation of PV
supported H-bridge inverter using bipolar PWM, and the
simulation and experimental results are compared. Fig. 8
shows the snap shot of the FPGA-based HIL verication of
the bipolar PWM for PV supported H-bridge inverter.
Fig. 9 shows the PV module current and power under
dynamic change in solar radiation level. During the period
t = 00.1 s, the radiation level is G = 500 W/m2. The
corresponding PV current and power is 2.2 A and 55 W,
respectively. After sudden change in radiation to G =
1000 W/m2, from t = 0.1 to 0.2 s, the PV current and power
are increased to 3.6 A and 125 W, respectively. From this
gure, the signicance of the HIL simulation is realised
such that the real PV system characteristics are attained in
the proposed approach during environmental changing
conditions.
Referring to Fig. 3, the gating signals are generated by
comparing the triangular carrier signal Vtri with the
modulating reference sine wave Vsin using the following

Fig. 8 FPGA-based HIL verication of bipolar PWM for H-bridge inverter

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Fig. 9 Dynamic change in solar radiation from G = 500 to 1000 W/m2, effect of PV module current and power

Similarly

control logic [30]

If Vsin . Vtri then S1 and S4 are ON,

VAB = +VPV

If Vsin , Vtri then S2 and S3 are ON,

VAB = VPV

The two-level PWM output voltage is obtained using HIL

simulation. Figs. 10a and b show the gating signal
generation using bipolar PWM technique in Xilinx test
bench simulation and experiment, respectively. Fig. 10c
shows the output voltage and current of the inverter,
through HIL simulation and experiment.
To check the harmonic content in the two-level PV
supported H-bridge inverter, frequency spectrum of the
inverter current is shown in Fig. 10d. The results clearly
show that the dominant harmonics are lying centred at the
carrier frequency of 3 kHz both in HIL simulation and in
experimental result. The value of the total harmonic
distortion in the inverter output current is about 13.65%, in
both the results. This shows that the result of FPGA-based
HIL simulation closely matches with the experimental results.
4.2 FPGA-based HIL simulation for PV supported
H-bridge inverter using unipolar SPWM
The FPGA-based HIL simulation for PV supported H-bridge
inverter using unipolar PWM technique is explained in this
section. The unipolar PWM signal is generated by
comparing triangular carrier signal Vtri with the bidirectional
modulating signal (Vsin and Vsin). Referring to Fig. 3, the
gating signals for the PV supported H-bridge inverter is
generated based on the following switching control logic
with three-levels of the output voltage [31]
If Vsin . Vtri then S1 is ON and
If

VAO = +VPV /2

Vsin , Vtri then S2 is ON and VAO = VPV /2

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if Vsin . Vtri then S3 is ON

and

If Vsin , Vtri then S4 is ON and

VBO = +VPV /2
VBO = VPV /2

The terminal O is the hypothetical neutral of the dc-link

voltage. Therefore the output voltage VAB has three-levels
+VPV, 0 and VPV because of unipolar switching pattern.
Figs. 11a and b shows the gating signal generation for the
unipolar PWM technique, Fig. 11c shows the output current
and voltage of the PV supported unipolar PWM-based
H-bridge inverter and Fig. 11d shows the frequency
spectrum of the output current, both for the HIL simulation
and experimental result. It can be noticed from the results
of the frequency spectrum that the dominant harmonics are
shifted towards twice of the effective switching frequency,
that is, at 6 kHz. The value of the total harmonic distortion
is about 4.10%, which is lesser then the bipolar PWM
technique.
4.3 Performance comparison of software
simulation and real-time HIL simulation
In this section, performance comparison of software
simulation and real-time HIL simulation is discussed. The
main advantage of the proposed real-time HIL simulation
over the pure software simulation is the performance
verication of the system in presence of the actual FPGA
controller. Following results will demonstrate the difference
in the performance because of sampling, computation time
and signal conversion delays of the FPGA controller.
Fig. 12a represents the H-bridge inverter output voltage for
the bipolar SPWM both for the software simulation and
real-time HIL simulation. The HIL simulation clearly shows
the delay in generation of PWM pulses. The real-time HIL
simulation incorporates the physical operating condition of
the digital controllers. The frequency harmonic spectrum
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Fig. 10 HIL simulation and experimental result of PV supported H-bridge inverter using bipolar SPWM
a Xilinx test bench waveform of gating signal
b Experimental result of gating signal
c Inverter output voltage and current of HIL simulation and experimental result
d Frequency spectrum of inverter output current through HIL simulation and experimental result

and total harmonic distortions produced by the three-level

inverter output voltage with software simulation and with
real-time simulation is shown in Fig. 12b. The software
simulation shows the characteristics of the ideal SPWM,
however, in real-time simulation the SPWM is ltered
because of sampling effect of the digital processor [32].
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Further the performance comparison has been done for the

current control mode of the VSI supported by the PV at a
xed switching frequency of 3 kHz. The inverter is tracking
a constant current through the load. Fig. 12c shows the
current tracking performance. The current tracking error in
real-time HIL simulation is larger than the software
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Fig. 11 HIL experimental result of PV supported H-bridge inverter using unipolar SPWM
a Xilinx test bench waveform of gating signal
b Experimental result of gating signal
c Inverter output voltage and current of HIL simulation and experimental result
d Frequency spectrum of inverter output current through HIL simulation and experimental result

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Fig. 12 Performance comparison of software simulation and HIL simulation

a Bipolar SPWM output voltage of inverter
b Frequency harmonic spectrum of three-level inverter output voltage using software simulation and HIL simulation
c Current tracking performance and its tracking error using software simulation and HIL simulation

simulation because of the delay effects of the FPGA

controller.

Conclusion

This paper proposes the FPGA-based HIL simulation for

rapid prototyping of the PV supported power electronics
converter circuits. The HIL simulation environment is
proved to be an efcient tool to develop switching control
strategies for the power converters used in the PV system
through automatic HDL code generation by XSG. The
actual characteristics of the PV module and VSI model are
realised in the MATLAB/SIMULINK. The implementation
of the bipolar and unipolar SPWM for VSI to generate the
AC output from the input DC of the solar PV justies the
concept of HIL simulation. The performance comparison of
the software simulation and HIL simulation demonstrated
the delay effect of the FPGA controller in real-time
implementation.

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