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Professionnel Documents
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APPLICATION NOTE
Introduction
Protection Philosophy
Figure 1. Addressing potential EMI problems at the beginning of a design saves both time and money.
power ground
Minimize the PCBs parasitic inductances
Reduce the loop area formed by the PCB traces
Select surface mount TVS devices
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Location
Figure 2. Locating the TVS devices close to the I/O connector ensures that a surge voltage entering the PCB will
be clamped before the pulse can be coupled into adjacent traces.
Figure 3. The length of the trace connecting the TVS device to the I/O connector should be minimized and small
in comparison with the trace between the connector and IC.
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Figure 4. A good PCB layout avoids locating critical signal lines near the edge of the PCB.
Ground Selection
Figure 5. Connecting the TVS devices to either chassis or power ground helps to prevent the noise signal from
being coupled into the protected ICs signal ground.
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Parasitic Inductances
Figure 6. The PCB layout and IC package parasitic inductances create a short duration voltage spike that
increases the clamping voltage of a TVS device.
if L 1 + L 2 + L 3 + 0
V Peak_Positive_Surge + V DD ) V F_D1
V Peak_Negative_Surge + * V F_D2
if L 1,L 2, and L 3 0 0
V Peak_Positive_Surge + V DD ) V F_D1 ) L 1
V Peak_Negative_Surge + * V F_D2 ) L 2
Loop Area
dI Surge
dt
dI Surge
dt
) L3
) L3
dI Surge
dt
dI Surge
dt
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Figure 7. The data and ground traces can form a loop that functions as an unintended antenna and increases the
RF susceptibility and emissions of the PCB.
Package Selection
Figure 8. Surface mount TVS devices have better surge suppression and high frequency characteristics than
leaded packages.
Bibliography
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