ASSIGNMENT 2

a) Using Case Statement

VHDL CODE:
library ieee;
use ieee.std_logic_1164.all;

entity count_beh is
port(clock,reset,dir:in bit;q:out bit_vector(2 downto 0));
end count_beh;

architecture beh_cnt of count_beh is

-- type state is ("000","001","010","011","100","101","110","111");
signal prestate:bit_vector(2 downto 0):=(others=>'0');
signal nextstate:bit_vector(2 downto 0):=(others=>'0');

begin
process (clock)
begin
if clock='1' then
q<=nextstate;
prestate<=nextstate;
end if;
end process;
process(dir,reset,prestate)
begin
if reset='1' then

nextstate<="000";
-- end if;

else
if dir='0' then
case prestate is
when "000" => nextstate<="001";
when "001" => nextstate<="010";
when "010" => nextstate<="011";
when "011" => nextstate<="100";
when "100" => nextstate<="101";
when "101" => nextstate<="000";
when "110" => nextstate<="000";
when "111" => nextstate<="000";
end case;
elsif dir='1' then
case prestate is
when "000" => nextstate<="101";
when "001" => nextstate<="000";
when "010" => nextstate<="001";
when "011" => nextstate<="010";
when "100" => nextstate<="011";
when "101" => nextstate<="100";
when "110" => nextstate<="000";
when "111" => nextstate<="000" ;
end case;

end if;
end if;
end process;

end beh_cnt;
-------------------------------------------------------------------------------------------------------

b) Using Conditional Signal Assignment

VHDL CODE:
library ieee;
use ieee.std_logic_1164.all;

entity count_data is
port(clock,reset,dir:in bit;q:out bit_vector(2 downto 0));
end count_data;

architecture data1_cnt of count_data is

signal prestate:bit_vector(2 downto 0):=(others=>'0');

signal count_state:bit_vector(2 downto 0):=(others=>'0');
signal s0:bit_vector(2 downto 0):=(others=>'0');
signal s1:bit_vector(2 downto 0):="001";
signal s2:bit_vector(2 downto 0):="010";
signal s3:bit_vector(2 downto 0):="011";
signal s4:bit_vector(2 downto 0):="100";
signal s5:bit_vector(2 downto 0):="101";

begin

prestate <= count_state when clock='1' and clock'event;

count_state <= s0 when reset = '1' else
s1 when prestate = "000" and dir = '0' else
s2 when prestate = "001" and dir = '0'else
s3 when prestate = "010" and dir = '0'else
s4 when prestate = "011" and dir = '0' else
s5 when prestate = "100" and dir = '0' else
s0 when prestate = "101" and dir = '0' else
s0 when prestate = "110" and dir = '0' else
s0 when prestate = "111" and dir = '0' else
s5 when prestate = "000" and dir = '1' else
s0 when prestate = "001" and dir = '1' else
s1 when prestate = "010" and dir = '1'else
s2 when prestate = "011" and dir = '1' else
s3 when prestate = "100" and dir = '1'else
s4 when prestate = "101" and dir = '1'else
s0 when prestate = "110" and dir = '1'else
s0 when prestate = "111" and dir = '1';
q <= count_data;

end data1_cnt;

c) Using JK Flip Flop

VHDL CODE:
library ieee;
use ieee.bit_1164.all;

entity and2 is
port(x,y: in bit; z: out bit);
end and2;

architecture and2 of and2 is

begin
z <= x and y;
end and2;

entity and3 is
port(x,y,t: in bit; z: out bit);
end and3;

architecture and3 of and3 is

begin
z <= (x and y) and t;
end and3;

entity or4 is
port(w,v,x,y: in bit; z: out bit);
end or4;

architecture or4 of or4 is

begin
z <= x or y or w or v;
end or4;

entity or3 is
port(v,x,y: in bit; z: out bit);
end or3;

architecture or3 of or3 is

begin
z <= x or y or v;
end or3;

entity nand2 is
port(x,y: in bit; z: out bit);
end nand2;

architecture nand2 of nand2 is

begin
z <= x nand y;
end nand2;

entity JKFF3 is
Port ( CLOCK : in bit;
J : in bit;

K : in bit;
RESET : in bit;
Q,Qbar : inout bit;
CLR:in bit);
end JKFF3;
architecture Behavioral of JKFF3 is

signal input: bit_vector (1 downto 0);

--signal CLR : bit;
begin
input <= J & K;
p: process(CLOCK,RESET) is
begin
if RESET = '1' then
Q <= '0';
Qbar <= '1';
elsif CLR = '0' then
Q <= '0';
Qbar <= '1';
elsif(CLOCK='1' and CLOCK'event) then
if(J='0' and K='0') then
Q <=Q;
Qbar <= not Q;
elsif(J='0' and K='1') then
Q <= '0';
Qbar <= '1';
elsif(J='1' and K='0') then

Q <= '1';
Qbar <= '0';
elsif(J='1' and K='1') then
Q <= NOT Q;
Qbar <= q;
end if;
end if;
end process;
end Behavioral;

entity syn_count6 is
port ( clk,DIR:
reset:

in bit;
in bit;

counter_states : out bit_vector(2 downto 0)

);
end syn_count6;

architecture Behavioral of syn_count6 is

signal A,B,C,DIR_bar,a1,a2,o0,o1,a3,a4,o2,a5,a6,a7 : bit;

signal Abar,Bbar,Cbar:bit:='1';

component and2
port(x,y: in bit;
z: out bit);

end component;
component and3
port(x,y,t: in bit;
z: out bit);
end component;

component or4
port(w,v,x,y: in bit;
z: out bit);
end component;

component or3
port(v,x,y: in bit;
z: out bit);
end component;

component JKFF3
port(CLOCK : in bit;
J : in bit;
K : in bit;
RESET : in bit;
Q,Qbar : inout bit;
CLR: in bit);
end component;

begin

DIR_bar <= not DIR;

--and2_1 : and2 port map (A,DIR_bar,a1);
--and2_2 : and2 port map (Abar,DIR,a2);
--or2_1 : or2 port map (a1,a2,o1);
--and3_1: and3 port map (A,DIR_bar,B,a3);
--and3_2: and3 port map (Abar,DIR,Bbar,a4);
--or2_2 : or2 port map (a3,a3,o2);
--nand2_1 : nand2 port map (B,C,na1);
and3_1: and3 port map (Abar,DIR,Bbar,a1);
and3_2: and3 port map (A,DIR_bar,C,a2);
and3_3: and3 port map (A,DIR_bar,B,a3);
and2_1 : and2 port map (B,C,a4);
or4_1 : or4 port map (a1,a2,a3,a4,o2);

and3_4: and3 port map (Cbar,DIR_bar,A,a5);

and3_5: and3 port map (C,DIR,Abar,a6);
and3_6: and3 port map (Abar,DIR,B,a7);
or4_2 : or4 port map (a5,a6,a7,a4,o1);
or3_1 : or3 port map (A,Bbar,Cbar,o0);

FF1 : JKFF3 port map (clk,o0,o0,reset,A,Abar,'1');

FF2 : JKFF3 port map (clk,o1,o1,reset,B,Bbar,'1');
FF3 : JKFF3 port map (clk,o2,o2,reset,C,Cbar,'1');

counter_states <= C & B & A;

end Behavioral;

Q2
a) Behavioral

b) Conditional Signal Assignment

AREA REPORT

c) JK Flip Flop

POWER REPORT
A) Behavioral

b) Conditional Signal Assignment

c) JK Flip Flop

TIMING REPORT
A) Behavioral

b) Conditional Signal Assignment

c) JK Flip Flop