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A Project Report on

Design of High Speed Operational Amplifier

with different types of compensation techniques

Submitted in Partial Fulfillment for the award of the Degree

MASTER OF TECHNOLOGY

in

Submitted By

(USN:2BV13LDT02)

Under the guidance of

ENGINEERING

B. V. BHOOMARADDI COLLEGE OF

ENGINEERING AND TECHNOLOGY HUBLI-31

2014-2015

B.V.BHOOMARADDI COLLEGE OF

ENGINEERING AND TECHNOLOGY HUBLI-31

CERTIFICATE

This is to certify that the Project report entitled Design of High

Speed Operational Amplifier with different types of compensation

techniques is a bonafide work carried out by Mr. Abhishek C Math

bearing (USN:2BV13LDT02) as a part of VISVESVARAYA TECHNOLOGICAL UNIVERSITYS M.Tech in VLSI Design and Testing at B. V.

Bhoomaraddi College of Engineering and Technology, Vidyanagar, Hubli for

the academic year 2014-2015.

Guide

Head of the Department

Dr.Ashok Shettar

Principal

External Viva

Name of Examiners

1) ..................

2)..................

DECLARATION

I Mr. Abhishek C Math, (USN:2BV13LDT02), student of 4th

semester M.Tech. in VLSI Design and Testing, B.V.Bhoomaraddi College of

Engineering and Technology, Hubli, hereby declare that under the supervision

of my guide Dr. Rajashekar B. Shettar, Department of Electronics and

Communication Engineering, B.V.Bhoomaraddi College of Engineering and

Technology, Hubli, have independently carried out the project entitled Design of High Speed Op Amp with different types of Compensation

Techniques, and submitted it in partial fulfillment for the award of Master

of Technology in VLSI Design and Testing by the Visvesvaraya Technological

University,Belgaum, during the academic year 2014-2015.

Date:

Place:HUBLI

Mr.Abhishek C Math

ABSTRACT

This thesis presents the analysis and design of a high speed CMOS op

amp with different types of compensation techniques which operates at 1.8V

power supply using 130nm CMOS Technology. Here different types of compensation techniques are used for an op amp and compared the results.The

op amp designed is a two stage CMOS op amp. This op amp employs a

Miller capacitor and is compensated with a Nulling resistor,Voltage buffer

and Current buffer to remove the positive zero. The op amp is designed to

exhibit a UGB of 1GHz and the corresponding Phase Margin of 600 with the

CL = 1pF and DC gain of 55dB. The gain transfer function is derived for

each topology and approximate transfer function co-efficient are found that

allows accurate estimation of zeros and poles. This op amp is designed for

high speed application.

ACKNOWLEDGMENTS

completion of our project and its report would be incomplete without mentioning the names of the people who helped us in accomplishing this.

I accord my sincere thanks our principal Dr. Ashok Shettar and VicePrincipal Prof.B.L.Desai for providing healthy environment in the college,

which helped in concentrating on the task. I express a deep sense of gratitude

to our H. O. D. Dr. Uma Mudenagudi for providing the inspiration

required for taking the project to its completion.

I express my deep sense of gratitude and earnest admiration for my guide

Dr. Rajashekar B. Shettar for their inspiring guidance and promising

support they gave during the course of completion.

I sincerely thank to our project coordinator Dr. Saroja Sidmal,for

great support and encouragement

I sincerely thank Smartplay Pvt Technology,Bangalore for offering

the Internship under the guidance of Dr. Ramesh. Karmungi and I also

thank Mr. Rakesh Sawant for the support and encouragement to pursure

my project work.

Last but not the least I like to thank all the staff members, teaching and

non - teaching staff for helping us during the course of the project.

I am deeply indebted to my family for their valuable and unfailing support.

Contents

1 Introduction

1.1 Problem Statement . . . .

1.2 Objective of the Project .

1.3 Methodology . . . . . . .

1.4 Organization of the report

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2 Literature Survey

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Feedback circuit theory . . . . . . . . . . . . . . . . . . . . . .

2.3 Stability of Feedback Systems . . . . . . . . . . . . . . . . . .

2.4 Basic Frequency Compensation Techniques of Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Parallel Compensation . . . . . . . . . . . . . . . . . .

2.4.2 Pole Splitting Single Miller Compensation (SMC) . . .

2.5 Other Multistage Operational Amplifier Compensation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 Nested Miller Compensation (NMC) and the Variants .

2.5.2 Single Miller FeedForward Compensation (SMFFC) . .

2.5.3 Nonstandard NMC Schemes . . . . . . . . . . . . . . .

2.5.4 No Capacitor Feed Forward (NCFF) . . . . . . . . . .

2.5.5 Negative Miller Capacitance Compensation (NMCC) .

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3.1 Origin of Right half Plane Zero . . . . . . . . .

3.2 Different types of Compensation Techniques . .

3.2.1 Nulling resistor . . . . . . . . . . . . . .

3.2.2 Voltage Buffer . . . . . . . . . . . . . . .

3.2.3 Current Buffer . . . . . . . . . . . . . .

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3.3

3.4

Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Miller Capacitance . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Zero nulling resistor . . . . . . . . . . . . . . . . . . .

4.2.2 Current buffer . . . . . . . . . . . . . . . . . . . . . .

4.2.3 Voltage buffer . . . . . . . . . . . . . . . . . . . . . .

5

Layout Design

5.1 What is layout design . . . . . . . . . .

5.2 Variability and Mismatch . . . . . . . .

5.2.1 Random Statistical Fluctuations

5.2.2 Process Biases . . . . . . . . . .

5.2.3 Systematic Variations . . . . . .

5.3 Rules of MOS transistor matching . . .

5.4 Layout Techniques . . . . . . . . . . .

5.5 Multifinger Transistor . . . . . . . . .

5.6 Symmetry . . . . . . . . . . . . . . . .

6.1 Nulling Resistor . . . . . . . .

6.1.1 Summary . . . . . . .

6.2 Voltage Buffer . . . . . . . . .

6.2.1 Summary . . . . . . .

6.3 Current Buffer . . . . . . . . .

6.3.1 Step Response . . . . .

6.3.2 Settling Time . . . . .

6.3.3 Design Parameters . .

6.3.4 Summary . . . . . . .

6.4 Comparision . . . . . . . . . .

6.5 Layout . . . . . . . . . . . . .

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7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.2 Future Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Bibliography

76

APPENDIX A

79

List of Figures

1.1

1.2

1.3

advancement in CMOS process technology [2] and [3]. . . . . .

Trends for transistor open-loop gain with CMOS process technology progression [2] and [3]. . . . . . . . . . . . . . . . . . .

Trends for transistor transition frequency (fT) with CMOS

process technology progression. . . . . . . . . . . . . . . . . .

2.1

2.2

2.3

2

3

4

Basicl negative feedback . . . . . . . . . . . . . . . . . . . .

Amplifier gain and phase versus frequency showing the phase

margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 SMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 SMCNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 NMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 RNMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 MNMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 NGCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 SMFFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 NCFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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20

3.1

3.2

3.3

3.4

3.5

Origin of positive zero . . . . . . . . . .

Nulling resistor . . . . . . . . . . . . . .

Voltage Buffer . . . . . . . . . . . . . . .

Current Buffer . . . . . . . . . . . . . . .

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26

4.1

4.2

Small signal model for nodal analysis of Miller compensation

of a two-stage op-amp. . . . . . . . . . . . . . . . . . . . . . . 30

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4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

5.11

5.12

5.13

5.14

Pole-zero plot for a two-stage op-amp demonstrating pole splitting due to the Miller capacitor . . . . . . . . . . . . . . . . .

Frequency response of the Miller compensation two-stage opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Miller compensated two-stage op-amp . . . . . . . . . . . .

Miller compensated op-amp with zero nulling resistor . . . . .

Small signal model of two stage op-amp with zero nulling resistor

Frequency response of the Miller compensated two-stage opamp with zero nulling resistor . . . . . . . . . . . . . . . . . .

A two-stage op-amp with a common-gate stage to feedback

the compensation current . . . . . . . . . . . . . . . . . . . . .

Small signal analytical model for common-gate stage indirect

compensated two-stage op-amp . . . . . . . . . . . . . . . . .

Frequency response of a two-stage op-amp with a commongate stage when z=UGB . . . . . . . . . . . . . . . . . . . . .

Pole-zero location of two stage op amp with current buffer

compensation technique . . . . . . . . . . . . . . . . . . . . .

Design plan of a two-stage op-amp with a common-gate stage

Op-amp with an NMOS Voltage Buffer. . . . . . . . . . . . . .

Various two-dimensional effects causing sizes of realized microcircuit components to differ from sizes of layout masks. . . .

Example Cell Template . . . . . . . . . . . . . . . . . . . . .

Fingering Of Transistors . . . . . . . . . . . . . . . . . . . .

Example Of Fingering A NAND Gate . . . . . . . . . . . . .

Transistor Power Sharing Example . . . . . . . . . . . . . .

Example Of Soft Connections . . . . . . . . . . . . . . . . .

(a)Simple Folding Of A MOSFET,(b) Multiple Fingers . . .

Differential pair . . . . . . . . . . . . . . . . . . . . . . . . .

Layout Of MO And M1 With Different Orientation . . . . .

Layout With Gate-Aligned Devices . . . . . . . . . . . . . .

Layout With Parallel-Gate Devices . . . . . . . . . . . . . .

Interdigitized layout of a differential pair a) Differential pair b)

Horizontal expansion c) Interdigitized layout (Drain areas are

different. Common centroid.) d) Interdigitized layout (Drain

areas are equal. Not common centroid.) . . . . . . . . . . . .

Gradient of KP on a wafer . . . . . . . . . . . . . . . . . . .

Common-centroid layout of a differential pair . . . . . . . .

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6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

AC response of the two stage op amp with the Nulling resistor

Two stage op amp with Voltage Buffer . . . . . . . . . . . . .

AC response of the two stage op amp with the Voltage buffer .

Two stage op amp with Current Buffer . . . . . . . . . . . . .

AC response of the two stage op amp with the Current buffer

Step Response of two stage op amp with Current buffer . . . .

Slew Rate of two stage op amp with Current buffer . . . . . .

Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . .

Layout of the two stage op amp with the Current buffer . . . .

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70

71

71

73

List of Tables

3.1

Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1

6.2

6.3

Summary of Two stage op amp with voltage buffer . . . . .

Variation of settling time of op amp with different tolerance

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Design Parameters . . . . . . . . . . . . . . . . . . . . . . .

Summary of Two stage op amp with current buffer . . . . .

Comparison of different types of compensation technique of

two stage op amp . . . . . . . . . . . . . . . . . . . . . . . .

6.4

6.5

6.6

ix

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. 72

Chapter 1

Introduction

Operational Amplifiers are one of the indispensable blocks of modern

integrated systems and are used in wide varieties of circuit topologies like

data converters, filters, references, clock and data recovery circuits. However, continued scaling in CMOS processes has continuously challenged the

established paradigms for operational amplifier (op-amp) design. As the feature size of CMOS devices keeps shrinking, enabling yet faster speeds, the

supply voltage is scaled down to enhance device reliability and to reduce

power consumption. The expressions for a short channel MOSFET transition frequency(fT ) and open loop gain (gm r0 ) are given as [1]

fT

Vov

L

(1.1)

L

(1.2)

Vov

where Vov , L, gm are the overdrive voltage, channel length, transconductance and output resistance respectively for a MOSFET

From Equations 1.1 and 1.2, it can be observed that downward scaling

in gate length results in a larger (fT ), and hence faster transistors. But the

higher speed comes at the cost of a reduction in transistors open loop gain.

Hence the amplifiers designed with scaled processes exhibit larger bandwidths

but lower open loop gains. Also with device scaling the supply voltage has

also been continually reduced. However, the threshold voltage of transistors

doesnt scale well in order to keep transistor leakage under control. This

will eventually preclude gain enhancing techniques like cascoding (vertically

gm r0

stacking transistors to increase gain) of transistors and gain-enhancement by

employing amplifiers in cascode configuration [1]. Figure 1.1 displays the

trend in scaling of transistor supply voltage (VDD) and digital and analog

threshold voltages with process technology or production year. The trends

have been compiled by combining data from the 2006 ITRS report update

[2] and the predictive sub-45nm device modeling [3].

Figure 1.1: Trends for transistor supply and threshold voltage scaling with

advancement in CMOS process technology [2] and [3].

From Figure 1.1, it can be observed that the NMOS transistor threshold

voltage (VTHN) is not projected to scale while the VDD will scale down

continually. Also the VDD for digital process is set to scale more than the

analog VDD, which will make seamless integration of analog circuits difficult

in digital processes.

Figure 1.2 shows the reduction in open-loop gain with process scaling.

The open loop gain value of around to value in 100s in AMIs 0.5m process

has dropped to 10s in the sub-100 nm processes. Also with scaling, the

process variations become more pronounced as indicated by the expression

1

given by [2]

for the threshold-voltage mismatch LW

V T H

1

LW

(1.3)

Figure 1.2: Trends for transistor open-loop gain with CMOS process technology progression [2] and [3].

This leads to significant random offsets in op-amps due to the device

mismatches.

Figure 1.3 shows the projected enhancement in the peak fT of the devices

in upcoming CMOS process technologies, which is a desirable progression.

Now, for an N bit resolution ADC, the open loop DC gain (AOLDC) of the

op-amp required is given as

1.1

Problem Statement

To design the high speed two stage operational amplifier with different types

of compensation techniques like nulling resistor, voltage buffer and current

buffer liwith UGB of 1GHz and dc gain of 55dB and compare the results.

The design is to be implemented using 130nm technology in MentorGraphics

tool.

Tool: MentorGraphics Pyxis Schematic tool, Maxima

Figure 1.3: Trends for transistor transition frequency (fT) with CMOS process technology progression.

1.2

To design the low power, high speed two stage operation amplifier with different types of compensation techniques in 130nm technology.

Performance of an op amp depends on numerous electrical characteristics

e.g., GBW,slew rate common mode range output swing offset etc. Two stage

operational amplifier are often used to achieve both high dc gain and large

output voltage swing. These op amps require frequency compensation. A

current buffer in series with miller capacitor is one of the possible solutions.

It is very efficient both for PSRR and GBW and does not reduce the op amp

output swing unlike the voltgae buffer approach. This approach also gives

a trade off between power consumption and area of compensation circuit

by reducing the required value of compensation capacitor which suited well

where the heavy capacitive load must be driven. Ability to use smaller Cc

provides a higher degree of freedom in trading noise performance with power

consumption .

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1.3

Methodology

through various papers. All the devices used in the design were characterized

and the required parameters like threshold voltage Vth ,VDS and VGS of a

transistor were extracted. After under-standing the working of amplifier,

basic circuits were simulated with ideal conditions and specifications. Later

with these specifications, the circuits are designed in MentorGraphics and

simulated using Edlo tool. The schematic and symbol representation for

major units of amplifier namely differential amplifier, current mirror is done

and the behaviour of each unit is verified by AC analysis.

1.4

the project.

Chapter 2 - Gives the Literature Survey of different types of compensation

techniques.

Chapter 3 - This chapter deals with Compensation strategy and origin of the

positive zero

Chapter 4 - Deals with the design of the two stage op amp with the different

types of compensation techniques.

Chapter 5 - Deals with the Layout design concepts.

Chapter6 - This chapter deals with Result Analysis of different types of compensation techniques and compared there results.

Chapter 2

Literature Survey

2.1

Introduction

Feedback is a powerful technique that finds wide application in analog circuits. The high gain from amplifiers ensures the closed loop transfer characteristics with negative feedback are independent of the Op Amp gain. However, an adequate gain is a key requirement to utilize this technique.

2.2

Figure 2.1 shows a general negative feedback system [7], where H(s) and G(s)

are called the feedforward and the feedback networks, respectively. Since the

output of G(s) is equal to G(s)Y(s), the input to H(s), called the feedback

error and output are given by

E(s) = X(s) G(s)Y (s)

(2.1)

(2.2)

H(s)

Y (s)

=

X(s)

1 + G(s)H(s)

(2.3)

Thus

The quantity H(s) is the open loop transfer function and Y(s)/X(s) is the

closed loop transfer function. H(s) represents the operational amplifier and

6

G(s) is a frequency independent quantity. In other words, a fraction of the out

signal is sensed and compared with the input and generating an error term.

In negative feedback system, the error term is minimized, thereby making

the output of G(s) an accurate copy of the input and hence the output of the

system is an accurate replica of the input [7]. Feedback circuits provide gain

desensitization, i.e. the closed loop gain is much less sensitive to the open

loop gain [5]. This property can be quantified as following

A

1

1

Y

=

(1

)

X

1 + A

(2.4)

where A and are the low frequency gain of H(s) and G(s) respectively,

and the dc gain A >> 1. It can be noted that the closed-loop gain is

determined, to the first order by the feedback factor, . More importantly,

even if the open-loop gain, A, varies by a factor of 2, Y/X varies by a small

percentage because 1/(A) << 1. The quantity A is called the loop gain.

The loop gain plays an important role in feedback system. As seen from

Equation 2.4 that the higher A is, the less sensitive Y/X will be to the

variation in A. From another perspective, the accuracy of the closed-loop gain

improves as the open loop gain or feedback factor are maximized. However,

as the feedback factor is increased, the closed loop gain decreases Y/X1/,

so there is an inherent trade-off between precision and the closed loop gain.

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Certain configurations of a feedback amplifier extend the closed bandwidth

of the amplifier beyond the open loop amplifier. Assuming the feedforward

amplifier in Figure 2.1 has a single transfer function as given below

A0

(2.5)

1 + s0

where A0 denotes the low frequency gain and 0 is the 3-dB bandwidth.

The transfer function of the closed loop system can then be expressed as

H(s) =

0

Y (s)

1+A0

=

s

X(s)

1 + (1+A

0 )0

(2.6)

The numerator in Equation 2.6 is the closed loop low frequency gain

equivalent Equation 2.4. The denominator provides the location of the pole

at (1 + A0 )0 Comparing this to Equation 2.5 the 3-dB bandwidth has

increased by a factor of (1+A0 ). The extended bandwidth comes at the cost

of proportional reduction in the gain as the product of gain and bandwidth

is a constant for such an operational amplifier. Another very important

property of negative feedback is the suppression of nonlinearity in analog

circuits [8]. Nonlinearity can be regarded as the variation of the small signal

gain with the input dc level. Negative feedback keeps the overall closed

loop gain nearly constant and almost independent of the amplifier open loop

gain. Therefore negative feedback circuits reduce distortion resulting from

the change in the slope of the amplifier transfer curve. Mathematical analysis

of the effect of a feedback system on nonlinearity of a circuit is very complex

and can be found in [3, 5].

2.3

The properties of feedback described in section 2.2 allow precise operations

by suppressing variations of the open loop characteristics. However, feedback

systems suffer from potential instability, that is, they may oscillate.

Considering the negative feedback system shown in Figure 2-2 the closed

loop transfer function can be written as

H(s)

Y (s)

=

X(s)

1 + H(s)

(2.7)

to infinity and the circuit starts to amplify its own noise until it eventually

begins to oscillate. This condition can be expressed as

|H(j1 )| = 1

6

H(j1 ) = 1800

which are called the Barkhausens Criteria. It can be observed that the

total phase shift around the loop at 1 is 3600 because the negative feedback

introduces itself a 1800 of phase shift. The 3600 of phase shift is required

for oscillation as the noise has to shift by 1800 to be in phase with the

signal to add. The other condition on loop gain being unity or greater is

required to enable the growth of the oscillation amplitude. The condition

necessary and sufficient for negative feedback stability is that all the poles of

the feedback system are have a negative and real part. This from Laplaces

criteria translates to the poles being on the left half side of the plane. It may

be difficult to analyze the stability of a complex system from looking at the

closed loop poles of the system, since finding the zeros of the denominator1 +

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

loop stability could be predicted from observing the open loop response of

the amplifier.

The concept of phase margin for an open loop amplifier is good indicator

of the stability of the closed loop system. From the Nyquist criterion If

|A(j)| > 1 at the frequency where ph A(j) = 1800 , then the amplifier

is unstable. Figure 2-3 shows the loop gain magnitude |A(j)| is unity at

frequency 0 . At this frequency the phase of A(j) has not reached 1800

for the case shown, and using the Nyquist criterion state we conclude that

this feedback loop is stable.//

Figure 2.3: Amplifier gain and phase versus frequency showing the phase

margin

As |A(j)| is made closer to unity at the frequency where ph A(j) =

1800 , the amplifier has a smaller margin of stability, and this can be specified in two ways [9]. The most common is the phase margin, which is defined

as follows: Phase margin = 1800 + (ph A(j) at frequency where |A(j)| =

1). The phase margin is indicated in Figure 2-3 and must be greater than 00

for stability. [3]

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

10

2.4

of Operational Amplifier

The single stage amplifiers are inherently stable and typically have excellent

frequency response assuming the gain bandwidth is ten times higher than

the single pole. However, single stage amplifiers suffer from low dc gain and

is even less for submicron CMOS transistors. In general, Op Amps require

at least two gain stages which introduce multiple poles in the frequency response. The poles contribute to the negative phase shift and may cause 6 F A

to reach 1800 before the unity gain frequency. Therefore due to insufficient

phase margin the circuit would oscillate. Thus the amplifier circuit needs to

be modified to increase the phase margin and stabilize the closed loop circuit.

This process is called gcompensationh. By intuition, two different approaches

may be taken to stabilize the loop. The more straightforward approach way

is make the gain drop faster in order for the phase shift to be less than 1800

at the unity gain frequency. This approach achieves stability by reducing the

bandwidth of the amplifier and the most popular pole splitting method uses

this procedure. Another compensation method pushes the phase crossover

frequency out by decreasing the total phase shift. In this particular case the

total number of poles needs to be reduced while still maintaining the dc gain.

This is achieved by introducing zeros into the open and close loop transfer

function to cancel the poles, or using feedforward paths to improve the phase

margin without narrow-banding the bandwidth as much as the pole splitting

does.

2.4.1

Parallel Compensation

capacitor is connected in parallel to the output resistance of a gain stage of

the operational amplifier to modify the pole. It is not commonly used in the

integrated circuit due to the large capacitance value required to compensate

the Op amp, which considerable die area.

2.4.2

Early in 1967, Widlar designed the LM101/741 [18] op amp which employed

the pole splitting frequency compensation method. This method was first

11

designs. In 1974, Solomon reported a tutorial study on the monolithic op amp

[2] and discussed the pole splitting technique. By putting a compensation

capacitor between the input and output nodes of the second inverting stage

of the op amp, the dominant pole is created due to Miller [15] feedback. This

method maintains a high midband gain for the op amp since the capacitor

does not affect the dc response of the amplifier. Fig. 2.3 shows the standard

SMC topology.

As the transistor gain of the second stage increases, the dominant pole

de- creases and the nondominant pole increases. In this way the two poles are

being split apart and stabilize the feedback amplifiers by greatly narrowing

the bandwidth. This simple pole splitting method also introduces a right

half plane zero which causes negative phase shift, as a result, the stability

is made a little poorer. The zero comes from the direct feedthrough of the

input to the output through the Miller capacitor. To eliminate the RHP zero

due to the feedthrough and increase the phase margin of the op amp, lead

compensation which adds a nulling resistor in series with the com- pensation

capacitor (SMCNR) to increase the impedance of the feedthrough path is

reported [4, 15]. Leung and Mok investigated the effect of the nulling resistor

to the positions of the poles as well as that of the zero and pointed out the pole

12

splitting would break down if the resistor becomes too big. When the resistor

gets very large, there is no pole splitting since the compensation capacitor is

actually open circuit. Fig. 2.4 shows the popular SMCNR structure.

2.5

Compensation Techniques

Many gain boosting schemes have been reported [5] to improve the gain.

In general, these gain enhancing designs require more complicated circuit

structure and a larger power supply voltage, but generate smaller output

swing. As a result, multiple stage amplifiers might be more suitable for

low power, low voltage, high density analog circuit designs. The frequency

response of the multistage amplifier is not as good as that of the single stage

and this amplifier has a higher probability of oscillation in feedback circuits.

One popular way to predict the closed loop stability is by measuring the

phase margin of the open loop gain response. PM must be greater than 00

for no oscillation to occur. A good performing amplifier will need a PM of

about 450 to 600 . Otherwise, the amplifier may exhibit ringing in the time

domain and peaking in the frequency domain [15].

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

13

2.5.1

Multistage amplifiers have more poles and zeros than do single stage amplifiers. The frequency response and time response are far more complicated

than those of the single stage op amps. As a result, all multistage amplifiers

suffer closed loop stability problems. Single Miller compensation is used for

the simple two-stage amplifier; while the extended version of the SMC compensation, nested Miller compensation (NMC) [15] is applied to amplifiers

with three or more stages. Because of the rapid bandwidth reduction, op

amps with more than four stages are rarely investigated. NMC exploits the

nested structure of feedback capacitors to cause the pole splitting compensation. There are some drawbacks related to the NMC approach. The total of

N-1 nested compensation capacitors must be placed between the dominant

node and the other nodes to split the individual poles from the dominant

output pole to stabilize an N stage op amp.Fig. 2.5 shows the structure of

a three stage NMC op amp. The nesting topology of the compensation capacitor reduces the bandwidth substantially [5]. The specific configuration

requires the compound noninverting gain stages to connect to the inverting

output stage in order to secure negative feedback for the nested compensation loops. The necessity to drive the compensation capacitors along with

the capacitive load requires the output stage to have a high transconductance

to attain wide bandwidth and high slew rate. Consequently, elevated power

consumption is unavoidable especially for large load capacitor.

To address the bandwidth degradation problem, the variations of the

NMC are developed. NMC using nulling resistor (NMCNR) [4, 15], reversed

nested Miller compensation (RNMC) [19], multipath NMC (MNMC) [5],

hybrid NMC (HNMC) [5], nested Gm-C compensation (NGCC) have been

presented. RNMC improves the bandwidth over NMC by the reversed compensation topology compared to NMC as shown in Fig. 2.6. The RNMC

technique sets the second gain stage negative and the output stage positive.

The Miller capacitor loop is around the second stage without connection to

the considerable output capacitive load. HNMC combines the NMC and the

RNMC topological properties in a multistage (above three) op amp. In this

circumstance, the circuit could consist of only inverting amplifier except for

the input stage. The difference between NMC and MNMC is the added feedforward amplifier stage -Af1 connected between the input of the first stage

and the input of the last stage of the multistage op amp as shown in Fig.

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

14

2.7.

The feedforward stage added can produce a LHP zero to counteract the

second nondominant pole to broaden the bandwidth. The increased circuit

complexity and power consumption should be considered. Moreover, the pole

zero doublets may seriously degrade the settling time of the amplifier.

The difference between NGCC and MNMC is that NGCC replicates the

feed- forward Gm (N-1) times for an N stage op amp recursively as shown in

Fig. 2.8 . Compared to MNC, NGCC has simpler stability conditions due

to the much simpler transfer function which makes the op amp design more

facile.

The basic idea of most of these variations of the NMC schemes is not

to drop the overall bandwidth of the multistage amplifiers by the pole zero

cancellation in the passband caused by the feedforward path of the multipath

topology. All of those compensation techniques mentioned above use Miller

capacitors whose sizes are related to the load capacitor value. The required

sizes of the compensation capacitors would escalate with larger capacitive

loads which make these techniques not suitable for low area need. The experimental results of the varied versions of NMC showed that the bandwidth

does not get improved significantly for considerable capacitive loads [19].

15

2.5.2

Many compensation techniques mentioned above are not suitable for large

load capacitors. The demand for lower power consumption, lower chip integration area, capability for driving large capacitive loads, and stable high gain

bandwidth of amplifiers calls for improved frequency compensation patterns.

The topologies using a single Miller capacitor in three stage amplifiers could

greatly reduce the needed sizes of the compensation capacitors compared to

NMC related schemes and result in amplifiers with smaller chip area. The

presented SMFFC and the modified SMC with the additional feedforward

path from the output of the first stage to the output load stage are designed

for a particular three stage amplifier specifically in the case of large capacitive loads. The topology of the SMFFC op amp is represented in Fig. 2.9.

Instead of using pole zero cancellation, SMC with one forward path adopts

the separate pole approach [12] for compensation in the situation of large

capacitive loads.SMFFC employs two forward paths and provide a LHP zero

to compensate the first nondominant pole to alleviate the bandwidth reduction and improve the phase margin. The strictly rational selection of gains

among the three stages is the key point for this SMFFC scheme. For the gain

distribution like Av1 >> Av2 >= Av3, the second and third poles of the

amplifier would be placed at higher frequencies that lead to a coarse single

16

pole system for an easier frequency compensation strategy. The appropriate

selection of the moderate gain of the second stage will then decrease the compensation capacitor size. Unfortunately, this method does not truly resolve

the compressed gain bandwidth issue due to the super high gain of the first

stage and the nature of the pole separation. Gain enhanced feedforward path

compensation (GFPC) [10] is much like the modified SMC version with one

feedforward path, but for two stage amplifiers.

2.5.3

The nonstandard NMC topologies have been investigated to deal with the

drawbacks with the NMC and MNMC in order to be able to drive large

capacitive loads. The reported strategies include damping factor control frequency compensation (DFCFC) [3], embedded RC compensation (ERC) [2],

active feedback frequency compensation (AFFC) [31], and dual loop parallel

compensation (DLPC) [32, 33]. The ERC duplicates the RC compensation

process N-2 times for an N stage op amp. ERC compensation circuits do

not load the output stage as NGCC circuit do. The noninverting gain stages

are not necessary in ERC as in NMC or the standard vari- ations of NMC.

ERC topology extends the bandwidth via the zero pole cancellation through

the embedded compensation network without connection to the output load.

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

17

Usually ERC uses a low gain, high conductance output stage to have the

similar load- ing isolation benefit as the buffer output stage of the Widlar architecture.DFCFC can substantially improve the bandwidth of a three stage

amplifier with good fre- quency and transient responses when driving large

capacitive loads. But it is not so effective for small capacitive load applications. Some other compensation methods turn out to be more suitable than

DFCFC when driving a small capacitive load.

2.5.4

One feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors is proposed by Thandri and

Silva- Martinez [3]. This NCFF method applies the feedforward path as

shown in Fig. 2.10 to create LHP zeros. By using the positive phase shift of

LHP zeros to cancel the negative phase shift of the poles, a high gain, high

bandwidth amplifier with a good phase margin is developed. Thandri does

mention some design considerations of the NCFF in the paper. For example,

the feedforward and second stage must place the nondominant poles after the

overall unity gain frequency of the amplifier to alle- viate phase deduction;

the pole zero cancellation should happen at high frequencies to achieve better

time domain response. Some other constraints of the NCFF scheme not

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

18

directly specified in the paper should also be recognized.The NCFF is not

suit- able for big capacitive loads as a result of the main design consideration

mentioned. The transient response might be degraded severely by the polezero doublets. A good performing amplifier should have both good frequency

response and transient response. The complexity of the presence of extra

poles and zeros can cause the design of the NCFF scheme to be very difficult

and the undesired low frequency pole-zero doublets may lengthen the settling

time of the amplifier or even make the closed loop unstable.

2.5.5

The negative Miller capacitance compensates high speed CMOS op amps that

consists of an operational transconductance amplifier (OTA) and a buffer.

The buffer with a dc gain of A is used to detach the OTA from the load.

The OTA is compensated with a capacitor Cc connected between the input

and output of the buffer. Assuming the op amp drives a load with a parallel

combination of a resistor RL and a capacitor CL. the effective capacitance

seen at the input of the buffer is Cin = Cc(1-A) and Cout = CL+Cc(11/A) at the output of the buffer. Since the gain of the buffer is positive and

smaller than one, the reflected Miller capacitor Cc(1- 1/A) at the output will

be negative. The total effective output capacitance is reduced to be smaller

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

19

than the original load capacitance due to the negative Miller capacitance.

NMCC can be applied to drive a large capacitive load. The experimental

results show that the NMCC design shifts the first nondominant pole to a

higher frequency while keeping the position of the dominant pole almost the

same. This NMCC scheme could increase both the bandwidth and phase

margin. Comer et al. [3] proposed a CMOS amplifier bandwidth extension

method by utilizing a negative capacitance circuit. Negative capacitance can

be generated by active circuitry using the Miller effect. The limitations of

current IC technolo- gies restrain the use of inductors and only small capacitors are available. With the innovative negative capacitor idea, compensation

practice could shape the frequency response with more freedom.

20

Chapter 3

Operational Amplifier

Compensation Strategy

The two stage Operational Transconductance Amplifier(OTA) is a widely

used analog building block.Indeed,it identifies a very simple and robist topology which provides good values for most of its electrical parameters such as

dc gain, output swing, linearity, CMRR, etc. To avoid closed loop instability, frequency compensation is a necessary in op amp design. For two stage

CMOS op amp, the simplest compensation technique is to connect a capacitor across the high gain stage.This results in the pole splitting phenomena

which improves the closed loop stability significantly.However , due to feedforward path through the miller capacitor, a right half plane (RHP) zero id

also created.

An uncompensated right half plane zero drastically reduces the maximum

achievable GBW, since it makes a negative phase contribution to the open

loop gain at a relatively high frequency. In order to compensate the right half

plane zero, an appropriate design approach is essential.Such a zero can be

nullified if the compensation capacitor is connected in conjunctin with either

a nullifying resistor or a common gate current buffer.After compensation of

right half plane zero, the maximum gain bandwidth is limited by second pole.

21

3.1

the phase of a positive zero, with that of a negative zero which is shown in

Figure 3.1. There is no need to have a second-order system for this purpose.

A first-order system can be taken as well. The Bode diagrams are sketched

for a first-order system with one single pole and one single zero. In the

second case the zero is positive. Both have obviously the same amplitude.

Consequently, amplitudes are not affected by signs.

They have a very different phase characteristic, however. In the first Bode

diagram the phase returns to zero for high frequencies. For the second diagram however, for a positive zero, the phase goes to 1800 . This is like having

a second pole, rather than a zero! This completely ruins our phase margin!!!

We have tried to limit the phase contribution of the non-dominant pole to

about 200 by carefully locating this non-dominant pole beyond the GBW. A

positive zero now shows up, which brings in another 900 . This will ruin the

phase margin. Moreover, the larger we make the compensation capacitance

Cc, the more this zero shifts to lower frequencies. Large values of Cc are

therefore not allowed.

In order to understand how we can abolish the positive zero, we have to

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

22

try to understand what its origin is, which adds another 900 phase shift. This

is a result of the feedforward through the compensation capacitance. Indeed,

the compensation capacitance is bidirectional after all, as most capacitances.

This means that feedback current and feedforward current flow at the same

time.

The feedback current is the Miller effect current from output to input as

shown in Figure 3.2. It flows between two nodes which are opposite in phase.

The feedforward current is only easy to see when we leave out the amplifier

itself. We now notice a feedforward current through Cc which causes a small

output signal which is in phase with the input. This is the current which

causes the zero. It is a positive zero because it provides an output signal

which is of opposite phase compared with the amplified output signal. To

abolish this positive zero, we have to make that compensation capacitance

unidirectional. In other words, we have to put a transistor in series, which

cuts the feedforward path.

Various techniques for the compensation of the right half plane zero in

two stage CMOS op amp have been proposed and as well adopted. A compensation technique was proposed which uses nulling resistor in series with

the compensation capacitor. In an another solution a voltage buffer is introducted in compensation branch which breaks the forward path. Both current

23

and voltage buffers can be adopted for compensation of the right half plane

zero due to their advantages over nulling resistor as it is more sensitive to

process and temperature variation.

3.2

1.Nulling resistor

2.Voltage buffer

3.Current buffer

3.2.1

Nulling resistor

The most popular compensation technique is that based on the nulling resistor, since it can be implementated using only an MOS transistor biased in

the triode region. In this approach the left half plane zero introduced by the

nulling resistor Rc in Figure 3.3

fz =

gm5

1

2 (gm5 Rc 1)Cc

(3.1)

It is not so easy, however, to match a resistor to a gm value. Especially

if the resistor is realized by means of a MOST in the linear region, then the

matching is more difficult. There is a simple solution to this problem, however. We increase the size of the resistor. This zero now turns into a negative

zero. In other words the minus sign in the expression of the zero compensates the minus sign in the gain expression. This negative zero is positioned

between the negative poles and can therefore be used to compensate one of

them.

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

24

3.2.2

Voltage Buffer

The adoption of an ideal voltage buffer (i.e., with zero output resistance) to

compensate the right half plane zero gives the same second pole as in resistor

technique and hence the same UGB. Usually the simple common drain in

Figure 3.4 is employed and connected between nodes. Taking into account for

the finite output resistance of the buffer which is about equal to 1/gm9, the

compensation branch introduces a left half plane zero at f z = gm9/2Cc.

The approach based on nulling resistor and voltage buffer give the same

compensation capacitor and hence the same GBW. However, a voltage buffer

in the compensation branch greatly reduces the output swing preventing its

use in many practical cases.

3.2.3

Current Buffer

efficient both for GBW and the PSRR performance. It also does not have

the drawback of the voltage buffer which reduces the output swing.

In this design approach value of Cc is much smaller. The ability to use

smaller provides a hig her degree of freedom in trading noise performance

25

with power consumption.For this purpose, the common gate in Figure 3.5

can be used.

3.3

Advantages:

1. Good GBW.

2. High PSRR.

3. Improved slew rate.

4. Area efficient(low Cc).

5. Power and area trade off.

6. Does not reduce output swing like voltage buffer.

Disadvantages:

1. Increased offset.

2. Additonal biasing current is required.

26

3.4

Specification

given in Table 3.1:

Parameter

Target

Supply Voltage

1.8V

Vin,cm

1.2V

DC Gain

> 55dB

UGB

> 1GHz

PM

60deg

Settling Time

< 3ns

CL

1pF

Technology

130nm

27

Chapter 4

Two stage operational amplifier

compensation techniques

4.1

Introduction

Two stage op-amps have been the dominant amplifier topologies used in

analog system design due their simple frequency compensation and relaxed

stability criterions. The two-stage op-amps have conventionally been compensated using Miller compensation or Direct Compensation technique. Figure 4.1 the shows block diagram of a twostage op-amp. The op-amp consists

of a diff-amp as the input stage. The second (gain) stage is biased by the

output of the diff-amp which is followed by an output buffer. The optional

output buffer is used to provide a current gain when driving a large capacitive

or resistive load [3].

4.2

Miller Capacitance

Before compensation, the poles of the two-stage cascade are given as,p1 =

1

and p2 = R21C2 , where Rk,Ck are the resistances and capacitances

R1 C1

respectively at nodes is employed to achieve pole splitting. In this technique,

the compensation capacitor (Cc) is connected between the output of the first

and second stages. The compensation capacitor splits the input and output

poles apart thus obtaining the dominant and non-dominant poles which are

spaced far away from each other [18],[6]. However, Miller compensation also

introduces a right-half-plane (RHP) zero due to the feed-forward current

28

from the output of the first stage to the op-amps output. Figure 4.2 shows

the small signal model for twostage opamp used for nodal analysis.

The small signal transfer function for a Miller compensation two-stage

opamp is given as,

(1 zs1 )

V out

= gm1 R1 gm2 R2

Vs

(1 ps1 ) (1

s

)

p2

(4.1)

z1 =

gm2

Cc

(4.2)

1

gm2 R2 R1 Cc

and the non dominant pole is located at

p1 =

p2 =

gm2 Cc

gm2

C1 + C2

(4.3)

(4.4)

The open-loop gain of the op-amp is given asAv = gm1 R1 gm2 R2 , while the

gm1

unity gain frequency (or gain-bandwidth) is given as U GB = 2Cc

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

29

Figure 4.2: Small signal model for nodal analysis of Miller compensation of

a two-stage op-amp.

The pole splitting for the two-stage op-amp due to Miller compensation

is illustrated

Figure 4-4 shows the frequency response of the Miller compensated twostage opamp. Since the phase contribution due to the RHP zero is given

as tan1 ffz1 it degrades phase margin of the op-amp from 900 and leads

to instability when the second pole moves closer to the unity-gain frequency

(UGB). Hence, not only the RHP zero flattens out the magnitude response

by cancelling the dominant pole roll-off, which is required to stabilize the

op-amp, it also decreases the phase margin which makes the op-amp stabilization difficult.

Upon closer analysis of the origin of the RHP zero, the compensation

current (ic), flowing across the compensation capacitor (Cc) from output

node to node-1, is given as ic= sCc(vout v1) = sCcvout sCcv1.The feedforward component of this current,iff = sCcv1, flows from node-1 to the

output, and the feed-back component, ifb = sCcvout, flows from the output

to node-1. The feed-forward current, iff, depends upon voltage v1, and so

does the current at the output(=(gm2- sCc)v1).When the total current at

2

) , a RHP

the output equals zero (i.e. frequency corresponding to z1 = gm

Cc

zero appears in the transfer function. This RHP zero can be eliminated by

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

30

Figure 4.3: Pole-zero plot for a two-stage op-amp demonstrating pole splitting due to the Miller capacitor

blocking the feed-forward compensation current, while allowing the feed-back

component of the compensation current to achieve pole splitting [8].

31

Several methods have been suggested in [7] and [6] to cancel the RHP

zero in the two-stage op-amp and are described in the following sub-sections.

A Miller compensated two-stage op-amp has been implemented with schematic

as shown in Figure 4.5. The high speed op-amps have been designed to drive

a typical load of 1pF. The op amp is designed in the 130nm technology in

MentorGraphics.

The following sub-sections discuss methods widely used to eliminate

the detrimental effects of the RHP zero on the phase margin in the Miller

compensated op-amps.

32

4.2.1

A common method to cancel the RHP zero is to use a zero nulling resistor

in series with the compensation capacitance, as shown in Figure 4.6.

Small signal model of OTA

The below Figure shows the small signal model of the two stage OTA with

the nulling resistor.The circuit has the following nodal equations.

gm1 V in +

gm2 V 1 +

V1

sCc

+ sC1V 1 + (

(V 1 V out)) = 0

R1

1 + sCcRz

V0

sCc

+ sC2V out + (

(V out V 1)) = 0

R2

1 + sCcRz

(4.5)

(4.6)

V out

a[1 s((Cc/gm2) RzCc)]

=

V in

1 + bs + cs2 + ds3

(4.7)

where

33

a = gm1 R1 gm2 R2

b = (C2 + Cc)R2 + (C1 + Cc)R1 + gm2 R1R2Cc + RzCc

c = [R1R2(C1C2 + CcC1 + CcC2) + RzCc(R1C1 + R2C2)]

d = R1R1RzC1C2Cc

If Rz is assumed to be less than R1 or R2 and the poles are widely spaced,

then the roots of the above transfer function can be approximated as

p1 =

1

1

(1 + gm2R2)R1Cc

gm2R2R1Cc

(4.8)

gm2Cc

gm2

C2

(4.9)

1

RzC1

(4.10)

1

Cc(1/gm1 Rz)

(4.11)

p2 =

p3 =

and

z1 =

34

Figure 4.7: Small signal model of two stage op-amp with zero nulling resistor

For Rz=1/gm2, the zero is pushed to infinity and for Rz1/gm2, the zero

appears in the left half plane (LHP). Thus for Rz=2/gm2, the RHP zero is

converted to an LHP zero of the same frequency location as that of the RHP

zero. A LHP zero helps in improving the phase margin of the opamp and

enhances stability.

A third pole is introduced at p3 which is far away from the second pole,

p2, as C1 << C2 and Rz = 1/gm2 [6]. The location of the zero may vary

depending upon the process variations in the resistor Rz, but this scheme

is effective enough to keep the RHP zero from degrading the phase margin.

The resistor Rz can be implemented using a transistor in triode region, and

can be made to track the value of 1/gm2 and cancel the RHP zero. However

the biasing of this triode transistor may require additional power [4].

The small signal frequency response for this circuit is shown in Figure

4.8. Here we can observe the improvement in phase margin (PM) from 750

to 890 by using the zero nulling resistor.

Maximum amd Minium Rz

In order to be effective, we have to position this zero close to the GBW, for

example at 10 times the GBW where the nondominant poles are. This yields

a new expression for Rz, which is now related to gm1 instead of gm2. We

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

35

with zero nulling resistor

simply position Rz between both the values obtained, with preference to be

closer to 1/10gm1.

Let us assume that z=10UGB

We know that

z1 =

1

Cc(1/gm1 Rz)

10U GB =

1

Cc(1/gm1 Rz)

(4.12)

(4.13)

1

1

< Rz <

gm2

10gm1

(4.14)

The goal is to find out what maximum GBW can be reached within a certain

CMOS technology. Also, we want to find the shortest way to design this

OTA. First of all, a number of design choices have to be made. They have all

been previously used. We list them again and introduce design parameters

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

36

of the non-dominant pole. Also, note that CL can be described in terms of

the width of the output transistor. Obviously, the larger the CL, the more

current we will need to drive it, and the larger the transistor width becomes.

We know

p2 =

gm2Cc

C1CL + CLCc + CcCL

(4.15)

gm2

1

C1

2CL Cc + 1

(4.16)

Therefore

p2 =

Assume

CL = Cc

Cc = C1 = Cgs2

p2 = GBW

p2

gm2

GBW =

=

2CL

GBW =

1

+1

2Cox(V gs V t)

1

2KL2

( 1 + 1)

therefore

(V gs V t)2

L2

From the above equation we can see that the maximum GBW does not

depend on the load capacitance.

Actually, increasing the load capacitance increases the width of the output

transistor and its current. The speed of the output transistor mainly depends

on its length.

The speed of a MOST is better represented by parameter fT. This is why we

now try to substitute the transistor parameters VGS-VT and L by parameter

fT.

GBW

Design Procedure

The design procedure in a broader sense involves the following sequence of

steps. Firstly selecting a specific topology, secondly determining the DC

currents, thirdly calculating the W/L ratios of each transistor, at the end

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

37

The design procedure assumes that the DC gain(Av), unity-gain bandwidth (GB), Input common-mode range[Vin(min) and Vin(max)], Load capacitance(CL), slew rate(SR), Settling Time(Ts), Output voltage swing[Vout(max)

and Vout(min)] and Power dissipation(Pdiss) are given.

1.The smallest device length that will keep the channel modulation parameter constant and give good matching for current mirrors has been chosen.

2. From the desired phase margin, the minimum value for Cc is chosen ,that

is for a 600 phase margin. We have used the following relationship. This

assumes that z > 10GB.

Cc > 0.22CL

3. The minimum value for the tail current (I5) from the largest of the two

values is determined.

I5 = SR.Cc

4. Design of S3 from the maximum input voltage specification.

S3 =

2I3

>1

K3V DD V in(max) [V T 3(max) + V T 1(min)]2

5. The pole and zero due to Cgs3 and Cgs4 will not be dominant by assuming

pole p3 to be greater than 10GB.

gm3

> 10GB

2Cgs3

6. Design for S1(S2) to achieve desired GB

gm2

K2I5

7. Design of S5 from the minimum input voltage.First we have calculated

VDS(Sat) and then we can find S5

gm1 = GBCc > S1 = S2 =

38

S5 =

2I5

K5[V DD(Sat)]2

8. Find S6 and I6 by letting the second pole (p2) be equal to 2.2 times GB.

)

Let Vsg4=Vsg6, which gives S6 = S4( gm6

gm4

Knowing gm6 and S6 allows us to solve for I6 as I6 =

gm62

2K6S6

S6 =

gm6

K6V ds6(Sat)

And then using the previous relationship to find I6. The proper mirror

between M3 and M4 is no longer guranted.

10. Design of S7 to achieve the desired current ratios between I5 and I6.

S7 =

I5

S6

I6

11.The Rz is calculated as

z1 =

gm6

gm6

Cc(1 gm6Rz)

CL + C1

Therefore

Rz =

4.2.2

Cc + CL + C1

gm6Cc

Current buffer

A common-gate stage can also be used to block the feedforward current from

node- 1 to the output node-2 [4]. Figure 4.9 shows a two-stage op-amp which

is indirect compensated using a common-gate stage. The transistor MCG

acts as a common-gate amplifier which blocks the feed-forward compensation current and allows the feedback compensation current to flow indirectly

39

from the output to the internal node-1. Such topologies are analyzed in the

next section, and they significantly improve the performance of the opamps

designed. As the compensation current is fed back indirectly from the node-2

(i.e. output node) to the node-1 in order to achieve pole splitting (and hence

dominant pole compensation), the class of compensation technique is called

Indirect Feedback Frequency Compensation or simply indirect compensation.

An analysis of the common-gate stage indirect compensated op-amp topology

is provided in the next section

compensation current

In order to develop an insight into indirect feedback compensation, the opamp topology indirectly compensated with common-gate stage is analyzed.

The small signal model for the common-gate stage op-amp topology is shown

in Figure 4.10

The model used for exact analysis has three nodes and hence three dependent variables, v1,vA and vout. Also in the model Vs=Vp-vin. A T-type

small signal model is used to represent the common-gate device MCG [6].

Here, the transconductance and output resistance of the common-gate device (MCG) are denoted as gmc and roc respectively. Also RA and CA are

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

40

Figure 4.10: Small signal analytical model for common-gate stage indirect

compensated two-stage op-amp

the resistance and capacitance at the low impedance node-A. On applying

nodal analysis on the model shown in Figure 4.10, we obtain the following

set of equations

gm1vs +

gm2v1 +

(v1 vA)

v1

+ v1sC1 gmcva +

=0

R1

roc

vout

+ voutsC2 + sCc(vout vA) = 0

R2

(vA v1)

vA

+ gmcvA + vAsCA +

+ sCc(vA vout) = 0

roc

RA

(4.17)

(4.18)

(4.19)

small signal transfer function

vout

b0 + b1 s

)

(4.20)

= Av(

vs

a0 + a1 s + a2 s 2 + a3 s 3

The third order transfer function given by Equation 4.20 consists of a

real LHP zero and three poles. The exact values of the transfer function

coefficients are

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

41

Av = gm1R1gm2R2

(4.21)

b0 = (1 + gmcRA)roc + RA

(4.22)

(4.23)

a0 = (1 + gmcRA)roc + RA + R1

(4.24)

a1 = gm2R2gmcR1rocCcRA+gm2R2R1CcRA+gmcRAroc(R1C1+R2(C2+Cc))

+R1RA(Cc+CA)+RA(R1C1+R2C2)+R1R2(C2+Cc)+roc(R2Cc+RA(Cc+CA))

a2 = (gmcRA+1)R2C1R1roc(C2+Cc)+R2rocRACC(C2+CA)+R1R2CcRACA

+R2C2RA(R1)C1 + Cc + CA) + rocCA) + R1C1RA(roc(Cc + CA) + R2C2).

a3 = R1C1R2rocRA(C2CA + C2Cc + CcCA)

(4.25)

C1,CA, we obtain the following modified transfer function coefficients,

b0 gmcRAroc

b1 RAroc(Cc + CA)

a0 (gmcRA + 1)roc

a1 gm2R2R1rocCc(gmcRA + 1)

a2 (gmcRA+1)R2C1R1roc(C2+Cc)+R2C2RA[roc(Cc+CA)+R1(Cc+CA+C1)]

a3 R1C1R2rocRA(C2Ca + C2Cc + CcCA)

Using the numerator expression, we obtain the location of the zero to be

at

z1

gmc

b0

=

b1

Cc + CA

(4.26)

42

which is evidently an LHP zero.With the assumption that |p1 | >> |p2 |, |p3 |,

the dominant real pole is given as

1

a0

=

(4.27)

a1

gm2R2R1Cc

Now for s >> p1 , the non-dominant poles p2 and p3 are real and spaced

apart when ( aa21 )2 >> 4 aa31 , see APPENDIX or

p1 =

The above condition is satisfied when

4gm2Cc(C2||Cc + CA)

C1(C2 + Cc)

This implies that the gm of the common-gate device (MCG) in Figure 4.9

should be large. When the condition given by above Equation is satisfied,

the non-dominant poles are given as

gmc >>

p2

a1

gm2Cc

=

a2

C1(C2 + Cc)

(4.28)

and

p3

a2

gmc

C2/C1

=

a3

CA + (C2||Cc) R1||roc(C2 + Cc||Cc)

(4.29)

gm1

(4.30)

2Cc

The second pole of Current buffer compensation is located at gm2Cc

CLC1

gm2

while the second pole for Miller compensation was located at C1+CL

.By

comparing the two expressions, we can observe that the second pole, p2, has

moved further away from the dominant pole by a factor of approximately

Cc/C1.This factor of Cc/C1 comes to around 10s in TSMC 130nm Technology.Also the LHP zero adds to the phase response in the vicinity of UGB

and enhance the phase margin.

This implies that we can achieve pole splitting with a much lower value

of compensation capacitor (Cc) and lower value of second stage transconductance (gm2). Lower value of gm2 translates into low power design as the bias

U GB =

43

current in second stage can be much lower. Alternatively, we can set higher

value of unity-gain frequency (fun) for the op-amp without affecting stability

and hence achieving higher bandwidth and speed. Moreover, the load capacitor can be allowed to be much larger for a given phase margin [9], [10]. The

higher value of |p2| can be explained by the fact that the first stages output

(i.e. node-1) is not loaded by the compensation capacitor [6]. In short, in

can be trivially concluded that indirect feedback compensation can lead to

the design of op-amps with significantly lower power, higher speed and lower

layout area.

The third pole (p3) doesnt move to lower frequency and interact with

the second pole (p2) as long as gmc is large and R1,C1 are smaller in value.

Looking at the case when the z=UGB and non-dominant poles are close

and form a conjugate pole pair when

gmc <

4gm2Cc(C2||Cc + CA)

C1(C2 + Cc)

(4.31)

s

r

r

a1

gm2gmc

gm2gmc

Re(p2,3 ) =

=

(4.32)

a3

C1[C2 + (1 + C2/Cc)CA]

C1C2

and the damping factor is given as

a2

1

=

2 a1 a3

2Cc

C1C2

gm2

(4.33)

gm2

|Re(p2,3 )| =

CL

gmcCL

gm2

>

gm2C1

CL

(4.34)

which again re-affirms the fact that the values of 1/gmc and C1 should

be small in order to move p2,3 away from p1 as farther as possible.

The below Figure shows the Frequency response of the two stage op amp

when z=UGB.

44

stage when z=UGB

Design Plan

The Design procedure of two stage OTA with current buffer is same as with

the nulling resistor, the only condition is that here we are making

z = U GB

We are placing the zero exactly on the UGB so that zero adds the extra

phase margin and gm1 = gmc. Here the non dominant poles are complex

conjugate. The below Figure 4.12 shows the Design plan two stage op amp

with current buffer. The Figure 4.13 shows the pole-zero location of current

buffer compensation technique.

The gm1 is calculated through the thermal noise spectral density. The

procedure starts with the thermal noise requirement for the Op Amp. Neglecting the flicker noise requirement, which contributes to the low frequency

noise spectrum, the input referred noise voltage can be expressed as shown

in Equation 4.35.

Sn (f ) = 24kT

gm3, 4

2 1

[1 +

]

3 gm1, 2

gm1, 2

(4.35)

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

45

Figure 4.12: Pole-zero location of two stage op amp with current buffer

compensation technique

and calculate the transconductance gain of transistors M1,2 from Equation

4.36

gm1, 2 =

16 kT

3 Sn (f )

(4.36)

In those cases, a more relaxed input referred noise voltage can be calculated

to obtain the input pair gm1,2. This requirement comes from comparing

the thermal noise of the capacitor at the output over the bandwidth of the

amplifier. This gives the following requirement

r

vno

kT /C

=

(4.37)

U GB

U GB

The input referred noise can then by a factor of 4-5 larger than the

value

q of expression in Equation 4.37. Therefore approximatelySn (f ) (4/C

5) kT

.The larger the noise specification, the smaller the transconductance

U GB

of the input pair is required.

46

4.2.3

Voltage buffer

and allow the feedback compensation current to flow from the output to

the node-1. Figure 4.13 shows an op-amp topology with an NMOS source

follower. Notice the way the compensation current is fed back from the

output to the node-1 in these op-amps. These topologies eliminates the

RHP zero although at the cost of additional power and transistors. Also due

to the use of a source follower, there exists a fixed DC voltage drop, equal to

VGS (or VSG for the PMOS buffer case) in the feedback signal path. This

voltage drop reduces the output swing, as a high output swing may triode

the source follower device and break down the compensation. The location

of the first pole remains the same as in the case of Miller compensation, and

[6] The design

the second pole also remains relatively unchanged atp2 gm2

C2

procedure for voltage follower is same as the nulling resistor.

47

48

Chapter 5

Layout Design

Today, layout design is carried out in an environment that is ever changing. The software tools and approaches, computing platforms, the companies

providing these tools, the customers we serve, the applications that are being implemented, and the market pressures we face are all changing year by

year. These changes make this industry an interesting one in which to be

involved.[19] However, lets not forget that the fundamental concepts behind

producing quality layout are based on physical and electrical properties that

never change

5.1

We define layout design as follows: The process of creating an accurate physical representation of an engineering drawing (netlist) that conforms to constraints imposed by the manufacturing process, the design flow, and the performance requirements shown to be feasible by simulation. Lets look at this

definition in greater detail as there are numerous implications buried within.

A process: First and foremost, layout design is a process with many

steps that should be followed in a logical order for optimal results. For example, the process of layout design may include setting up a database or

suite of tools with the appropriate layers; defining the oorplan of each cell or

chip; and/or running verification checks in the proper order.

49

Creation: Design and creation are usually synonymous, and layout design is no exception. Implementing one schematic in two different technologies usually results in layouts that look quite different, thus demonstrating

the creative nature of the trade. In the same way, a schematic that will be

used in two different regions of the chip may result in two different architectures, adapted to their geographical location.

Accuracy: Although layout design is a creative process, we must not forget that the first requirement of the final layout must be that it is equivalent

on a transistor- by-transistor basis to the engineering drawing. Redesigning

the configuration of transis- tors to improve the circuit is not the role of the

layout designer unless you plan to take over (or already have taken over) the

circuit design task as well.

Physical representation: CMOS ICs are made using an extremely

complicated process that in the end results in tiny transistors and wires being constructed and connected on a silicon substrate. Layout design is the

art of drawing these transistors and wires as they look like in silicon; thus,

the layout can be thought of as the physical representation of the circuit.

Engineering drawing: This may sound a bit old-fashioned, but it is ac- curate.

Transistor-level or gate-level schematics : have historically been the

primary drawing and in many companies they remain so. Fancier methodologies these days result in some layout designers receiving a large text-based

file called a netlist. However, in order for humans to understand a netlist,

it is usually accompanied by a block-level schematic or drawing. Engineers

(or equivalents) are the main providers of the drawings, but as the indus- try

changes this may change as well.

Conform: By conforming, we mean meeting the requirements of and not

necessarily the smallest or best design possible. There are many trade-off to

be made in the process of design: re- liability, manufacturability, exibility,

and (perhaps most importantly) time to market, to name a few. Of course,

there are minimum requirements that have to be met, but to achieve the optimal design at the expense of the project schedule is not practical in todays

marketplace. Constraints im- posed by the manufacturing process: These

constraints include layout design rules such as the smallest width a metal

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

50

track can be, but also many other manufacturability or reliability guidelines

that will improve the overall quality of the layout. For example, in the case of

a metal track, a wider line may improve the manufacturability of the design

and thus should be used where space permits.

Constraints imposed by the design flow: These constraints include

guidelines established to enable all other tools that are to be used in the design ow to be able to eficiently use the completed layout. For example, some

routers like to have connections to cells on a regular pitch, while others do

not care. Another example is the methodology to add text to layout so that

the text can be used later for identification purposes. Constraints imposed

by the performance requirements shown to be feasible by simulation: An

engineer completing a circuit design with- out detailed knowledge of how the

circuit will be implemented in layout is required to make some assumptions.

For example, the engineer designing the circuit will not know the exact area

of the block without implementing the circuit in layout and so must make an

educated estimate based on the information available. The total area figure

may be important to know so that the maximum line length within the block

is also known. This normally cannot be avoided, and the trick is to try to

communicate these assumptions and thus constrain the layout accordingly.

In our example the total area esti- mate used by the circuit designer should

also be used by the layout designer as a target area, and differences from this

estimate on the low or high side should be fed back to the circuit designer

for re simulation.

5.2

effective sizes and electrical properties of the components to differ from those

intended by the designer. We may categorize these effects as being either

systematic variations, process variations, or random variations.

5.2.1

of a polysilicon resistor, the edges of the poly exhibit microscopic irregulari-

51

ties that give them a slightly ragged appearance. Some of these irregularities

stem from the granularity of the polysilicon, while others result from imperfections in the photoresist. The granularity of the polysilicon also causes

variations in poly thickness and resistivity.[19] Other types of devices exhibit

different types of fluctuations, but all of these fall into one of two categories:

fuctuations that occur only along the edges of the device and fuctuations

that occur throughout the device. The former are called peripheral fuctuations because they scale with device periphery, while the latter are called

areal fluctuations because they scale with device area. The nature of these

scaling relationships can be deduced from statistical arguments.

5.2.2

Process Biases

in the layout database because the geometries shrink or expand during photolithography, etching, diffusion, and implantation. The difference between

the drawn width of a geometry and its actual measured width constitutes

the process bias. Process biases can introduce major systematic mismatches

in poorly designed components.

5.2.3

Systematic Variations

can cause the effective sizes of the components to differ from the sizes of the

glass layout masks. Some examples of these effects are illustrated in Fig. 5.1

For example, Fig. 5.1(a) shows how an effective well area will typically be

larger than its mask due to the lateral diffusion that occurs not just during ion

implantation but also during later high-temperature steps, such as annealing.

Another effect, known as overetching, occurs when layers such as polysilicon

or metal are being etched. Figure 5.1(b), for example, shows overetching that

occurs under the SiO2 protective layer at the polysilicon edges and causes

the polysilicon layer to be smaller than the corresponding mask layout. A

third effect is shown in Fig. 5.1(c), where an -channel transistor is shown

as we look along the channel from the drain to the source. The width of

the transistor is defined by the width of the active region (as opposed to the

width of the polysilicon line), and this width is determined by the separation

of the isolation oxide between transistors (i.e. the field-oxide in a LOCOS

process). The p+ field implant under the field-oxide causes the effective

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

52

This increased doping raises the effective transistor threshold voltage near the

sides of the transistors and therefore decreases the channel- charge density

at the edges. The result is that the effective width of the transistor is less

than the width drawn on the layout mask.[20]

Figure 5.1: Various two-dimensional effects causing sizes of realized microcircuit components to differ from sizes of layout masks.

5.3

1.

2.

3.

4.

5.

6.

7.

8.

Orient transistors in the same direction.

Keep the layout of the transistors as compact as possible.

Whenever possible use Common centroid layouts.

Place transistors segments in the areas of low stress gradients.

Place transistors well away from the power devices.

For current matching keep overdrive voltage large.

For voltage matching keep overdrive voltage smaller.

53

5.4

Layout Techniques

1. Use a predefined template for PMOS and NMOS transistor placement.

The architecture of a cell should be defined beforehand, and this tem- plate

should encapsulate the basic oorplan of a group of cells. Figure 5.2 shows

an example of a cell template Use transistor fingering for large and critical

transistors. A cell template similar to Figure 5.2 defines the maximum width

of a transistor by the cell height. How do we lay out a transistor that exceeds

this height? The solution is to finger the transistor into multiple transistors

that are connected in parallel.

Figure 5.3 shows three equivalent layout designs of a transistor that is

100mm wide.

2. There is an advantage with an even number of fingers: the active ca- pacitance is less, because the drain region is surrounded with gate poly instead of

field. Another reason to use fingering is to optimize the resistance of the gate

poly along the width of the transistor. Since the gate poly is driven from one

end and gate poly is resistive, there may be reason to have a guideline that

states the maximum width of a single finger. Fingering is the only way to

meet this guideline for large transistors. Fingering multiple transistors that

are connected in series is trickier. Figure 5.4 shows an example of fingering

a two-input NAND gate. Fingering the PMOS devices is straightforward;

however, fingering the series NMOS devices is more difficult because the order of connectivity of the devices must be maintained.

3. Share power supply nodes to save area. Sharing nodes whenever possible is a concept that is easy to understand. Power supply nodes are most

easily shared because they are very common and easy to connect. Very significant area savings can be achieved. The main reason that area is saved is

that both sides of a row of contacts are used and there is no need to space two

active regions apart from each other. Figure 5.5 illustrates this technique.

Note that power nodes can be shared be- tween transistors of different widths

with a slight overhead of inserting a poly to active space at the end of the

smaller transistor.

4. Determine minimum number of contacts for source and drain connections. One simple rule might be to as many as you can using the minimum

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

54

design rule between two contacts. This guideline is most re- liable and maximizes the performance of the transistor. The downside of this approach is

that the routability over the transistor is limited. If increased routability is

required and accounted for in the circuit design, fewer than the maximum

number of contacts may be optimal for the overall layout design. This approach must be considered carefully and accounted for in the circuit design

process.

5.5

Multifinger Transistor

Wide transistors are usually folded so as to reduce both the S/D junction

area and the gate resistance. A simple folded structure such as that in

Fig.5.7 (a) may prove inadequate for very wide devices necessitating the use

of multiple fingers[Fig.5.7 (b)]. As a rule of thumb, the width of each

finger is chosen such that the resistance of the finger is less than the inverse

transconductance associated with the finger .In low-noise applications, the

gate resistance must be one-fifth to one-tenth of .

55

5.6

Symmetry

Symmetry must be applied to both the devices of interest and their surrounding environment. Symmetries in fully differential circuits introduce input referred offsets, thus limiting the minimum signal level that can be detected. While some mismatch is inevitable inadequate attention to symmetry in the layout may result in large offsets. Symmetry also suppresses the

ef- fect of common-mode noise and even-order nonlinearity. Let us consider

the differential pair of Fig.5.8 as the starting point. If, as depicted in Fig.5.9

, the two transistors are laid out with different orientations, the match- ing

greatly suffers because many steps in lithography and wafer processing behave differently along different axes. Thus, one of the configurations in

Figure 5.10 and Figure 5.11 provides a more better solution.

When laying out any device the key is symmetry, especially when laying

out fully-differential components. For matched devices, use interdigitized or

common centroid layout techniques. A matched device is one where two

transistors need to have exactly the same geometries. Examples include

current mirrors and differential pairs. An interdigitized layout is shown in

Figure 5.12. Notice that the two transistors have been split into smaller

size devices and interleaved. This layout minimizes the effects of process

variations on the parameters of the transistors. The idea behind splitting

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

56

a transistor up is to average the process parameter gradient over the area

of the matched devices. For example, the process variation of KP and of

the transconductance parameter on the wafer is characterized by a global

variation and a local variation.[20] Global variations appear as gradients on

the wafer as in Figure 5.13. However, local variations describe the random

change in the parameter from one point on the chip to another nearby point.

By using layout techniques such as interdigitized and common-centroid, the

process variation can hopefully be averaged out among the matched devices.

When laying out wider matched transistors the common-centroid layout may

be a better choice. This layout technique is illustrated in Figure 5.14 and

Figure 5.15 for the case of 8 matched M1 and M2 transistors of a differential

pair.

57

58

59

60

b) Horizontal expansion c) Interdigitized layout (Drain areas are different.

Common centroid.) d) Interdigitized layout (Drain areas are equal. Not

common centroid.)

61

62

63

Chapter 6

Simulation Results and Layout

This section expands on the simulation results obtained from the different

types of the compensation techniques for two stage op amp.The amplifier

is to be powered from 1.8V power supply. The Unity Gain Bandwidth targeted was 1GHz and the corresponding Phase Margin was 600 .Based on the

proposed compensation technique a CMOS op amp has been designed and

simulated in a TSMC 130nm technology.

6.1

Nulling Resistor

In Figure 6.1 shows the schematic of the Two stage op amp with the nulling

resistor.The summary of the result is reported in the Table 6.1.

The AC response of the two stage op amp is shown in the below Figure 6.2.

The dc gain achieved is 61dB and the UGB is 235MHz and the corresponding

Phase Margin is 60.150 with the power dissipation of 1.94mW.

6.1.1

Summary

in below table.

6.2

Voltage Buffer

In Figure 6.3 shows the schematic of the Two stage op amp with the nulling

resistor.The summary of the result is reported in the Table 6.2

64

Table 6.1: Summary of Two stage op amp with nulling resistor

Parameter Nulling resistor

DC Gain

61dB

UGB

235MHz

PM

60.15deg

Cc

1.2pF

Pdiss

1.94mW

The AC response of the two stage op amp is shown in the below Figure 6.4.

The dc gain achieved is 54dB and the UGB is 478MHz and the corresponding

Phase Margin is 60.90 with the power dissipation of 2.22mW.

6.2.1

Summary

in below table.

65

Figure 6.2: AC response of the two stage op amp with the Nulling resistor

Table 6.2: Summary of Two stage op amp with voltage buffer

Parameter Voltage Buffer

DC Gain

54dB

UGB

478MHz

PM

60.9deg

Cc

0.7pF

Pdiss

2.22mW

6.3

Current Buffer

In Figure 6.5 shows the schematic of the Two stage op amp with current

buffer.The summary of the result is reported in the Table 6.3.

The AC response of the two stage op amp is shown in the below Figure 6.6.

The dc gain achieved is 59.8dB and the UGB is 1GHz and the corresponding

Phase Margin is 61.20 with the power dissipation of 2.66mW.

6.3.1

Step Response

In Figure 6.6, a step from ground to VDD is applied at the input with unity

feedback configuration.As we measured,The amplifier slew rate is 707V /us

66

as shown in Figure 6.7.

6.3.2

Settling Time

The Unity gain follower configuration of two stage op amp with current

buffer is also use for settling time and peak over shoot measurement.This

is the length of time for the output voltage of an op amp to approach and

remain within a certain tolerance of its final value. This is usually specified

for a full scale input step. Op amp is baised as shown in Figure 6.5.Figure

6.7 shows the settling time for different tolerance value.

The below Table shows the settling time with the different tolerance

values.

Table 6.3: Variation of settling time of op amp with different tolerance values

Tolerance(%) Settling time(ns)

0

20

1

17.95

2

3.4

3

3.2

67

Figure 6.4: AC response of the two stage op amp with the Voltage buffer

6.3.3

Design Parameters

Table 6.4 lists the relevant transconductance and parasitic values used during

calculation and the achieved values during simulation and compares the pole

locations.

Table 6.4: Design Parameters

Parameter Designed

Simulated

gm1,2

1.428mA/V 1.8087mA/V

gmc

1.428mA/V 1.676mA/V

gm5

4.356mA/V 6.53mA/V

P1

740kHz

783.84kHz

P2,3

2GHz

2.66GHz

6.3.4

Summary

in below table.

68

Table 6.5: Summary of Two stage op amp with current buffer

Parameter Current Buffer

DC Gain

59.8dB

UGB

1GHz

PM

61.12deg

Cc

0.4pF

Pdiss

2.66mW

Settling Time

3.4ns

Slew Ratw

707V/us

6.4

Comparision

The below table shows the comparison of the different types of compensation

techniques of two stage op amp.

69

Figure 6.6: AC response of the two stage op amp with the Current buffer

Figure 6.7: Step Response of two stage op amp with Current buffer

70

Figure 6.8: Slew Rate of two stage op amp with Current buffer

71

stage op amp

Parameter Nulling Resistor Voltage Buffer Current buffer

UGB

235MHz

478.84MHz

1GHz

DC Gain

61dB

54.4dB

59.8dB

PM

60.15 deg

60.9 deg

61.12deg

Cc

1.2pF

0.7pF

0.4pF

Pdiss

1.94mW

2.22mW

2.66mW

6.5

Layout

This prototype design of the indirect feedback frequency compensation is implemented in TSMC 130nm technology. In analog design, matching is very

important. Particularly, Op Amps need high matching to achieve low input

referred offset and high noise rejection. The matching between transistors is

mainly dependent on

1. Size of transistors

2. Shape of transistors

3. Orientation of transistors

The below Figure shows the Layout of a Two stage op amp with the

current buffer compensation technique.Both the schematic and Layout is

matched perfectly.

72

Figure 6.10: Layout of the two stage op amp with the Current buffer

73

Chapter 7

Conclusion and Future scope

7.1

Conclusion

with their pros and cons in order for a designer to choose the appropriate

scheme for a particular application. This thesis further explores a creative

indirect feedback compensation method which overcomes the major drawback of bandwidth narrowing by the widely used polesplitting method. It

can improve the phase margin as well as extend the bandwidth of the Op

Amp. The indirect feedback method can be easily applied to the existing

popular two gain stage Op Amp architectures with very little alteration.

The mathematical derivation and circuit simulation demonstrate the advanced properties and improved performance of this feedforward compensation technique.The three compensated OTA is compared with gain, UGB,

Power dissipation,Phase Margin.

The indirect feedback technique discussed in this thesis is a practical and

superior compensation scheme for Op Amps, and results in amplifiers with

much higher speeds and smaller areas.The two stage op amp with current

buffer compensation achieved is 1GHz UGB and corresponding phase margin

of 61.120 while driving a capacitive load of 1pF and DC gain of 59.8dB.We

can observe that Cc of current buffer is reduced to 0.4pF when compared

to Cc of nulling resistor of 1.2pF. Current buffer compensated OTA there

is improvement in the gain, UGB, PM and area requirement is also less

compared to nulling resistor compensated OTA.

74

7.2

Future Scope

As a part of future research the compensation method developed for the two

stage amplifier can be extended to realize a three stage and multi-stage amplifiers. A formal derivation and design procedure for multi stage amplifier

employing can be developed using the indirect feedback frequency compensation technique.

75

Bibliography

[1] X. H. Fan, C. Mishra, and E. Sanchez-Sinencio, Single miller capacitor

frequency compensation technique for low-power multistage amplifiers

IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 584-592, 2005.

[2] P. R. Gray, and R. G. Meyer,, Analysis and design of analog integrated

circuits, ,3rd ed., New York: Wiley, 1993.

[3] G. Palmisano, and G. Palumbo, A compensation strategy for two-stage

CMOS opamps based on current buffer IEEE Transactions on Circuits

and Systems I-Fundamental Theory and Applications, vol. 44, no. 3, pp.

257-262, Mar, 1997.

[4] B. K. Ahuja, An Improved Frequency Compensation Technique for

CMOS Operational-Amplifiers IEEE Journal of Solid-State Circuits,

vol. 18, no. 6, pp. 629-633, 1983

[5] K. N. Leung, and P. K. T. Mok,Analysis of multistage amplifierfrequency compensation IEEE Transactions on Circuits and Systems

I-Fundamental Theory and Applications, vol. 48, no. 9, pp. 1041-1056,

Sep, 2001.

[6] H. Lee, and P. K. T. Mok, Active-feedback frequency-compensation technique for low-power multistage amplifiers IEEE Journal of Solid-State

Circuits, vol. 38, no. 3, pp. 511-520, 2003.

[7] D.A.Johns and K.Martin, Analog Integrated Circuit Design, New

York:John Wiley and Sond,Inc.,1997.

[8] A. Pugliese, F. A. Amoroso, G. Cappuccino et al., Design approach for

fastsettling two-stage amplifiers employing current-buffer Miller compen-

sation Analog Integrated Circuits and Signal Processing, vol. 59, no.

2, pp. 151-159, 2009.

[9] H. Mahattanakul, and J. Chutichatuporn, Design procedure for twostage CMOS opamp with flexible noise-power balancing scheme IEEE

Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 8,

pp. 1508-1514, 2005.

[10] R. J. Reay, and G. T. A. Kovacs,, An Unconditionally Stable 2-Stage

CMOS Amplifier IEEE Journal of Solid-State Circuits, vol. 30, no. 5,

pp. 591-594, 1995.

[11] A. Pugliese, F. A. Amoroso, G. Cappuccino et al., Design approach for

fastsettling two-stage amplifiers employing current-buffer Miller compensation Analog Integrated Circuits and Signal Processing, vol. 59, no.

2, pp. 151-159, 2009.

[12] A. Pugliese, F. Amoroso, G. Cappuccino et al., Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation Electronics Letters, vol. 43, no. 23, pp. 1257-1258, 2007.

[13] M. Loikkanen, and J. Kostamovaara, Improving capacitive drive capability of two-stage op amps with current buffer Proceedings of the 2005

European Conference on Circuit Theory and Design, Vol 1, pp. 99-102,

2005.

[14] Mahattanakul, J., Design Procedure for Two-Stage CMOS Operational

Amplifiers Employing Current Buffer IEEE Transaction on Circuits

and Systems II- Express Briefs, vol. 52, no. 11, Nov 2005.

[15] Saxena, V. and Baker, R. J., Indirect Compensation Technique for LowVoltage Op-Amps Proceedings of the 3rd Annual Austin Conference on

Integrated Systems and Circuits (ACISC), May 7-9, 2008.

[16] Behzad Razavi Design of analog cmos integrated circuits McGrawHill, 2001.

[17] Phillip E. Allen and Douglas R. Holberg CMOS analog circuit Design

McGraw-Hill, 2001.

77

[18] Baker, R.J., CMOS: Circuit Design, Layout, and Simulation 2nd Ed.,

Wiley Inter science, 2005.

[19] Dan Clein, CMOS IC LAYOUT Concepts, Methodologies, and Tool

2nd Ed., Wiley Inter science, 2005.

[20] Alan Hastings, The Art of Analog Layout (Sencond Edition) 2007.

IEEE Journal of Solid-State Circuits, vol. SC-14, Issue 6, Dec.1979,

pp.1111-1114. 1996.

[21] Pelgrom, M. J. M., Duinmaiger, A. C. J., andWelbers, A. P. G, Matching Properties of MOS Transistors 2007. IEEE J. Solid-State Circuits,

Vol. SC-24, Oct. 1989, pp. 1433-1439.

78

APPENDIX A

Roots of quadratic Equation

A second-order polynomial often appears in the denominator or numerator of

a transfer function, and the zeros of this polynomial are the poles or zeros of

the transfer function. In this appendix, the relationships between the zeros of

a quadratic and its coefficients are explored for a few specific cases of interest.

Also, the conditions under which a dominant root exists are derived.

Consider the roots of the quadratic equation

as2 + bs + c = 0

(7.1)

the two roots of this equation, r1 andr2 are given by the quadratic formula:

b b2 4ac

(7.2)

r1,2 =

2a

where it is understood that the square root of a positive quantity is positive. Factoring b out of the square root and rearranging gives

r

4ac

b

(7.3)

r1,2 = (1 1 2 )

2a

b

b

(1 D)

(7.4)

2a

The quantity under the square root in (7.3) has been replaced by D in

(7.4), where

r1,2 =

4ac

(7.5)

b2

Now, consider the locations of the roots if coefficients a, b, and c all have

the same sign. In this case, both roots are in the left half-plane (LHP), as

will be shown next. First, note that if all the coefficients have the same sign,

then

D =1

b

>0

2a

(7.6)

4ac

>0

(7.7)

b2

Let us divide the above equation(7.7) into two different regions.First,if

0<

4ac

<1

b2

(7.8)

1 D are both positive.As a result, the roots are both negative and real,

b

because 2a

< 0.

Now consider the other region for (7.7),which is

4ac

>1

(7.9)

b2

conjugate with a real part of b/2a, which is negative.So the roots are again

in the LHP.LHP. Therefore, when coefficients a, b, and c all have the same

sign, both roots are in the LHP. Next, consider the locations of the roots if

coefficients a and b have have the same sign and c has a different sign. In this

case, one real root is in the right half-plane (RHP) and the other is in the

LHP. To prove this, first note from(7.5) that D 1 here because 4ac/b2 < 0.

Therefore both roots are real and D > 1, so

1+

and

D>0

(7.10)

D<0

(7.11)

1+

Substituiting into (7.2), one root will be positive and the other negative(

the sign of b/2a is negative here).

Finally, let us consider the conditions under which LHP roots are real

and widely spaced. From (7.2), real LHP roots are widely spaced if

or

b

b

(1 + D) << (1 D)

2a

2a

1 + D >> 1 D

(7.12)

(7.13)

Substituting the expression for D in (1.5) into (1.9) and simplifying leads

to an equivalent condition for widely spaced roots, which is

4ac

<< 1

b2

under this condition , one root is

4

(7.14)

80

r2 =

b

b

b

(1 + D) (1 + 1) =

2a

2a

a

(7.15)

b

(1 D)

2a

r

b

4ac

r1 = (1 1 2 )

2a

b

b

4ac

r1 = (1 (1 2 ))

2a

2b

r1 =

r1 =

c

b

(7.16)

1x1

x

2

has been used. Here,|r1 | << |r2 | because |r1 | cb << ab |r2 |.If there

roots are poles,r1 corresponds to the dominant pole, and r2 gives the nondominant pole.

81

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