Recent Development of Finfet Technology For Cmos Logic and Memory

Recent Development of
FinFET Technology for CMOS

Logic and Memory
Chung-Hsun Lin
EECS Department
University of California at Berkeley
Outline
Why FinFET
Recent FinFET Develop
Triple-gate FinFET, Omega FET, Nanowire FinFET,

Independent gate, Multi-channel FinFET, Metal-gate/high-K
FinFET, Strained FinFET, Bulk FinFET
Memory
FinFET process
Unique features of FinFET
Mobility, workfunction engineering, corner effect, QM,
volume inversion
Issues
DRAM, SONOS, SRAM
Conclusion
NTUEE Seminar 2006/04/29
Chung-Hsun Lin - 2
MOSFET Scaling
ITRS 2001 Projection
The first transistor

1947
The Power5
microprocessor
Technology Scaling
GATE LENGTH (nm)
100
10
LOW POWER
HIGH PERFORMANCE
1
2000
2005
2010
2015
2020
YEAR
Investment
Better Performance/Cost
Same transistor
design concept
Market Growth
Chung-Hsun Lin - 3
Scaling : Moores law

Technology Drivers
Reduced cost /
function
Improved
performance
Greater circuit
functionality
Source: Intel
Chung-Hsun Lin - 4
Bulk-Si MOSFET Scaling Issues
Leakage current is the primary barrier to scaling

To suppress leakage, we need to employ:
Higher body doping lower carrier mobility, higher
junction capacitance, increased junction leakage
Thinner gate dielectric higher gate leakage
Ultra-shallow S/D junctions higher Rseries
Desired characteristics:
- High ON current (Idsat)

- Low OFF current
S
D
Source
courtesy of Prof. Kuroda

Keio University
Substrate
Lg
Tox
Gate
Leff
Xj Drain
Nsub
Chung-Hsun Lin - 5
Issues for Scaling Lg to <25 nm
VT variation (statistical dopant fluctuations)
Leakage
Incommensurate gains in Idsat with scaling
limited carrier mobilities
parasitic resistance
Chung-Hsun Lin - 6
Advanced MOSFET Structures
Leakage can be suppressed by using a thin body
Double Gate
Ultra-Thin Body
Gate
Source
SOI
Drain
SiO2
TBOX
TSi
Source
Gate 1
Vg
SOI
Drain
TSi
Tox Gate 2
Silicon Substrate
Chung-Hsun Lin - 7
Thin-Body MOSFETs
Control short-channel effects with Tbody

No channel doping needed!
Relax gate oxide (Tox) scaling
Double-Gate is even more effective
Scalable to 10nm gate lengths
Gate
Source
Gate
Drain
Source
Buried Oxide
Substrate
Ultra-Thin Body
Tbody
Drain
Gate
Double-Gate
Chung-Hsun Lin - 8
Electric Field Reduction
Reduced vertical field

in DG and UTB
E eff =
Gate
Qinv + Qdepl
Si
No doping =
No Qdepl!
Expected to benefit:
Mobility
Gate Leakage
Bulk
Gate
Qinv
Qdepl
Qinv
Buried Oxide
Substrate
Thin-Body
Chung-Hsun Lin - 9
Thin-Body MOSFETs
Control short-channel effects with Tbody
Relax gate oxide (Tox) scaling

Ion
Cload
Improved mobility
DG
Lower vertical electric field
Bulk
No impurity scattering
Improved swing
Vgate
Better control of SCE
Lower VT
No depletion or junction capacitance
Idrain
Double-Gate is even more effective
Scalable to 10nm gate lengths
Potentially less Vt scatter (dopant fluctuation)
Chung-Hsun Lin - 10
Circuit level benefits

Thin body devices
9
9
9
9
Good control of SCE

Steep Sub-threshold
swing
Higher Idsat
Lower Capacitance - No
Cjunc and Cdepl
Better CV/I delay at
lower power
FO4 Inverter Delay [ps]
Bulk
UTB
DG
20
10
8
6
4
2
Tbody,UTB
= 5nm
Tbody,UTB
< 5nm
50
35
25
18
Technology Lgate [nm]
Source: Leland Chang
Chung-Hsun Lin - 11
Double-Gate MOSFETs
Gate 1
S
D
Gate 2
Current flow
Planar DG
MOSFET
Current flow
S
D
Gate 2
D
Gate 1
Gate 2
Current flow
FinFET
Gate 1
Vertical DG
MOSFET
Chung-Hsun Lin - 12
Multi-Gate FinFET
Drain
Drain
Gate
Gate
Gate
Source
Gate
Gate
Gate
Source
Drain
Drain
Drain
Gate
Planar
DG-FET
Source
90
Rotation
Source
FinFET
Rotation allows for self-aligned gates

Layout similar to standard SOI FET
Chung-Hsun Lin - 13
FinFET Process Flow

Si Fin
SiO2
Resist
BOX
Poly
SOI Substrate
Fin Patterning
Poly Gate Deposition/Litho

NiSi
Si3N4
Spacer
Gate Etch
Spacer Formation
S/D Implant + RTA

Silicidation
Chung-Hsun Lin - 14
FinFET Device Structure
Source
Gate
Drain
All features defined by optical lithography

and aggressive trimming
Chung-Hsun Lin - 15
10nm FinFET TEM
NiSi
Poly-Si
220
SiO2 cap
Lg=10nm
Si Fin
BOX
Chung-Hsun Lin - 16
10nm FinFET I-V
Dual N+/P+ poly gates:

- Need VT control
Low DIBL
NMOS:
PMOS:
120 mV/V
71 mV/V
Good SCE despite thick

Tox (27 EOT) & Wfin
(26nm)
- Due to large S/D
doping gradient &
spacer thickness
-3
10
Drain Current [A/m]
Vd=-1.2V
Vd=1.2V
0.1V
-0.1V
-5
-5
10
10
-7
10
-7
10
PMOS
NMOS
S=125
mV/dec
S=101
mV/dec
-9
10
-3
10
-9
-1
10
Gate Voltage [V]
Chung-Hsun Lin - 17
Acceptable DIBL and

subthreshold slope down
to below 20nm Lgate
Nearly ideal (60mV/dec)
subthreshold slope at
long Lgate
NMOS better than PMOS
due to slower As
diffusion
160
160
NMOS
PMOS
W =26nm
120
120
fin
80
80
40
40
20
40
60
80
100
DIBL (mV/V)
Subthreshold Slope (mV/dec)
Short-Channel Effects
Gate Length (nm)
Chung-Hsun Lin - 18
Orientation
Dra
in
<100>
So
urc
e
Gate
(110)
(100)
~(111)
(110)
(110)
Surface
<110>
Rotation by 45 changes orientation from (110) to (100)

Intermediate rotation similar to (111)
Chung-Hsun Lin - 19
500
500
400
(100)
300
200
100
(111)
(110)
400
300
200
100
(110)
(111)
(100)
0
0.2 0.4 0.6 0.8 1.0
Effective Field [MV/cm]
Oxynitride
Oxynitride
Hole Mobility [cm /Vs]
Electron Mobility [cm /Vs]
How Mobility Changes
0.2 0.4 0.6 0.8 1.0

Effective Field [MV/cm]
By shifting away from (100):

e is degraded, h is enhanced
Can we benefit from changing the N/P ratio?
Chung-Hsun Lin - 20
Gate Delay
PMOS enhancement (20%)

is larger than NMOS
degradation (8%)
Net delay improvement
Trade off h and e
NOR: PMOS stack
h very important
Most improvement
NAND: NMOS stack

h less important
Least improvement
% Delay Speedup vs. (100)
20
Fanout=4
Lgate=35nm
h, e
15
NOR
10
Inv
5
NAND
Oxynitride
(100)
(111)
(110)
Orientation
(100) NMOS
(110) PMOS
Chung-Hsun Lin - 21
Optimized FinFET
Source
Gate
Gate
Drain
Source
Source
Drain
Drain
Drain
Source
(110) PMOS
(100) NMOS
Trade off layout area for performance

Chung-Hsun Lin - 22
FinFET Layout Area

(100)
(110)
(111)
o
o
45 N / 90 P
o
o
90 N / 45 P
Inverter
50
Layout Area [m ]
Layout Area [m ]
0.8
0.6
0.4
0.2
40
30
20
10
0.0
Idsatn,p=1.1mA
Idsatn,p=110mA
Non-(100) orientation saves area

Higher PMOS Idsat reduces drawn W
45 orientation is less area efficient for smaller W
These devices are small anywaydoes it matter?
Use only in critical path?
Chung-Hsun Lin - 23
Hybrid-Orientation-Technology (HOT)
Super HOT: SOI version

DSB: bulk version
Chung-Hsun Lin - 24
VT: What CMOS Needs
Need symmetrical VTs for

proper CMOS operation
Need low VTs for speed
VDD
Output
Inverter Response
VIN=
VTN
VIN=
VDD-VTP
Input
VDD
Chung-Hsun Lin - 25
Gate Work Function
0.4
0.2
VT=0.4V
0.6
N Poly
Threshold Voltage [V]
0.8
P Poly
VTn
-VTp
1.0
VT=0.2V
0.0
4.52eV
4.95eV
-0.2
4.2
4.4 4.6 4.8 5.0 5.2

Gate Workfunction [eV]
Single gate material

VTn = -VTp = 0.4V
N+/P+ Poly
VTn = -VTp = -0.2V
For low body doping,
desired M values are:
~ 4.5 eV for NMOS
~ 5.0 eV for PMOS
Need two separate work
functions for NMOS and
PMOS!
Chung-Hsun Lin - 26
Molybdenum M Engineering
by Ion Implantation
M can be lowered by
N+ implantation and
thermal anneal
M increases with
dose
energy
(N segregates to SiO2
interface & forms Mo2N)
P. Ranade et al., IEDM 2002
Anneal time = 15m except for 900oC (15s)

TMo = 15nm
Chung-Hsun Lin - 27
Mo-Gated FinFETs (PMOS)

Y.-K. Choi et al., IEDM 2002
-3
Drain Current, Id [A/um]
10
-5
10
-7
10
Lg=80nm, TSi=10nm
Vds=0.05V
Alternative technique:
Vt shift
Full silicidication (NiSi) of

n+/p+ Si gates
-9
10
-11
10
-13
10
-0.8
|Vt|=0.2V for lightly doped

body, and is adjustable
by N+ implantation
(J. Kedzierski et al., W. Maszara et al.,

Z. Krivokapic et al., IEDM 2002)
Mo
15
-2
MoN(N2=5x10 cm )
-0.6 -0.4 -0.2 0.0
Gate Voltage, Vg[V]
0.2
Potential issues include:

- dopant penetration
- thermal stability
- stress/adhesion
- gate dielectric reliability
Chung-Hsun Lin - 28
Corner Effect in Triple or More Gates

Corner Effect
Different Vth at corner region
Significant subthreshold leakage current
Strong corner radius, body doping dependence
B. Doyle et al., VLSI Tech., p. 133, 2003
Chung-Hsun Lin - 29
Corner Effect [1]

Vg=0.2 V
Vg=1 V z
z
y
G
S
2D current density distribution
4x10
z direction
y direction
z direction
y direction
0
3x10
2x10
1x10
10
15
20
Position (nm)
Current Density (A/cm )
DESSIS 3-D device

simulator
Ideal rectangular fin
shape
Nsub=1e15cm-3
Current Density (A/cm )
25
30
10
15
20
25
30
Position (nm)
Chung-Hsun Lin - 30
Corner Effect [2]

Nsub=5e18cm-3
2.0x10
2
)
Current Density (A/cm
Vg=0.2 V
flat
1.5x10
1.0x10
5.0x10
0.0
-0.015
-0.010
-0.005
0.030
0.025
0.020
0.015
0.010
is
0.000
X Ax
is
0.005
0.005
0.010
0.015
Ax
corner
0.000

z
20
20
2x10
20
1x10
0.030
0.025
0.020
0.015
0.010
-0.015
-0.010
-0.005
is
0.000
X Ax
is
0.005
0.005
0.010
0.015
Ax
Vg=1 V
20
3x10
Electron Density (cm
-3
4x10
0.000
Chung-Hsun Lin - 31
3D Simulation w/ Various Shape of Corner
Normalized Drain Current (A/m)
Lg=1m, Wsi=30nm, Hsi=30nm, Tox=1nm

R=0, 5, 10, 15m
1E-5
1E-7
1E-9
R=15nm
R=10nm
R=5nm
R=0nm
1E-11
1E-13
0.0
0.5
1.0
1.5
Gate Voltage (V)

2.0
Normalized Drain Current (A/m)
-5
8.0x10
-5
6.0x10
-5
4.0x10
R=15nm
R=10nm
R=5nm
R=0nm
-5
2.0x10
0.0
0.0
0.5
1.0
1.5
2.0
Gate Voltage (V)

Chung-Hsun Lin - 32
Short Channel Behavior

MG device with sharp corner shows better
short channel behavior than the rounded
corner
100
R=0nm
R=15nm
80
DIBL (mV/V)
60
40
20
200
400
600
800
1000
Gate Length (nm)

Chung-Hsun Lin - 33
Double-humps induced by cap transistor

30x30nm structure, Tox=3nm,
Lg=1mm, Nsub=5e18cm-3
Cap transistor induced lower Vt is
very significant.
It may attribute to thicker Tox, and
more partial depleted.
-6
4.0x10
dGm/dVg
Nsub=5e18cm
1E-7
-3
Drain Current (A)
-6
3.0x10
1E-5
30x30nm
Lg=1m, Tox=3nm
-6
2.0x10
-6
1.0x10
0.0
0.3
0.6
0.9
1.2
1.5
1.8
1E-9
1E-11
1E-13
1E-15
1E-17
0.0
Gate Voltage (V)
0.5
1.0
1.5
2.0
Gate Voltage (V)
Chung-Hsun Lin - 34
Volume Inversion [1]
Gate
Gate
T si
Gate
Gate
eDensity
eDensity
6.1E+13
6.1E+13
5.3E+13
5.3E+13
T si
4.5E+13
4.5E+13
3.6E+13
3.6E+13
2.8E+13
2.8E+13
2.0E+13
2.0E+13
sub
=10
15
cm
Oxide
-3
sub
=10
18
cm
-3
Oxide
The electron density distribution from the 3-D ISE

device simulator. Volume inversion is significant in
intrinsic channel SDG (left).
Chung-Hsun Lin - 35
Inversion charge sheet density (C/cm )
Volume Inversion [2]

Electric Potential (V)
0.6
15
-3
Nsub = 10 cm
0.5
0.4
0.3
0.2
0.1
0.0
s0, 10nm
s, 10nm
s0, 20nm
s, 20nm
0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (V)
1E-5
15
-3
Nsub = 10 cm
1E-7
1E-9
Tsi
1E-11
1E-13
Tsi = 10 nm
Tsi = 20 nm
1E-15
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
For intrinsic channel doping, volume inversion is valid and the

potential through the Si film is flat in the subthreshold region.
The inversion charge (current) in the subthreshold region is
proportional to Tsi.
Chung-Hsun Lin - 36
QM Surface Potential Correction
Undoped case
Chung-Hsun Lin - 37
I-V Verification
Model can predict both subthreshold and strong inversion

region well.
1E-6
Drain Current (A/m)
Drain Current (A/m)
1E-4
1E-8
1E-10
Symbols: 2D simulation
Lines: Model
Classic
QM
1E-12
1E-14
6.0x10
-5
5.0x10
-5
4.0x10
-5
3.0x10
-5
2.0x10
-5
1.0x10
-5
Symbols: 2D simulation
Lines: Model
Classic
QM
0.0
0.5
1.0
1.5
Gate Voltage (V)

2.0
0.0
0.5
1.0
1.5
2.0
Gate Voltage (V)

Chung-Hsun Lin - 38
S/D Series Resistance Issue
J. Kedzierski et al., IEDM 2001
S/D series resistance will degrade the performance of thin body

device
Can be improved by the selective Si epitaxy raised S/D
Chung-Hsun Lin - 39
Outline
Why FinFET

Memory
FinFET process
volume inversion
Issues
DRAM, SONOS, SRAM
Conclusion
Chung-Hsun Lin - 40
Triple-Gate Transistor
B. Doyle et al., VLSI Tech. 2003
Chung-Hsun Lin - 41
Omega-Gate Transistor
Chung-Hsun Lin - 42
5nm Nanowire FinFET
Chung-Hsun Lin - 43
Independent Gate FinFET
Control the threshold voltage

Ideal rectangular shape of Si fin
Chung-Hsun Lin - 44
Independent Gate FinFET
Chung-Hsun Lin - 45
Multi-Channel FinFET
Chung-Hsun Lin - 46
Metal Gate FinFET
Chung-Hsun Lin - 47
Metal-Gate FinFET
K.G. Anil et al., VLSI Tech. 2005
Vth adjustment
Improvement of Ion
Chung-Hsun Lin - 48
TiN/HfO2 FinFET
Vth adjustment
Reduce Gate leakage
N. Collaert et al., VLSI Tech. 2005
Chung-Hsun Lin - 49
Inverted T Channel (ITFET)
UTB + FinFET
Continuous effective width
L. Mathew et al., IEDM 2005
Chung-Hsun Lin - 50
Strained FinFET
25% drain current enhancement of PFET by introducing

recessed Si0.8Ge0.2 S/D
P. Verheyen et al., VLSI 2005
Compressive stress and raised S/D
Chung-Hsun Lin - 51
Impact of Gate-Induced Strain

MuGFETs with TiSiN gate (+3GPa stress as deposited)
500
400
400
4%
(100) metal
(110) metal
(100) poly ref
(110) poly ref
300
(100) metal
(110) metal
(100) poly ref
(110) poly ref
10%
300
200
59%
200
100
100
NMOS
0
0
0.2
0.4
0.6
8%
PMOS
0
0.8
0.2
Stress [MPa]
yy
zz
Experiment
y
Inverse PR Model
-540
-290
0.6
0.8
Mobility Enhancement [%]
Eeff=0.4MV/cm
xx
0.4
-1900
(100)
NMOS
(110)
NMOS
(100)
PMOS
(110)
PMOS
59
10
59
-1
10
Chung-Hsun Lin - 52
Issue of Fin Formation

K. Endo et al., IEDM 2005
Neutral beam etching can accomplish damage (defect) free fabrication

of high aspect ratio fin.
Higher mobility is obtained in NB device due to atomically-flat surface
Chung-Hsun Lin - 53
Sidewall Spacer Transfer (SWT) Process
Both gate and fin are formed by SWT

SiN is selected as hard mask material
for Si RIE on top of fin
A. Kaneko et al., IEDM 2005
Can be used as the CMP stopper during

poly gate planarization (important for
gate SWT)
Suppress the agglomeration of Si fin
during selective Si epi
Prevent the leakage of the top corner
Used as RIE stopper in the gate RIE
process
Chung-Hsun Lin - 54
SWT Process
The threshold voltage

uniformities for SWT
FinFETs of 15nm fin and
15nm gate length over
the wafer is better than
ArF and EB lithography
Chung-Hsun Lin - 55
Selective Gate Sidewall Spacer Formation
Chung-Hsun Lin - 56
FinFET on Bulk Si Substrate
Bulk FinFET has the advantages of cheaper wafer cost, ease of

combination with conventional bulk CMOS.
K. Okano et al., IEDM 2005
Chung-Hsun Lin - 57
Characteristics of Bulk FinFET
Better subthreshold swing

Better short channel control
Negligible body effect
T. Park et al., VLSI 2003
Chung-Hsun Lin - 58
Outline
Why FinFET

Memory
FinFET process
volume inversion
Issues
DRAM, SONOS, SRAM
Conclusion
Chung-Hsun Lin - 59
DRAM application of Bulk FinFET
Chung-Hsun Lin - 60
DRAM application of Bulk FinFET
Negative word line bias is introduced due to lower VT
Chung-Hsun Lin - 61
NWL Scheme
Lower VT (doping concentration) FinFET combined

with NWL scheme can provide lower leakage and
higher performance
NWL bias is critical to refresh fail bit
Chung-Hsun Lin - 62
SONOS Application of FinFET
J. Hwang et al., TSMC 2005
High Performance FinFET SONOS flash cells

with gate length of 20nm is demonstrated.
Program/erase window of 2V with high P/E
speed (Tp=10ms, TE=1ms)
Chung-Hsun Lin - 63
SONOS Application of FinFET
Excellent endurance: up to
10K P/E cycles
Good retention: 1.5V after
10years retention time
J. Hwang et al., TSMC 2005
Chung-Hsun Lin - 64
FinFETs based 6-T SRAMs

load
WL
V DD
M2
M5
access
BL
M4
VR
VL
M1
M6
M3
pulldown
BL
Large fraction of
the total chip area
will be memory1
Leakage problem
Limited by impact
of variations
FinFETs offer good control of short channel effects

1Source
: Ranganathan, 2000
Chung-Hsun Lin - 65
Static Noise Margin

The minimum noise
voltage at the storage
node needed to flip the
state
Large SNM is desirable
Make pulldown device

stronger relative to
access transistor
Source: Bhavnagarwala, 2001
Chung-Hsun Lin - 66
Probability
SNM spread with variations

0.3
Tsi = 11nm
0.25
Tsi = 15nm
Thicker Si body better

Higher performance
due to Rs limitations
0.2
0.15
0.1
0.05
Greater noise
immunity (SNM)
Lesser spread in
SNM
0
0.1
0.15
0.2
SNM (V)
0.25
Taurus Device Simulation

Chung-Hsun Lin - 67
SNM spread with variations
Probability
0.3
TSi = 15nm
(110) / 1fin
(100 )/
2 fins
0.2
(100)/
1fin
To improve SNM
a)
Wpulldown - 2 fins
b)
Laccess
c)
0.1
eff, pulldown>eff, access
(100)pulldown device
(110) access device
0
0.1
0.15
0.2
SNM (V)
0.25
Taurus Device Simulation

Chung-Hsun Lin - 68
FinFET Circuit design tradeoffs
Advantages
Excellent SCE
control
Scalability
Double-gates are
self-aligned
Insensitivity to
channel doping
Limitations
Gate material
Contact/Series
resistance
Area efficiency
(fin pitch)
Back gate routing
Chung-Hsun Lin - 69
Conclusion
Unique FinFET physics are introduced.
Recent developing effort on FinFET
technology are discussed
Independent gate, Multi-channel FinFET, Metalgate/high-K FinFET, Strained FinFET, Bulk FinFET
FinFET based CMOS and memory cells are
very promising for sub-32 technology
node.
Chung-Hsun Lin - 70
Thank you very much

for your attention
Chung-Hsun Lin - 71

Recent Development of Finfet Technology For Cmos Logic and Memory

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Recent Development of Finfet Technology For Cmos Logic and Memory

Transféré par

Droits d'auteur :

Formats disponibles

Recent Development of

FinFET Technology for CMOS

Recent FinFET Develop

Triple-gate FinFET, Omega FET, Nanowire FinFET,

DRAM, SONOS, SRAM

The first transistor

GATE LENGTH (nm)

NTUEE Seminar 2006/04/29

Scaling : Moores law

NTUEE Seminar 2006/04/29

Bulk-Si MOSFET Scaling Issues

Leakage current is the primary barrier to scaling

- High ON current (Idsat)

courtesy of Prof. Kuroda

NTUEE Seminar 2006/04/29

Issues for Scaling Lg to <25 nm

VT variation (statistical dopant fluctuations)

Incommensurate gains in Idsat with scaling

limited carrier mobilities

NTUEE Seminar 2006/04/29

Advanced MOSFET Structures

Leakage can be suppressed by using a thin body

NTUEE Seminar 2006/04/29

Control short-channel effects with Tbody

Electric Field Reduction

Reduced vertical field

NTUEE Seminar 2006/04/29

Control short-channel effects with Tbody

No channel doping needed!

Relax gate oxide (Tox) scaling

Double-Gate is even more effective

Scalable to 10nm gate lengths

Potentially less Vt scatter (dopant fluctuation)

NTUEE Seminar 2006/04/29

Circuit level benefits

Good control of SCE

FO4 Inverter Delay [ps]

NTUEE Seminar 2006/04/29

Rotation allows for self-aligned gates

NTUEE Seminar 2006/04/29

FinFET Process Flow

Poly Gate Deposition/Litho

NTUEE Seminar 2006/04/29

S/D Implant + RTA

FinFET Device Structure

All features defined by optical lithography

NTUEE Seminar 2006/04/29

10nm FinFET TEM

NTUEE Seminar 2006/04/29

10nm FinFET I-V

Dual N+/P+ poly gates:

Good SCE despite thick

NTUEE Seminar 2006/04/29

Gate Voltage [V]

Acceptable DIBL and

Subthreshold Slope (mV/dec)

Gate Length (nm)

NTUEE Seminar 2006/04/29

Rotation by 45 changes orientation from (110) to (100)

NTUEE Seminar 2006/04/29

Hole Mobility [cm /Vs]

Electron Mobility [cm /Vs]

How Mobility Changes