I.

OBJECTIVES
To be able to construct an input module to the Z-80 ANALAB microprocessor

consisting of at least three switches

To construct an output module of 8 LEDs, the lighting pattern of which would

be dictated by ANALAB programs that corresponds to switch combinations of the

input module
II.

PRELIMINARY REPORT
A.

Block Diagram
Input
module

B.

Microprocessor

Output
module

Block Diagram Description

The proposal shall be designed by virtue of I/O interfacing with the

ANALAB 2.0. The entire setup shall consist of three blocks namely, the input
module, the microprocessor, and the output module.
The input module, as the name implies, shall be used as an input to the
microprocessor. This module shall consist of a number of switches, which shall
serve as a conditioning factor for whatever output the microprocessor must show.
The major link between the input and the output of the setup will be the
microprocessor block. For this project, the ANALAB 2.0 microprocessor will be
used. This block will be fed with Z80 program that will be used to correlate the
input module with the output module.
The last block will now be the output module. This module will be the
representation of whatever program was run into the microprocessor. This module

will now consist of several LEDs for the display of both the input and
microprocessor output.
C.

Circuit Diagram
Input Module

Output Module

D.

Circuit Diagram Description

The input module is built with tri-state buffer, an address decoded, and

logic to generate the device select pulse. The decoder (74LS138N) is used to
examine the address bus for the port address of the microcomputer. When the port
address is present and IORD is equal to zero, a device select pulse (DSP) will be
generated. The latter will gate data onto the data bus through the eight tri-state
transmitters (buffer 74LS138N) enabled by the DSP.
When and only when, the instruction for the decoded port address is
executed, the low-order address will be the decoded address and the IORD line
will be low. This will cause the output of IC3A to go low, generating a device
select pulse labeled IOSEL. The IOSEL DSP is used to enable the 74LS244,
causing the settings of the eight switches to placed on the data bus. The
microprocessor latches this data byte and stores it in the accumulator on the rising
edge of IORD.
The design of the microcomputer output module requires the use of a latch
to catch the data when it is output on the system data bus. Again a DSP must be
generated, this time by combining the address select signal and the IOWR control
signal. The DSP is then used to clock the latch connected to the system data bus.
E.

Parts List

(1) 74LS30N

(1) DIP switch

(2) 74LS03N

(11) Resistors

(2) 74LS04N

(1) 74100N

(1) 74LS244N

(8) LED

(1) 74LS138N

III.

ANALAB SAMPLE PROGRAMS

A.

Running lights
Using switch status to output pattern
SUB A

// clear accumulator //

LD B, 05H

// switch S2 is closed //

LD C, 01H

// termination of rotation //

TEST: IN A, (87H)

// read input port //

CP B

// compare accumulator with register B //

JP Z, RUN

// perform subroutine RUN if condition is met //

JR TEST

// return to TEST if condition is not met //

RUN: LD A, 01H
LOOP: OUT (07H), A

// initial state for rotation //

// program the port //

CALL DELAY

// time delay //

RL A

// rotate LED //

CP C

// compare accumulator with terminating state //

JP NZ, LOOP

// return to cycle if condition is not met //

JR TEST

// return to input bit test if condition is met //

DELAY: LD HL, FFFFH

// set counter for time delay //

LD DE, 0001H
LOOP1: SBC HL, DE

// decrement counter until zero //

JR NZ, LOOP1
RET
Using ANALAB system bus to output pattern
START: SBC A
LD B, 01H
LD A, 01H

// clear accumulator //
// termination of rotation //
// initial state for rotation //

LOOP: OUT (07H), A

// program the port //

CALL DELAY

// time delay //

RL A

// rotate LED //

CP B

// compare accumulator with terminating state //

JP NZ, LOOP

// return to cycle if condition is not met //

JR START

// restart program if condition is met //

DELAY: LD HL, FFFFH

// set counter for time delay //

LD DE, 0001H
LOOP1: SBC HL, DE

// decrement counter until zero //

JR NZ, LOOP1
RET
B. Blinking lights
Using switch status to output pattern
SUB A

// clear accumulator //

LD B, 06H

// switch S1 is closed //

TEST: IN A, (87H)

// read input port //

CP B

// compare accumulator with register B //

JP Z, BLINK

// perform subroutine BLINK if condition is met //

JR TEST

// return to TEST if condition is not met //

BLINK: LD A, 00H

// initial state for rotation //

OUT (07H), A

// program the port (turn off LEDs) //

CALL DELAY

// time delay //

CPL

// complement last output of accumulator //

OUT (07H), A

// program the port (turn on LEDs) //

CALL DELAY

// time delay //

JR TEST

// return to input bit test if condition is met //

DELAY: LD HL, FFFFH

LD DE, 0001H

// set counter for time delay //

LOOP: SBC HL, DE

// decrement counter until zero //

JR NZ, LOOP
RET
Using ANALAB system bus to output pattern
BLINK: LD A, 00H

// initial state for rotation //

OUT (07H), A

// program the port (turn off LEDs) //

CALL DELAY

// time delay //

CPL

// complement last output of accumulator //

OUT (07H), A

// program the port (turn on LEDs) //

CALL DELAY

// time delay //

JR BLINK

// restart program //

DELAY: LD HL, FFFFH

// set counter for time delay //

LD DE, 0001H
LOOP: SBC HL, DE
JR NZ, LOOP
RET

// decrement counter until zero //