80386 and 80486 processors

Limitations of 80286 that lead to 80386

80286

has only a 16 bit processor.

Maximum
80286

segment size of 80286 is 64 KB.

cannot be easily switched between real

mode and protected mode.

The

amount of memory addressable by the 80286

is 16M byte.
To

increase the over all system performance.

80386 Microprocessor

Flexible

32-

bitmicroprocessorintroduc
ed byIntelin 1985.
The

chip of 80386 contains

132 pins & total 129

80386 Microprocessor
Four

level protection mechanism

Pipelined
High

instruction Execution.

speed numeric support via

80287 and 80387 coprocessor.

Uses

3-stage pipelines.

Supports

multitasking with

protection.

Versions of 80386
80386DX the full version

The first member in 80386 family

this CPU could work with 16-bit and 32-bit external buses.

Comprises of both 32-bit internal registers and 32-bit

external bus.

80386SX the reduced bus version

low cost version of the 80386.

This processor had 16 bit external data bus,32-bit internal
registers and 24-bit external address bus.

80386SL

Register Organization Of 80386

Register Organization Of 80386

(1). The 80386 has eight 32 - bit general purpose registers which
may be used as either 8 bit or 16 bit registers.

(2). A 32 - bit register known as an extended register, is

represented by the register name with prefix E.

(3). Example : A 32 bit register corresponding to AX is EAX,

similarly BX is EBX etc.

(4). The 16 bit registers BP, SP, SI and DI in 8086 are now
available with their extended size of 32 bit and are names as
EBP,ESP,ESI and EDI.

System

Address Registers:

The

80386 supports Three types of descriptor

table, viz.
(1) Global Descriptor Table (GDT),
(2) Interrupt Descriptor Table (IDT),
(3) Local Descriptor Table (LDT),

They

holds the addresses of corresponding

segments.
8

Segment Selectors
Once

the descriptors are defined ,

how does the processor make use of
them?

Any

16 bit value that u write into a

segment register is called a selector,
because it selects a segment
descriptor from a descriptor table.

15

0 INDEX

TI RPL

Loading Segment Selectors

Any

given selector value selects one and only

one descriptor

When

loading segment selector ,the 80386

check that

The selector index is within the descriptor table

limit

The selector references the correct descriptor

table

The descriptor is of correct type

Local Descriptor Table

Local Descriptor Table(LDT)

GDTR

Each task can have access

to own private descriptor
table(LDT) in addition to
GDT.

15

0
LIMIT

31

GDT

BASE

LDTR

15

selector

LDTR
0
15
cache
LIMIT
31

LDT0

BASE

Contains descriptors that

provide access to code
and data in segments of
memory that are reserved
for the current task.

program invisible

LDTn

11

Loading Segment Selectors

Offset
2 1

Index
TI

RPL

GDT
GDT 2
GDT 1
GDT 0
GDTR

Flag Register of 80386 Microprocessor

The Flag register of 80386 is a 32 bit register. Out of the 32

bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is
always set at 1.

Two extra new flags are added to the 80286 flag to derive the
flag register of 80386. They are VM and RF flags.

Flag Register of 80386 Microprocessor

(1). IOPL

(Input Output Privilege Level) flags:- For

protected mode operations indicates the privilege
level, 0 to 3, at which your code must be running in
order to execute any I/O-related instructions.
(2). VM Virtual 8086 mode flag:- When it is set, the x86
processor is basically converted into a high-speed
8086 processor.
(3). RF:- Resume Flag Used with debugging to
selectively mask some exceptions.
(4). NT :- (Nested Task) It indicates that current task is
nested within another task in protected mode

Central Processing Unit

Memory Management Unit

Bus Control Unit

Architecture of 80386
Central

Processing Unit

Memory
Bus

Management Unit

Control Unit

Central Processing Unit

The CPU is further divided into:
Execution Unit
Instruction Unit
Execution

Unit:

Execution unit has 8 General and Special purpose registers,

which are either used for handling data or calculating offset
addresses.

The 64-bit barrel shifter increases the speed of all

shift, rotate.

Multiply/divide logic implements the bit-shift-rotate

algorithms to complete the operation in minimum
time.

Instruction Unit:
It

decodes the opcode bytes received

from the 16-byte instruction code
queue and arrange them into a 3decoded instruction queue.

After

decoding it is passed to control

section for deriving necessary control

The 80486 microprocessor

80486 is the next in Intels upward compatible 80x86

architecture.

Only few differences between the 80486 and 80386, but

these differences created a significant performance
improvement.

32 bit microprocessor and same register set as 80386.

Few additional instructions were added to its instruction set.

4 gigabyte addressing space .

Memory Management Unit

MMU consists of a segmentation unit and paging unit.

Segmentation

Unit:

Uses of two address components - segment and offset for

relocability and sharing of data.

It allows a maximum segment size of 4GB.

Memory Management Unit

Paging

Unit

It organizes physical memory in terms of pages of

4KB size.

It works under the control of segmentation unit

i.e. each segment is divided into pages.

It converts linear addresses into physical

addresses.

The control and attribute PLA checks privileges

at page level.

Bus Control Unit

It

has a prioritizer to resolve the

priority of various bus requests. This
controls the access of the bus.

The

address driver drives the bus

enable and address signals A2 A31.

Memory System of the 80386

The memory bank are accessed via four bank enable signals BE0,BE1,BE2
and BE3.
Bank3

1G*8

Bank 2

Bank1

1G*8

1G*8

Bank 0

1G*8

32 bit

BE0,BE1,BE2 and BE3 are active low signals.

Privilege protection
80386

protection mechanism

Memory management

Privilege protection

privilege level protection

PL0 (highest)

PL1

PL2

PL3(lowest)

numerically

Smaller PL means a

Improvements made in 80486

The

new design of 80486 allows the

instruction to execute with fewer clock

cycles.
486

is packed with 168 pin grid array

package instead of the 132 pin used for 386

processor.

Improvements made in 80486

Highly integrated device

80486 was powered with a 8KB cache memory.

Some new 80486 instructions are included to maintain the

cache.

Math co-processor is integrated on the chip allows it to

execute instructions 3 times faster as 386/387 combination.

Built-in parity checker & generator

Burst mode memory read & write

Why mode matters

Key

differences among the x86

modes:
How

memory is addressed and

mapped

What

instruction-set is available

Which

registers are accessible

Which

exceptions may be
generated

What

data-structures are required

Thank you