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Syllabus:
Boolean algebra, minimization of boolean functions; logic gates; digital IC families
(DTL,TTL,ECL,MOS,CMOS ). Combinatorial circuits: arithmetic circuits, code
converters, multiplexers, decoders, PROMs and PlAs. Sequential circuits: latches
and flip flops, counters and shiftregisters. Sample and hold circuits, ADCs, DACs.
Semiconductor memories.
Exam Year
87
88
89
90
91
92
93
94
95
96
97
98
99
00
1 mark Ques
2 mark Ques
5 mark Ques
Total Marks
16
21
14
16
17
16
Exam Year
01
02
03
04
05
06
07
08
09
10
11
12
13
1 mark Ques
2 mark Ques
5 mark Ques
Total Marks
16
14
19
20
12
12
16
16
13
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NUMBER SYSTEMS
1) The subtraction of the binary number Y from
another binary number X, done by adding the
2s complement of Y to X, results in a binary
number without overflow. This implies that the
result is:
(a) Negative and is in normal form
(b) Negative and is in 2s complement form
(c) Positive and is in normal form
(d) Positive and is in 2s compliment form
[1987 :1 mark]
(b) 1
(c) 32,767
(d) 65,535
[1993 : 1 Mark]
(b) 101111
(d) 110001
[2001 : 1 Mark]
[1997 : 1 Mark]
4) An equivalent 2s complement
representation of the 2s complement
number 1101 is
(a) 110100
(c) 110111
(b) 001101
(d) 111101
5) The 2s complement representation of -17
is
(a) 101110
(c) 111110
(a) B(A+C)(+ C )
TRA
(d) B (A+C)( + C )
2005 :2 Marks
]
BC D
+ A B C D + AB CD
be minimized to
(a) Y= ABC D +
B C
(b) Y= ABC D + BC
(c) Y= A BC D
D
(d) Y= A BCD +
(b)
X Y
(c) X Y
(d)
XY
[2013 : 2 Marks]
+
can
+A C D
+ A BC D
BC
D + A BC
BC
D + AB CD
[2007 : 2 Mark]
[ X + Z {Y +( Z + X Y ) }] { X + Z ( X +Y ) }=1
Then
(a) Y=Z
(b) Y= Z
(c) Z=1
(d) Z=0
[2009 : 2 Marks]
(c)
X Y,X Y
X Y,X YZ
,X Y Z
X Y Z , X YZ,X Y
(d)
X Y Z , X YZ,X YZ
,X Y Z
(a)
(b)
[2012 : 1 Mark]
14) In the circuit shown below Q1, has
negligible collector-to emitter saturation
voltage and the diode drops negligible
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