Proceeding of the 11th World Congress on Intelligent Control and Automation

Shenyang, China, June 29 - July 4 2014

An Improved PID Controller for Switching

Converters
Ghulam Abbas, Umar Farooq, Jason Gu, M. Usman Asad
Department of Electrical Engineering, The University of Lahore, Lahore Pakistan
*
Department of Electrical & Computer Engineering, Dalhousie University Halifax, N.S., Canada
ghulam.abbas@ee.uol.edu.pk, engr.umarfarooq@yahoo.com, Jason.gu@dal.ca, usmanasad01@hotmail.com
The paper thus suggests another technique for constructing
the PID controller on the basis of classical theory of control
system using root-locus rather than adopting the basic and
modified PID control schemes. Being well-aware of the basic
control technique, the designer has more control on placing the
poles and zeros of the lead-lag controller for superior transient
response. The PID controller derived from root-locus based
lead-lag controller is further reconfigured into the PID-DOO
for better static and dynamic response. At last, digitization of
the PID controller is made for easier implementation.

Abstract This paper describes the design and construction of an

improved PID controller for a DC-DC buck converter working in
Continuous Conduction Mode (CCM). The converter operates at
a switching frequency of 1MHz. The lead-lag controller is first
designed on the basis of classical theory of control systems using
root-locus technique. The controller is then equivalently
converted into a PID controller. The application of the derivative
part of the PID controller on the output voltage signal rather
than on the output voltage error signal reduces both the
maximum percent overshoot and the settling time. The modified
but improved form of PID controller is known as PID controller
with Derivative on Output Only (PID-DOO). The analog PID
controller is converted into a digital controller for the easier
implementation. MATLAB/Simulink based simulation results are
presented to validate the design procedure.

This paper is organized as follows: We start (Section II) by

reviewing the small-signal model of a buck converter. Section
III presents the detailed design procedure for a lead-lag
controller using root-locus technique. The lead-lag controller is
then transformed into the PID controller which is then
converted into its modified form i.e. PID-DOO for superior
static and dynamic response. Computer simulation results using
MATLAB/Simulink environment are given in section IV.
Finally conclusions are drawn in Section V. A detailed account
on the references used in this article is given in the end.

Keywords-component; Continuous Conduction Mode; rootlocus; PID; PID-DOO; MATLAB/Simulink; lead-lag

I.

INTRODUCTION

Achieving optimal response for high-frequency low-power

switching converters has been the chief aim of the SMPS
designers. Both the static and dynamic performance can be
improved using control techniques such as model-based
predictive control [1, 2], hysteresis-based mixed-signal voltagemode control [3], sliding mode control [4], adaptive control [5,
6], current-mode control [7, 8], hybrid posicast control [9],
neuro-fuzzy control [10], multi-mode control [11, 12], etc.
Rather than adopting the complicated and complex control
techniques, this paper presents the classical control theory
based control technique for better performance.

II.

A well-defined linear dynamic model of the converter is

required by the controller. Among the various switching
converters, we are considering a buck converter, also known as
step-down dc-dc converter, which converts a higher
unregulated DC input voltage Vin into a lower regulated output
voltage Vout at a required voltage level. The block diagram
incorporating a buck converter and a feedback loop is
illustrated in Fig. 1. The converter consists of a power
switching network (transistors Q1 and Q2) and a second-order
LC low-pass filter with parasitics such as inductor DC
resistance, RL, and capacitor equivalent series resistance, RC,
denoted explicitly. Second order parasitic resistances, such as
capacitor equivalent series inductance (ESL) and
interconnection impedances, are not represented. The capacitor
ESR, RC, results in introducing a zero frequency to the transfer
function [15]. The input DC supply voltage is chopped by the
switching network and therefore the converter is often called a
chopper which produces a reduced average voltage. The
component values used are indicated in Table 1.

It is interesting to observe that more than half of the

control loops are of PID or modified PID type [13]. Delicate
and fine tuning of PID controllers has been made on-site using
many different types of tuning rules proposed in the literature.
Although the basic and modified PID control schemes, such as
I-PD control, one-degrees-of-freedom PID control, twodegrees-of-freedom PID control, etc. have proved their
usefulness in providing satisfactory control and may possess
on-line automatic tuning capabilities, but in many given
situations they may not provide optimal control. For example,
owing to the heuristic approach adopted by the Ziegler-Nicolas
tuning method [14], the tuning process may become quite
laborious to achieve the excellent command tracking
performance. Poor load and line regulation is not desirable
particularly for the portable applications.

978-1-4799-5825-2/14/$31.00 2014 IEEE

MATHEMATICAL MODEL OF BUCK CONVERTER

1445

The quality factor, Q which is the combined Q-factor of

the LC filter and the output load, represents the damping effect
in the second-order system because of the load resistance, R in
the power stage. The resistance, RL comprises the DCR of the
inductor, the trace resistance, and the turn-on resistance of the
power MOSFETs. It is concluded that the stray resistances RL
and RC (if their values are quite low) do not affect the number
of poles and zeros in the transfer functions. They only
contribute to the gain of the converter.

Figure 1.

Closed-loop voltage-controlled power switching converter.

TABLE I.

BUCK CONVERTER PARAMETERS WITH THEIR TYPICAL

VALUES
Symbol
R
RL
RC
L
C
Vin
Vout
Vref
fs
Ts
H(s)

Value
4.5
505 m
5 m
4.7 H
4.7 F
3.6 V
2V
2V
1 MHz
1 s
1

Bode Diagram
Gm = Inf , Pm = 25.8 deg (at 7.08e+004 Hz)
50

Magnitude (dB)

Parameter
Load Resistance
Series Resistance of Inductor
Series Resistance of Capacitor
Output Filter Inductor
Output Filter Capacitor
Input Voltage
Output Voltage
Reference Voltage
Switching Frequency
Sampling Period
Sensor Gain

For the component values shown in Table 1, the transfer

function of the power stage described by (1) produces a pair of
complex conjugate poles at 1105 ( -0.7787 j 2.1031) with
a Q value of 1.44 and a zero at 6.77 MHz. The poles cause a
phase margin of 25.8 at the gain crossover frequency of 70.8
kHz. The Bode plot shown in Fig. 2 clearly indicates that this
system has a very small phase margin. A compensator, thus,
must be designed to provide gain at low frequencies high
enough to minimize output steady-state error and provide tight
output voltage regulation, high 0-dB gain crossover frequency
(bandwidth) about an order of magnitude below the switching
frequency to allow the power supply to respond to transients
quickly, and sufficient phase margin to ensure stability. The
phase margin of the compensated system should be in the range
of 45 to 60 to meet the transient response requirements [18].

The open-loop control-to-output voltage transfer function

in s-domain is given by (1) [16, 17].

s
+1

R ESR

= Vin ( s)
2

R + RL s + s + 1
2

Q0
0

-50
-100
-150
0

Phase (deg)

R
Vin ( s)
( RC Cs + 1)
R + RL
v0 ( s)

=
d
R + RC 2 L

+ C ( R & RL ) + RC C s + 1
LC
s +
R + RL
R + RL

(1)

-45
-90
-135
-180
3

10

10

ZERO =
Q=

(3)
1

0 ( L ( R + RL ) + C ( R & RL ) + RC C )

10

10

CONTROLLER DESIGN

PID controller derived from root-locus based lead-lag

controller is configured to get PID-DOO for optimal response.
Thus the first stepping stone is to design a root-locus based
lead-lag controller. The key point of designing a compensator
using root-locus is to select a point in the s-plane to be the
location for a dominant closed-loop pole. The selection of this
point is based on the transient performance specifications and
should produce a closed-loop system that will satisfy the
required specifications. The root-locus should pass through this
point to meet the specifications. Recall that for the selected
point in s-domain to be on the uncompensated system's rootlocus for a positive value of gain 0 < K < , it must satisfy the
following two conditions, i.e., the angle and magnitude criteria:

(2)

1
RC C

10

Figure 2. (a) Bode plot of the open-loop buck converter power stage.

III.
R + RC
LC
R + RL

10

Frequency (Hz)

with

0 =

10

(4)

where 0 and ZERO represent the LC filter complex double

pole and output capacitor ESR zero respectively.

1446

G p ( s ).Gcl ( s ) = 1800 ( 2l + 1) ; l = 0,1, 2,...

Step Response

(5)

2.5
Digital

K c .G p ( s ).Gcl ( s ) = 1

(6)

Analog
2

The DC gain Kc of the compensator is computed by

fulfilling the magnitude criterion at s1 i.e. K c .G p ( s ).Gcl ( s ) = 1

1.5
Vout (V)

in order to ensure s1 to be a closed-loop pole.

In order to design the lag compensator, first the ratio of the
actual steady-state error to the desired steady-state error, , is
calculated which is essentially equal to = z2 p2 > 1 . The
zero of the special lag compensator is usually placed to the
right of the real-axis projection of the dominant closed-loop
pole by a factor of M. That is to say,

z2 =

Re [ s1 ]
M

0.5

where = 50-100

(7)

V o u t (V )

G ( s)

p1 > z1 > z2 > p2 > 0,

z1 z2 = p1 p2

(8)

0.8

1
-4

x 10

2.5

3.5

4.5
-4

iL
0.6

0.6

x 10

iL (A )

0.4

2.04
2.02
2
1.98
1.96

Using the design procedure outlined above and assuming

the damping ratio of 0.6 and B = n , for the 0-dB crossover
frequency (bandwidth, B ) of 200 kHz which is 5 times below
the switching frequency, we come with the following phase
lead-lag compensator.

( s + 1.087110 )( s + 1.508 10 )
G ( s ) = 126.3971
( s + 1.544 10 ) ( s + 639)

0.2

Figure 3. (a) Output voltage response by analog controller and its digital
counterpart.

The compensator designed on the basis of root-locus is

generally given as:
Gcl ( s )
cg




( s + z1 ) ( s + z2 )
Gc ( s ) = K c
.
,
( s + p1 ) ( s + p2 )

Time (sec)

The pole is then placed to the right of the zero by a factor

of .

(9)

0.4
0.2
0
2

The simulation results shown in Figs. 3 and 4 suggest that

the controller designed on the basis of root-locus shows a little
bit more overshoot at start-up. Although it is difficult to
achieve overshoot-free start-up, the overshoot can be reduced
to a tolerable extent by fine-tuning the controller. The rootlocus based control technique also finds its limitation where the
addition of more poles and zeros in the compensated system
reduces the validity of the second-order equations, particularly
in terms of overshoot. This results in more iterations in
choosing the locations for the compensator poles and zeros.
Even more iterations do not give guarantee of significant
improvements in performance. Different locations for s1 can
also be selected. Both the above solutions are cumbersome and
toilsome. Rather than following the controller retuning
approach (sometimes becomes laborious), we propose an
improved PID controller which not only reduces the overshoot
at start-up but also reduces the settling time.

2.5

3.5
Time (s)

4.5
-4

x 10

Figure 4. Transient load response.

In order to derive the PID-DOO from lead-lag controller,

we proceed as follows:
The classical PID controller is described as:

s
1
+ d
GPID ( s ) = K p 1 +
i s d s +1
Kp
K
K s
= Kp + i + d
Ki =
; Kd = K p d ;
s d s +1
i

The solution involves the reconfiguration of the lead-lag

controller into a PID controller with Derivative on Output Only
(PID-DOO).

1447

( K p d + K d ) s 2 + ( K p + Ki d ) s + Ki
d s2 + s

(10)

where i and d are known as the integral and derivative

times respectively whereas K p , Ki , and K d are the
proportional, integral, and derivative constants, respectively.
Assuming that the compensator poles and zeros are in the
left-half plane, the single-stage phase lead-lag compensator as
already remarked is given by:

( s + z1 ) . ( s + z2 )
( s + p1 ) ( s + p2 )
s 2 ( z1 + z2 ) s + z1 z2
= Kc 2
s ( p1 + p2 ) s + p1 p2

Gc ( s ) = K c

(11)

The comparison of both the controllers PID as well as the

single-stage phase lead-lag gives the PID controller parameters
in terms of lead-lags as:
Kc

s 2 ( z1 + z2 ) s + z1 z2

s 2 ( p1 + p2 ) s + p1 p2

K p d + K d ) s 2 + ( K p + K i d ) s + Ki
(
=

Figure 5. Block digram showing a change in configuration from normal PID

to PID-DOO for a single-stage compensator.

d s2 + s

(12)

Step Response
2.5

Assuming

PID-DOO
PID
2

Vout (V)

1.5

0.5

(13)
0

0.2

0.4

0.6

0.8

1
-4

Time (sec)

x 10

(a)
60
PID
PID-DOO

Definitely the derived PID controller will show the same

performance as that of the lead-lag controller. It is interesting to
note that the application of the derivative part of the PID
controller on the output voltage signal rather than on the output
voltage error signal reduces both the maximum percent
overshoot at the start-up and the settling time. This
configuration of the derived PID controller reduces the
overshoot and the control signal peak value due to the fact that
that the derivative is not being taken on the step input. Fig. 5
shows a change in configuration from normal PID to PID-DOO
for a single-stage compensator.

40

u(t)

20

-20

The closed-loop step response shown in Fig. 6 (a) clearly

shows that the PID-DOO configuration not only reduces the
overshoot from 20.3% to 7.7% but also improves the settling
time from 5.52 s to 3.81 s. Improvement in steady-state error
is also observed. The control signal u(t), the input to the plant
in response to a step reference signal, for both the cases is
shown in Fig. 6 (b).

-40
1

4
5
Time (s)

9
-5

x 10

(b)
Figure 6. (a) Output voltage response by the analog PID and PID-DOO
controllers. (b) Control signal u(t).

1448

Moving the derivative action out of the forward path

prevents an impulse from appearing as part of the control signal
u(t) when the reference input is a step function. This results in
the reduction of overshoot at start-up for the PID-DOO
configuration. Simulation results validate the effectiveness of
the suggested control configuration.

Fig. 10 shows that the output voltage follows the step

changes in the reference voltage. In this way we can obtain
various demand levels of output voltage provided that the
output voltage remains below the input voltage as the topology
is the buck converter. The controller thus offers excellent
setpoint (reference) tracking.

Using the forward Euler transformation technique for the

integral term and the trapezoidal for the derivative term, analog
controller described in (10) can be converted into a discretetime PID controller as:

The performance characteristics offered by the controller

clearly mention that the converter has a satisfactory time
response. It shows better load and line regulation. This clearly
depicts that digital counterpart of the root-locus based derived
analog PID controller can be used to control the high-frequency
low-power switching converters for optimal response.

d [ n]
Ts
Ts
GPID ( z) =
= K p + Ki
+ Kd
e [ n]

z 1

d 2

Ts

(14)
z 1
1
+

z + 1
z 1

z +1

Output Voltage Response

The above controller in the difference equation form can

equivalently be expressed as:
d [ n ] = .d [ n 1] + .d [ n 2] + .e [ n ]

1.5

Vout (V)

(15)

+ .e [ n 1] + .e [ n 2]

where

(Ts

{K

d + 2)
p

i s

{(T

(Ts
(Ts

Ts d + 2 K p + K d d

{ K T (T
=
=

(Ts

d + 2)

d 2)
;
d + 2)

)}

};

d + 2) 4 ( K p + Kd d )

(Ts

d + 2)

d 2 ) ( Ki Ts K p ) + 2 K d d

(Ts

d + 2)

0.5

(16)

0.2

0.4
0.6
Time (sec)

0.8

1
-3

x 10

Figure 7. (a) Outpot voltage response of the discrete-time PID controller.

};

Vout (V)

IV. SIMULATION RESULTS

MATLAB/Simulink based simulation results are presented
to investigate the static and dynamic performance of the
discrete-time controller. A measure for assessing performance
of the control scheme is made in terms of time-domain
specifications pertaining to the output voltage response. Fig. 7
clearly depicts that the discrete-time PID based compensated
buck converter shows an underdamped output voltage
response. The response shows a settling time of 40 s and very
less maximum overshoot /undershoot.

2.1
2.08
2.06
2.04
2.02
2
1.98
1.96
1.94
1.92
1.9

1.5

2.5

3.5

4.5

5
-4

x 10
0.6
0.5
iL (A)

0.4

In order to investigate the dynamic response of the system,

Fig. 8 shows the load transient response. For a 50% change of
load, the output voltage settles to its steady-state value of 2 V
within 15 s. This shows that the controller shows excellent
load regulation. It is observed from Fig. 9 that the
perturbations or changes made in the input voltage are also
compensated by the discrete controller to ensure superior line
regulation.

0.3
0.2
0.1
0

1.5

2.5

3
3.5
Time (sec)

4.5

Figure 8. Load regulation for a 50% change of load.

1449

5
-4

x 10

digital controllers, the analog controller is digitized into its

digital counterpart for easier implementation through
microcontrollers, DSP processors, FPGAs, etc. Simulation
results are provided to validate the design technique. Future
work involves the implementation of digital controller by
FPGA.

2.15

V out (V )

2.1
2.05
2
1.95
1.9
1.85

1.5

2.5

3.5

4.5

REFERENCES

5
x 10

-4

[1]

[2]

V in (V )

4.5
4
3.5
3

[3]
1.5

2.5

3
3.5
Time (sec)

4.5

5
x 10

[4]

-4

Figure 9. Line regulation.

[5]

3.2
Vref (V)
Vout (V)

[6]

2.8

[7]
2.6

[8]
2.4

[9]
2.2

[10]

1.8

[11]
1.5

2.5

3
3.5
Time (sec)

4.5

5
-4

x 10

[12]

Figure 10. Reference voltage tracking.

V. CONCLUSION
The paper comprehensively describes the detailed design
procedure for an improved PID controller which is derived
from the root-locus based lead-lag controller. The lead-lag
controller is designed for the higher bandwidth for better
transient response. The higher the bandwidth, the better is the
transient response. Consequently, the derived PID controller
shows better performance. A little bit more overshoot at startup offered by PID controller can be reduced by reconfiguring it
into PID-DOO. As a consequence, the overall response shows
very little overshoot and less settling time. Thus without
following the complicated and entangled control algorithms,
the performance can be improved by reconstructing the
already-existing configuration. In order to have more control,
the PID controller is derived from root-locus rather than
following the heuristic approach. Realizing the significance of

[13]
[14]
[15]

[16]

[17]

[18]

1450

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