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# ECE442

SolidStateDevices&Circuits
Review

Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
jschutt@emlab.uiuc.edu
JoseE.SchuttAine ECE442

Vin = A sin t

## C must be large enough so that RC time

constant is much larger than period

JoseE.SchuttAine ECE442

Example
Find the barrier voltage across the depletion region of a silicon
diode at T = 300 K with ND=1015/cm3 and NA=1018/cm3.
Use

N AND
Vo = VT ln

2
ni

@ 300K,
ni = 1.5 1010 /cm3
VT = 0.026 V
1018 1015
1013
Vo = o = 0.026ln
= 0.026ln

(1.5 )2 1020
2.25

## Vo = o = 0.026 29.12 = 0.7571 volts

Vo = o = 0.7571 volts

JoseE.SchuttAine ECE442

Example
Two diodes are connected in series as shown in the figure with Is1
=10-16 A and Is2 =10-14 A. If the applied voltage is 1 V, calculate the
currents ID1 and ID2 and the voltage across each diode VD1 and VD2.

## The diode equations can be written as:

VD 1 VD 2
I
I
S1
I D1 = I S 1eVD1 / VT I D 2 = I S 2eVD 2 / VT
e VT = D1 = 1
IS 2
I D2
I
from which VD1 VD 2 = VT ln S 1 = 0.12
IS 2
Using KVL, we get VD1 + VD 2 = 1 from which VD 2 = 0.44 V and VD1 = 0.56 V

## I D1 = 1016 e0.56 / 0.026 = 0.22 A=I D 2

JoseE.SchuttAine ECE442

ID =

W
Cox (VGS VT )VDS
L

VDS  (VGS VT )
Cox =

ox
tox

3.9 o
=
tox

## Cox: gate oxide capacitance

: electron mobility
L: channel length
W: channel width
VT: threshold voltage

JoseE.SchuttAine ECE442

## MOS Triode Region - 2

VGS > VT
VDS < (VGS VT )

W
1 2
I D = nCox (VGS VT )VDS VDS
2
L

## Charge distribution is nonuniform across channel

Less charge induced in proximity of drain

JoseE.SchuttAine ECE442

## MOS Active Region

Saturation occurs at pinch off when

## VDS = (VGS VT ) = VDSP

VGS > VT
VDS > (VGS VT )
(saturation)

W
2
I D = nCox
(VGS VT )
2L
JoseE.SchuttAine ECE442

## CMOS Logic Gate Circuits

Two Networks
Pull-down network (PDN) with NMOS
Pull-up network (PUN) with PMOS
PUN conducts when inputs are low
and consists of PMOS transistors

## PDN consists of NMOS transistors

and is active when inputs are high

## PDN and PUN utilize devices

In parallel to form OR functions
In series to form AND functions
JoseE.SchuttAine ECE442

Pull-Down Networks

Y = A+ B

JoseE.SchuttAine ECE442

Y = AB

Pull-Up Networks

Y = AB

Y = A+B

JoseE.SchuttAine ECE442

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## Basic Logic Function

Basic
Function

INVERTER

NOR

NAND

Symbol
# Devices
PUN

1
PMOS

2
PMOS-Series

2
PMOS-Parallel

# Devices
PDN

1
NMOS

2
NMOS-Parallel

2
NMOS-Series

Truth
Table
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## Pull-Down and Pull-Up Functions

Pull-up network (PUN)
Pull-down network (PDN)

Key features
When PDN switch is on, PUN switch is off
and vice versa
Conditions for being on and off are
complementary
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## Pull-Down and Pull-Up

PDN-parallel
NMOS

YDP = A + B

PUN-series
PMOS

Truth Tables

JoseE.SchuttAine ECE442

YUS = AB

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BJT Bias
2. Emitter Bias

## Provides good stability with respect to

changes in with temperature
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## Bias is to keep MOS in saturation region

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## Common Source MOSFET Amplifier

Small-Signal Equivalent Circuit for MOS (device only)

1 'W
2
I D = kn (VGS VT )
2 L

I D
VGS

2I D
Veff

g m = 2kn' W / L

## where VGS VT = Veff

gm is proportional to =

gm =

=
VGS =VGSQ

JoseE.SchuttAine ECE442

ID
W /L
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## MOSFET Output Impedance

To calculate rds, account for
VDS
rds =
I D

=
VGS =VGSQ

I DP

1
2
W
Cox [VGS VT ]
2L

1
=
I DP

1 'W
2
= kn (VGS VT )
2 L

## rds, accounts for channel width modulation resistance.

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## Source Follower Configuration

Since source is not tied to the substrate,
we need to model the body effect. Note:
substrate is always tied to ground.

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## Bias: Choose R1 & R2 to set VBVE is then set. Choose RE

to set IE~IC. Quiescent point of Vout will be determined by
RC. Emitter is an AC short.
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## r: input resistance looking into the base

rx: parasitic series resistance looking into base ohmic base resistance
gm: BJT transconductance
ro=rce: output collector resistance related to the Early effect
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Hybrid- Parameters
iC
gm =
vBE

I C = cons tan t

IC
=
VT

## Can show that

r = ( + 1) re

v
r is defined as : r =
ib
Since ib =

g m v

then r =

gm

gm =

re

= g m r

## rce = ro is associated with the Early effect

VA
VA
=
rce = ro =
IC I B
JoseE.SchuttAine ECE442

1 1
gm + =
r re
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## MOS Topologies - Ideal

Avo
Rin
Rout

CS

CG

SF

g m RD

g m RD

RD

1
gm

RD

1
gm

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## BJT Topologies - Ideal

Avo

CE

CB

EF

g m RC

g m RC

Rin

r
+1

Rout

RC

RC
JoseE.SchuttAine ECE442

r + RE ( + 1)
RE & r /( + 1)
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Example
Given VBEON=0.6V, find the gain for the circuit shown

VBQ = 1.5 V
VEQ = 1.5 V 0.6 V = 0.9 V
0.9
0.9
IE 
=
= 0.9 mA
RE1 + RE 2 1 k

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Example (Cont)
I C  0.9 mA VoutQ = 12 V 0.9 10 = 3 V
AC analysis: RE2 is shorted and RE=RE1=100. Since
is not known, use:

AMB =

RC
RE + re

with  1

VT 26
re =
=
= 28.8
I E 0.9
AMB

10,000
=
= 77.5
100 + 28.8
JoseE.SchuttAine ECE442

AMB = 77.5
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