Using a Debye Polarization Cell to Predict Double-Layer Capacitor Performance

R. M. Nelms

D. R. Cahela and B. J. Tatarchuk

Department of Electrical Engineering

200 Broun Hall
Auburn University, AL 36849-5201

Department of Chemical Engineering

230 Ross Hall
Auburn University, AL 36849-5 127

Abstract
Double-layer capacitors (DLCs) are relatively
complex devices. Different models have been proposed for
DLCs. Presented in this paper is an evaluation of the Dehye
Polarization cell as a model for a double-layer capacitor. The
elements in this circuit model can be related to the chemical
reactions which occur inside the DLC. Circuit element values
are found from AC impedance measurements for a DLC and a
computer program which utilizes a nonlinear least squares
fitting technique. Variations in circuit element values with DC
bias level and manufacturing have been investigated. The
performance of the Dehye Polarization Cell in slow discharge
and pulse load applications has been compared to actual circuit
measurements and to simulated results using a classical
equivalent circuit.

I. INTRODUCTION
Double-layer capacitors (DLCs) are characterized by very
high capacitance values and low voltage ratings. For
example, capacitors are commercially available with
capacitances as high as 2700 F; voltage ratings seldom
exceed 3 V. DLCs are primarily applicable in electrical
systems which have a high peak to average power ratio where
the peak power is required infrequently. Examples of
electrical systems which fall into this category are an electric
vehicle [ 1,2], electromechanical actuation [3], phased array
radar [4], ride-through capability for adjustable speed drives
[5], and pulse communication systems [6]. The impact of
DLCs on the performance of these systems requires the
inclusion of a suitable DLC model into the overall system
model.
The focus of this paper is an examination into using a
Debye polarization (DP) cell [7,8], which is shown in Fig. 1,
to predict DLC performance. In the DLC, charge is stored in
the double layer formed at the interface between a large
surface area material such as activated carbon and an liquid
electrolyte [9,10]. RI is the separator resistance and depends
on the concentration and conductivity of the electrolyte used
in the DLC. The Helmholtz double-layer capacitance, Cd, is
influenced by the temperature and concentration of the
electrolyte and the surface area of the electrode material. The
charge transfer resistance ktand adsorption capacitance C,
represent charge transfer due to Faradaic reactions at the
surface of the electrode material and are affected by
temperature.
The circuit parameters for Fig. 1 are determined using a
two-step process. First, AC impedance measurements are
acquired using an experimental setup which consists of an
EG & G Princeton Applied Research potentiostat/galvanostat

0-7803-5589-X/99/$10.000 1999 IEEE

h4273A and model 5210 lock-in amplifier. Using this setup,

a small amplitude sinusoidal voltage is applied to the DLC
and the resulting sinusoidal current is measured. The
magnitude and phase of the impedance are then calculated
from the voltage and current. The maximum amplitude of the
sinusoidal voltage is 10 mV, and its frequency can be varied
from 50 pHz to 100 kHz. The small sinusoidal voltage can
be superimposed on a DC bias level, so the small signal
model for the DLC obtained from these measurements can be
studied as a function of DC bias level.
In the second step, equivalent circuit parameters are
calculated from the AC impedance measurements using the
computer program EQUIVCRT [7]. This program utilizes
nonlinear least squares fitting techniques to determine circuit
parameters for a wide variety of equivalent circuits. The
topology of a particular equivalent circuit is input by the user.
Program output inchdes values for the circuit elements and
statistical information which indicates how well the
equivalent circuit and circuit parameters fit the experimental
data.
AC impedance data for an ELNA 50F DLC operating at six
different DC bias levels are presented in the next section of
this paper. Equivalent circuit parameters for the DP cell are
then calculated as a function of DC bias level. Measurements
were also taken for five 50F DLCs, and equivalent circuit
parameters calculated to examine potential variations in the
manufacturing process. Described in the final section of this
paper is an investigation into the performance of the DP cell
in two DLC applications: a slow discharge and a pulse load.
The DP cell is evaluated by comparing its circuit response to
experimental data and to a circuit response from the classical
equivalent circuit.

2411

6
Fig. 1. Debye Polarization Cell.

11. THE EFFECTS OF DC BIAS LEVEL

AC impedance data were acquired for an ELNA 50F DLC
at six different DC bias levels: 0, 0.5 V, 1.0 V, 1.5 V, 2.0 V,
and 2.5 V. This data was first reported in [l 11 and is repeated
here in Fig. 2 for completeness. It can be seen in this figure
that the magnitude curves shift downward slightly as the DC
bias level increases. The magnitude increases as the
frequency decreases, which is indicative of a capacitive
circuit element. The magnitude is less than 0.1 Q in the
frequency range of 0.1 Hz to approximately 25 kHz. The

magnitude begins increasing as the frequency increases above

25 kHz because of the inductance of the test leads in the
experimental setup. It can also be seen in this figure that the
phase plots are not very sensitive to DC bias level. The phase
angle approaches -90" as the frequency decreases as is
expected for a capacitive element. It is approximately zero
from 1 Hz to 1 kHz and approaches 90" as the frequency
increases toward 100 kHz.
The data plotted in Fig. 2 are utilized as input into the
computer program EQUIVCRT to calculate circuit
parameters for the DP cell. Only data in the frequency range

10

--c Mag-OV
dMag-0.5V
--c. Mag-1V
Mag-1.5V
t Mag-2V
-*- Mag-2.5V

1.OE-03 1.OE-02 1.OE-01 1.OE+OO 1.OE+01 l.OE+02 1.OE+03 1.OE+04 1.OE+05

Frequency (Hz)

75
--e Phase-OV

60

$m

+Phase-0.5V

45

30

Phase-1.5V

15
.?-

Phase-2V

-+Phase-2.5V

Phase-1V

-15

a -30
-45
-60

-75
-90
1.OE-03 1.OE-02 1.OE-01 1.OE+OO I.OE+OI 1.OE+02 1.OE+03 1.OE+04 1.OE+05

Frequency (Hz)

Fig. 2. AC Impedance Data as a Function of Bias Level for an ELNA 50F DLC.

2412

of 1 mHz to 10 kHz is used in the parameter calculations.

The inductive effects seen for frequencies greater than 10
kHz are produced by the test leads in the experimental setup.
An inductance could have been added in series with RI in
Fig. 1 to model circuit behavior for frequencies greater than
10 W,however, it was decided to set the upper frequency at
10 kHz for the calculations. Fig. 3a is a plot of RI and %, as
a function of DC bias level. RI begins at a value of 93.1 mQ,
decreases to a value of 65.5 mQ at a bias of 1 V, and then
increases with bias until it reaches a value of 72.4 mR. The
manufacturer's data sheet for this DLC lists an internal
resistance which is less than or equal to 80 mQ. RI falls
within this range for bias levels greater than 1 V. The charge
transfer resistance R,behaves similarly to RI; its value
initially decreases and then increases rapidly for bias levels
greater than 1.5 V. Capacitances Cd, C,, and Cloldare plotted
as a function of bias level in Fig. 3b. Clotal,the total
capacitance, is defined as the sum of Cd and Ca. In spite of
fluctuations in both Cd and C,, C,,,,, increases smoothly with
DC bias level.
01

111. MANUFACTURING VARIATIONS

Five test capacitors were randomly selected from a group
of one hundred capacitors that were purchased at the same
time. AC impedance data were collected for these capacitors
operating at a DC bias level of 2.5 V over the frequency
range of 1 mHz to 100 kHz. The computer program
EQUIVCRT was then utilized to calculate circuit parameters
for the DP cell using data in the frequency range of 1 mHz to
10 kHz. The average value and standard deviation for each
circuit parameter were calculated to examine variations
produced by the manufacturing process. The calculated
values are given in Table 1. Note that the average value of
RI falls within the manufacturer's specifications for internal
resistance. The standard deviation for RI is less than that for
k,.Capacitance Cd shows the widest variation as the
standard deviation is approximately 12.4% of the average
value. On a percentage basis, the standard deviation for Clold
is the smallest for the capacitances.
Table 1. Average Value and Standard Deviation for DP Cell
Circuit Parameters for Five DLCs.

,
i

<

0 09 5-

oost

RI
- Cd
,

k
l
C,

- Ctotal
- ._

Average Value
69.2 m a
7.85 F
61.6 mR
33.3 F
41.1 F

Standard Deviation
3.47 mQ
0.9753 F
6.24 mR
1.01 F
0.416 F

001 -

IV. CIRCUIT PERFORMANCE

45
40

4
I

30

'-

10

5-

05

15

25

DC Bias Level 0

(b)
Fig. 3. Plot of DP Cell Circuit Parameters as a Function of
DC Bias Level for an ELNA 50F DLC.

An ELNA 50F DLC was subjected to two different tests to

evaluate how well the DP cell predicts circuit behavior. The
first test is a slow discharge. The DLC is charged to rated
voltage, a fixed resistance is connected to the DLC, and the
DLC voltage and current are recorded during the discharge
using a TDS744A Tektronix oscilloscope. The second test is
a pulse load. A fixed resistance is periodically connected
across the DLC and the voltage and current recorded. Using
parameters calculated from EQUIVCRT, the DP cell is
simulated in PSPICE, and the results compared to the
experimental voltage and current waveforms.
The simulated waveforms are also compared to circuit
waveforms obtained from another PSPICE simulation which
models the DLC with the classical equivalent circuit of Fig.
4. In this circuit, ESR is the equivalent series resistance, EPR
is the equivalent parallel resistance, and C is the capacitance.
The EPR models leakage phenomenon in the DLC. Leakage
rates for DLCs are typically on the order of hours. As a
result, the EPR is neglected in the simulation results
presented here because the length of the tests is less than 100
seconds. The ESR is determined by charging the DLC to its

2413

P
RE

Fig. 5. Test Setup.

Fig. 4. Classical Equivalent Circuit for a DLC.

ESR (R)

0.2576

7
ci;
29 mQ

c (F)
50

25mQ

142 NQ

rated voltage, connecting a known resistive load, and

measuring the voltage across and the current flowing from
the DLC. The change in voltage and current at the moment
of switch closure can be utilized to calculate a value for the
ESR [12]. It is important to note that the contact resistance in
the circuit is included in this ESR value. For the analysis
described here, the capacitance is assumed to be the rated
value of 50 F. The circuit parameters are shown below in
Table 2.

RA

Fig. 6. Test Setup with Contact Resistances.

The test setup utilized to obtain the experimental circuit

waveforms is shown in Fig. 5. Resistances RA and RE3 can
be adjusted to provide any desired current level. The
MOSFET is an International Rectifier IRL3803 with an onresistance of 6 mR. A function generator supplies the
required drive signals to the MOSFET through a standard
gate drive circuit. Recall from Fig. 3 and Table 1 that the
resistances in the DP cell are on the order of a few milliohms,
which is the same order of magnitude as the contact
resistances in the test setup. As a result, the contact
resistances must be measured and included in PSPICE
simulations of the DP cell. After the test circuit was
constructed in the laboratory, contact resistances were
measured with a Fluke 8840A multimeter, which has an
accuracy of 5 % digits. The measured contact resistances are
shown in Fig. 6.
For the slow discharge test, the 50F DLC is charged to
approximately 2.5 V, RA is removed from the circuit, and RE3
is a 3.9 R resistor, which has a resistance of 3.844 R as
measured by the Fluke 8840A multimeter. The MOSFET is
continuously gated on for 100 seconds. The actual capacitor
voltage and current were measured and recorded from the
circuit of Fig. 5. In all PSPICE simulations, the MOSFET
switch was modeled by a voltage-controlled switch with an
on-resistance of 6 m a . For simulations with the classical
equivalent circuit, the capacitor is replaced by the ESR and C

of Fig. 4 with values given in Table 2. Recall that the ESR in

this circuit contains all of the contact resistances, because it is
calculated from in-situ circuit measurements. The contact
resistances must be included for simulations using the DP
cell; therefore, the capacitor in Fig. 6 is replaced by the DP
cell.
The actual capacitor voltage and the simulated capacitor
voltage from both the classical equivalent circuit and the DP
cell are plotted as a function of time in Fig. 7 for the slow
discharge test. Note that both simulations accurately predict
the initial drop in capacitor voltage when the switch is first
closed. The simulated waveforms closely track the actual
waveform for approximately the first 15 seconds. After this
point, the DP cell predicts a lower voltage for the remaining
85 seconds. The capacitor voltage from the classical
equivalent circuit diverges slightly from the actual waveform
after 50 seconds.
The current waveforms for the slow discharge test are
shown in Fig. 8. Both the classical equivalent circuit and the
DP cell predict a higher initial current than is actually
measured in the circuit of Fig. 5. The current from the DP
cell falls off at a much faster rate than that from the classical
equivalent circuit. It falls below the actual current around 60
seconds. The actual current and the current from the classical
equivalent circuit are moving together at the end of the 100
second test.

2414

The pulse load test was conducted next. For this test, the
DLC was initially charged to 2.5 V, RA = 61 R, and RB = 1
R. Using the Fluke 8840A, these resistances were measured
to be 61.123 R and 0.877 R, respectively. The MOSFET is
gated with a 250 Hz waveform that has an on-time of 0.55
ms. The actual voltage and simulated voltage waveforms are
plotted for a 2 ms window in Fig. 9. The actual waveform
was captured when the DLC had discharged to about 2.28 V.
The spike in this waveform is switching noise generated by
the rapid turn-on of the MOSFET switch. Although it is
difficult to discern from the plot, the capacitor voltage from
the classical equivalent circuit and the DP cell lie on top of
each other.
The current waveforms for the pulse load test are plotted in
Fig. 10. The DP cell predicts the lowest current amplitude.
The current predicted by the classical equivalent circuit has
almost the same magnitude as the actual current. Note that
both the rise and fall times of the actual current are less than
that for either simulated waveform. Also the top of the
current pulse is flat for both simulated waveforms. The
actual voltage waveform of Fig. 9 also exhibited non-zero
rise and fall times.

Both the DP cell and the classical equivalent circuit predicted

a higher current than was actually measured. The DP cell
and classical equivalent circuit predict approximately the
same voitage waveform for the pulse load. The voltage drop
predicted by both circuits is less than the actual voltage drop.
The current waveform predicted by the classical equivalent
circuit almost matches the measured current waveform; the
DP cell current is slightly less than the current in the classical
equivalent circuit.

V. CONCLUSION
AC impedance measurements are frequently utilized to
characterize many electrical devices such as batteries. An
equivalent circuit for a double-layer capacitor (DLC),
referred to as the Debye Polarization Cell, has been presented
in this paper. The elements in this circuit can be related to
the physical phenomena inside the DLC. Using AC
impedance measurements for a DLC, parameter values for
the circuit elements can be calculated using a computer
program that employs a nonlinear least squares fitting
technique.
This procedure was illustrated using AC
impedance measurements for an ELNA 50F DLC at six
different DC bias levels. Plots of the magnitude and phase of
the impedance as a function of frequency indicate that the DC
bias level- does not have a significant impact on either
quantity. Resistances in the DP cell initially decrease with
DC bias level but then increase for bias levels greater than
1.5 V. The total capacitance of the DP cell increases with
DC bias level. It is interesting to note that total capacitance is
always less than the rated capacitance of the device. This can
be attributed to the small signal characterization of the device
by the application of a small sinusoidal voltage.
The ability of the DP cell to predict DLC performance was
evaluated in two different applications: a slow discharge and
a pulse load. The DP cell was simulated using PSPICE, and
the results compared to experimental measurements and
simulated results from a classical equivalent circuit. In the
slow discharge test, the DP cell predicts a lower capacitor
voltage than the measured capacitor voltage. The voltage
predicted by the classical equivalent circuit very nearly
matches the actual capacitor voltage. The lower capacitance
in the DP cell causes the capacitor voltage to decay faster.

2415

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T. C. Murphy and W. E. Kramer, U.S. Department of
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vector
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B. V. Tilak, C. P. Chen, and S. K. Rangarajan, A

model to characterize the impedance of electrochemical
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[9] D. R. Cahela, Electrochemical Impedance Spectroscopy

of Metal FiberIActivated Carbon Fiber Composite
Materials for Electrochemical Capacitors, Ph.D.
Dissertation, Auburn University, March 1998.
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of the IECON97 23 International Conference on
Industrial Electronics, Control and Instrumentation,
Vol. 3, pp. 1068-1073, November 1997.

[l I] R. M. Nelms, D. R. Cahela, R. L. Newsom, and B. J.

Tatarchuk, A comparison of two equivalent circuits for
double-layer capacitors, Proceedings of the Fourteenth
Annual IEEE Applied Power Electronics Conference,
Vol. 11, pp. 692-698, March 1999.

[12] R. L. Spyker and R. M. Nelms, High current

performance of 470F double-layer capacitors,
Proceedings of the 12th Annual IEEE Applied Power
Electronics Conference, Vol. 2, pp. 590 - 595, February
1997.

2.5

0.0I
0

20

40

60

80

100

Xrne (s)
Fig. 7. Capacitor Voltage vs. Time for Slow Discharge Test.

w
.0

0.2-

0.0

2416

2.2-

Actual
Classical

a
rn
m
b 2.0c

>

.8-

1.6-

0.0000

0.0005

0.0010
lime (s)

0.0015

0.0020

Fig. 9. Capacitor Voltage vs. Time for the Pulse Load Test.

2.0

3 1.5

..............

Actual
Classical
DP Cell

0.5

0.0

0.0000

0.0005

0.0010
Time (s)

0.0015

Fig. 10. Capacitor Current vs. Time for Pulse Load Test.

2417

0.0020