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Question 01:
Briefly explain the followings
a) Silicon Controlled Rectifier(SCR)
b) Triac
c) Insulated-Gate Bipolar Transistor (IGBT)
d) Shift registers
e) Sample and Hold circuitry
Question 02:
a) Draw a complete logic circuit of half adder and explain the operation of it.
b) Design a circuit to add a 2-bit binary number to another 2-bit binary number
(eg:- 01 + 01 = 10 , 11+01 =100) and explain the operation of it.
c) Design an asynchronous counter with modulus of eleven (MOD 11) with a regular
binary
sequence
0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011
( use J-K flip-flops)
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Question 03:
a) Design a circuit to eliminate contact bounce of a mechanical switch shown in
Figure Q3(a). (Use a suitable latch.)
Figure Q3 (a)
b) Following inputs(S,R,EN) are given to a gated S-R latch that is initially RESET.
Determine the Q output waveform.
Figure Q3 (b)
c) Design a synchronous counter using J-K flip-flops with the irregular binary count
sequence 001,010,111,101 , including state diagram, present statenext state table,
transition table for J-K flip-flop, Karnaugh maps, logic expressions for all J and K inputs
and circuit diagram.
Question 04:
a) A computer provide control signals(digital signal) via DAC (digital to analog converter)
to control speed of a motor. Output of the DAC ( analog current 0 - 2mA ) is amplified and
it produce motor speed from 0 to 1000rpm. Computer should be able to produce a motor
speed which is within 2 rpm of the desired speed. ( step size no greater than 2 rpm).How
many bits required as the inputs of DAC.
Figure Q4 (a)
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b) Find the output voltage for the R-2R DAC of Figure Q4(b). The digital input is 1102
( VRef= 5V dc , R= 15k, 2R= 30k, RF= 15k , Find currents I0, I1, I2 and use formula
V0 = - ITRF )
Figure Q4 (b)
c) Determine the followings for the ADC shown in Figure Q4(c).
i.
Resolution of the ADC
ii.
Digital equivalent obtained for analog input VA = 2.628V
iii.
Conversion time
(clock frequency = 1 MHz, Threshold voltage VT =0.1mV , DAC full scale output 10.23V ,
DAC input 10 bits)
Figure Q4 (c)
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