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# 1) A bulb in a stair case has two switches, one switch being at the ground floor and the

other one at the first floor. The bulb can be turned ON and also can be turned OFF by
any one of the switches irrespective of the state of the other switch. The logic of
switching of the bulb resembles
(A) AND gate (B) OR gate (C) XOR gate (D) NAND gate

(GATE-2013)

Solution: Let the two bulbs be p1 and p2
P1
OFF
OFF
ON
ON

P2
OFF
ON
OFF
ON

OUTPUT
OFF
ON
ON
OFF

## 2 )In the sum of products function f(X,Y,Z)=(2,3,4,5),the prime implicants are

A )XY,XY
C)XYZ,XYZ,XY

B) XY,XYZ,XYZ
D)XYZ,XYZ,XYZ,XYZ,
(GATE-2012)

Solution:

## 3) The two numbers represented in signed 2s complement form are

P=11101101 and Q=11100110.If Q is subtracted fromP,the value obtained in
signed 2s complement form is
A )100000111 B)00000111

C)11111001 D)111111001

Solution: P=11101101 Q=11100110
Subtract Q hence find out 2s complement=00011010
P=11101101 Q=00011010 Discard the carry 00000111

(GATE-2008)

4) Which of the Boolean expression correctly represents the relation between P,Q,R and M1?
(GATE 2008)

A) M1 = (P OR Q) XOR R
B) M1 = (P AND Q) XOR R
C) M1 = (P NOR Q) XOR R
D) M1 = (P XOR Q) XOR R
Solution: M1=[(PQ)(P+Q)] XOR R
=[(P+Q)(P+Q)] XOR R
=(PQ+PQ) XOR R
=P XOR Q XOR R.
5 ) For the circuit shown in the figure I0-I3 are inputs to the 4:1 multiplexer R(MSB0 and
are control bits
(GATE-2008)

## The output Z can be represented by

A ) PQ+PQS+QRS
B )PQR+PQS
C )PQR+PQR+PQRS+QRS
D )PQR+PQRS+PQRS+QRS

## 6) The Boolean expression Y=ABCD+ABCD+ABCD+ABCD can be minimised to

A) ABCD+ABC+ACD
B) ABCD+BCD+ABCD
C) ABCD+BCD+ABCD
D) ABCD+BCD+ABCD

(GATE-2007)

7) In the following circuit, output at the second mux x is given by (GATE-2007)

A)
B)
C)
D)

X = ABC+ABC+ABC+ABC
X = ABC+ABC+ABC+ABC
X = AB+BC+AC
X = AB+BC+AC
Solution : For MUX 1
A(S1)
0
0
1
1

B(S1)
0
1
0
1

Y1
0
1
1
0

Y1=AB+AB
For MUX 2
Y1(S1)
0
0
1
1

C(S0)
0
1
0
1

Y
0
1
1
0

Y=Y1C+Y1C
= (AB+AB)C+(AB+AB)C
Therefore Y = ABC+ABC+ABC+ABC

8 ) For the circuit shown, the counter state (Q1,Q0) follows the sequence (GATE-2007)

## (A) 00, 01, 10, 11, 00 .

(B) 00, 01, 10, 00, 01 .
(C) 00, 01, 11, 00, 01 .
(D) 00, 10, 11, 00, 10

Solution: D0=(Q0+Q1)=Q0. Q1 and D1=Q0
Q1(t)
0
0
1
0
.
.

Q0(t)
0
1
0
0
.
.

Q1(t+1)=D1=Q0(t)
0
1
0
0
.
.

Q1(t+1)=D0=(Q0+Q1)
1
0
0
1
.
.

## 9 ) The number of product terms in the minimized sum-of-product expression obtained

through the following K-map is (d denotes dont cares)
(GATE-2006)
(A) 2 (B) 3 (C) 4 (D) 5

10) For the circuit shown in figure below,two 4-bit parallel-in-serial-out shift registers are
loaded with the data shown are used to feed the data to full adder. Initially,all the flip=flops are
in clear state.After applying two clock pulses,the outputs of the full-adder should be
(GATE 2006)

(A) S = 0
(B) S = 0
(C) S = 1
(D) S = 1

C0 = 0
C0 = 1
C0 = 0
C0 = 1

11) Decimal 43 in Hexa-decimal and BCD number system is respectively
(A) B2,0100 0011
(B) 2B, 0100 0011
(C) B2, 0011 0100
(D) B2, 0100 0100

(GATE-2005)

Solution: First, convert the given code to BCD code and then to binary code.
12) The Boolean function f implemented in the figure using two multiplexers using two input
multiplexers is
(GATE-2005)

(A) ABC+ABC
(B) ABC+ABC
(C) ABC+ABC
(D) ABC+ABC

Solution:Selection line B can be 0 or 1
When B=0 CBA
When B=1 CBA
Therefore f=ABC+ABC

(GATE-2004)

## (A) change in the input immediately reflected in the output

(B) change in the output occurs when the state of the master is affected
(C) change in the output occurs when the state of the slave is affected
(D) both the master and slave states are affected at the same time
14) The range of signed decimal numbers that can be represented by 6-byte 1s complement
number is
(GATE-2004)
A)
B)
C)
D)

-31 to +31
-63 to +64
-64 to +63
-32 to +31

Solution: Complement range of numbers is 2n-1 +1 to 2n-1 -1
When n=6 it ranges from -31 to +31
15) A digital system is required to amplify a binary-encoded audio signal. The user should be
able to control the gain of the amplifier from a minimum to a maximum of 100 increments.
The minimum number of bits required to encode,in straight binary ,is (GATE-2004)
(A) 8
(B) 5
(C) 6
(D) 7
Solution:2 to the power of 7 =128
Therefore for 100 increments 7 bits are required.

16) Choose the correct one from among the alternatives A,B,C,D after matching an item from
Group-1 with the most appropriate item in Group-2
(GATE-2004)
Group-1
P:Shift Register
Q:Counter
R:Decoder
A)
B)
C)
D)

Group-2
1:Frequency Division Multiplexing
3:Serial to parallel data conversion

P-3,Q-2,R-1
P-3,Q-1,R-2
P-2,Q-1,R-3
P-1,Q-2,R-2

17) The figure shows the internal schematic of a TTL AND-OR-INVERT(AOI) gate.For the
inputs shown in figure, the output Y is
(A) 0 (B) 1 (C) AB (D) (AB)
(GATE-2004)

Solution:In TTL AND-OR inverter gate,propagation delay of transistor depends on
RC elements,When inputs are floating output is zero.

## 18) The output Y in the circuit is always 1 when

A) two or more of the inputs P,Q,R are 0
B)two or more of the inputs P,Q,R are 1
C) any odd number of the inputs P,Q,R is 0
D) any odd number of the inputs P,Q,R is 1
Solution: The output expression Y in the circuit
Y=PQ+PR+RQ
So that two or more inputs are 1,Y is always 1.

(GATE-2011)

19) When the output Y in the circuit below is 1it implies that data has
A) Changed from 0 to 1
B) Changed from 1 to 0
C) Changed in either direction
D) Not changed

(GATE-2011)

Solution: When data is0 Q is 0
And if q is 1 first fliopflop data is changed to 1
Qis 1it results in first D
Q is connected to2nd flipflop so that Q2=1
So that inputs of AND gate is 1.Hence Y=1

## 20) The logic function implemented by the circuit below is

A)F=AND(P,Q) B)F=OR (P,Q) C)F=XNOR(P,Q) D)F=XOR(P,Q)

(GATE-2011)

Solution:0 is connected to I0 and I3
1 is connected to I1 and I2
Therefore F=PQ+PQ=XOR(P,Q)

21) In an 8085 microprocessor, the instruction CMP B has been executed while the content of
the accumulator is less than that of register B. As a result
(A) Carry flag will be set but Zero flag will be reset

(GATE 2003)

(B) Carry flag will be rest but Zero flag will be set
(C) Both Carry flag and Zero flag will be rest
(D) Both Carry flag and Zero flag will be set
ANS:A
SOL : CMP B
If A<R

## ;Compare the accumulator content with context of Register B

; CY is set and zero flag will be reset.

22)

## The 8255 Programmable Peripheral Interface is used as described below.

(i) An A/D converter is interface to a microprocessor through an 8255.The conversion
is initiated by a signal from the 8255 on Port C. A signal on Port C causes data to be
stobed into Port A.

(GATE 2004)

(ii) Two computers exchange data using a pair of 8255s. Port A works as a bidirectional
data port supported by appropriate handshaking signals.
The appropriate modes of operation of the 8255 for (i) and (ii) would be
(A) Mode 0 for (i) and Mode 1 for (ii)
(B) Mode 1 for (i) and Mode 2 for (ii)
(C) Mode for (i) and Mode 0 for (ii)
(D) Mode 2 for (i) and Mode 1 for (ii)
Ans: D
SOL :
For 8255, various modes are described as following.
Mode 1 : Input or output with hand shake
In this mode following actions are executed
1. Two port (A & B) function as 8 - bit input output ports.
2. Each port uses three lines from C as a hand shake signal
3. Input & output data are latched.
Form (ii) the mode is 1.
Mode 2 : Bi-directional data transfer
This mode is used to transfer data between two computer. In this mode port A
can be configured as bidirectional port. Port A uses five signal from port C as
handshake signal.
For (1), mode is 2
(GATE 2004)
23)

The number of memory cycles required to execute the following 8085 instructions
(i) LDA 3000 H
(ii) LXI D, FOF1H
would be
(A) 2 for (i) and 2 for (ii) (B) 4 for (i) and 3 for (ii)
(C) 3 for (i) and 3 for (ii) (D) 3 for (i) and 4 for (ii)
ANS: B
SOL : LDA 16 bit & Load accumulator directly this instruction copies data byte
from memory location (specified within the instruction) the accumulator.
It takes 4 memory cycle-as following.
1. in instruction fetch

1. in copying data from memory to accumulator
LXI D, (F0F1)4 ; It copies 16 bit data into register pair D and E.
It takes 3 memory cycles.
(GATE 2004)
24)

## Consider the sequence of 8085 instructions given below

LXI H, 9258
MOV A, M
CMA
MOV M, A
Which one of the following is performed by this sequence ?
(A) Contents of location 9258 are moved to the accumulator
(B) Contents of location 9258 are compared with the contents of the accumulator
(C) Contents of location 8529 are complemented and stored in location 8529
(D) Contents of location 5892 are complemented and stored in location 5892
ANS:A
SOL :
; 9258H HL

LXI H, 9258H
MOV A, M

; (9258H) A

CMa

MOV M, A

; AM

## This program complement the data of memory location 9258H.

(GATE 2004)

25)

It is desired to multiply the numbers 0AH by 0BH and store the result in the
accumulator. The numbers are available in registers B and C respectively. A partof the
8085 program for this purpose is given below
MVI A, 00H
LOOP -----------

----HLT
END
The sequence of instructions to complete the program would be
(A) JNX LOOP, ADD B, DCR C
(B) ADD B, JNZ LOOP, DCR C
(C) DCR C, JNZ LOOP, ADD B
(D) ADD B, DCR C, JNZ LOOP
ANS:D
SOL :
MVI A, 00H

; Clear accumulator

## ; Add the contents of B to A

DCR C

; Decrement C

JNZ LOOP

HLT
END
This instruction set adds the contents of B to accumulator to contents of C times.

(GATE2005)
26)

## Consider an 8085 microprocessor system.

The following program starts at location 0100H.
LXI SP, OOFF
LXI H, 0701
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches 0109 H is
(A) 20 H (B) 02 H (C) 00 H (D) FF H
ANS:C
SOL : 0100H LXI SP, 00FF

## 0103H LXI H, 0701 ; Load HL with 0107H

0106H MVI A, 20H ; Move A with 20 H
0108 H SUB M

## ; Subtract the contents of memory

; location whose address is stored in HL

0109H ORI 40H

## ; Add the contents of memeory location

; whose address is stored in HL to A
; and store in A

## HL contains 0107H and contents of 0107H is 20H

Thus after execution of SUB the data of A is 20H - 20H = 00
(GATE2005)
27) If in addition following code exists from 019H onwards,
ORI 40 H
What will be the result in the accumulator after the last instruction is executed ?
(A) 40 H (B) 20 H (C) 60 H (D) 42 H
ANS:C
SOL: Before ORI instruction the contents of A is 00H. On execution the ORI 40H
the contents of A will be 40H
00H = 00000000
40H = 01000000
ORI 01000000
After ADD instruction the contents of memory location whose address is stored
in HL will be added to and will be stored in A
40H + 20 H = 60 H
(GATE2006)
28) An I/O peripheral device shown in Fig. (b) below is to be interfaced to an 8085
microprocessor. To select the I/O device in the I/O address range D4 H - D7 H, its chip-select
(CS) should be connected to the output of the decoder shown in as
below :

## (A) output 7 (B) output 5

(C) output 2 (D) output 0

ANS:B

(GATE2006

## 29) Following is the segment of a 8085 assembly language program

LXI SP, EFFF H
CALL 3000 H
:
:
:
3000 H LXI H, 3CF4
PUSH PSW
SPHL
POP PSW
RET
On completion of RET execution, the contents of SP is
(A) 3CF0 H (B) 3CF8 H (C) EFFD H (D) EFFF H
ANS:B
SOL : LXI, EFFF H ; Load SP with data EFFH
:
:
:
3000H LXI H, 3CF4 ; Load HL with data 3CF4H

## PUSH PSW ; Store contnets of PSW to Stack

POP PSW
; Restore contents of PSW from stack
PRE
; stop
Before instruction SPHL the contents of SP is 3CF4H.
After execution of POP PSW, SP + 2 SP
After execution of RET, SP + 2SP
Thus the contents of SP will be 3CF4H + 4 = 3CF8H
(GATE2007)
30) An 8085 assembly language program is given below.
Line 1: MVI A, B5H
2: MVI B, OEH
3: XRI 69H
5: ANI 9BH
6: CPI 9FH
7: STA 3010H
8: HLT
The contents of the accumulator just execution of the ADD instruction in line 4 will be
(A) C3H (B) EAH (C) DCH (D) 69H
ANS: B
SOL : Line 1 :
MVI A, B5H ; Move B5H to A
2 : MVI B, 0EH
; Move 0EH to B
3 : XRI 69H
; [A] XOR 69H and store in A
; Contents of A is CDH
; Add the contents of A to contents of B and
; store in A, contents of A is EAH
5 : ANI 9BH
; [a] AND 9BH, and store in A,
; Contents of A is 8 AH
6 : CPI 9FH
; Compare 9FH with the contents of A
; Since 8 AH < 9BH, CY = 1
7 : STA 3010 H
; Store the contents of A to location 3010 H
8 : HLT
; Stop
Thus the contents of accumulator after execution of ADD instruction is EAH.
(GATE 2007)
31) After execution of line 7 of the above program, the status of the CY and Z flags will be
(A) CY=0, Z=0 (B) CY=0, Z=1 (C ) CY=1, Z=0 (D) CY=1, Z=1
ANS:C
SOL : The CY = 1 and Z = 0

(GATE 2008)

## 2710 LXI H, 30A0 H

2414 PCHL
All address and constants are in Hex. Let PC be the contents of the program counter and HL be
the contents of the HL register pair just after executing PCHL.
Which of the following statements is correct ?
(A)PC= 2715H
HL =30A0H
(B)PC=30A0H
HL= 2715H
(C)PC= 6140H
HL =6140H
(D)PC =6140H
HL= 2715H
ANS:C
SOL:
2710H LXI H, 30A0H
; Load 16 bit data 30A0 in HL pair
; 6140H " HL
2714H PCHL
Copy the contents 6140H of HL in PC
Thus after execution above instruction contests of PC and HL are same and that is 6140H
(GATE 2009)
33) In a microprocessor, the service routine for a certain interrupt starts from a fixed location
of memory which cannot be externally set, but the interrupt can be delayed or rejected Such an
interrupt is
ANS:D
SOL: Vectored interrupts : Vectored interrupts are those interrupts in which program
control transferr to a fixed memory location.
Maskable interrupts : Maskable interrupts are those interrupts which can be rejected or
delayed by microprocessor if it is performing some critical task.

34) For the 8085 assembly language program given below, the content of the accumulator
after the execution of the program is

Ans: C
SOL:

(GATE 2011)
35) An 8085 assembly language program is given below. Assume that the carry flag is Initially
unset. The content of the accumulator after the execution of the program is

ANS: C
SOL :

(GATE 2013)

## 36) For 8085 microprocessor, the following program is executed

MVI A, 05H;
MVIB, 05H;
DCR B;
JNZ PTR;
HLT;
At the end of program, accumulator contains
(A) 17 H (B) 20 H (C) 23 H (D) 05 H
Sol:
Accumulator changes as follows (05 + 05 + 04 +03 +02 +01)H
At the end of Loop accumulator contains = 14H

37) The number of hardware interrupts (which require an external signal to interrupt)
Present in an a 8085 microprocessor are
a)1 b)4

c) 5

(GATE2000)

d)13

Ans: C
Sol: 1) Trap
2) RST 7.5
3) RST 6.5
4)RST 5.5

5)INTR

## 38) In a microprocessor, the address of the next instruction to be execute, is stored in

(GATE1993)
a) Stack pointer b) address latch c) program counter d) general purpose register.
SOL: Program counter is one which stores the address of next instruction to be executed.

39) The contents of Register B and accumulator A of 8085 microprocessor are 49H and 3AH
respectively. The contensts of A nad the status of carry flag(cy) and sign flag(S) after
execting SUB B instructions are
a) A=F1,CY=1,S=1 B) A=0F,CY=1,S=1
C) A=F0,CY=-0,S=0 D) A=1F,CY=1,S=1
ANS:A
SOL:
A3AH=00111010
B49H=01001001

(GATE 1993)

SUB A11110001
CY=1,S=1,A=F1.
40) An instruction used to set the carry fag in a computer can be classified as
a) data transfer instruction
b) arithimetic
c) logical

(GATE2000)

d) program control
Ans:B
SOL: After performing an arithmetic operations the status of the flags is changed.
41) In a microprocessor, the address the next instruction to be execute, is stored in (Gate1993)
b) Stack pointer b) address latch c) program counter d) general purpose register.
SOL: Program counter is one which stores the address of next instruction to be executed.

## 42) when a cpu Is interrupted it

a) stops execution of instructions

(GATE 1995)

## b) acknowledges interrupt and branches to subroutine

c) acknowledges interrupt and continues
d) acknowledges interrupt and wiats for the next instruction from the interrupting device
SOL: when ever an interrupt is executed it stops executing the current instruction and transfer to
the subroutine and after completing the subroutine it returns back to the main program where it has
been interrupted.

(GATE 1995)

## a) Direct transfer of data between memory and accumulator

b) direct transfer of data between memory and i/o devices without the use of micorpocesor
c) Transfer of datsa exclusively within microprocessor register
d) a fast transfer of data between microprocessor and I/O devices