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Module 10: Memory Interfacing

68000 Microprocessor

Types of memory
Industry-standard memory pinouts
68000 asynchronous bus signals
Glue logic design
Memory
y control signal
g
g
generator
DTACK generator
Bus error generator

2006-2008 mzabidi@ieee.org

10-1

Generic CPU - Memory Interface

CPU - Memory Interface usually consists of:

68000 Microprocessor

uni-directional address bus


bi directional data bus
bi-directional
read control line
write control line
ready control line
size (byte, word) control line

address bus
data bus

CPU

Read
Write
Ready
size

Memory

Memory access involves a memory bus transaction

read:
(1) set address, read and size,
(2) copy data when ready is set by memory

write:
it
(1) set address, data, write and size,
(2) done when ready is set

2006-2008 mzabidi@ieee.org

10-2

Memory Types

68000 Microprocessor

ROM : Read-Only Memory


Non-volatile (data retained even without power)
Exists
E i
on allll computers
Functions on embedded systems: power-on self test, monitor program,
application program.
Functions on general-purpose computer: power-on self test, basic
input/output system (BIOS), monitor program, etc

RAM : Random Access Memoryy


Volatile (data disappears without power)
Functions on general purpose computer: main memory for running
operating system and application program
Functions on embedded systems: scratch-pad memory
May not be required on very simple embedded systems

2006-2008 mzabidi@ieee.org

10-3

ROM Types

68000 Microprocessor

MROM : Mask-programmed read-only memory


Programmed (contents set) at the factory
Low
L
cost per unit
i
High NRE (non-recurring engineering) cost

PROM : Programmable
g
ROM

Programmable once

EPROM : erasable programmable ROM


Programmable & erasable 1000x
Must be erased using ultra-violet (UV) light before reprogramming
Device uses expensive
p
ceramic p
package
g & has a q
quartz window to
allow UV to pass through
Used for prototyping. When design is sold to customers, cheaper
OTPROM is used instead.

2006-2008 mzabidi@ieee.org

10-4

ROM Types

68000 Microprocessor

EEPROM : Electrically-erasable PROM


Reprogrammable 1000x
Can
C b
be erased
d completely
l l or b
byte-by-byte
b b
Expensive
Can be reprogrammed in-system (without removing from circuit board)

Flash memory
Electrically erasable block-by-block
Reprogrammable 10
10,000x
000x
Very high density
Cheapest type of non-volatile memory, used in thumb drives

OTPROM : One-time programmable ROM


Uses the same die as EPROM but uses a plastice package so it
cannot be erased
Used in embedded systems which will never be reprogrammed

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10-5

Types of RAM

68000 Microprocessor

SRAM : Static Random Access Memory


upside: fast and no refresh required
downside:
d
id not so d
dense and
d not so cheap
h
often used for caches
Easy to interface. Well use this type.

DRAM : Dynamic Random Access Memory


upside: very dense (1 transistor per bit) and inexpensive
downside: requires refresh circuit and often not the fastest access
times
often used for main memories
More
M
complex.
l
O
Out off the
h scope off this
hi course.

2006-2008 mzabidi@ieee.org

10-6

68000 Microprocessor

Memory Organization

Number of address and data lines on a memory


chip is related to how bits are arranged
y
internally
Number of locations = 2 ^ address lines

Example: 27C64 chip has 13 lines numbered


from A0 through A12

Example: 27C64 chip has 8 data lines numbered


from D0 through D7

Memory organization is a shorthand notation to


describe all the information stated above
Memory
y organization
g
is 2 ^ ((address lines)) x
data lines

Example: 27C64 EPROM is has 8K x 8


organization

13

A0-A12

It has
h 213 = 23 x 210 = 8 x kil
kilo = 8192 llocations
ti

Number of bits per location = data lines

Address
bus

8 kil
kilo llocations
ti
x 8 = 8192 x 8 = 65536 bit
bits ttotal
t l

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27C64
8K x 8
EPROM
D0-D7
8

Data
bus
10-7

JEDEC

68000 Microprocessor

Joint Electronic Device


Engineering Council
St d d pinout
Standard
i
t ffor many
related memories
Interchangeability of
d i
devices
ffrom diff
differentt
vendors

2006-2008 mzabidi@ieee.org

10-8

More JEDEC

2006-2008 mzabidi@ieee.org

68000 Microprocessor

10-9

68000 Microprocessor

JEDEC Industry Standard Pinouts


2764 EPROM

6264 SRAM

Vpp

28

V CC

N.C.

28

V CC

A12
A7

2
3

27
26

PGM
N.C.

A12
A7

2
3

27
26

WE
CS2

A6
A5

4
5

25
24

A8
A9

A6
A5

4
5

25
24

A8
A9

A4
A3

6
7

23
22

A11
OE

A4
A3

6
7

23
22

A11
OE

A2
A1

8
9

21
20

A10
CE

A2
A1

8
9

21
20

A10
CS1

A0
D0

10
11

19
18

D7
D6

A0
D0

10
11

19
18

D7
D6

D1
D2

12
13

17
16

D5
D4

D1
D2

12
13

17
16

D5
D4

GND

14

15

D3

GND

14

15

D3

2006-2008 mzabidi@ieee.org

10-10

Part Numbers vs Capacity

68000 Microprocessor

Its very easy to derive memory capacity from the part number

From capacity (bits), divide by 8 to get number of addresses (byte


locations).
locations)
Chip

Capacity

2732

32 kilobits

4k x 8

12

2764

64 kilobits

8k x 8

13

27128

128 kilobits

16k x 8

14

27256

256 kilobits

32k x 8

15

27512

512 kilobits

64k x 8

16

27C010

1 Megabit

128k x 8

17

27C020

2 Megabit

256k x 8

18

27C040

4 Megabits

512k x 8

19

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Organization #addr lines

10-11

EPROM Control Signals


Address
bus

68000 Microprocessor

A0-An

D0-Dm

OE

Data
bus

CS
PGM

Pin Name

Meaning

CS

Chip Select

OE
PGM

Function
Enables chip operation

Output Enable Performs a read operation


Program

Used only when programming the chip

If chip selected but OE = 1, data bus is placed on a high-impedance state (Hi-Z)


CS may also be called CE (Chip Enable)

2006-2008 mzabidi@ieee.org

10-12

SRAM Control Signals


Address
bus

68000 Microprocessor

A0-An

OE

D0-Dm

Data
Bus

CS
WE

Pin Name

Meaning

CS

Chip Select

OE
O
WE

Function
Enables chip operation

Output Enable
ab e Performs
e o s a read
ead ope
operation
at o
Write Enable

Performs a write operation

If OE and
d WE are active
ti att the
th same time,
ti
a write
it operation
ti be
b performed
f
d

2006-2008 mzabidi@ieee.org

10-13

SRAM Read Timing Parameters

68000 Microprocessor

tRC (Read cycle time)


shortest time allowed between 2 consecutive reads
tAA ( Address access time)
how long it takes to get stable output after a change in address
tCE (Chip select to output)
how long it takes to get valid data after CE is asserted.
tOE (output enable time):
how long it takes for valid data to become available on data pins when
OE and CS are both asserted.
tOH (output-hold time)
length of time data stays valid on data pins after address changes
tOZ (output-disable time):
how long it takes for the three-state output buffers to enter highimpedance state after OE or CS are negated
negated.

2006-2008 mzabidi@ieee.org

10-14

68000 Microprocessor

Static RAM Read Timing

stable

ADDR

stable

stable

tAA

Max(tAA, tACS)

CS_L

tOH

tACS
OE_L

tAA
DOUT

tOZ
valid

tOE

tOZ
valid

tOE
valid

WE_L = HIGH

2006-2008 mzabidi@ieee.org

10-15

Memory and Peripheral Interface Pins

68000 Microprocessor

Recall from last chapter: 68000 control signals and Memory


subsystems signals are not the same
Data bus

Address bus

68000
CPU

Memory
Device
Read/Write
Address Strobe
Data Strobe(s)
Data Transfer Acknowledge

Glue
Logic

Chip Enable
Output Enable
Write Enable

We need g
glue to p
put them together!!
g

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10-16

Glue Logic

68000 Microprocessor

List of circuits we need to interface 68000 with memory

Memory control circuit

Address decoder covered next chapter

Generate CE* signals


E
Ensures
one and
d only
l one device
d i ttalks
lk tto th
the CPU att any titime

DTACK* Generator

Generates OE*
OE and WE*
WE signals required by memory chips

Informs the 68000 that the current bus cycle is complete


One DTACK* source for every device
Some 68000 peripherals has built-in DTACK* generator (68681 DUART,
68230 PIT, 68901 MFP etc)

BERR* G
Generator
t ((optional)
ti
l)

Informs the 68000 that there is a problem current bus cycle


Enables the 68000 to retry the memory access or shut down the offending
program

2006-2008 mzabidi@ieee.org

10-17

Asynchronous Bus Operation

68000 Microprocessor

The basic 68000 asynchronous operation is


The 68000 puts an address on the address bus and asserts Address
Strobe (AS*) to signal memory and I/O devices that a valid address is
available on the bus
The memory or I/O device asserts Data Transfer Acknowledge
(DTACK*) to signal the 68000 that

Valid data is available on the data bus during a read operation (the 68000
latches data when DTACK* is asserted)
Data has been successfully written to the memory or I/O device

Asynchronous operation allows the 68000 to interface with


slow memory or I/O memory devices
A 68000 memory access takes a minimum of eight clock
states numbered from clock states S0 to S7

2006-2008 mzabidi@ieee.org

10-18

Memory Read Cycle

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68000 Microprocessor

10-19

Word vs Byte Read

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68000 Microprocessor

10-20

Write Cycle

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68000 Microprocessor

10-21

Word vs Byte Write

2006-2008 mzabidi@ieee.org

68000 Microprocessor

10-22

68000 Microprocessor

Read vs Write Bus Cycles


During S0:
The processor drives
R/W high to identify a
read cycle

During S1:
The processor
drives a valid
address

S0

During S2:
The processor
asserts AS,
UDS, LDS

S1

S2

S3

S4

S5

During S4:
DTACK is
sampled

S6

S7

S0

S6 going
to S7:
Data is
latched

S1

S2

S3

During S3:
R/W is driven low.
It was high during
S0 to S2.

S4

S5

S6

S7

Data drivern by 68k


first, then validated by
UDS, LDS one bus
state later

S0

CLK
R/W*
A1-A23
AS*
UDS*,LDS*
DTACK*
D0-D7,D8-D15

Memory Read
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Memory Write
10-23

Bus Cycle 1, 2
MOVE.W

68000 Microprocessor

#$1234,$6886

Opcode
Fetch:
$31FC.

Fetch
immediate
data:
$1234.

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10-24

Bus Cycle 3,4


MOVE.W

68000 Microprocessor

#$1234,$6886

Fetch
destination
address.
$6886

Write data to
memory:

2006-2008 mzabidi@ieee.org

10-25

68000 Microprocessor

Simplified Timing Relationship


00001000
00001000
00001004
00001008
0000100C
00001010
00001010=
00001012
Bus Cycle

303C 1234
D038 1011
11C0 1010

0031

ORG
MOVE.W
ADD.B
MOVE.B

$1000
#$1234,D0
$1011,D0
D0,$1010

ORG
DC W
DC.W
DS.W

$1010
49
1

Addr Bus 1000

1002

1004

1006

1011

1008

100A

1010

Data Bus 303C

1234

D038

1011

--31

11C0

1010

65--

R/W*
/ *

UDS

LDS

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10-26

68000 Microprocessor

Understanding UDS* & LDS*

Internal
Signal
A23

A1
A0

WORD/BYTE

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Bus
Signal
A23

A1
UDS

WORD/BYTE

A0

UDS LDS

LDS

10-27

68000 Microprocessor

Understanding UDS* & LDS*


UDS*

LDS*

R/W*

Even
(D8-D15)

Odd
(D0-D7)

IInternal
t
l Processor
P
Operation

No valid data

No valid data

Word read

Valid data
Bit 8-15

Valid data
Bit 0-7

Odd byte read

No valid data

Valid data
Bit 0-7

Even byte read

valid data
Bi 8
Bit
8-15
1

No valid data

Word write

Valid data
Bit 8-15

Valid data
Bit 0-7

Odd byte write

Valid data
Bit 0-7

Valid data
Bit 0-7

Even byte write

Valid data
Bit 8-15

Valid data
Bit 8-15

Operation

Read

Write

We must not activate the wrong memory chip during byte writes.
2006-2008 mzabidi@ieee.org

10-28

Asynchronous Bus Control Signals


UDS*
Word address 15
$000000
$000002
$000004
$000006
$000008
$00000A
$00000
$00000C
$00000E
$000010

LDS*
87

Even bytes

2006-2008 mzabidi@ieee.org

Address generated by program


0

A31

A24 A23

Not
connected
to any pin

$FFFFF2
$FFFFF4
$FFFFF6
$FFFFF8
$FFFFFA
$FFFFFC
$FFFFFE

68000 Microprocessor

A1 A0
UDS
or
LDS

To A1A23 pins

Access Type

A0

UDS*

LDS*

Word

Even byte

Odd byte

Odd bytes

10-29

Memory Control Logic

UDS*
UDS

LDS*

R/W*
R/W

2006-2008 mzabidi@ieee.org

68000 Microprocessor

UPRD*

To OE* pin of even


(upper) memory chips

LORD*
LORD

To OE* pin of odd


(lower) memory chips

UPWR*

To WE* p
pin of even
(upper) memory chips

LOWR*

To WE* pin of odd


(lower) memory chips

10-30

Improved Memory Control Logic


R/W*

UDS*

LDS*

To OE* pin of all


memory chips

UPWR*

To WE* pin of even


memory chips

LOWR*

To WE* pin of odd


memory chips

Causes both even/odd chips to place data on upper/lower data bus for both byte reads
and word reads.

When reading a word, the whole bus is read by the 68k.

RD*

A single RD* line is enough!

68000 Microprocessor

This actually takes care of the majority of read operations (including all instruction
fetches).

When reading a byte


byte, 68k will read only the correct byte
byte, and ignore the other byte
byte.

Refer to Slide 10-14.

2006-2008 mzabidi@ieee.org

10-31

68000 Microprocessor

6264 Connections

Connect all low address lines directly to memory chip


chip, the rest to address decoder
Connect lower address bus to Odd Memory, upper address to Even memory
68000

Address bus

A1-A23

Upper data bus

D8-D15

Address
decoder

A0-A12

Even
SRAM

OE* WE*

LDS*

2006-2008 mzabidi@ieee.org

Memory
control
logic

D0-D7

D0-D7

CS

R/W*
UDS*

D0-D7

A1-A13
3

D8-D15

A1-A13

AS*

A14-A23
3

Lower data bus

D0-D7
A0-A12

CS

Odd
SRAM

OE* WE*

RD*
UPWR*
LOWR*

10-32

2006-2008 mzabidi@ieee.org
Lower data bus
L

Up
pper data bus

From
m 68000

D7
D6
D5
D4
D3
D2
D1
D0

D7
D6
D5
D4
D3
D2
D1
D0

D7
D6
D5
D4
D3
D2
D1
D0

D7
D6
D5
D4
D3
D2
D1
D0

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

From glue logic


From
m 68000

Connections From RAM & ROM Side


68000 Microprocessor

10-33

Wait States

68000 Microprocessor

Depending on the speed of your processor, the access times of your


memory and peripheral chips, it may be necessary to add a few clock
cycles
cyc
es into
o the
e 68000
68000ss bus cycle.
cyc e
The extra cycles are called wait states
This gives slower devices time to respond. Wait states are used only for
the slow devices; fast devices still run at full speed
speed.
For 68000, DTACK* input high causes the processor to wait.
To insert a wait state for a given device
we need
d to
t detect
d t t an access to
t that
th t device
d i
and hold DTACK* inactive for the required additional clock cycles.

In other words, use the chip select for a given device to delay DTACK*
going
i llow.

Today fast memory is cheap, so knowing how generate DTACK delay is


not that important any more

2006-2008 mzabidi@ieee.org

10-34

DTACK* Generator & Access Time

68000 Microprocessor

EPROM
or
SRAM

Address
bus

CS*

Address
decoder

SEL*

Delay
circuit

DTACK*

AS*

Speed of memory chip is


Alamat
Alamat sah
measured by
y address access
CS*
time (tac)
OE*
tac = delay from receiving a read
Data sah
Data
command and actually having
t
the data ready
DTACK* sampled by 68k at falling edge of S4
Data is sampled
p
at falling
g edge
g of S6
If DTACK* is high when sampled, 68k will keep inserting wait states
AC

2006-2008 mzabidi@ieee.org

10-35

Relation of DTACK* with tac

68000 Microprocessor

Access time is from address ready (latest by rising edge of S2) and data ready (sampled by
68k on falling edge of S6)
Effectively, 68k gives memory 2.5 clock cycles to prepare requested data
For 68k operating at 10 MHz, this is equiv. 100 ns x 2.5 = 250 ns.

If tac 250 ns, leave DTACK* grounded.

SYSCLK

S0

S1

S2

S3

S4

S5

S6

S7

R/W*
A1A23
AS
*

Valid data

D0DTACK*
Address bus stable ((although
g AS*
have not reported it)

2006-2008 mzabidi@ieee.org

Data read byy 68k


t ac max

10-36

68000 Microprocessor

Wait State Calculation

Convert access time to equivalent clock cycles.

Subtract 2.5 to get required wait state

Example for 68k @ 10 MHz / EEPROM @ 400 ns -> tAC = 4 clock cycles.
4 - 2.5 = 1.5

Round up

1.5 -> 2 wait states are needed


SYSCLK

S0

S1

S2

S3

S4

S
Sw

S
Sw

S
Sw

S
Sw

S5

S6

S7

R/W*
A1-A23
AS*
D0-D15

Valid data

DTACK*

Address bus & R/W signals stable

Data latched by 68k


t ac
= 400 ns

2006-2008 mzabidi@ieee.org

10-37

68000 Microprocessor

Example DTACK* Circuit for 4 Wait States


AS*
1WAIT
SEL*

SYSCLK

PRE

PRE

CLK

CLK

DTACK*

SYSCLK
SEL*
1WAIT
DTACK*
DTACK

2006-2008 mzabidi@ieee.org

10-38

Selectable DTACK* Wait States

68000 Microprocessor

Selectable 1 - 8 clock cycles


1

# wait states
DTACK*

Jumper block
UDS
UDS*
LDS*

1
1

CLR*
A
B

QA QB QC QD QE QF QG Q 1

SYSCLK

74LS164
SIPO shift register

SEL*

SYSCLK
CLR*
QA
2006-2008 mzabidi@ieee.org

10-39

Optional Bus Error Logic

AS* low will enable shift register


(SRG), at start of every bus cycle
In 8 E-clocks (80 cycles of main
CPU clock), output QH will be 1
and sends BERR*

68000 Microprocessor

If AS* becomes low at end of bus


cycle (because DTACK or VPA is
received),
ece ed), S
SRG
G will ca
cancel
ce sshifting
g
BERR* becomes L only if
DTACK* or VPA* was not
received and 68k was waiting
g too
long

MC
68000

2006-2008 mzabidi@ieee.org

10-40