EEE 21: Switching Theory and Digital Logic Design

Roel M. Ocampo, PhD

Computer Networks Lab (Rm 209)
981-8500 local 3323
roel@upd.edu.ph

Instructor

Lecture instructor

Consultation hours:
T, W, F 8am-12noon

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Credits

Unless otherwise indicated, most slides

used in this course were authored by or coauthored with Prof. Anastacia Ballesil

Combinational logic analysis and design.

Digital integrated circuit building blocks.
Design of digital subsystems. Analysis and
synthesis of sequential circuits. Introduction to
hardware description languages.

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Course Description

Course description

(Wikipedia)
A Symbolic Analysis of Relay and Switching
Circuits

master's thesis written by Claude E. Shannon at MIT

in 1937 (he was only 21 at the time)

Boolean algebra could be used to simplify the

arrangement of the relays that were the building
blocks of the electromechanical automatic telephone
exchanges

should also be possible to use arrangements of

relays to solve Boolean algebra problems.

"possibly the most important, and also the most

famous, master's thesis of the century"

1 Introduction to digital systems

1.1 Digital vs. analog
1.2 Number systems
2 Boolean algebra
2.1 Definition
2.2 Logic functions and set theory
2.3 Fundamental theorems
2.4 Evaluating Boolean expressions
2.5 Minimization by algebraic
manipulation
2.6 Gates and functionally complete sets
2.7 Realization of Boolean functions
using logic gates
2.8 Analysis of combinational circuits
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Course Syllabus

0 Course outline, grading procedure,

class policies

Course Syllabus

2.9 Forms of Boolean expressions, canonical forms

2.10 Formulating Boolean expressions
2.11 All-NAND and all-NOR implementations
2.12 Non-ideal conditions in combinational circuits
3 Other methods of minimizing combinational
logic circuits
3.1 Logical adjacency
3.2 Karnaugh maps
3.2.1 SOP
3.2.2 POS
3.3 Incompletely specified functions
3.4 Hazard-free circuits (reading assignment)
3.5 Map-entered variables

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3.6.1 Implicants, prime implicants and

cubical representation
3.6.2 Forming prime implicants and
obtaining minimal cover
3.6.3 Petricks method
3.6.4 Decimal Quine-McCluskey
3.6.5 Incompletely specified functions
and the tabular method

Course Syllabus

3.6 Tabular method of minimization

3.7 Multiple output circuits

4 Combinational building blocks

4.1 Adders
4.2 Comparators
4.3 Encoders and decoders
4.4 Data selectors / multiplexers and demultiplexers
4.5 Array logic

5 Mixed rails
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Course Syllabus

6 Introduction to sequential circuits

6.1 Canonical model, memory elements,
transition and excitation functions
6.2 Analysis of synchronous sequential circuits
6.3 Mealy and Moore machines
6.4 State minimization
6.4.1 By inspection
6.4.2 By partitioning
6.4.3 By implication
7 Synthesis of synchronous sequential circuits
8 Course wrap-up

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2 units lecture
1 unit discussion class (DC)

Credit, UVLE

Course credit: 3 units

UVLE online resources

https://uvle.up.edu.ph
Search for EEE21 (Ocampo)
Enrollment key: eee21aug2014

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Grading

No exams. Just quizzes.

Quizzes will not be announced. Coverage
may include material scheduled to be
lectured during the week, so study the
material in advance

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Grading

Pre-final grade = 60% quizzes + 40% DC

(DC: seatwork, problem set, recitation, etc)
Exemption: pre-final score of 60
Final exam for those not exempted, or if you
wish to improve your grade
Final grade = 70% pre-final + 30% final exam
92

88

84

80

76 72 68

64

60

<60

1.0

1.25

1.5

1.75

2.0

2.75

3.0

5.0

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2.25

2.5

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Policies

Complaints on grading

Must be made at most one week after results are

returned

Corrections will not be entertained after one week

Missed exams

Must submit an official excuse slip as soon as

you're back

Can only have up to two quizzes excused

Will need to take relevant portion of final exam to

make up

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University policy on cheating

Policies

Title 3, Chapter 76, Art 456:

A student shall be subject to disciplinary
action for any of the following acts:
a. Any form of cheating in examinations
or any act of dishonesty in relation to
his/her examinations

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I will file disciplinary cases with the appropriate

body or authority

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