Memory BIST Diagrams

Chapter 4 Memory Test Architectures and Techniques
Chip-Level
Embedded
Memory
Logic
Memory Access
PLL
TAP
JTAG Boundary Scan
Figure 4-1 Introduction to Memory Testing
Design-for-Test for Digital ICs and Embedded Core Systems

1999 Prentice Hall, All Rights Reserved
Alfred L. Crouch
Row/Word-Address
Select
Select
Column/Bit-Data
Column/Bit-Data
Storage
6 Transistor SRAM Cell

Row/Word-Address
Storage
Select
Column/Bit-Data
1 Transistor DRAM Cell

Row/Word-Address
Storage
Select
Column/Bit-Data
2 Transistor EEPROM Cell
Figure 4-2 Memory Types

Alfred L. Crouch
Data Bus: To Multiple Memory Arrays
Address Bus: To Multiple Memory Arrays
Bus
Enable
Data In
Data Out
Memory: Data Width by Address Depth
32 x 512
Address In
Read/WriteBar
Memory Array
Address Decode to Row Drivers
Data Decode to Column Drivers
Output Enable
Control Circuitry to Read, Write,

and Data Output Enable
Control Signals: Individual Signals to This Memory Array
Figure 4-3 Simple Memory Organization

Alfred L. Crouch
Chip FloorPlan
Memory 1
M
e
m
o
r
y
3
Memory
2
- Aspect Ratio
- Access Time
- Power Dissipation
Memory 4
Figure 4-4 Memory Design Concerns

Alfred L. Crouch
Chip FloorPlan
Memory 1
M
e
m
o
r
y
Memory
2
- Routing
- Placement & Distribution

- Overall Power Dissipation
Processor
Local
Logic
Memory 4
Figure 4-5 Memory Integration Concerns

Alfred L. Crouch
32
Embedded
Microprocessor
Core
Data
24
Embedded
Memory
Array
Address
3
Control
Functional Memory Test
Data
Address
Control
32
Embedded
Memory
Array
24
3
Direct Access Memory Test
Invoke
BIST Controller
Done
Reset
Embedded
Memory
Array
Hold
Fail
BIST Memory Test
Figure 4-6 Embedded Memory Test Methods

Alfred L. Crouch
column # >
row # > 0
row # > 1
data bit cell
row # > 2
Figure 4-7 Simple Memory Model

Alfred L. Crouch
Data in Bit Cells

May Be Stuck-At
Logic 1 or Logic 0
word stuck-at
data value 1110
address A031>
address A032>
address A033>
single bit stuck-at 1
single bit stuck-at 0
Figure 4-8 Bit-Cell and Array Stuck-At Faults

Alfred L. Crouch
Data in Bit Cells

May Be Bridged
to Other Bit Cells
horizontal (row)
bit bridging
vertical (column)
bit bridging
word bridging
unidirectional
one-way short
random
bit bridging
word bridging
bidirectional
two-way short
Figure 4-9 Array Bridging Faults

Alfred L. Crouch
10
Column Decode
X
C
O
Select Lines
R
O
0
Row Decode
stuck-at faults result
in always choosing
wrong address
Row Decode
bridging faults result
in always selecting
multiple addresses
o
d
e
Column Decode
bridging faults result
in always selecting
multiple data bits
Column Decode
Select Line
stuck-at faults result
faults result in
in always choosing
similar array
wrong data bit
fault effects
Figure 4-10 Decode Faults

Alfred L. Crouch
11
Data around target

cell is written with
complement data
Complementary
Data around
Target Cell
Address 21 = A
Address 22 = 5
Address 23 = A
Address 24 = 5
alternating 5s and As make for a natural checkerboard pattern

Figure 4-11 Data Retention Faults

Alfred L. Crouch
Blue: Pass
Red: Fail
12
Column
Data Fault
Physical Memory Organization

Row Address
Fault
Logical Memory Organization

Stuck-At
Bit Faults

Bridged
Cell Faults

Figure 4-12 Memory Bit Mapping

Alfred L. Crouch
13
Address 00 >
Address 01 >
Address 02 >
Address 03 >
Addr(00) to Addr(Max)
Read(5)-Write(A)-Read(A) Address 04 >
Increment Address
Address 05 >
Address 06 >
Read(A)-Write(5)-Read(5) Address 07 >
Increment Address
Address 08 >
Address 09 >
Addr(Max) to Addr(00)
Read(5)-Write(A)-Read(A) Address 10 >
Decrement Address
Address 11 >
Address 12 >
Read(A)-Write(5)-Read(5) Address 13 >
Decrement Address
Address 14 >
Address 15 >
Address 16 >
Address 17 >
Address 18 >
Address 19 >
Address 20 >
Address 21 >
Address 22 >
Address 23 >
Write(5)-Initialize
Increment Address
Read(5)
Decrement Address
Read (A)------->
Write (5)
Read (5)
Increment Address
March C+ Algorithm
Memory Array with 24 Addresses

with Algorithm at Read (A) Stage
Figure 4-13 Algorithmic Test Generation

Alfred L. Crouch
14
Boundary at some level

of scanned registration
or pipelining away
from the memory
array
Data
Data
Memory
Detection of
incoming
signals
Control of
outgoing
signals
Array
Address
Control
scan-memory
boundary
Minimum Requirement
Detection up to Memory Input
and Control of Memory Output
Concern: the Logic between

the Scan Test Area and the
Memory Test Area Is not
Adequately Covered
Non-Scanned Registration inside the Boundary

but Before the Memory Test Area Results in
a Non-Overlap Zone
Figure 4-14 Scan Boundaries

Alfred L. Crouch
15
The Memory Array is modeled

for the ATPG Engine so the
ATPG Tool can use the memory
to observe the inputs
and control the outputs
Data In
Din
Dout
Data Out
Memory
Array
Address
Ain
ATPG
Model
Control
Read/Write
Scan
Architecture
Figure 4-15 Memory Modeling

Alfred L. Crouch
16

is blocked off
as if the memory was
cut out of the circuit
Scan Mode
Control of
outgoing
signals
Data In
Gated Data Out
Detection of
incoming
signals
Memory
Array
can be
Address
Multiplexed Data Out
removed
from
All Registers
are in the
scan chain
architecture
netlist for
ATPG purposes
Control
scan black-box
boundary
Observe-only registers
used for detection of memory
input signals
Gate or Multiplexor is used

to Blockfix to a known
valuethe Memory
Output Signals
Figure 4-16 Black Box Boundaries

Alfred L. Crouch
17

is blocked off
Input is passed
to output as the
form of output
control
Data In
Bypass Data Out
Detection of
incoming
signals
Memory
array
can be
Address
removed
from
netlist for
ATPG purposes
Control
scan black-box
boundary
used for detection of memory
input signals
Multiplexor is used to
pass the input directly
to the output
Figure 4-17 Memory Transparency

Alfred L. Crouch
18
Detection of incoming
data signals done here
is blocked off
Input is passed
to output with
registration
Data In
Bypass Data Out

Memory
In ideal sense,
timing should
also be matched
array
can be
Address
removed
from
netlist for
ATPG purposes
Control
scan black-box
boundary
not needed on data since
register emulates memory
Register and multiplexor

is used to emulate memory
timing and output
Figure 4-18 The Fake Word Technique

Alfred L. Crouch
19
Data Bus: Possibly to Multiple Memory Arrays
Address Bus: Possibly to Multiple Memory Arrays
Data In
Data Out
Memory: data width by address depth
32 x 512
Address
Read/WriteB
Memory Array
Address Decode to Row Drivers
Data Decode to Column Drivers
Output Enable
Control Circuitry to Read, Write,

and Data Output Enable
Control Signals: Individual Signals to This Memory Array

Test Must Access the Data, Address, and Control Signals
in order to Test This Memory
Figure 4-19 Memory Test Needs

Alfred L. Crouch
20
Chip Level
Invoke
Retention
Debug
Algorithm Controller
Address Generator
Data Generator
Done
Fail
Debug_data
Memory Array(s)
Comparator
INPUTS
Invoke: Start BIST
Retention: Pause BIST and Memory Clocking
Debug: Enable BIST Bitmap Output
OUTPUTS
Fail: A Memory Has Failed a BIST Test
Done: Operation of BIST Is Complete
Debug_data: Debug Data Output
OPERATIONS
Address: Ability to Apply Address Sequences
Data: Ability to Apply Different Data Sequences
Algorithm: Ability to Apply Algorithmic Control Sequences
Comparator: Ability to Verify Memory Data
Figure 4-20 Memory BIST Requirements

Alfred L. Crouch
Retention
Release
Bitmap
Algorithm Controller
Address Generator
Data Generator
Comparator
Invoke
21
Din
Memory
DI Array Do
Ain
Write_en
WRB
Read_en
CEB
done
Fail
Hold_out
Bitmap_out
Dout
Clk
INPUTS
Invoke: invoke the BIST (apply muxes and release reset)
Retention: enable retention algorithm and pause
Release: discontinue and release pause
Bitmap: enable bitmap output on fail occurrence
OUTPUTS
Fail: sticky fail flagdynamic under bitmap
Done: operation of BIST is complete
Bitmap_out: fail data under bitmap
Hold_out: indication of pause
Figure 4-21 An Example Memory BIST

Alfred L. Crouch
22
Chip Level
bitmap_out1
Memory Array
with BIST
Invoke
done1 fail1
bitmap_out2
Memory Array
with BIST
Reset
Bitmap
done2 fail2
bitmap_out3
Memory Array
with BIST
Hold_1
Hold_2
Hold_3
Hold_4
done3 fail3
bitmap_out4
Memory Array
with BIST
so
s1
done4 fail4
fail 1-4
done 1-4
Invoke: a global signal to invoke all BIST units
Reset: a global signal to hold all BIST units in reset done fail diag_out
Bitmap: a global signal to put all BIST units in debug mode
Hold_#: individual hold signals to place memories in retention
or to select which memory is displayed during debug
done: all memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold mode will present debug data
Figure 4-22 MBIST Integration Issues

Alfred L. Crouch
23
bitmap_out1
Memory Array
with BIST
Invoke
done1
Reset
fail1
bitmap_out2
Memory Array
with BIST
Bitmap
done2
fail2
Hold_1
Memory Array
with BIST
bitmap_out3
Hold_2
done3
fail3
Hold_3
Hold_4
Memory Array
with BIST
done4
bitmap_out4
so
s1
fail4
fail 1-4
done 1-4
Invoke: must be a logic 0 when BIST is not enabled

Reset: should be a logic 0 when BIST is not enabled
done
fail diag_out
Bitmap: should be a logic 0 when BIST is not enabled

Hold_#: should be a logic 0 when BIST is not enabled
done: should not be connected to package output pin when BIST is not enabled
fail: should not be connected to package output pin when BIST is not enabled
diag_out: should not be connected to package output pin when BIST is not enabled
Figure 4-23 MBIST Default Values

Alfred L. Crouch
n
Invoke
n
Reset
n
Bitmap
Hold_1
Hold_2
Hold_n
M
e
m
o
r
y
invoke
1-m
done
A 1-n
r
r
a
y
s
M
e
m m
o
r
y
with fail
1-n
I M
n B debug
d I
e S hold_l1
p T
e s hold_l2
n
d
hold_1m
e
n
t
Bank 1
scan_out
1-n
24
done
A 1-m
r
r
a
y
s
with
fail
1-m
m I M
n B
d I
e S
p T
e s
n
d
e
n
t
Bank 2
m
diag_out
1-m
so
s1
Invoke: global signal invokes bank 1 BIST
Reset: global signal holds bank 1 BIST in reset
diag_out
Bitmap: global signal that enables BIST debug
fail
done
Hold_#: paired hold signals to place memories in retention

or to select which memory is displayed during debug
done: bank n memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold will present debug data
Figure 4-24 Banked Operation

Alfred L. Crouch
25
LFSR - PRPG
DQ
DQ
DQ
CLK
MBIST
Address
Functional
5
A
0
F
Memory Array
MBIST Data In
Data
Functional Data In
Algorithm
Sequencer
MBIST
Control
Functional
Functional & MBIST Data Out
DQ
DQ
Data Out
DQ
CLK
LFSR - MISR
Figure 4-25 LFSR-Based Memory BIST

Alfred L. Crouch
26
The Address sequence can be shifted

both forward and backward to provide
all addresses
The Data sequence can be shifted
across the data lines, and can also
provide data for a comparator
0
0
1
0
1
1
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
Address
Memory Array
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Data
0
1
0
0
1
0
Read/Write
The Control sequence can be

shifted across the read-write
or output enable or other
control signals
Figure 4-26 Shift-Based Memory BIST

Alfred L. Crouch
27
MBIST
Address
Functional
Read-Only Memory Array

MBIST
Functional
Read Control
Functional Data Out
Data Out
MBIST
DQ
DQ
DQ
CLK
LFSR - MISR
Figure 4-27 ROM BIST

Alfred L. Crouch
28
Memory Testing Fundamentals Summary

Memory Testing Is Defect-Based
Memory Testing Is Algorithmic
Different Types of MemoriesDifferent Algorithms
A Memory Fault Model Is Wrong Data on Read
Memory Testing Relies on Multiple-Clue Analysis
A Memory Test Architecture May CoExist with Scan
A Memory Can Block Scan Test Goals
Modern Embedded Memory Test Is BIST-Based
BIST Is the Moving of the Tester into the Chip
BIST-Based Testing Allows Parallelism
Parallel Testing Impacts Retention Testing
Parallel Testing Impacts Power Requirements
Parallel Testing Requires Chip-Level Integration
Figure 4-28 Memory Test Summary

Alfred L. Crouch

Memory BIST Diagrams

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Chapter 4 Memory Test Architectures and Techniques

Chapter 4 Memory Test Architectures and Techniques

Figure 4-1 Introduction to Memory Testing

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

6 Transistor SRAM Cell

1 Transistor DRAM Cell

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Data Bus: To Multiple Memory Arrays

Address Bus: To Multiple Memory Arrays

Control Circuitry to Read, Write,

Control Signals: Individual Signals to This Memory Array

Figure 4-3 Simple Memory Organization

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Figure 4-4 Memory Design Concerns

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

- Placement & Distribution

Figure 4-5 Memory Integration Concerns

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Direct Access Memory Test

BIST Memory Test

Figure 4-6 Embedded Memory Test Methods

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

data bit cell

Figure 4-7 Simple Memory Model

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Data in Bit Cells

single bit stuck-at 1

single bit stuck-at 0

Figure 4-8 Bit-Cell and Array Stuck-At Faults

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Data in Bit Cells

Figure 4-9 Array Bridging Faults

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

bridging faults result

stuck-at faults result

wrong data bit

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Data around target

alternating 5s and As make for a natural checkerboard pattern

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Physical Memory Organization

Logical Memory Organization

Physical Memory Organization

Physical Memory Organization

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Memory Array with 24 Addresses

Figure 4-13 Algorithmic Test Generation

Design-for-Test for Digital ICs and Embedded Core Systems

Chapter 4 Memory Test Architectures and Techniques

Boundary at some level

Concern: the Logic between